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CSE 467 1Verilog Digital System Design

Register Transfer LevelRegister Transfer Level

Design withDesign withVerilogVerilog

Adapted from Z.Adapted from Z. NavabiNavabiPortions Copyright Z. Navabi, 2006


Register Transfer Level DesignRegister Transfer Level Design

withwithVerilogVerilog

2.1 RT Level Design2.1 RT Level Design

2.1.1 Control/data partitioning2.1.1 Control/data partitioning

2.1.2 Data part2.1.2 Data part

2.1.3 Control part2.1.3 Control part

2.2 Elements of Verilog2.2 Elements of Verilog

2.2.1 Hardware modules2.2.1 Hardware modules

2.2.2 Primitive instantiations2.2.2 Primitive instantiations

2.2.3 Assign statements2.2.3 Assign statements

2.2.4 Condition expression2.2.4 Condition expression2.2.5 Procedural blocks2.2.5 Procedural blocks

2.2.6 Module instantiations2.2.6 Module instantiations

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Register Transfer Level DesignRegister Transfer Level Design

with Verilogwith Verilog2.3 Component Description in Verilog2.3 Component Description in Verilog

2.3.1 Data components2.3.1 Data components

2.3.2 Controllers2.3.2 Controllers

2.4 Testbenches2.4 Testbenches

2.4.1 A simple tester2.4.1 A simple tester

2.4.2 Tasks and functions2.4.2 Tasks and functions

2.5 Summary2.5 Summary


RT Level DesignRT Level Design

RT level design:RT level design:

Taking a high level description of a designTaking a high level description of a design

PartitioningPartitioning

Coming up with an architectureComing up with an architecture

Designing the bussing structureDesigning the bussing structure

Describing and implementing various components of theDescribing and implementing various components of the

architecturearchitecture

Steps in RT level design:Steps in RT level design:

Control/Data PartitioningControl/Data Partitioning

Data Part DesignData Part Design Control Part DesignControl Part Design

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RT Level DesignRT Level Design

RT LevelRT Level

DesignDesign

Control/dataControl/data


Data PartData Part Control PartControl Part



RT LevelRT Level

DesignDesign



Data PartData Part Control PartControl Part

Control/data

Partitioning

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RT Level Design

Flags & status

Opcode

Data flowControl signals

ControlDataPath

Reg

Control

Outputs

Control

Inputs

Data Inputs

Data Outputs


Data PartData Part

RT LevelRT Level

DesignDesign



Data PartData Part Control PartControl PartData Part

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Data PartData Part

Flags & status

Opcode


DataPath

Reg

Data Inputs

Data Outputs


Data PartData Part

modulemodule DataPathDataPath(DataInput, DataOutput, Flags, Opcodes,(DataInput, DataOutput, Flags, Opcodes,ControlSignals);ControlSignals);

inputinput [15:0] DataInputs;[15:0] DataInputs;outputoutput [15:0] DataOutputs;[15:0] DataOutputs;outputoutput Flags, ...;Flags, ...;outputoutput Opcodes, ...;Opcodes, ...;inputinput ControlSignals, ...;ControlSignals, ...;// instantiation of data components// instantiation of data components// ...// ...// interconnection of data components// interconnection of data components// bussing specification// bussing specification

endmoduleendmodule

DataPath ModuleDataPath Module

Control Signals:Control Signals:

Inputs to data part,Inputs to data part,

sent to the datasent to the data

components andcomponents and

bussesbusses

Output Signals:Output Signals:

Going to the controlGoing to the control

part, provide flagspart, provide flags

and status of the dataand status of the data

Control Signals for theControl Signals for the

busses: Select the sourcesbusses: Select the sources

and routing of data fromand routing of data from

one data componentone data component

to anotherto another

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Data PartData Part

modulemodule DataComponentDataComponent((DataInDataIn,, DataOutDataOut, ControlSignals);, ControlSignals);

inputinput [7:0][7:0] DataInDataIn;;outputoutput [7:0][7:0] DataOutDataOut;;inputinput ControlSignals;ControlSignals;// Depending on ControlSignals// Depending on ControlSignals// Operate on// Operate on DataInDataIn andand// Produce// Produce DataOutDataOut

endmoduleendmodule

Partial Verilog Code of a Data ComponentPartial Verilog Code of a Data Component

Data Component:Data Component:

Shows how theShows how the

component uses itscomponent uses itsinput control signalsinput control signals

to perform variousto perform various

operations on itsoperations on its

data inputsdata inputs


Control PartControl Part

RT LevelRT Level

DesignDesign



Data PartData Part Control PartControl PartControl Part

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Flags & status

Opcode


Control

Control

Outputs

Control

Inputs

Consists of one orConsists of one ormore state machinesmore state machines

to keep the state ofto keep the state of

the circuit.the circuit.

Makes decisions asMakes decisions as

to when and whatto when and what

control signals tocontrol signals to

issue depending onissue depending on

its state.its state.



modulemodule ControlUnitControlUnit(Flags, Opcodes, ExternalControls, ControlSignals);(Flags, Opcodes, ExternalControls, ControlSignals);

inputinput Flags, ...;Flags, ...;inputinput Opcodes, ...;Opcodes, ...;inputinput ExternalControls, ...;ExternalControls, ...;outputoutput ControlSignals;ControlSignals;// Based on inputs decide :// Based on inputs decide :// What control signals to issue,// What control signals to issue,// and what next state to take// and what next state to take

endmoduleendmodule

Outline of a ControllerOutline of a Controller

Takes controlTakes control

inputs from theinputs from the

Data PartData Part

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Elements of VerilogElements of Verilog

We discuss basic constructs of Verilog language for describing aWe discuss basic constructs of Verilog language for describing a

hardware module.hardware module.


Elements of VerilogElements of Verilog

HardwareHardware

ModulesModules

PrimitivePrimitive

InstantiationsInstantiations

AssignAssign

StatementsStatements

ConditionCondition

ExpressionExpressionProceduralProcedural

BlocksBlocks

ModuleModule


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Hardware ModulesHardware Modules

HardwareHardware

ModulesModules

PrimitivePrimitive


AssignAssign


ConditionCondition


BlocksBlocks

ModuleModule


Hardware

Modules



modulemodule module-namemodule-nameList of ports;List of ports;DeclarationsDeclarations......Functional specification of moduleFunctional specification of module......

endmoduleendmodule

Module SpecificationsModule Specifications

KeywordKeywordThe MainThe Main

ComponentComponent

of Verilogof Verilog

KeywordKeyword

Variables, wires, andVariables, wires, and

module parametersmodule parameters

are declared.are declared.

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There is more than one way to describe a Module in Verilog.There is more than one way to describe a Module in Verilog.

May correspond to descriptions at various levels of abstraction or toMay correspond to descriptions at various levels of abstraction or to

various levels of detail of the functionality of a module.various levels of detail of the functionality of a module.

Descriptions of the same module need not behave in exactly the sameDescriptions of the same module need not behave in exactly the same

way nor is it required that all descriptions describe a behavior correctly.way nor is it required that all descriptions describe a behavior correctly.

We discuss basic constructs of Verilog language for a hardware moduleWe discuss basic constructs of Verilog language for a hardware module

description.description.

We show a small example and several alternative ways to describe it inWe show a small example and several alternative ways to describe it in

Verilog.Verilog.


Primitive InstantiationsPrimitive Instantiations

HardwareHardware

ModulesModules

PrimitivePrimitive


AssignAssign


ConditionCondition


BlocksBlocks

ModuleModule


Primitive

Instantiations

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a

s

b

s_bar

a_sel

b_sel

w

A Multiplexer Using Basic Logic GatesA Multiplexer Using Basic Logic Gates

Logic GatesLogic Gates

calledcalled

PrimitivesPrimitives



modulemodule MultiplexerAMultiplexerA((inputinput a, b, s,a, b, s, outputoutputw);w);wirewire a_sela_sel,,b_selb_sel, s_bar;, s_bar;notnot U1 (s_bar, s);U1 (s_bar, s);andand U2 (U2 (a_sela_sel, a, s_bar);, a, s_bar);andand U3 (U3 (b_selb_sel, b, s);, b, s);oror U4 (w,U4 (w, a_sela_sel,,b_selb_sel););

endmoduleendmodule


InstantiationInstantiation

of Primitivesof Primitives

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Assign StatementsAssign Statements

HardwareHardware

ModulesModules

PrimitivePrimitive


AssignAssign


ConditionCondition


BlocksBlocks

ModuleModule


Assign

Statements


Assign StatementsAssign Statements

modulemodule MultiplexerB (MultiplexerB (inputinput a, b, s,a, b, s, outputoutputw);w);

assignassign w = (a & ~s) | (b & s);w = (a & ~s) | (b & s);

endmoduleendmodule

Assign Statement and BooleanAssign Statement and Boolean

ContinuouslyContinuously

drivesdrives with thewith the

right hand sideright hand side

expressionexpression

Using BooleanUsing Boolean

expressions toexpressions to

describe the logicdescribe the logic

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Condition ExpressionCondition Expression

HardwareHardware

ModulesModules

PrimitivePrimitive


AssignAssign


ConditionCondition


BlocksBlocks

ModuleModule


Condition

Expression


Condition ExpressionCondition Expression

modulemodule MultiplexerC (MultiplexerC (inputinput a, b, s,a, b, s, outputoutputw);w);assignassign w = s ? b : a;w = s ? b : a;

endmoduleendmodule

Assign Statement and Condition OperatorAssign Statement and Condition Operator

Can be used whenCan be used when

the operation of athe operation of a

unit is too complexunit is too complex

to be described byto be described by

Boolean expressionsBoolean expressions

Very Effective inVery Effective in

describing complexdescribing complex

functionalitiesfunctionalitiesUseful in describingUseful in describing

a behavior in aa behavior in a

very compact wayvery compact way

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Procedural BlocksProcedural Blocks

HardwareHardware

ModulesModules

PrimitivePrimitive


AssignAssign


ConditionCondition


BlocksBlocks

ModuleModule


Procedural

Blocks


Procedural BlocksProcedural Blocks

modulemodule MultiplexerD (MultiplexerD (inputinput a, b, s,a, b, s, outputoutput w);w);regreg w;w;alwaysalways @(a, b, s)@(a, b, s)beginbegin

ifif (s) w = b;(s) w = b;elseelse w = a;w = a;

endendendmoduleendmodule

Procedural StatementProcedural Statement

alwaysalways

statementstatement

if-elseif-else

statementstatement

Can be used when theCan be used when the

operation of a unit isoperation of a unit is

too complex to betoo complex to be

described by Boolean ordescribed by Boolean orconditional expressionsconditional expressions

Sensitivity listSensitivity list

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Module InstantiationsModule Instantiations

HardwareHardware

ModulesModules

PrimitivePrimitive


AssignAssign


ConditionCondition


BlocksBlocks

ModuleModule

InstantiationsInstantiationsModule

Instantiations



modulemodule ANDOR (ANDOR (inputinput i1, i2, i3, i4,i1, i2, i3, i4, outputoutput y);y);

assignassign y = (i1 & i2) | (i3 & i4);y = (i1 & i2) | (i3 & i4);

endmoduleendmodule

////

modulemodule MultiplexerE (MultiplexerE (inputinput a, b, s,a, b, s, outputoutput w);w);

wirewire s_bar;s_bar;

notnot U1 (s_bar, s);U1 (s_bar, s);

ANDOR U2 (a, s_bar, s, b, w);ANDOR U2 (a, s_bar, s, b, w);

endmoduleendmodule

Module InstantiationModule Instantiation

ANDORANDOR

module ismodule is

defineddefined

ANDORANDOR

module ismodule isinstantiatedinstantiated

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Multiplexer Using ANDORMultiplexer Using ANDOR

i1

i2

i3i4

y w

ANDORa

s

b


Component DescriptionComponent Description

in Verilogin Verilog

ComponentComponent

DescriptionDescription

DataData

ComponentsComponents ControllersControllers

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Data ComponentsData Components

ComponentComponent


DataData

ComponentsComponentsControllersControllers

Data

Components


DataData

ComponentsComponents

MultiplexerMultiplexer Flip-FlopFlip-Flop

CounterCounter Full-AdderFull-Adder

Shift-RegisterShift-Register ALUALU

InterconnectionsInterconnections

Data ComponentsData Components

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DataData






MultiplexerMultiplexer

Multiplexer


MultiplexerMultiplexer

`timescale`timescale 1ns/100ps1ns/100ps

modulemodule Mux8 (Mux8 (inputinput selsel,, inputinput [7:0] data1, data0,[7:0] data1, data0,outputoutput [7:0] bus1);[7:0] bus1);

assignassign #6 bus1 =#6 bus1 = selsel ? data1 : data0;? data1 : data0;endmoduleendmodule

Octal 2-to-1 MUXOctal 2-to-1 MUX

Selects its 8-bitSelects its 8-bit

oror inputinput

depending on itsdepending on its

input.input.

Defines a Time Unit of 1 nsDefines a Time Unit of 1 ns

and Time Precision of 100and Time Precision of 100psps..

A 6-ns DelayA 6-ns Delay

is specified for allis specified for all

values assigned tovalues assigned to

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DataData






Flip-FlopFlip-Flop

Flip-Flop


Flip-FlopFlip-Flop


modulemodule Flop (reset, din,Flop (reset, din, clkclk,, qoutqout););inputinput reset, din,reset, din, clkclk;;outputoutput qoutqout;;regreg qoutqout;;alwaysalways @(@(negedgenegedge clkclk))beginbegin

ifif (reset)(reset) qoutqout

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DataData






CounterCounter

Counter


CounterCounter

`timescale`timescale 1ns/100ps1ns/100psmodulemodule Counter4 (Counter4 (inputinput reset,reset, clkclk,,

outputoutput [3:0] count);[3:0] count);regreg [3:0] count;[3:0] count;

alwaysalways @(@(negedgenegedge clkclk))beginbeginifif (reset) count

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DataData






Full-AdderFull-Adder

Full-Adder


Full-AdderFull-Adder


modulemodule fulladderfulladder ((inputinput a, b,a, b, cincin,, outputoutput sum,sum, coutcout););assignassign #5 sum = a ^ b ^#5 sum = a ^ b ^ cincin;;assignassign #3#3 coutcout = (a &= (a &b)|(ab)|(a && cin)|(bcin)|(b && cincin););

endmoduleendmodule

Full-Adder Verilog CodeFull-Adder Verilog Code

Full-Adders are usedFull-Adders are used

in data part forin data part for

buildingbuilding

Carry-Chain addersCarry-Chain adders

A combinationalA combinational

circuitcircuit

All ChangesAll Changes

Occur after 5 nsOccur after 5 ns

All ChangesAll Changes

Occur after 3 nsOccur after 3 nsOne delay forOne delay for

every output:every output:

tPLHtPLH andand tPHLtPHL

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DataData






Shift-RegisterShift-Register

Shift-Register


Shift-RegisterShift-Register`timescale`timescale 1ns/100ps1ns/100ps

modulemodule ShiftRegister8ShiftRegister8((inputinput slsl,, srsr,, clkclk,, inputinput [7:0][7:0] ParInParIn,,inputinput [1:0] m,[1:0] m, outputoutput regreg [7:0][7:0] ParOutParOut););

alwaysalways @(@(negedgenegedge clkclk))beginbegincasecase (m)(m)

0:0: ParOutParOut

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Shift-Register (Continued)Shift-Register (Continued)`timescale`timescale 1ns/100ps1ns/100ps

modulemodule ShiftRegister8ShiftRegister8((inputinput slsl,, srsr,, clkclk,, inputinput [7:0][7:0] ParInParIn,,inputinput [1:0] m,[1:0] m, outputoutput regreg [7:0][7:0] ParOutParOut););

alwaysalways @(@(negedgenegedge clkclk))beginbegincasecase (m)(m)

0:0: ParOutParOut

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ALUALU`timescale`timescale 1ns/100ps1ns/100ps

modulemodule ALU8 (ALU8 (inputinput [7:0] left, right,[7:0] left, right,inputinput [1:0] mode,[1:0] mode,output regoutput reg [7:0][7:0]ALUoutALUout););

alwaysalways @(left, right, mode)@(left, right, mode) beginbegincasecase (mode)(mode)

0:0:ALUoutALUout = left + right;= left + right;1:1:ALUoutALUout = left - right;= left - right;2:2:ALUoutALUout = left & right;= left & right;3:3:ALUoutALUout = left | right;= left | right;defaultdefault::ALUoutALUout = 8'bX;= 8'bX;

endcaseendcaseendendendmoduleendmodule

An 8-bit ALUAn 8-bit ALU

2-bit2-bit Input toInput to

select one of its 4select one of its 4

functionsfunctions

AddAdd

SubtractSubtract

ANDAND

OROR


ALU (Continued)ALU (Continued)`timescale`timescale 1ns/100ps1ns/100ps

modulemodule ALU8 (ALU8 (inputinput [7:0] left, right,[7:0] left, right,inputinput [1:0] mode,[1:0] mode,output regoutput reg [7:0][7:0]ALUoutALUout););

alwaysalways @(left, right, mode)@(left, right, mode) beginbegincasecase (mode)(mode)

0:0:ALUoutALUout = left + right;= left + right;1:1:ALUoutALUout = left - right;= left - right;2:2:ALUoutALUout = left & right;= left & right;3:3:ALUoutALUout = left | right;= left | right;defaultdefault::ALUoutALUout = 8'bX;= 8'bX;

endcaseendcaseendend

endmoduleendmodule

An 8-bit ALUAn 8-bit ALU

The Declaration ofThe Declaration of

both asboth as

andand

Because ofBecause of

assigning it withinassigning it within

a Procedural Blocka Procedural Block

BlockingBlocking

AssignmentsAssignments

alternativealternative

puts allputs all ss ononifif ontainsontains

anything butanything but s ands and ss

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DataData







Interconnections



Partial Hardware UsingPartial Hardware Using andand

BsideAsideInbus

select_source

ABinput

Function

Outbus

8 8

8 8

8

Mux8 and ALUMux8 and ALU

examples formingexamples forming

a Partial Hardwarea Partial Hardware

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ALU8 U1 ( .left(Inbus), .right(ABinput),ALU8 U1 ( .left(Inbus), .right(ABinput),.mode(function), .ALUout(Outbus) );.mode(function), .ALUout(Outbus) );

Mux8 U2 ( .sel(select_source), .data1(Aside),Mux8 U2 ( .sel(select_source), .data1(Aside),.data0(Bside), .bus1 (.data0(Bside), .bus1 (ABinputABinput));));

Verilog Code of The Partial Hardware ExampleVerilog Code of The Partial Hardware Example

Instantiation ofInstantiation of

andand

andand ::

Instance NamesInstance Names

A Set of parenthesisA Set of parenthesis

enclose portenclose port

connections to theconnections to the

instantiated modulesinstantiated modules



ALU8 U1 (ALU8 U1 ( InbusInbus,,ABinputABinput, function,, function, OutbusOutbus ););Mux8 U2 (Mux8 U2 ( select_sourceselect_source, Aside,, Aside, BsideBside,,ABinputABinput ););

Ordered Port ConnectionOrdered Port Connection

An Alternative formatAn Alternative format

of port connectionof port connection

The actual portsThe actual ports

of the instantiatedof the instantiated

componentscomponents

are excludedare excluded

The list of local signalsThe list of local signals

in the same order asin the same order as

their connecting portstheir connecting ports

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ControllersControllers

ComponentComponent


DataData

ComponentsComponentsControllersControllersControllers



Controller OutlineController Outline

DecisionsBased on :Inputs ,

Outputs ,State

Issue ControlSignal

Set Next State

Go to Next State

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Controller:Controller:

Is wired into data part to control its flow of data.Is wired into data part to control its flow of data.

The inputs to it controller determine its next states and outputs.The inputs to it controller determine its next states and outputs.

Monitors its inputs and makes decisions as to when and what outputMonitors its inputs and makes decisions as to when and what output

signals to assert.signals to assert.

Keeps the history of circuit data by switching to appropriate states.Keeps the history of circuit data by switching to appropriate states.

Two examples to illustrate the features of Verilog for describing stateTwo examples to illustrate the features of Verilog for describing state

machines:machines:

SynchronizerSynchronizer

Sequence DetectorSequence Detector





SequenceSequence

DetectorDetector

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SynthesizerSynthesizerSequenceSequence

DetectorDetector

Synchronizer



SynchronizingSynchronizing

Clk

adata

synched

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modulemodule Synchronizer (Synchronizer (inputinput clkclk,, adataadata,,outputoutput regreg synched);synched);

alwaysalways @(@(posedgeposedge clkclk))if (if (adataadata == 0) synched

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State Machine DescriptionState Machine Description

Searches onSearches on

ititss inputinput

for thefor the

110 Sequence110 Sequence

When the sequenceWhen the sequence

is detected, the wis detected, the w

Output becomes 1Output becomes 1

and stays 1 for aand stays 1 for a

complete clock cyclecomplete clock cycle

If110 is detected

on a, then wgets

1, else wgets 0.

clk

a w



Sequence Detector State MachineSequence Detector State Machine

Initial

State

01

1

1

0

0

1

0reset

S0

0 0 10

S1 S2 S3

States are named:States are named:

,, ,, ,,

The State in whichThe State in which

the 110 sequence isthe 110 sequence is

detected.detected.

It Takes at leastIt Takes at least

3 clock periods to3 clock periods to

get to theget to the statestate

A Moore MachineA Moore Machine


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modulemodule Detector110 (Detector110 (inputinput a,a, clkclk, reset,, reset, outputoutput w);w);parameterparameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11;[1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11;regreg [1:0] current;[1:0] current;

alwaysalways @(@(posedgeposedge clkclk))beginbeginifif (reset) current = s0;(reset) current = s0;

elseelsecasecase (current)(current)s0:s0: ifif (a) current

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......................................................

......................................................alwaysalways @(@(posedgeposedge clkclk))beginbegin

ifif (reset) current = s0;(reset) current = s0;elseelsecasecase (current)(current)s0:s0: ifif (a) current

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endend................................................................................................................assignassign w = (current == s3) ? 1 : 0;w = (current == s3) ? 1 : 0;

endmoduleendmodule

Verilog Code forVerilog Code for 110110 DetectorDetector

Assigns aAssigns a toto

utput whenutput when

Machine ReachesMachine Reaches

toto StateState

Outside of theOutside of the

Block:Block:

A combinationalA combinational

circuitcircuit


TestbenchesTestbenches


A SimpleA Simple

TesterTester

TasksTasks

AndAndFunctionsFunctions

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A Simple TesterA Simple Tester


A SimpleA Simple

TesterTester

TasksTasks

AndAnd

FunctionsFunctions

A Simple

Tester




modulemodule Detector110Tester;Detector110Tester;regreg aaaa, clock,, clock, rstrst;;wirewire wwww;;Detector110Detector110 UUT (UUT (aaaa, clock,, clock, rstrst,,wwww););

initial begininitial beginaaaa = 0; clock = 0;= 0; clock = 0; rstrst = 1;= 1;

endendinitial repeatinitial repeat (44) #7 clock = ~clock;(44) #7 clock = ~clock;initial repeatinitial repeat (15) #23(15) #23 aaaa = ~= ~aaaa;;initial begininitial begin

#31#31 rstrst = 1;= 1;#23#23 rstrst = 0;= 0;

endendalwaysalways @(@(wwww)) ifif ((wwww == 1)== 1)

$display$display ("A 1 was detected on w at time = %t",("A 1 was detected on w at time = %t", $time$time););endmoduleendmodule

Testbench forTestbench for

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modulemodule Detector110Tester;Detector110Tester;regreg aaaa, clock,, clock, rstrst;;

wirewire wwww;;Detector110Detector110 UUT (UUT (aaaa, clock,, clock, rstrst,,wwww););....................................................................................................


Begins withBegins withthethe

keywordkeywordUnlike otherUnlike other

descriptionsdescriptions

doesndoesnt have inputt have input

or output portsor output ports

Inputs are Declared asInputs are Declared as

The Instantiation ofThe Instantiation of

ModuleModule

Outputs areOutputs are

declared asdeclared as



....................................................

....................................................initial begininitial begin

aaaa = 0; clock = 0;= 0; clock = 0; rstrst = 1;= 1;endendinitial repeatinitial repeat (44) #7 clock = ~clock;(44) #7 clock = ~clock;initial repeatinitial repeat (15) #23(15) #23 aaaa = ~= ~aaaa;;initial begininitial begin

#31#31 rstrst = 1;= 1;#23#23 rstrst = 0;= 0;

endend


statementstatement

drives test valuesdrives test values

into the variablesinto the variablesconnected to theconnected to the

inputs.inputs.AnAn statement: Astatement: A

sequential statement thatsequential statement that

runs once and stopsruns once and stops

when it reaches its lastwhen it reaches its last

statementstatement

All Initial BlocksAll Initial Blocks

Start at Time 0 andStart at Time 0 and

Run ConcurrentlyRun Concurrently

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....................................................

....................................................initial begininitial begin

aaaa = 0; clock = 0;= 0; clock = 0; rstrst = 1;= 1;endendinitial repeatinitial repeat (44) #7 clock = ~clock;(44) #7 clock = ~clock;initial repeatinitial repeat (15) #23(15) #23 aaaa = ~= ~aaaa;;initial begininitial begin

#31#31 rstrst = 1;= 1;#23#23 rstrst = 0;= 0;

endend Testbench forTestbench for

For InitializingFor Initializing

the Input Signalsthe Input Signals

Repeats 44 times ofRepeats 44 times of

complementing thecomplementing the

input with 7nsinput with 7ns

delay, generates adelay, generates a

periodic signalperiodic signal

onon

SignalSignal is alsois also

assigned a periodicassigned a periodic

signal, with asignal, with a

different frequencydifferent frequencyWaits 31 ns beforeWaits 31 ns before

assigningassigning toto



....................................................

....................................................alwaysalways @(@(wwww)) ifif ((wwww == 1)== 1)

$display$display ("A 1 was detected on w at time = %t",("A 1 was detected on w at time = %t",$time$time););

endmoduleendmodule


Reports theReports the

Times at whichTimes at which

thethe VariableVariable

becomesbecomes

BlockBlock

Wakes up whenWakes up when

ChangesChanges

This Note Will AppearThis Note Will Appear

in the Simulationin the SimulationEnvironmentEnvironmentss

Window:Window: ConsoleConsole oror

TranscriptTranscript

A VerilogA Verilog

System TaskSystem Task

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Tasks And FunctionsTasks And Functions


A SimpleA Simple

TesterTester

TasksTasks

AndAnd

FunctionsFunctions

TasksAnd

Functions


Tasks And FunctionsTasks And Functions

VerilogVerilogTasks and Functions:Tasks and Functions:

System tasks for Input, Output, Display, and Timing ChecksSystem tasks for Input, Output, Display, and Timing Checks

User defined tasks and functionsUser defined tasks and functions

Tasks:Tasks:

Can represent a sub module within aCan represent a sub module within aVerilogVerilog modulemodule

Begins with aBegins with a tasktaskkeywordkeyword

Its body can only consist of sequential statements likeIts body can only consist of sequential statements like if-elseif-else andand

casecase

Functions:Functions:

Can be used for corresponding to hardware entitiesCan be used for corresponding to hardware entities

May be used for writing structured codesMay be used for writing structured codes

Applications: Representation of Boolean functions, data and codeApplications: Representation of Boolean functions, data and code

conversion, and input and output formattingconversion, and input and output formatting

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Funky parallelismFunky parallelism

Hardware is inherently parallelHardware is inherently parallel

FPGA = Fine-grained massively parallel computerFPGA = Fine-grained massively parallel computer

VerilogVerilog = Funky parallel programming language= Funky parallel programming language

CSE 467 Verilog Digital System Design 78

VerilogVerilog tips and trapstips and traps

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Constants: 32 bits, decimalConstants: 32 bits, decimal

wire [7:0]wire [7:0] foofoo = 127; // synthesis warning!= 127; // synthesis warning!

wire [7:0]wire [7:0] foofoo = 8= 8d127;d127;

wire [7:0]wire [7:0] foofoo = 8= 8b11111111;b11111111;

wire [7:0]wire [7:0] foofoo = 8= 8hff;hff;

wire [7:0]wire [7:0] foofoo = 8= 8hFF;hFF;

watch out: 1010 looks like 4watch out: 1010 looks like 4b1010!b1010!


TruncationTruncation wire [7:0] a = 8wire [7:0] a = 8hAB;hAB;

wire b; // oops! forgot widthwire b; // oops! forgot width

wire [7:0] c;wire [7:0] c;

assign b = a; // synthesis warning if lucky.assign b = a; // synthesis warning if lucky.

assign c = a;assign c = a;

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reg vsreg vs. wire. wire

wire f;wire f; regregg, h;g, h;

assign f = a & b;assign f = a & b;

always @(always @(posedge clkposedge clk))

g

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(blocking)(blocking) ==vsvs.

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CSE 467 85Verilog Digital System Design85

VerilogVerilog Stratified Event Queue [2]Stratified Event Queue [2]

within a block,blocking

assignments,are in order


Incomplete sensitivity listsIncomplete sensitivity lists always @(a or b) // italways @(a or b) // its or, not ||s or, not ||

f = a & b;f = a & b;

always @(a)always @(a)

f = a & b;f = a & b;

alwaysalways

f = a & b;f = a & b; Just use always@(*) for combinational logicJust use always@(*) for combinational logic

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always @(posedge CLK)begin

temp = B;B = A;

A = temp;end


A

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The following code executes incorrectlyThe following code executes incorrectly

One block executes firstOne block executes first

Loses previous value of variableLoses previous value of variable

Non-blocking assignment fixes thisNon-blocking assignment fixes this

Both blocks are scheduled byBoth blocks are scheduled byposedgeposedge CLKCLK


A = B;end


B = A;end

always @(posedge CLK)beginA

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04 RTL Design