Digital PWM IC Control Technology and Issues

Prof. Seth R. Sanders (sanders@eecs.berkeley.edu)

Angel V. Peterchev

Jinwen Xiao

Jianhui Zhang

EECS DepartmentUniversity of California, Berkeley

2

Digital Control Advantages

� implement advanced control schemes

� multi-mode control (high/low power modes)

� adaptive algorithms

� spread-spectrum switching for EMI reduction

� flexibility and programmability

� integrate supervisory functions - fault detection, management, and reporting

� communicate with other digital devices - voltage scaling

� immunity to analog component variations and noise

� largely automated digital design flow

3

Io

Digitally-Controlled Buck Converter

Vref

digital PWM controller power train load

Vx

DT

Vin

0

Vx Vout = DVin

Vd discrete duty ratio

T

ADC PID DPWM

VinVd

∆Vadc ∆Vdpwm

quantizers

L

C

4

Quantization Resolution Issues

� Microprocessor VRM example

11 bits5 mV1 V12 V

Ndpwm∆VdpwmVoutVin

� IC Digital PWM (DPWM) implementation with fsw = 1 MHz

requires

� 211 x 1 MHz = 2 GHz clk in counter-comp. scheme

� 211 = 2048 stages in a ring-oscillator-mux scheme

� Analogous requirement on A/D sampling process

5

Limit Cycling

DPWM levels

0 error bin

-1 LSB error bin

1 LSB error bin

transient

Vo

ADC levels

Resolution (DPWM) < Resolution (ADC)

� Possible limit cycling in steady state at freq. < fsw

� Hard to predict amplitude and frequency

� Output noise, EMI

6

Limit Cycling Avoided

� Resolution (DPWM) > Resolution (ADC)

� Use integral term in control law

DPWM levels ADC levels

0 error bin

-1 LSB error bin

1 LSB error bin

transient

Vo

7

No-Limit-Cycle Conditions

1. Resolution (DPWM) > Resolution (ADC)

2. Integral control is used

3. Nyquist stability criterion satisfied (quantization modeled with describing function)

8

Digital Dither (2-bit)

9

Experimental ExampleVo

(V)

Vin = 5 V, Vref = 1.5 V, fsw = 250 kHz

time (ms)

Ndpwm = 7 bit hardware

Nadc = 9 bit

time (ms)

Ndpwm = 7 bit + 3 bit dither

Nadc = 9 bit

10

CMOS Hardware Ckt Cells: (1) DPWM

• Ring-MUX scheme• 5-bit DPWM hardware + 5-bit digital dither• 1 µA at 600 kHz PFM sampling frequency• 0.015 sq. mm in 0.25 micron CMOS

32-tap Differential Ring

5-bit MUX5

VDDIbias

D

Ts

DTs

PWM

11

(2) Ring-ADC Architecture

Counter

Counter

Counter

Counter

Σ

Σ

Analog Block

Digital Block

De

VDD

VSS

Vref

M

M

f1 f2

Vo

• ∆V � ∆I � ∆f � De

• Windowed quantization range

• Insensitive to switching noise

• Digital block synthesizable

• Automatic monotonicity

• Wide Vo operating range

• 16 mV/step, 80 mV window, 0.15mm2 in 0.25 µm CMOS

12

Application Example: Handset Power Management

Io

Ctrl (PWM)

Ctrl (PFM)

C

Vx LVin: 5.5-2.8 V Vo

ControllerVref

Battery Cellular phone chip set

Io: 0- 400 mABuck converter system Vo: 1.0-1.8 V, tolerance 2-3%

Ctrl

13

Dual-mode System DiagramVin

Vref

Vo

VxLogic

PID Digitaldither Ring

osc.

MUX

Ring ADC

De

D

Comparator

GNDMODE

PFM control DPWM

PWM control

SimplfiedPower train

C

L Vo

Buck converter IC

system clock

• Dual mode controller• Digital Pulse Width Modulator (DPWM) • Power switches, drivers• On-chip power management – input voltage to 5.5 V

14

PFM Mode Diagram & Switching Behavior

• Converter discontinuous conduction• Fixed on-time control• Zero-DC-bias comparator for low power

DPFM

0

DPWMSample

Vx

C

L Vo

VinVref

Sample

Vo

Vref

Ctrl

Ctrl

15

Load Transient ResponseVin= 3.2 V, Vo= 1.2 V.Load step 100 mA 150mA

50mAIo

Vo, 20mV/div, AC coupled 12mV

Vo, 20mV/div, AC coupled

Io

100mA

0.1mA

PWM Mode, 500µs/div

PFM Mode, 10µs/div

• PWM mode: both steady-state voltages in ADC zero-error bin

• PFM mode: voltage ripple <25mV @100 mA

16

0.50.550.6

0.650.7

0.750.8

0.850.9

0.951

0.1 1 10 100 1000Output current Io (mA)

Effi

cien

cy

PWMPFM

Efficiency: PWM and PFM ModesVin= 4.5 V Vo= 1.5 V

• PWM efficiency drops off at low Io• PFM efficiency high at low Io• Composite efficiency high over wide Io range

17

Chip MicrographActive area 2 mm2

1.6

mm

2.6 mm

Controller

Powertrain

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Advanced Functions: Multi-mode & On-Line Optimizing Control

Ton

Teff

control switch

synchronous rectifier

Discontinuous Conduction Mode Continuous

PID control

adaptive power-minimization control

control switch

synchronous rectifier

variable switching frequency

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Discontinuous Conduction Mode at Light Load

�Efficient operation over wide load range critical to battery life in mobile applications

�Turn synch. rectifier off when inductor current crosses zero

� Higher efficiency due to reduced rms current

control switch

inductor current

avg load current

0

synch. rectifier

20

Synch. Rect. Turn-off Timing

21

Synch. Rect. Turn-off Timing (light load data range)

local minimum due to resonant switching

synch. rect. on

force synch. rect. off

cont. cond. mode

discont. cond. mode

sync

h. r

ect.

off

22

Synch. Rect. Turn-on Timing

23

Synchronous Rectifier Timing Adaptation

� Synch. rect. timing as function of load current is adjusted to minimize power loss

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Summary• See www-power.eecs.berkeley.edu for pubs and

more details;

• Fundamental issues addressed: quantization resolution, sampling, limit cycling

• Low-power, robust CMOS analog-digital interface

• More than 3-fold quiescent current reduction for portable applications

• Power management function integrated in low-voltage CMOS process

• Enables tunable, programmable compensator, direct communication with digital systems, etc