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CONTENTS... 2000 DP-0X Chassis Projection Television Information
INSTRUCTOR… Alvie Rodgers C.E.T. (Norcross, GA.)
JANUARY 19, 2001 Training Materials Prepared by: ALVIE RODGERS C.E.T.
2000 MODEL RELEASE
MODEL CHASSIS 53FDX01B DP-05 43FDX01B DP-05F 53SDX01B DP-06 61SDX01B DP-06
DIGITAL
53SWX01W DP-07 61SWX01W DP-07 53SDX88BA DP86V 60SDX88BA DP86V
DP-0X CHASSIS TABLE OF CONTENTS SECTION (1) GENERAL INFORMATION: • DP-0X FUNCTION Reference Chart --------------------------------------------------------------------------------- 01-01 • PTV CHASSIS to CHASSIS Cross Reference Chart -------------------------------------------------------------- 01-03 • PTV CHASSIS to CHASSIS Cross Reference Chart -------------------------------------------------------------- 01-04 • CTV MODEL to CHASSIS Cross Reference Chart --------------------------------------------------------------- 01-05 • CTV CHASSIS to MODEL Cross Reference Chart --------------------------------------------------------------- 01-06 • DP-06 and DP-07 REAR PANEL ------------------------------------------------------------------------------------- 01-07 • DP-05 and DP-05F REAR PANEL ----------------------------------------------------------------------------------- 01-08 SECTION (2) MICROPROCESSOR INFORMATION: • Microprocessor PORT DESCRIPTION Explanation ------------------------------------------------------------ 02-01 • Microprocessor PORT DESCRIPTION Circuit Diagram -------------------------------------------------------- 02-10 • DP-05 and 05F Microprocessor PORT DESCRIPTION Explanation ------------------------------------- 02-11 • DP-05 and 05F Microprocessor PORT DESCRIPTION Circuit Diagram --------------------------------- 02-12 • Microprocessor DATA COMMUNICATION Explanation ----------------------------------------------------- 02-13 • Microprocessor DATA COMMUNICATION Circuit Diagram ------------------------------------------------ 02-18 • DP-05 and 05F Microprocessor DATA COMMUNICATION Explanation ------------------------------ 02-19 • DP-05 and 05F Microprocessor DATA COMMUNICATION Circuit Diagram ------------------------- 02-20 • On Screen Display OSD Signal Path Explanation ------------------------------------------------------------------ 02-21 • On Screen Display OSD Signal Path Circuit Diagram ------------------------------------------------------------- 02-23 • Audio and Video MUTE Explanation -------------------------------------------------------------------------------- 02-24 • Audio and Video MUTE Circuit Diagram --------------------------------------------------------------------------- 02-26 • DP-05 and 05F Audio and Video MUTE Explanation --------------------------------------------------------- 02-27 • DP-05 and 05F Audio and Video MUTE Circuit Diagram ---------------------------------------------------- 02-28 • Mute Circuit SURROUND PWB Explanation --------------------------------------------------------------------- 02-29 • Mute Circuit SURROUND PWB Circuit Diagram ----------------------------------------------------------------- 02-30 • DP-05 and 05F Mute Circuit SURROUND PWB Explanation ---------------------------------------------- 02-31 • DP-05 and 05F Mute Circuit SURROUND PWB Circuit Diagram ------------------------------------------ 02-32 • MEMORY INITIALIZATION Explanation ---------------------------------------------------------------------- 02-33 • EEPROM I2C AVERAGE DATA VALUES --------------------------------------------------------------------- 02-34 • DAC 1 and 2 Pin Function Explanation ---------------------------------------------------------------------------- 02-37 SECTION (3) POWER SUPPLY DIAGRAMS: • POWER ON/OFF Explanation --------------------------------------------------------------------------------------- 03-01 • POWER ON/OFF Circuit Diagram ----------------------------------------------------------------------------------- 03-04 • Green and Red LED Used for Visual Trouble Shooting Explanation ----------------------------------------- 03-05 • Green and Red LED Used for Visual Trouble Shooting ---------------------------------------------------------- 03-08 • DP-05 and 05F Green and Red LED Used for Visual Trouble Shooting Explanation ------------------ 03-09 • DP-05 and 05F Green and Red LED Used for Visual Trouble Shooting ----------------------------------- 03-10 • Low Voltage Power Supply SHUT DOWN Explanation --------------------------------------------------------- 03-11 • Low Voltage Power Supply SHUT DOWN Diagram ------------------------------------------------------------- 03-15 • High Voltage Green and Red LED Used for Visual Trouble Shooting Explanation ------------------------- 03-16 • High Voltage Green and Red LED Used for Visual Trouble Shooting ----------------------------------------- 03-18 • High Voltage Power Supply SHUT DOWN Explanation -------------------------------------------------------- 03-19 • High Voltage Power Supply SHUT DOWN Diagram ------------------------------------------------------------ 03-24
Continued on Next Page
January 19, 2000 Table of Contents Page 1 of 3
DP-0X CHASSIS TABLE OF CONTENTS SECTION (4) VIDEO CIRCUIT INFORMATION: • Model VIDEO Signal Circuit Description ----------------------------------------------------------- 04-01 • Model VIDEO Signal Circuit -------------------------------------------------------------------------- 04-02 • COMPONENT Circuit Description ------------------------------------------------------------------ 04-03 • COMPONENT Circuit Diagram ---------------------------------------------------------------------- 04-04 • DP-05 and 05F COMPONENT Circuit Description ---------------------------------------------- 04-05 • DP-05 and 05F COMPONENT Circuit Diagram -------------------------------------------------- 04-06 • CHROMA After Flex Converter Circuit Description ---------------------------------------------- 04-07 • CHROMA PHASE ROTATION Circuit Description -------------------------------------------- 04-08 • CHROMA After Flex Converter Circuit Diagram -------------------------------------------------- 04-09 • SYNC Circuit Description ----------------------------------------------------------------------------- 04-10 • SYNC Circuit Diagram --------------------------------------------------------------------------------- 04-11 • COMPONENT SYNC SEPARATION Circuit Description ------------------------------------- 04-12 • COMPONENT SYNC SEPARATION Circuit Diagram ---------------------------------------- 04-13 • DP-05 and 05F COMPONENT SYNC SEPARATION Circuit Description ----------------- 04-14 • DP-05 and 05F COMPONENT SYNC SEPARATION Circuit Diagram --------------------- 04-15 • Auto Brightness Limiter ABL Description ---------------------------------------------------------- 04-16 • Auto Brightness Limiter ABL Circuit ---------------------------------------------------------------- 04-17 • Horizontal and Vertical SWEEP LOSS Detection Circuit Description -------------------------- 04-18 • Horizontal and Vertical SWEEP LOSS Detection Circuit ---------------------------------------- 04-19 • Zenith ZP-04 (Using 3-Line Comb Filter Video Signal Path Description ------------------------ 04-20 • Zenith ZP-04 (Using 3-Line Comb Filter Video Signal Path -------------------------------------- 04-21 SECTION (5) AUDIO CIRCUIT INFORMATION: • AUDIO SIGNAL (Main & Terminal) Circuit Description -------------------------------------- 05-01 • AUDIO SIGNAL (Main & Terminal) Circuit Diagram ------------------------------------------ 05-02 • AUDIO SURROUND Circuit Description ---------------------------------------------------------- 05-03 • AUDIO SURROUND Circuit Diagram -------------------------------------------------------------- 05-04 • DP-05 and 05F CHASSIS SURROUND Circuit Description ------------------------------------ 05-05 • DP-05 and 05F CHASSIS SURROUND Circuit Diagram --------------------------------------- 05-06 SECTION (6) DIGITAL CONVERGENCE CIRCUIT INFORMATION: • DIGITAL CONVERGENCE Interface Circuit Description -------------------------------------- 06-01 • DIGITAL CONVERGENCE Interface Circuit Diagram ------------------------------------------ 06-05 • CLU-572 TSI Remote Control used on DP-05, DP-05, DP-06 and DP-07 Chassis ------------ 06-06 • CLU-573 TSI Remote Control used on AP-93R Chassis ------------------------------------------ 06-07 • CLU-614 MP Remote Control used on DP-85V Chassis ------------------------------------------ 06-08 • CLU-436 UII Remote Control used on AP-91 and AP-01 Chassis ------------------------------- 06-09 • DP-05 and 05F DIGITAL CONVERGENCE Interface Circuit Description ------------------ 06-10 • DP-05 and 05FF DIGITAL CONVERGENCE Interface Circuit Diagram -------------------- 06-11
Continued on Next Page
January 19, 2000 Table of Contents Page 2 of 3
DP-0X CHASSIS TABLE OF CONTENTS SECTION (7) DEFLECTION CIRCUIT: • DEFLECTION POWER SUPPLY Generation Circuit Description --------------------------- 07-01 • DEFLECTION POWER SUPPLY Generation Circuit Diagram ------------------------------ 07-02 • HORIZONTAL DRIVE Circuit Description ------------------------------------------------------- 07-03 • HORIZONTAL DRIVE Circuit Diagram ---------------------------------------------------------- 07-06 SECTION (8) ADJUSTMENTS: • FACTORY RESET PROCEDURE AND CONDITION ------------------------------------------- 08-01 • SIGNAL PWB IDENTIFICATION ------------------------------------------------------------------- 08-03 • DEFLECTION PWB IDENTIFICATION ----------------------------------------------------------- 08-04 • CONTROL PWB IDENTIFICATION ---------------------------------------------------------------- 08-05 • SUB POWER SUPPLY PWB IDENTIFICATION ------------------------------------------------- 08-06 • CRT PWB IDENTIFICATION ------------------------------------------------------------------------ 08-07 • CLOCK SPEED ACCELERATION ------------------------------------------------------------------- 08-08 • HIGH VOLTAGE ADJUSTMENT -------------------------------------------------------------------- 08-09 • HIGH VOLTAGE LIMITER CIRCUIT CHECK ---------------------------------------------------- 08-10 • FLYBACK PROTECTION CIRCUIT CHECK ----------------------------------------------------- 08-11 • SWEEP LOSS DETECTION CIRCUIT CHECK --------------------------------------------------- 08-12 • POWER SUPPLY VOLTAGE CHECK -------------------------------------------------------------- 08-13 • MAGNET AND YOKE LOCATIONS --------------------------------------------------------------- 08-14 • ADJUSTMENT ORDER ------------------------------------------------------------------------------- 08-15 • PRE HEAT RUN ---------------------------------------------------------------------------------------- 08-16 • CUT OFF ADJUSTMENT ----------------------------------------------------------------------------- 08-17 • PRE-FOCUS ADJUSTMENT ------------------------------------------------------------------------- 08-18 • DCU CROSS HATCH PHASE SETTING ----------------------------------------------------------- 08-19 • HORIZONTAL POSITION (COARSE) ADJUSTMENT ----------------------------------------- 08-20 • RASTER TILT ------------------------------------------------------------------------------------------- 08-21 • BEAM ALIGNMENT ---------------------------------------------------------------------------------- 08-22 • RASTER POSITION [Off-Set for Red and Blue] ---------------------------------------------------- 08-23 • HORIZONTAL AND VERTICAL SIZE ADJUSTMENT ---------------------------------------- 08-24 • BEAM FORM ADJUSTMENT ----------------------------------------------------------------------- 08-26 • LENS FOCUS ADJUSTMENT ----------------------------------------------------------------------- 08-27 • STATIC FOCUS ADJUSTMENT -------------------------------------------------------------------- 08-28 • BLUE DEFOCUS ADJUSTMENT ------------------------------------------------------------------- 08-29 • WHITE BALANCE ADJUSTMENT ----------------------------------------------------------------- 08-30 • SUB BRIGHTNESS ADJUSTMENT ---------------------------------------------------------------- 08-31 • HORIZONTAL POSITION (FINE) ADJUSTMENT ----------------------------------------------- 08-32 • OVERLAY DIMENSIONS ---------------------------------------------------------------------------- 08-33 • STOPPING POSITIONS IN THE 3X3, 5X7 and 13X9 MODES --------------------------------- 08-38 • DIGITAL CONVERGENCE -------------------------------------------------------------------------- 08-40 SECTION (9) KEY COMPONENTS: • DP-06 KEY COMPONENTS ------------------------------------------------------------------------ 09-01
January 19, 2000 Table of Contents Page 3 of 3
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Page 01 -01
2000 Model Functions (1 of 2)
MO
DEL
No
53SD
X88B
A53
SDX0
1B53
FDX0
1B43
FDX0
1B53
SWX0
1WIQ
50H
95W
IQ50
H94
W50
NH
P40
060
SDX8
8BA
61SD
X01B
61SW
X01W
IQ60
H95
WIQ
60H
94W
60N
HP
400
CH
ASS
ISD
P86V
DP0
6D
P05
DP0
5FD
P07
ZP04
(OEM
)ZP
05 (O
EM)
SP05
(OE
M)
Aspe
ct4X
34X
34X
34X
316
X 9
4X3
4X3
4X3
List
enin
g M
odS
tand
ard
No
Yes
No
No
Yes
No
No
No
List
enin
g M
odN
ight
No
Yes
No
No
Yes
No
No
No
List
enin
g M
odM
axim
umN
oY
esN
oN
oY
esN
oN
oN
o
Spk
Set
up F
ront
L-R
Inte
rnal
No
Yes
No
No
Yes
No
No
No
wE
xt A
mp
wLa
rge
No
Yes
No
No
Yes
No
No
No
wE
xt A
mp
wS
mal
lN
oY
esN
oN
oY
esN
oN
oN
o
Sur
roun
dN
oY
esN
oN
oY
esN
oN
oN
o
Sub
Woo
fer
No
Yes
No
No
Yes
No
No
No
Dig
Inpu
t C
oaxi
alV
1/V
2N
oY
esN
oN
oY
esN
oN
oN
o
Opt
ical
V1/
V2
No
Yes
No
No
Yes
No
No
No
SR
S M
ode
On-
Off
No
No
Yes
Yes
No
Yes
Yes
Yes
Gra
phic
EQ
7 b
and
Yes
No
No
No
No
No
No
No
Wire
less
Sou
nd S
yste
mM
ainP
inP
Rea
rY
esN
oN
oN
oN
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Wire
less
Sou
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yste
m
Mai
nPin
PN
oN
oN
oN
oN
oN
oN
oN
o
Sub
Woo
fer S
yste
m
Sub
Vol
ume
Yes
Yes
No
No
Yes
No
No
No
INFO
RM
ATIO
NS
peci
al E
vent
Rem
inde
rY
esN
oN
oN
oN
oN
oN
oN
o
Cal
enda
rY
esN
oN
oN
oN
oN
oN
oN
o
Aut
o H
elp
No
No
No
No
No
No
No
No
GU
IDE+
PR
OG
RAM
GU
IDE
WIT
H IR
BLA
STER
OTH
ERS
On
TV
Adv
ance
d A
uto
Dem
o H
old
Pow
erY
esY
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esY
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On
TV
Men
u B
utto
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TV
Cur
sor K
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Pan
elY
esY
esY
esY
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On
Rem
ote
Sle
ep T
imer
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
On
Rem
ote
Hel
pY
esY
esY
esY
esY
esY
esY
esY
esO
n R
emot
e C
omm
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al S
kip
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
On
Pin
P
Sin
gle
Pin
P S
ize
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
On
Pin
P
Mul
ti P
inP
7 P
ixY
esN
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Pin
PM
ulti
Pin
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No
No
No
No
No
No
No
No
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Pin
P
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ti P
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3 P
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nY
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Pin
P
Stro
be A
ctio
nY
es (7
Pix
)Y
es (3
Pix
)Y
es (3
Pix
)Y
es (3
Pix
)Y
es (3
Pix
)Y
es (3
Pix
)Y
es (3
Pix
)Y
es (3
Pix
)
On
Pin
P
Var
iabl
e po
sitio
n on
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gle
Pin
PN
oN
oN
oN
oN
oN
oN
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Set
Up
Plu
g an
d P
lay
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y S
et U
p w
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lock
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SN
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ower
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ume
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
V C
hip
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SP
Mat
rixN
oN
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oN
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oN
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t Mut
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Page 01 -02
2000 Model Functions (2 of 2) M
OD
EL N
o53
SDX8
8BA
53SD
X01B
53FD
X01B
43FD
X01B
53SW
X01W
IQ50
H95
WIQ
50H
94W
50N
HP4
0060
SDX8
8BA
61SD
X01B
61SW
X01W
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H95
WIQ
60H
94W
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HP4
00C
HAS
SIS
DP8
6VD
P06
DP0
5D
P05F
DP0
7ZP
04 (O
EM)
ZP05
(OEM
)SP
05 (O
EM)
CO
NTR
OL
PA
NE
L2
Pie
ceY
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esY
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esN
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es1
Pie
ceN
oN
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oFR
ON
T P
AN
EL
Pow
erY
esY
esY
esY
esY
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esY
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esC
H U
pC
urso
r Up
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
CH
Dow
nC
urso
r Dow
nY
esY
esY
esY
esY
esY
esY
esY
esV
ol U
pC
urso
r Rig
htY
esY
esY
esY
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esY
esY
esY
esV
ol D
own
Cur
sor L
eft
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Inpu
tE
xit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Men
uY
esY
esY
esY
esY
esY
esY
esY
esM
agic
Foc
us D
ig A
rray
Sta
ticY
es M
.F.
Yes
M.F
.Y
es (S
T)Y
es (S
T)Y
es M
.F.
Yes
(ST)
Yes
(ST)
Yes
(ST)
IR R
ecei
ver
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Dim
mer
Sen
sor
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Inpu
t 3S
Inpu
tY
esY
esY
esY
esY
esY
esY
esY
esV
Inpu
tY
esY
esY
esY
esY
esY
esY
esY
esL/
Mon
o In
put
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
R In
put
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
RE
AR
PA
NE
LA
nt A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Ant
BY
esY
esY
esY
esY
esY
esY
esY
es T
o C
onve
rter
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Inpu
t 1
Com
pone
ntN
oY
esY
esY
esY
esY
esY
esY
esS
Inpu
tY
esY
esY
esY
esY
esY
esY
esY
esV
Inpu
tY
esY
esY
esY
esY
esY
esY
esY
esL/
Mon
o In
put
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
R In
put
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Inpu
t 2C
ompo
nent
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
S In
put
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
V In
put
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
L/M
ono
Inpu
tY
esY
esY
esY
esY
esY
esY
esY
esR
Inpu
tY
esY
esY
esY
esY
esY
esY
esY
esD
ig A
udio
Inpu
t Coa
xial
No
Yes
No
No
Yes
No
No
No
Dig
Aud
io In
put O
ptic
alN
oY
esN
oN
oY
esN
oN
oN
oM
onito
r Out
SY
esY
esY
esY
esY
esY
esY
esY
esV
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LY
esY
esY
esY
esY
esY
esY
esY
esR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Aud
io H
i-Fi O
utL
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
RY
esY
esY
esY
esY
esY
esY
esY
esW
irele
ss O
utL
Yes
No
No
No
No
No
No
No
RY
esN
oN
oN
oN
oN
oN
oN
oS
ub W
oofe
r Out
Yes
Yes
No
No
Yes
No
No
No
Rea
r Spk
Out
LY
esY
esN
oN
oY
esN
oN
oN
oR
Yes
Yes
No
No
Yes
No
No
No
PTV MODEL TO CHASSIS CROSS REFERENCE CHART
ModelNo Chassis ModelNo Chassis ModelNo Chassis43FDX01B DP05F 50SX6P AP43B 60SX11K AP53D43GX01B AP02 50UX10B AP23 60SX11KA AP53DP46EX2B/K AP22 50UX11K AP23 60SX12B AP63B46EX3B/BS AP32 50UX14B AP33 60SX13K AP63B46EX4K/KS AP32 50UX15K AP33 60SX1K AP1446GX01B AP92R 50UX18B AP43 60SX2K AP2446UX10BA AP13 50UX19K AP43 60SX3B AP3446UX10BF AP23 50UX22B AP53 60SX4K AP3446UX11KA AP13 50UX22BA AP53P 60SX8B AP43B46UX11KF AP23 50UX23K AP53 60SX9K AP43B46UX12B AP33 50UX23KA AP53P 60UX54B AP7346UX13K AP33 50UX26B AP63 60UX55K AP7346UX16B AP43 50UX27K AP63 60UX57B AP83R46UX17K AP43 50UX52B AP73 60UX58B AP8346UX20B AP53 50UX53K AP73 60UX58K AP8346UX20BA AP53P 50UX57B AP83R 60UX59B AP9346UX21K AP53 50UX58B AP83 61DMX01W NEW46UX21KA AP53P 50UX58K AP83 61HDX01W DP8546UX24B AP63 50UX59B AP93 61HDX98B DP8546UX25K AP63 50UX7B/K/W AP13 61SBX01B AP93R46UX50B AP73 50UX8D/W AP13 61SBX59B AP9346UX51K AP73 52LDX99B DL1 61SDX01B DP0646UX7B/K AP13 53FDX01B DP05 61SWX01W DP0750CX01B AP90R 53SBX01B AP93R 70SBX74B AP7450CX29B AP90 53SBX59B AP93 CT4271 VP650ES1B/K AP31 53SDX01B DP06 CT4275 VP6X250EX01B AP91R 53SDX88BA DP86V CT4520K VP7X250EX10B AP32 53SDX89B DP86 CT4521K VP7X250EX11BV AP32 53SWX01W DP07 CT4525 VP250EX12B AP32F 55EX15K AP52 CT4531 VP250EX12BA AP32V 55EX1K AP12 CT4532 VP250EX12BX AP52 55EX7K AP32 CT4533K VP9X150EX13K AP32F 55EX9K AP32 CT4534 VP350EX13KA AP32V 55FX20B AP62 CT4535K VP9X150EX13KX AP52 55FX48B AP82 CT4536 VP350EX14BV AP52 55FX49B AP92 CT4546 VP350EX16B AP52 55UX58B AP83P CT4555 VP350EX20B AP52 55UX58BA AP83 CT4580K VP7X250EX2K AP22 55UX59B AP93 CT5033K VP9X150EX39B AP91 60CX01B AP90R CT5071 VP650EX6K AP32 60CX29B AP90 CT5072 VP650EX8K AP32 60EX01B AP91R CT5075 VP6X250FX18B AP62 60EX28B AP52P CT5080 VP7X250FX19K AP62 60EX38B AP52P CT5081K VP7X250FX30B AP62 60EX39B AP91 CT5522K VP7X250FX48B AP62P 60FX32B AP62 CT5533K VP9X150FX49B AP92 60GX49B AP92 CT5582K VP7X250GX10B AP92R 60SBX72B AP74 CU4600K VP8X250GX20B AP92R 60SBX78B AP84 CU4601K VP8X250GX49B AP92 60SDX88B DP86 CU5000K VP8X250SBX70B AP74 60SDX88BA DP86V CU5001B VP8X250SBX78B AP84 60SX10B AP53D CU5002K VP8X250SX5P AP33B 60SX10BA AP53DP CU5003D VP8X2
PAGE 01-03
PTV CHASSIS TO MODEL CROSS REFERENCE CHART
Chassis ModelNo Chassis ModelNo Chassis ModelNoAP02 43GX01B AP53 50UX23K AP92R 46GX01BAP12 55EX1K AP53D 60SX10B AP92R 50GX10BAP13 46UX10BA AP53D 60SX11K AP92R 50GX20BAP13 46UX11KA AP53DP 60SX10BA AP93 50UX59BAP13 46UX7B/K AP53DP 60SX11KA AP93 53SBX59BAP13 50UX7B/K/W AP53P 46UX20BA AP93 55UX59BAP13 50UX8D/W AP53P 46UX21KA AP93 60UX59BAP14 60SX1K AP53P 50UX22BA AP93 61SBX59BAP22 46EX2B/K AP53P 50UX23KA AP93R 53SBX01BAP22 50EX2K AP62 50FX18B AP93R 61SBX01BAP23 46UX10BF AP62 50FX19K DL1 52LDX99BAP23 46UX11KF AP62 50FX30B DP05F 43FDX01BAP23 50UX10B AP62 55FX20B DP05 53FDX01BAP23 50UX11K AP62 60FX32B DP06 53SDX01BAP24 60SX2K AP62P 50FX48B DP06 61SDX01BAP31 50ES1B/K AP63 46UX24B DP07 53SWX01WAP32 46EX3B/BS AP63 46UX25K DP07 61SWX01WAP32 46EX4K/KS AP63 50UX26B DP85 61HDX01WAP32 50EX10B AP63 50UX27K DP85 61HDX98BAP32 50EX11BV AP63B 60SX12B DP86 53SDX89BAP32 50EX6K AP63B 60SX13K DP86 60SDX88BAP32 50EX8K AP73 46UX50B DP86V 53SDX88BAAP32 55EX7K AP73 46UX51K DP86V 60SDX88BAAP32 55EX9K AP73 50UX52B NEW 61DMX01WAP32F 50EX12B AP73 50UX53K VP2 CT4525AP32F 50EX13K AP73 60UX54B VP2 CT4531AP32V 50EX12BA AP73 60UX55K VP2 CT4532AP32V 50EX13KA AP74 50SBX70B VP3 CT4534AP33 46UX12B AP74 60SBX72B VP3 CT4536AP33 46UX13K AP74 70SBX74B VP3 CT4546AP33 50UX14B AP82 55FX48B VP3 CT4555AP33 50UX15K AP83 50UX58B VP6 CT4271AP33B 50SX5P AP83 50UX58K VP6 CT5071AP34 60SX3B AP83 55UX58BA VP6 CT5072AP34 60SX4K AP83 60UX58B VP6X2 CT4275AP43 46UX16B AP83 60UX58K VP6X2 CT5075AP43 46UX17K AP83P 55UX58B VP7X2 CT4520KAP43 50UX18B AP83R 50UX57B VP7X2 CT4521KAP43 50UX19K AP83R 60UX57B VP7X2 CT4580KAP43B 50SX6P AP84 50SBX78B VP7X2 CT5080AP43B 60SX8B AP84 60SBX78B VP7X2 CT5081KAP43B 60SX9K AP90 50CX29B VP7X2 CT5522KAP52 50EX12BX AP90 60CX29B VP7X2 CT5582KAP52 50EX13KX AP90R 50CX01B VP8X2 CU4600KAP52 50EX14BV AP90R 60CX01B VP8X2 CU4601KAP52 50EX16B AP91 50EX39B VP8X2 CU5000KAP52 50EX20B AP91 60EX39B VP8X2 CU5001BAP52 55EX15K AP91R 50EX01B VP8X2 CU5002KAP52P 60EX28B AP91R 60EX01B VP8X2 CU5003DAP52P 60EX38B AP92 50FX49B VP9X1 CT4533KAP53 46UX20B AP92 50GX49B VP9X1 CT4535KAP53 46UX21K AP92 55FX49B VP9X1 CT5033KAP53 50UX22B AP92 60GX49B VP9X1 CT5533K
PAGE 01-04
CTV MODEL TO CHASSIS CROSS REFERENCE CHART
ModelNo Chassis ModelNo Chassis ModelNo Chassis13SA10B OEM 31KX41K M1CLXU 36SX78B M8LXU13VR12B OEM 31KX6B G9LXU1M 36TX53K M7LXU19VR13B OEM 31KX7B G9LXU1M 36UX01B M1020CX20B PANA 31KX9K G9LXU1M 36UX52B M7LXU20MA1B FH92XS-1 31UX5B A3LXU 36UX58B M7LXU220SA2B M2XU 32CX10B A3LXU2 36UX59B M9LXU20SA3B M3L 32CX11B A3LXU3 CT1386W/B G720SA4B M2XU 32CX12B A3LXU4 CT2075W G7NU20SA5B M3XU 32CX32B A3LXU3 CT2076W/B G7NU27AX0B M1LXU 32CX33B A3LXU3 CT2077W/B G7XU27AX1B M1LXU 32CX38B A3LXU3 CT2079B G7XU27AX2B M1LXU 32CX39B M9LXU CT3170 G7LXU27AX3B M1CLXU 32CX39B M9LXU CT3175 G7LXU27AX4B M1CLXU 32CX7B A3LXU2 CT3190B/K G9LXU27AX5BX M1CLXU 32FX41B-501 M7LXU CT3196B/K G9LXU27CX01B SHARP 32FX48B M7LXU2 CT3198K G9LXU27CX0B M1CLXU 32FX49B M9LXU CT7872B/K G9LXU27CX15B M3LXU 32GX01B M10 CT7880 G7NU27CX1B M3LXU 32TX78B A3LXU3 CT7881B/K G9LXU27CX21B M3LXU2 32TX79K A3LXU3 CT7882B/K G9LXU27CX22B Zenith GX 32UX01B M10 CT7883B A1LXU27CX25B M3LXU 32UX51B M7LXU CT7892B/K G9LXU27CX28B NA6L Pan 32UX58B M7LXU2 CT7893B A1LXU27CX29B OEM 32UX59B M9LXU CT7894B A1LXU27CX31B Zenith GX 32UX8B A4LXU CT7896B G9LXU27CX3B A3LXU 35CX30B A3LXU3 CT7897B G9LXU27CX4B A3LXU 35CX45B A3LXU4 CT7898B G9LXU27CX5B M3LXU 35TX10B A3LXU CT7899K G9LXU27CX6B M3LXU 35TX20B A3LXU227CX75B M3LXU2 35TX30B A2LXU27CX7B M3LXU2 35TX50B A2LXU27DX5B A1LXU 35TX59K A2LXU27FX48B NA6D Pan 35TX69K A2LXU27FX90BC A2LXU 35TX79K A4LXU27GX01B PANA 35TX88B A3LXU327MM20B PA-1 35TX89K A3LXU327MMV30B PA-2 35UX60B A2LXU27UX01B PANA 35UX70B A4LXU27UX5B A3LXU 35UX70B A4LXUP31CX4B A3LXU 35UX80B A4LXUP31CX5B A3LXU2 1995 35UX85B A6LXU31CX5B A3LXU2 1996 36CX35B M7LXU31CX6B A3LXU2 36FX38B M7LXU231DX10B M1LXU1 36FX42B-501 M7LXU31DX11B M1CLXU 36FX48B M7LXU231DX20B M1LXU1 36FX49B M9LXU31DX21B M1CLXU 36GX01B M1031DX22B M1CLXU 36MMV60B MM131GX31B M1CLXU 36MMV70B MM131KX1B G9LXU1M 36SDX01B MM-1T31KX2B G9LXU1M 36SDX01BR MM-1R31KX39K M1CLXU 36SDX88B MM131KX3K G9LXU1M 36SX72B M8LXU
PAGE 01-05
CTV CHASSIS TO MODEL CROSS REFERENCE CHART
Chassis ModelNo Chassis ModelNo Chassis ModelNoA1LXU CT7893B G9LXU CT3198K M7LXU2 36FX38BA1LXU CT7883B G9LXU CT7896B M8LXU 36SX72BA1LXU 27DX5B G9LXU CT7892B/K M8LXU 36SX78BA1LXU CT7894B G9LXU CT3196B/K M9LXU 36FX49BA2LXU 35TX50B G9LXU CT7881B/K M9LXU 36UX59BA2LXU 35UX60B G9LXU CT7882B/K M9LXU 32CX39BA2LXU 35TX59K G9LXU1M 31KX3K M9LXU 32UX59BA2LXU 35TX30B G9LXU1M 31KX1B M9LXU 32FX49BA2LXU 27FX90BC G9LXU1M 31KX2B M9LXU 32CX39BA2LXU 35TX69K G9LXU1M 31KX6B MM1 36MMV70BA3LXU 27CX3B G9LXU1M 31KX7B MM1 36MMV60BA3LXU 35TX10B G9LXU1M 31KX9K MM1 36SDX88BA3LXU 27UX5B M10 36UX01B MM-1R 36SDX01BRA3LXU 27CX4B M10 32GX01B MM-1T 36SDX01BA3LXU 31CX4B M10 36GX01B NA6D Pan 27FX48BA3LXU 31UX5B M10 32UX01B NA6L Pan 27CX28BA3LXU2 32CX10B M1CLXU 31DX22B OEM 13SA10BA3LXU2 31CX6B M1CLXU 27CX0B OEM 19VR13BA3LXU2 35TX20B M1CLXU 31DX21B OEM 13VR12BA3LXU2 32CX7B M1CLXU 27AX4B OEM 27CX29BA3LXU2 1995 31CX5B M1CLXU 31KX39K PA-1 27MM20BA3LXU2 1996 31CX5B M1CLXU 27AX5BX PA-2 27MMV30BA3LXU3 32TX78B M1CLXU 27AX3B PANA 27UX01BA3LXU3 35TX89K M1CLXU 31DX11B PANA 27GX01BA3LXU3 35TX88B M1CLXU 31GX31B PANA 20CX20BA3LXU3 32TX79K M1CLXU 31KX41K SHARP 27CX01BA3LXU3 32CX38B M1LXU 27AX0B Zenith GX 27CX22BA3LXU3 32CX33B M1LXU 27AX1B Zenith GX 27CX31BA3LXU3 32CX32B M1LXU 27AX2BA3LXU3 32CX11B M1LXU1 31DX20BA3LXU3 35CX30B M1LXU1 31DX10BA3LXU4 35CX45B M2XU 20SA2BA3LXU4 32CX12B M2XU 20SA4BA4LXU 32UX8B M3L 20SA3BA4LXU 35TX79K M3LXU 27CX5BA4LXU 35UX70B M3LXU 27CX25BA4LXUP 35UX80B M3LXU 27CX1BA4LXUP 35UX70B M3LXU 27CX15BA6LXU 35UX85B M3LXU 27CX6BFH92XS-1 20MA1B M3LXU2 27CX75BG7 CT1386W/B M3LXU2 27CX21BG7LXU CT3170 M3LXU2 27CX7BG7LXU CT3175 M3XU 20SA5BG7NU CT2075W M7LXU 36UX52BG7NU CT2076W/B M7LXU 32UX51BG7NU CT7880 M7LXU 32FX41B-501G7XU CT2079B M7LXU 36TX53KG7XU CT2077W/B M7LXU 36FX42B-501G9LXU CT3190B/K M7LXU 36CX35BG9LXU CT7872B/K M7LXU2 32UX58BG9LXU CT7898B M7LXU2 36UX58BG9LXU CT7897B M7LXU2 36FX48BG9LXU CT7899K M7LXU2 32FX48B
PAGE 01-06
REAR PANEL for the53SDX01B, 61SBX01B (DP-06) and 61SWX01W, 53SWX01W (DP-07)
AUDIOTO HI-FI
R L
SUBWOOFER
PAG
E 01-07
ANT A
ToConverter
VIDEO
(MONO)
AUDIO
INPUT 1 INPUT 2
L
R
S-VIDEO
MONITOROUT
Y
PBCB
PRCR
ANT B
+
REAR SPEAKER8 ONLY
-R
+
-L
OPTICALINPUT
COAXIALINPUT
VIDEO
(MONO)
AUDIOR
S-VIDEO
VIDEO
(MONO)
AUDIO
L
R
S-VIDEO
Y
PBCB
PRCR
STOPCONNECT ONLY 8 Ohm SPEAKERSDO NOT SHORT CIRCUIT
THESE TERMINALS.(such damage is NOT COVEREDby your television warranty)
REAR PANEL for the 53FDX01B (DP-05) and 43FDX01B (DP05F)
AUDIOTO HI-FI
R L
PAG
E 01-08
ANT A
ToConverter
VIDEO
(MONO)
AUDIO
INPUT 1 INPUT 2
L
R
S-VIDEO
MONITOROUT
Y
PBCB
PRCR
ANT B
VIDEO
(MONO)
AUDIOR
S-VIDEO
VIDEO
(MONO)
AUDIO
L
R
S-VIDEO
Y
PBCB
PRCR
SECTION 2
MICROPROCESSOR INFORMATION
MICROPROCESSOR PORT DESCRIPTION
PAGE 02-01
DP-0X MICROPROCESSOR PORT DESCRIPTION EXPLANATION: The DP-0X Microprocessor is a Dual In-Line 64 pin chip. Generic number is MN102H51K. The Microprocessor is responsible for many different operations related to the control of the Projection Television. Some of these con-trols are automatic and some require customer intervention, either by the Remote control or front panel keys and/or by the customer’s menu. When power is first applied, the Microprocessor receives it’s B+. This Microprocessor utilizes a 3.3V power sup-ply instead of the usual 5V as in past chassis. As the 3.3V is rising, the Reset IC (I006) holds the reset pin (54) low long enough for the main B+ to stabilize. After stabilization, the Reset IC brings pin (54) high. During the Reset condition, the Microprocessor is initiated into its start up state. At the same time this is happening, the Microprocessor Oscillator is generating the Micro-processor’s internal clock. The Crystal responsible for this is X001 (4Mhz) connected to pins (52 and 53). When trouble shooting a Microprocessor for problems, it’s very important to remember the sequence described above. Always examine the process before looking for any other problem area. The order is; 1. Vcc Applied. Generated from the Always Voltage (STY+7V I905) on the Sub Power Supply then through
the (STBY +5V I008 on the Signal PWB) to the 3.3V regulator Q026. 2. Ground is available. Look for open traces, etc…. 3. The Reset circuit is working (I006). It should hold the Reset pin on the Microprocessor Low until main Vcc
is stabilized. 4. The Oscillator is running. Be careful here because a low resistance measuring probe will kill the Oscillator or
give a false reading. After checking for the preliminary functionality of the circuits described above, then check for active clock pulses leaving data port pins. (See the Data Communications Circuit Diagram for details). If some other IC is grounding the data or clock pins, the Microprocessor will not work. This usually require a Pull-Up resistor. If no Pull-Up resistor is noted in the schematic, then the responsibility for Pull-Up lies within the Microprocessor. Unloading the pin in a good way to investigate for Pull-Up. When a command is entered by either Remote Control, Front Keys or some internal process, the Microprocessor runs a set of predetermined routines. These routines are hard programmed into the Microprocessor RAM and are unchangeable. There are routine instructions that can be modified by either the customer or the Servicer and in-volve pre-programmed routines and variables entered by the customer or technician. These would include such things as changing the channel , audio set-ups, on/off timer, auto-link, etc... CONTROL OF THE PROJECTION TELEVISION: • Receiving Infrared Remote Control Commands • Receiving Key Input Commands • Controlling the On and Off state of the High Voltage Power Supply. • Interaction between the Customer’s Menu and Chassis controls. • Outputting On Screen Display information. • Interaction between the Servicer’s Menu and Chassis I2C Data Bus controls. • Automatically Scanning the Tuner’s searching for Active Channels when requested by the Customer
from the Menu. • Automatically Controlling the Tuners when Channels are changed for the Main and PinP Tuners. • Automatically Controlling the Video Processor (Rainforest IC) when directed by the Customer. • Controlling the Audio Circuits when directed by the Customer. • Controlling Switching between Tuner (Main), AVX 1, 2, 3 and 4, Component 1, 2, and Tuner 2 (AUX)
or In From Converter. The following section will explain the controls listed above.
Continued on Next Page
MICROPROCESSOR PORT DESCRIPTION
PAGE 02-02
Continued from Preceding Page Receiving Infrared Remote Control Commands: Whenever the Customer utilizes the Infrared Remote, the IR receiver will detect these 38Khz Infrared pulse train and amplify them. These pulses are delivered to the Microprocessor at Pin (1). The Microprocessor decodes this data train and sets off the internal routine related to the command. There is a time when the Microprocessor ignores the remote commands and that is when the Digital Convergence Unit, (DCU here after) is in operation. The Microprocessor receives a BUSY notification that the DCU is in op-eration and simply doesn’t respond to remote commands. (See the Digital Convergence Interconnect Diagram and explanation for complete details.) The BUSY signal is generated from the DCU at pin (10). Then out pin (1) of the PSD1 connector to pin (10) of I004 DAC2. I004 sends the information via SCL1 and SDA1 lines from Pin (14 and 15) to the Microprocessor pins (2 and 3). Receiving Key Input Commands: The front panel function keys are detected by the Microprocessor via R2 ladder style circuit. In other words, in-side the microprocessor is a group of comparators. The function keys are strung together and each one has a dif-ferent resistor value to ground. When the key is pressed, the comparators detect the change is resistance to ground at pin (20) Clock and convert the related DC value into data the Microprocessor can understand. The following shows the resistor value to ground from pin (20) of the Microprocessor, though pin (7) of the PFS connector to the individual keys. Channel Up = ground Channel Down = 1K Volume Up = 1K + 1.5K or 2.5K Volume Down = 1K + 1.5K + 2.7K or 5.2K AVX = 1K + 1.5K + 2.7K + 4.7K or 9.9K Menu = 1K + 1.5K + 2.7K + 4.7K + 10+ or 19.9K Controlling the On and Off state of the High Voltage Power Supply. The Power On/Off function switch has STBY+3.3V applied for the Sub Power Supply, via pin (8) of the PFS connector through a 1K resistor. The output of the Power On/Off switch is sent through pin (6) of the PFS to Q014. Q014 is turned on at this time and connected to it’s Emitter is Data from the Microprocessor pin (21). The Data is routed from Q014’s Collector to Key In pin (10) of the Microprocessor. When the Microprocessor re-ceives this data at pin (10), it knows to turn on or off the television. This function is performed by and output from pin (53) which controls Q002. This output from this pin is High when the set is On and Low when the set is Off. (For more details related to Power On/Off, see the Power On & Off Circuit Diagram Explanation and Diagram). Interaction between the Customer’s Menu and Chassis controls. When the Customer accesses the Main Menu, selections can be made by scrolling up and down or left to right. Each selected input activates a set of instructions within the Microprocessor and determines the output state of the related pins. Outputting On Screen Display information. When it’s necessary, the Microprocessor generates 1uSec pulses from pins (37 Red, 38 Green and 39 Blue) that are sent to the Rainforest IC (IX01) pins (37 Blue, 38 Green and 39 Red) as OSD signals. When the OSD sig-nals are high, they turn on the output of the Red or Green or Blue amps inside the Rainforest IC and output a pulse to the CRTs to generate that particular character in the particular color. (See the On Screen Display Circuit Diagram and Explanation for further details.)
(Continued on page 3)
MICROPROCESSOR PORT DESCRIPTION
PAGE 02-03
(Continued from page 2)
Interaction between the Servicer’s Menu and Chassis I2C Data Bus controls. When it becomes necessary for the Service Technician to make an adjustment to the set, the Service Menu must be entered. This is accomplished with the TV turned off, then by pressing and holding the INPUT Key and then the POWER SWITCH. The Adjustment Menu will be displayed at this time. With the Service Menu activated, the Technician moves up and down to the desired adjustment using the Remote control or front panel Up or Down cursor keys. To make the adjustment, the Technician uses the Remote control or front panel Left and Right cursor Keys to change the data values for the particular adjustment. The Microprocessor controls the individual IC related to the adjustment using I2C technology. I2C technology allows the Microprocessor to control and IC using only two pins, (SCL and SDA). The following pins on the Microprocessor and the ICs that it controls are described in the following table.
(See the Adjustment Section for actual adjustment made in the Service Mode condition). Automatically Scanning the Tuner’s searching for Active Channels when requested by the Customer from the Menu. When the Projection is first installed, the active channels must be scanned and memorized in the Channel Scan List. This list is actually stored within the EEPROM and the Microprocessor uses the information to Scan up or down. Held within the Microprocessor is the Initial FCC Lookup table. This table give information related to all the channels frequency, band, and channel number. The frequency is actually a given value for the Phase Lock Loop circuit within the tuner. Then band is data to tell the band selection circuit in the tuner where the particular channel is located and the channel number is given to the microprocessor to indicate what OSD outputs to pro-duce. When the set is first opened, it’s in what is called Factory Reset Condition. For the Tuner this means that the signal source is AIR, and channels 2 through 13 are in the channel scan list. Before the customer runs Auto Program, they must set the signal source to the type they are using, Air, Cable 1 or Cable 2. After the source is set, the customer then proceeds with Auto Programming. When Auto Programming is initiated, the Microprocessor has a specific program to run. This program starts by placing the tuner in the lowest channel in the lowest band. That would normally be channel 2. Then the program instruct the Microprocessor to look for Sync. To do this, the Microprocessor actually need Horizontal Blanking (H.Blk) at pin (49) which is labeled H.Sync and Video Sync (24) labeled Main/Sub SD Det. Horizontal Blanking is use as a gate pulse for the coincidence detector. Within the coincidence detector is a cir-cuit that looks at the timing of the Sync in relationship to (H.BLK). If the signal being checked is not in time with (H.Blk). The signal is ignored. However, if the signal being monitored is in coincidence with (H.Blk) the signal is deemed to be true Video Sync and that particular channel is stored as an active channel in the EEPROM Scan List. Then the Microprocessor sends information to the tuner to move up one channel and the whole process begins again. This is repeated until every channel is checked. After completion of the scan, the microprocessor retrieves information from the EEPROM concerning the first channel in the lowest band that appears in the scan list and directs the tuner to tune to that channel.
(Continued on page 4)
PINS CONTROLLED ICs
2 SDA1 and 3 SCL1 I401 AV Selector, I002 EEPROM, I003 DAC 1, I004 DAC 2
59 SDA2 and 60 SCL2 U204 3D/YC, I701 Deflection Drive, IX01 Rainforest, IS03 Front Audio Control, IS05 Front EQ, IS10 Center EQ, IS08 Center/LFE/PinP Audio Control, IS01 DAC3, I201 1H Main Video, and I403 H Sub Video.
57 SDA3 and 58 SCL3 IS11 Rear Audio Control.
MICROPROCESSOR PORT DESCRIPTION
PAGE 02-04
(Continued from page 3)
Automatically Controlling the Tuners when Channels are changed. (See Figure 1) MAIN TUNER: When channels are changed, the Microprocessor runs another routine. This routine detects the command if it’s input by the Remote Control or the Front keys, whether it’s Scan Up/Down or direct access, and begins to control the Tuner. First the Microprocessor output a Mute command to blank the video, then data is sent to the tuner to move it to the desired channel. After that the Microprocessor again checks the coincidence detector for active sync. If active sync is detected, the Microprocessor opens what is called the AFC Loop. The AFC Loops com-prises two cycles trying to lock the tuner to the specific IF frequency of 45.5 Mhz. A DC voltage is sent from ei-ther the Main Tuner U201 pin (10) or the PinP Tuner U202 pin (21) back to the Microprocessor pin (6). This DC voltage indicates the error between the IF detected and the IF frequency reference. This error voltage tells the Microprocessor to do one of two things. 1st, if the error is large, the Microprocessor changes the Programmable Divider’s division rate to a larger or smaller degree to get closer to the actual IF frequency desired. Or 2nd move the Pulse Swallow division rate to either 1/32 or 1/33. The Pulse Swallow tuning circuit is a second divider that is on the output from the Prescaler. The main Prescaler takes the very high frequency output from the tuners mixer circuit which is produced when the tuners main oscillator is beat against the incoming RF frequency. The Pro-grammable Divider is instructed by the Microprocessor exactly what division rate to apply to the Beat Frequency generating the IF frequency. The IF frequency is then sent through the Pulse Swallow circuit which again divides the IF frequency at a much smaller rate . This allows the IF output frequency to become much more finite and can correct for much smaller errors between the Phase comparators reference frequency. The error voltage generated is directed back to the main internal Oscillator in the front end and corrects for Tuning errors. (See the Microprocessor Data Communications Circuit Diagram Explanation for Details related to Data Com-munication for controlling the Main Tuner).
(Continued on page 5)
MainOsc
MixBand
TuningVoltage
RFProgramm-
ableDivider
PulseSwallow1/32 or
1/33
PhaseComparator
RefOsc
IFComparator
Interface
TuningVoltage+33V
Video
MAINMICROPROCESSOR
Data Clock Load AFC
5K
RefFreq.
ErrorAmp
Video Det
45.5K
BM (B+ Mains)
B+ Distribution
INTEGRATED TUNER
IF Out IF In
Pre-ScallerFixed
Figure 1
MICROPROCESSOR PORT DESCRIPTION
PAGE 02-05
(Continued from page 4)
Automatically Controlling the Tuners when Channels are changed. (See Figure 1) PinP TUNER: As far as the internal function of the PinP Tuner, it is the same as the Main Tuner. (See the Microprocessor Data Communications Circuit Diagram Explanation for Details related to Data Com-munication for controlling the Main Tuner). When the customer presses the PinP button on the Remote Control, the Microprocessor outputs Clock, Data and Enable controls to the Flex Converter. The Flex Converter also has the PinP circuit inside. The Clock, Data and Enable pins on the Microprocessor are pins (20 Clock, 21 Data and 46 FCENABLE) These are routed to the Level Shift IC, I014 pins (2, 3 and 4). They are output on pins (18, 17 and 16) to the Flex Converter U205 con-nector PFC1 and input on pins (10, 11 and 12). The Flex Converter’s PinP unit is then switched on and insertion is made into the regular Main Video line. The position of the PinP window, the PinP window itself and other dif-ferent display conditions are controlled by this process. When SWAP is pressed on the remote control, the chan-nel or input that the PinP tuner was on, now becomes the Main Video’s source and the channel or input that the Main signal was on, now becomes the PinP source. Automatically Controlling the Video Processor (Rainforest IC) when directed by the Customer. The Rainforest IC has many enhancement circuits built in. These would include the Black Peak Expansion circuit, the Dynamic Noise Reduction circuit, Time Compression and of course Sharpness, Black Level and Contrast ad-justments as well. • Black Peak Expansion Circuit:
This circuit is utilized to increase the contrast ratio. The standard video signal is 1 Volt Peak to Peak (p/p hear after), the actual video (Y) content is 730mVp/p. The 1 Vp/p is explained it IRE figures from this point on. The Standard video signal is divided into units called IRE. The units are equal to 140 total for the 1Vp/p signal. Sync occupies 40IRE which are negative. And the Luminance represents 100 IRE units. Each unit represents 7.1428mVp/p of information. (See Figure 2 below.) The Black Peak Expansion circuit monitors the 1/2 way point of luminance, (50 IRE or 357mV) and pulls the signal towards pure black or the 7.5 IRE level. This increases the distance from Black Peak to White Peak which is contrast.
• Dynamic Noise Reduction Circuit: This circuit again monitors the area from 50 IRE down and subtracts noise. This circuit is dynamic meaning that it characteristics change. In other words, the subtraction process is greater near black level that it is near 50 IRE. The subtraction is 6dB at maximum, meaning that there would be some frequency loss near black, but the noise which is seen as white speckles would be reduced.
• Time Compression Circuit: Any time an analog signal is passed through a capacitive circuit, its high frequencies are reduced. To re-place these high frequencies, Hitachi uses Time Compression. This circuit is on the order of Aperture Compensation, however it differs in the fact that it uses 5 delay lines. The actual signal should look like
(Continued on page 6)
Figure 2
MICROPROCESSOR PORT DESCRIPTION
PAGE 02-06
(Continued from page 5)
Figure 3, however after passing through a capacitive circuit, it looks like Figure 4. After Time Compres-sion takes place, the beginning rise is advanced. Just before white peak the signal is delayed. Just before the signal falls the signal is advanced and just before the signal reaches black peak the signal is delayed. This causes the signal to appear more like the actual signal and thus restores the high frequencies lost through capacitance.
• Sharpness: During the Time Compression process, switching pulses that are detected at the transition point, (A tran-sition is the point at which the luminance signal goes for black to white or white to black) are used in the sharpness circuit.. This signal is the routed through a sort of variable resistor and according to how much sharpness the customer has selected, determines how much of the transition signal is added to the origi-nal signal. The greater the sharpness setting, the greater the transition signal added.
Controlling the Audio Circuits when directed by the Customer. The customer has control over how the set accesses audio information for all of it’s inputs. The tuner for example is an integrated type. This not only means that held within the Main Tuner are all the necessary components for Reception and Video detection. It also has a built in audio and MTS decoder. The Main Tuner outputs Left Total and Right Total signals. (Left Total and Right Total means that the encoding for Pro-Logic is held within the indi-vidual signal.) The customer can select first of all, how the Tuner decodes it’s audio. Stereo, Mono, or SAP can be selected. The Main Tuner must tell the Microprocessor what signal it is receiving. The Main Tuner has a ST LED output at pin (19) which tells the Microprocessor it is receiving MTS Stereo and a SAP LED output at pin (20) which tells the Microprocessor it is receiving Second Audio Program. How these are selected by the con-sumer via the Main Menu determines the output from the Microprocessor. • ST LED is routed from the Main Tuner at pin (19), through Q204, to the DAC1 I003 pin (10). The DAC1
outputs Clock and Data via pins 15 SCL1 and 14 SDA1 signals to the Microprocessor input on pins 3 SCL1 and 2 SDA2. The Microprocessor knows how to switch the tuners decoder circuit by making judgment upon these inputs. Then the Microprocessor can use Clock, Data and Enable lines to control the Tuner.
(Continued on page 7)
Figure 6 Figure 7
Original Signal Transition Point pulses
Figure 8
Transition Pulses Added
Figure 3 Figure 4
Actual Signal After passing through a capacitor
Figure 5
After Time Compression
MICROPROCESSOR PORT DESCRIPTION
PAGE 02-07
(Continued from page 6)
• SAP LED is routed from the Main Tuner at pin (20), through Q203, to the DAC1 I003 pin (9). The DAC1 outputs Clock and Data via pins 15 SCL1 and 14 SDA1 signals to the Microprocessor input on pins 3 SCL1 and 2 SDA2.
The Microprocessor knows how to switch the tuners decoder circuit by making judgment upon these inputs. Then the Microprocessor can us Clock, Data and Enable lines to control the Tuner. Clock, Data and Enable lines for the Main Tuner are output from the Microprocessor at pins (20, 21 and 44) re-spectively. Pin (44) FEENABLE1 goes directly to the Main Tuner at pin (6), where as the Clock and Data lines must be routed through the Level Shift IC I014 to be brought up to 5V. Clock and Data arrive at I014 at pins (2 and 3) and are output at pins (18 and 17). They arrive at the Main Tuner at pins (4 and 5). The PinP Tuner doesn’t have MTS capability. It only output mono audio, so no switching takes place for the PinP Tuner U202 audio circuit. The only difference for the PinP tuner control lines is related to the PinP Enable line. This is output from the Microprocessor pin (43 FEENABLE2) to the PinP Tuner at pin (17). Clock and Data are the same as for the Main Tuner. (See Microprocessor Data Communications Circuit Diagram and Explanation for further details). Controlling Switching between Tuner (Main), AVX 1, 2, 3 and 4, Component 1, and 2, and Tuner 2 (AUX) or In From Converter. The different inputs can be selected by the Remote Control or the Front Panel switches. This is accomplished by the INPUT button. Each time the Input button is pressed, the different inputs are sequentially selected. The se-quential order is, Main Tuner, AVX 1, AVX 2, AVX 3, AVX 4, 2nd Antenna and back to Main Tuner. Also, if there are S-Inputs on AVX1, 2 or 4, there is an internal mechanical switch inside the S-Jack that tells the Micro-processor an S-Jack is inserted. Then when that particular input is selected, it automatically selects S as it’s source. The same thing holds true for Component inputs. The set should never have Component inputs and S-Jack inserted at the same time and a black and white picture will be displayed. (See Video Signal Processing for details related to Video Switching.)
Page 02-08
Pin No. ID Function Active 1 IRIN Receives Remote Control Inferred pulses. Data
2 SDA1 Serial Data Sent and Received from the EEPROM, A/V Selector, DAC1, DAC2. Function of I2C. Data
3 SCL1 Serial Clock Synchronization Sent to the EEPROM, A/V Selector, DAC1, DAC2. Function of I2C. Data
4 Dimmer Receives DC voltage generated from the Photo Receiver on the Front Panel monitoring Room Light. For AI DC
5 AD Key In Receives Level Shifted DC voltage from Front Panel Key presses. DC
6 Main/Sub AFC Receives the Main Tuner AFC or Sub AFC DC Voltage switched by I005. Used during channel change. DC
7 Key In When the Power switch is pressed, Clock data from pin 21 is routed through Q014 back to this pin. Power is toggled On or Off. Data
8 Not Used Not Used N/A
9 Not Used Not Used N/A
10 Main FV Det Receives Composite 1 V Sync from I015 pin 4 for OSD Positioning. Sync
11 Sub FV Det Receives Composite 2 V Sync from I016 pin 4 for OSD Positioning. Sync
12 DSP Busy Receives the Busy command from the Digital Surround Processor on the Surround PWB. DC
13 DSP SO Control command to the DSP Unit for controlling Modes. Data
14 DSP Dir Receives Digital Surround Processor Error information from the DSP unit on the Surround PWB. Data
15 DSP SS Control command to the DSP Unit for controlling Modes. Data
16 DSP SCK Digital Surround Processor Clock. Data
17 DSP S1 Control command to the DSP Unit for controlling Modes. Data
18 DSP ERR Mute Mutes Audio when a DSP Dir input is detected. (DSP Error). DC High
19 DSP Reset Resets the DSP module on the Surround PWB DC High
20 Clock Sent to the Level Shift I014 then to both Tuners and the Flex Converter as a timing signal. Also see pin 7. Data
21 Data Sent to the Level Shift I014 then to both Tuners and the Flex Converter to control each unit. Data
22 Comp 1/2 FH Det Either Component One or Two Horizontal Input from I005 through Q046. Used for OSD Display. And Auto Link DC
23 AC In Receives Timing pulses for advancing the Clock. Received from the Smitt Amp Q008 and Q009 60Hz.
24 Main/Sub SD Det Station Detection. Used during Auto Programming and when channels are changed to open AFC Loop. Switched by I005. Sync
25 VDD Stby +3.3V generated by 0029. Main Microprocessor B+. DC
26 CHL Clamp level High DC
27 VRefFHS Use as a reference signal within the Microprocessor High Frequencies. DC
28 CVBS0 Composite Sync used for Closed Caption Detection for the Main Tuner. Sync
29 VSS Ground N/A
30 CVBS1 Not Used. Composite Sync used for Closed Caption Detection for the PinP Tuner. N/A
31 VREFLS Reference Signal used within the Microprocessor Low Frequencies. N/A
32 CLL Internal function of the Microprocessor. N/A
33 AVDD Stby +3.3V generated by 0029. DC
34 COMP Internal function of the Microprocessor. DC
35 IREF Internal function of the Microprocessor. DC
DP-0X CHASSIS MICROPROCESSOR I-001 PIN/PORT DESCRIPTION 1 through 35
Page 02-09
Pin No. ID Function Active 36 VREF Internal function of the Microprocessor. DC
37 OSD R Outputs Red characters for the Service Menu. Data
38 OSD G Outputs Green characters for the Service Menu. Data
39 OSD B Outputs Blue characters for the Service Menu. Data
40 HALF TONE Controls the Translucency of the Main Menu Background. Low = Clear, Mid = Transparent, Hi = Gray. Data
41 PDO Internal function of the Microprocessor. DC
42 BVC0I Internal function of the Microprocessor. DC
43 FE ENABLE 2 Front End Enable. Enables the reception of data from the Microprocessor by the PinP Tuner. Data
44 FE ENABLE 1 Front End Enable. Enables the reception of data from the Microprocessor by the Main Tuner. Data
45 V.MUTE Mutes Audio and Video through Q008 and Q010 to Sub Video and Surround PWB during channel change. High = Mute DC
46 FC ENABLE Flex Converter Enable Line. Allows the Flex Converter to receive commands from the Microprocessor. Data
47 OSD X0 Reference Frequency for OSD. Determines the OSD Size. Data
48 OSD X1 Reference Frequency for OSD. Determines the OSD Size. Data
49 H SYNC Receives Horizontal Blanking pulses 3.3Vp/p for OSD positioning. Generated from H Blk through Q006 H Blk
50 SD SELECT Sent through Q030 to I015 for setting the internal selection switches. Hi = Main, Lo = Sub DC
53 Power ON/OFF This output goes high when the Power Button is pressed for ON and Low for Off. DC
54 RESET Low when Power first applied then rises to a high of 3.3V. Received from I006. Resets the Microprocessor. DC
55 VSYNC Receives Vertical Blanking pulses 3.3Vp/p for OSD positioning. Generated from V Blk through Q005 Data
56 P BLK Sent to the Rainforest IC IX01. Used to Mute the Video during Channel change, Child Lock, AVX selected with no input. Hi = Mute DC
57 SDA3 Serial Data Sent to the Rear Audio Output IC IS11 on Surround PWB. Controls Volume, Bass, Treble, and Bal. Function of I2C. Data
58 SCL3 Serial Clock Sent to the Rear Audio Output IC IS11 on Surround PWB. Used for Timing of Data. Function of I2C. Data
59 SDA2 Serial Data Sent to U204, I701, IX01, IS03, IS05, IS10, IS08, IS01, I201 and I403. Function of I2C. Data
60 SCL2 Serial Clock Sent to U204, I701, IX01, IS03, IS05, IS10, IS08, IS01, I201 and I403. Function of I2C. Data
61 VDD Stby +3.3V generated by 0029. Main Microprocessor B+. DC
62 OSC In OSC In (4MHz) Data
63 OSC Out OSC Out (4MHz) Data
64 VSS Ground. N/A
DP-0X CHASSIS MICROPROCESSOR I-001 PIN/PORT DESCRIPTION 36 through 64
51 OSD BLK Outputs a pulse slight wider and in time with the OSD characters to clean up video where character will be displayed. Data
52 TEST Use by the factory for internal test of the Microprocessor and to place in a specific set of criteria. DC
Main V. Chip Data and CCD
Sub V. Chip Data
Main FV Det
G+Reset
DP0X SYSTEM CONTROL PORT DESCRIPTION
Sub FV Det
Comp
IRef
PAGE 02-10
I014LevelShift
CLOCK
DATA
ENABLE
AFC
MAINTUNER
Audio DSPAC3/ProLogic
I001
6
62
63
64
1
28
30
10
8
U201
Main/Sub AFC
IRIn
VSS (Gnd)
OSC Out
OSC In
CLH 26
27VRefHS
57
58 SCL3
SDA3
ADKeyIn
5Ft. Panel Control Keys
Key In
DATA
CLOCK
ENABLE
AFC
PinPTUNER
11
7
U202
34
35
17
18DSP Err Mute
16
15
19
46
20
21
DSP SI
DSP Sck
DSPSS
DSPRST
FC Enable
Clock
Data
Clock
Data
Enable
Flex Conv & PinPUnit
U205
DSP Err
DSP SI
DSP Sck
DSPSS
DSPRST
FE Enable1
SO Select
FE Enable2
AVDD 3.3V
Test
DSP S0
DSP Busy
SCL2
SDA2
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
3D/YCComb Filter
Front AudioControl
Front EQ
Cent EQ
Deflection
44
50
60
59
13
12
I701
IS10
IS05
U204
SCL
SDA
SCL
SDA
Cent/LFE/Audio Control
1 H Main Video
IS01
IS08
SCL
SDA
RainforestIC
IX01Reset 54
32CLL
43
BVCOI 42
33
52
IS03
IS05
SCL
SDA
SCL1
SDA1
SCL
SDA
SCL
SDA
EEPROM
DAC 1
DAC 23
2I004
I003
I002
SDA
SCL
Rear AudioControl IS11
Half Tone
B+Fail
Power On/Off 53
9
40
55VSync
36VRef
39
47
4
51
29
23
37
41
VSS (Gnd)
Dimmer
OSD Blk
AC In
POO
OSD R
OSD Xo
OSD B
OSD X1 48
38OSD G
N/C
P Blk. 56
61VDD (3.3V)
SCL
SDAI201
SCL
SDAA/V
SelectorI401
Power Switch
49
24Main/Sub SD Det
H.Blk/H.Sync SCL1 H Sub Video
SDAI403
DAC3
45VMute
DP-05 and DP-05F MICROPROCESSOR PORT DESCRIPTION
PAGE 02-11
DP-05F PORT DESCRIPTION Refer to the DP-05 and DP-05F System Control Port Description Circuit Diagram The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 System Control Port Description Cir-cuit Diagram is; • The DP-05 and DP-05F doesn’t have the DSP Module. Therefore, it uses a SRS Surround PWB. There is no
Rear or Center Audio, so the Serial Data Communications (SCL3 and SDA3) to the Rear Audio B+ isn’t Used.
• The Data Communications to the Level Shift IC (I014) going to the (DSP) is not used. • The Rear Audio IC, Center Audio IC and the Center Graphic EQ IC are not used. • The Front Audio Control IC designation is (IA05). • The DAC3 IC designation is (IA01). All else remains the same. (See Next page for diagram).
Main V. Chip Data and CCD
Sub V. Chip Data
Main FV Det
G+Reset
DP-05 and DP-05F SYSTEM CONTROL PORT DESCRIPTION
Sub FV Det
Comp
IRef
PAGE 02-12
I014LevelShift
CLOCK
DATA
ENABLE
AFC
MAINTUNER
I001
6
62
63
64
1
28
30
10
8
U201
Main/Sub AFC
IRIn
VSS (Gnd)
OSC Out
OSC In
CLH 26
27VRefHS
57
58 SCL3
SDA3
ADKeyIn
5Ft. Panel Control Keys
Key In
DATA
CLOCK
ENABLE
AFC
PinPTUNER
11
7
U202
34
35
17
18DSP Err Mute
16
15
19
46
20
21
DSP SI
DSP Sck
DSPSS
DSPRST
FC Enable
Clock
Data
Clock
Data
Enable
Flex Conv &PinP Unit
U205
FE Enable1
SO Select
FE Enable2
AVDD 3.3V
Test
DSP S0
DSP Busy
SCL2
SDA2
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
3D/YCComb Filter
Front AudioControl
Deflection
44
50
60
59
13
12
I701
U204
SCL
SDA
1 H Main Video
IA01
RainforestIC
IX01
Reset 54
32CLL
43
BVCOI 42
33
52
IA05
SCL
SDA
SCL1
SDA1
SCL
SDA
SCL
SDA
EEPROM
DAC 1
DAC 23
2I004
I003
I002
Half Tone
B+Fail
Power On/Off 53
9
40
55VSync
36VRef
39
47
4
51
29
23
37
41
VSS (Gnd)
Dimmer
OSD Blk
AC In
POO
OSD R
OSD Xo
OSD B
OSD X1 48
38OSD G
N/C
P Blk. 56
61VDD (3.3V)
SCL
SDAI201
SCL
SDAA/V
SelectorI401
Power Switch
49
24Main/Sub SD Det
H.Blk/H.Sync
SCL1 H Sub Video
SDAI403
DAC3
45VMute
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MICROPROCESSOR DATA COMMUNICATION DESCRIPTION
PAGE 02-13
Use this explanation in conjunction with the Microprocessor Data Communications circuit diagram. The Microprocessor must keep in communication with the Chassis to maintain control over the individual cir-cuits. Some of the circuits must return information as well so the Microprocessor will know how to respond to different request. The Microprocessor uses a combination of I2C Bus communication and the Serial Data, Clock and Load lines for control. The I2C communication scheme only requires 2 lines for control. These lines are called SDA and SCL. Serial Data and Serial Clock respectively. The Microprocessor also requires the use of what are called Fan Out IC or DACs, (Digital to Analog Converters). This allows the Microprocessor to use only two lines to control many different circuits. Also, due to the fact that this Microprocessor operates at the new 3.3Vdc voltage, it requires a Level Shift IC to bring up the DC level of the control lines to make it compatible with the connected ICs. The Microprocessor communicates with the following ICs: ON THE SIGNAL PWB: Main Tuner U201 PinP Tuner U202 EEPROM I002 Flex Converter U205 DAC1 I003 DAC2 I004 Level Shift I014 3D Y/C U204 Main Video Chroma I201 ON THE TERMINAL PWB: A/V Selector I401 Sub Video Chroma I403 ON THE DEFLECTION PWB: Sweep Control I701 ON THE SUB VIDEO PWB (2H VIDEO): Rainforest IX01 ON THE SURROUND PWB: Front Audio Control IS03 Center/LFE (Low Frequency Effects) Audio Control IS08 Surround Board DAC3 IS01 Front Equalizer IS05 Center Equalizer IS10 Rear Audio Control IS11 Audio DSP (Digital Signal Processor) DSP Unit HC4051 The following explanation will deal with the communication paths used between the Microprocessor and the re-spected ICs. ON THE SIGNAL PWB: Main Tuner U201 The Microprocessor controls the Main Tuner by Clock, Data and Enable lines. Clock, Data and Enable lines for the Main Tuner are output from the Microprocessor at pins (20 Clock, 21 Data and 44 FEENABLE1) respectively. Pin (44) FEENABLE1 goes directly to the Main Tuner at pin (6), where as the Clock and Data lines must be routed through the Level Shift IC I014 to be brought up to 5V. Clock and Data from the Microprocessor arrive at I014 (Level Shift) at pins (2 and 3) and are output at pins (18 and 17). They arrive at the Main Tuner at pins (4 and 5).
(Continued on page 14)
MICROPROCESSOR DATA COMMUNICATION DESCRIPTION
PAGE 02-14
(Continued from page 13)
PinP Tuner U202 The only difference for the PinP tuner control lines is related to the PinP Enable line. This is output from the Microprocessor pin (43 FEENABLE2) to the PinP Tuner at pin (17). Clock and Data are the same as for the Main Tuner. For further details about tuner operation, please see the Microprocessor Port Description and Circuit Dia-gram. EEPROM I002 The EEPROM is ROM for many different functions of the Microprocessor. Channel Scan or Memory List, Customer set ups for Video, Audio, Surround etc… are memorized as well. Also, some of the Microprocessors internal sub routines have variables that are stored in the EEPROM, such as the window for Closed Caption detection. Data and Clock lines are SDA1 from pin (2) of the Microprocessor to pin (5) of the EEPROM and SCL2 from pin (3) of the Microprocessor to pin (6) of the EEPROM. Data travels in both directions on the Data line. Flex Converter U205 The projection television is capable of two different horizontal frequencies. 31.5Khz for everything except HD and 33.75Khz for HD. (High Definition). The Flex Converter is responsible for receiving any video input and converting it to the related output. This output is controlled by sync and by the customer’s menu and how it is set up. The set up can be 4X3 or 16X9 sometimes called letterbox. The Flex Converter can take any NTSC, S-In, Component in in NTSC, Progressive, Interlaced, 480I, 720P, 1080I signal. Control for the Flex Converter is Clock, Data and Enable lines. Clock, Data and Enable lines for the Flex Converter are output from the Microprocessor at pins (20 Clock, 21 Data and 46 FCENABLE). FCENABLE Clock and Data lines must be routed through the Level Shift IC I014 to be brought up to 5V. They arrive at I014 at pins (2 Clock, 3 Data and 4 FCENABLE) and are output at pins (18, 17 and 16) respectively. DAC1 I003 This Digital to Analog converter acts as an extension of the Microprocessor. Sometimes called an Expansion IC. The purpose of this IC is to reduce the number of pins, (fan out) of the Main Microprocessor I001. The Main Microprocessor send Clock and Data via I2C bus to the DAC1 IC. The output from the Microprocessor is pin (2 SDA1 and 3 SCL1) which arrives at the DAC1 IC at pins (5 and 6) respectively. The following is a list of the input and output pins on DAC1. PIN FUNCTION 1 IR Det The IR pulse from the Remote Control is monitored when Auto Link is set. (See Auto Link in Index). 2 YN Det Active Low. This pin monitors for active sync when Auto Link is set. (See Auto Link in Index). 3 Blk Main Normal High, Blanking Low. Blanks Y-Cb/Cr into Flex Converter. 4 MTS Places the Main Tuner pin (21 mode) into MTS Stereo. If Tuner receiving MTS signal. See pin 10. 5 F Mono Places the Main Tuner pin (22 mono) into forced Mono Mode. 6 Ant Switches the antenna block into Antenna A or Antenna B when selected. 7 Blk Sub Normal High, Blanking Low. Blanks PinP Sub Y-Cb/Cr on Terminal PWB before going into Flex Converter. 8 Gnd Ground 9 SAP Det The Main Tuner outputs an SAP LED signal when SAP is detected. Active Low. 10 ST Det The Main Tuner outputs an ST LED signal when Stereo is detected. Active Low. 11 SAD0 Ground Not Used 12 SAD1 Ground Not Used 13 SAD2 Ground Not Used 14 SDA Data I2C communications between DAC1 and Microprocessor 15 SCL Clock I2C communications between DAC1 and Microprocessor 16 Vcc IC B+. (STBY +5V)
(Continued on page 15)
MICROPROCESSOR DATA COMMUNICATION DESCRIPTION
PAGE 02-15
(Continued from page 14)
DAC2 I004 This Digital to Analog converter acts as an extension of the Microprocessor. Sometimes called an Expansion IC. The purpose of this IC is to reduce the number of pins, (fan out) of the Main Microprocessor I001. The Main Microprocessor send Clock and Data via I2C bus to the DAC2 IC. The output from the Microprocessor is pin (2 SDA1 and 3 SCL1) which arrives at the DAC2 IC at pins (5 and 6) respectively. The following is a list of the input and output pins on DAC2. PIN FUNCTION 1 YUV Det1 Detects activity on Component Input number 1. 2 YUV Det2 Detects activity on Component Input number 2. 3 FH Det Out 1 Test Point 1 (TP1). 4 Sel5 Controls IX02 on 2H PWB. Selects either Y Cb/Cr or Y IQ to compensate for Chroma Phase angle used in Auto Color. 5 F Mono Places the Main Tuner pin (22 mono) into forced Mono Mode. 6 FH Det Out 1 Test Point 2 (TP2). 7 31/33 Notifies the DCU related to Horizontal Frequency. Either 31.5Khz for everything but HD or 33.75Khz for HD.
The DCU uses two sets of memory. One for everything but HD and one for HD. This relates to both Digital Convergence adjustment data and for Magic Focus memory. Also notifies the Dynamic Focus Horizontal Parabolic generator to compensate for phase distortion. Also, notifies I701 Horizontal Drive generation IC concerning the Horizontal operation frequency.
8 Gnd Ground 9 CS Sel Not Used. 10 Busy Informs the Microprocessor that the DCU is in the Digital Convergence Adjustment Mode. The Micro. Ignores IR pulses. 11 SAD0 Ground Not Used 12 SAD1 Ground Not Used 13 SAD2 IC B+. (STBY +5V). 14 SDA Data I2C communications between DAC2 and Microprocessor 15 SCL Clock I2C communications between DAC2 and Microprocessor 16 Vcc IC B+. (STBY +5V). Level Shift I014 The Microprocessor operates at 3.3Vdc. Most of the Circuits controlled by the Microprocessor operate at 5Vdc. The Level Shift IC steps up the DC voltage to accommodate. 3D Y/C U204 The 3D Y/C module is a Luminance/Chrominance separator, as well as a 3D adder. Separation takes place digi-tally inside the module. Using advanced separation technology, this module separates and doesn’t produce dot pattern interference or dot crawl. The 3D effect is a process of adding additional signals to the Luminance and Chrominance. These signals relate specifically to transitions. Transitions are the point where the signal goes from dark to light or vice versa. The 3D adds a little more black before the transition goes to white and a little more white just before it gets to white. It also adds a little more white just before it goes dark and a little more dark just before it arrives. This gives the impression that the signal pops out of the screen or a 3D effect. The Microprocessor communicates with the 3D Y/C module via I2C bus data and clock. The communications ports are from the Microprocessor pins (59 SDA2 and 60 SCL2) to the 3D Y/C PYC1 connector pins (2 and 3) respectively. The Microprocessor also is able to turn on and off circuits within the 3D Y/C module determined by customer menu set-up. Main Video Chroma I201 The Main Video Chroma IC processes the video and chroma from the 3D Y/C module for the main picture. It converts video into Y and chroma into Cr/Cb (NTSC Only). Communication from the Microprocessor via pins (59 SDA2 and 60 SCL2) to I201 pins (34 and 33) respectively.
(Continued on page 16)
MICROPROCESSOR DATA COMMUNICATION DESCRIPTION
PAGE 02-16
(Continued from page 15)
ON THE TERMINAL PWB: A/V Selector I401 The A/V Selector IC is responsible for selecting the input source for the Main Picture as well as the source for the PinP or Sub picture. Communication from the Microprocessor via pins (2 SDA1 and 3 SCL1) to the PST1 connector pins (5 and 6) respectively then to I401 pins (34 and 33) respectively. Sub Video Chroma I403 The Sub Video Chroma IC processes the video and chroma for the Sub or PinP picture. It converts video into Y and chroma into Cr/Cb (NTSC Only). Communication from the Microprocessor via pins (59 SDA2 and 60 SCL2) to connector PST1 pins (1 and 2) I403 pins (34 and 33) respectively. ON THE DEFLECTION PWB: Sweep Control I701 The Sweep Control IC is responsible for generating Horizontal Drive and Vertical Drive signals. The Micro-processor must tell the IC when certain things are done in the Service Menu. When Cut Off is performed, the Vertical is collapsed. The Microprocessor tells I701 to stop producing Vertical Drive. At the same time, I701 must stop the Spot Killer circuit from operating. This is accomplished by placing pin (24 DAC3) high which activates QN07 which inhibits spot killer high. Also, when H.Phase is adjusted, the Microprocessor controls the H. Drive signals phase in relationship to H.Blk which is timed with video sync. This gives the appearance that the horizontal centering is being moved. Communication from the Microprocessor via pins (59 SDA2 and 60 SCL2) to the PSD2 connector pins (2 and 3) and then to I701 pins (16 and 17) respectively. ON THE SUB VIDEO PWB (2H VIDEO): Rainforest IX01 The Video Processing IC (Rainforest) is responsible for controlling video/chroma processing before the signal is made available to the CRTs. Some of the emphasis circuits are controlled by the customer’s menu. As well as some of them being controlled by AI, (Artificial Intelligence). Communication from the Microprocessor via pins (59 SDA2 and 60 SCL2) to the PSZ2 connector pins (1 and 2) and then to IX01 pins (27 and 26) respectively. ON THE SURROUND PWB: Surround Board DAC3 IS01 This Digital to Analog converter acts as an extension of the Microprocessor. Sometimes called an Expansion IC. The purpose of this IC is to reduce the number of pins, (fan out) of the Main Microprocessor I001. The Main Microprocessor send Clock and Data via I2C bus to the DAC3 IC. The output from the Microprocessor is pins (59 SDA2 and 60 SCL2) then through the connector PSU1 pins (2 and 1) which arrives at the DAC3 IC at pins (14 and 15) respectively. The following is a list of the input and output pins on DAC3. PIN FUNCTION 1 SW Sel 1 Turns on/off QS01 which either adds or doesn’t add Sub Woofer to Front L and Front R for 3 way audio set up. 2 DSP CSI Digital Surround Module signal. If the Coax Audio input is noisy, the DSP tells DAC3 to 2X invert the signal. 3 Opti/Coax Sel Controls IS17. Determins if the signal is 2X inverted due to noise. 4 RSPOFF Turns off the Rear Speaker outputs. Controlled by the customer’s menu. 5 CSPOFF Turns off the Center Speaker outputs. Controlled by the customer’s menu. 6 FSPOFF Turns off the internal Front Speaker outputs. Controlled by the customer’s menu. 7 SWSEL 2 Controls QS25 to add Front Left and Right to Sub Woofer. 8 Gnd Ground
(Continued on page 17)
MICROPROCESSOR DATA COMMUNICATION DESCRIPTION
PAGE 02-17
(Continued from page 16) 9 P. Vol Perfect Volume On/Off controlled by the customer’s menu. Note, when in Pro-Logic mode, Perfect Volume is Off. 10 DSPREQ DSP Request Input. 11 SAD0 Ground Not Used 12 SAD1 Ground Not Used 13 SAD2 Ground Not Used 14 SDA2 Data I2C communications between DAC3 and Microprocessor 15 SCL2 Clock I2C communications between DAC3 and Microprocessor 16 Vcc IC B+. (STBY +5V) Front Audio Control IS03 The Front Audio Control IC has the ability to adjust balance, treble, bass, volume and mute. This mute is the one that is activated when the mute button is pressed on the remote control. Communication from the Microprocessor via pins (59 SDA2 and 60 SCL2) then through the connector PSU1 pins (2 and 1) which arrives at the IS03 at pins (4 and 5) respectively. Center/LFE (Low Frequency Effects) Audio Control IS08 This IC has the ability to adjust balance, treble, bass, volume and mute for the Center channel. This mute is the one that is activated when the mute button is pressed on the remote control. It also adjust the volume for the Sub Woofer called LFE (Low Frequency Effects). Communication from the Microprocessor via pins (59 SDA2 and 60 SCL2) then through the connector PSU1 pins (2 and 1) which arrives at the IS08 at pins (4 and 5) respectively. Front Equalizer IS05 The Front Audio can be frequency adjusted to suite the particular room environment. The individual frequency notches are adjusted via the customer’s menu. The following frequency notches are adjusted by this IC. 60HZ, 250HZ, 1KHz, 3KHz, and 10KHz. Communication from the Microprocessor via pins (59 SDA2 and 60 SCL2) then through the connector PSU1 pins (2 and 1) which arrives at the IS05 at pins (17 and 16) respectively. Center Equalizer IS10 The Center Audio can be frequency adjusted to suite the particular room environment. The individual fre-quency notches are adjusted via the customer’s menu. The following frequency notches are adjusted by this IC. 60HZ, 250HZ, 1KHz, 3KHz, and 10KHz. Communication from the Microprocessor via pins (59 SDA2 and 60 SCL2) then through the connector PSU1 pins (2 and 1) which arrives at the IS05 at pins (17 and 16) respectively. Rear Audio Control IS11 The Rear Audio Control IC has the ability to adjust balance, treble, bass, volume and mute. This mute is the one that is activated when the mute button is pressed on the remote control. Communication from the Microprocessor via pins (57 SDA3 and 58 SCL3) then through the connector PSU1 pins (4 and 3) which arrives at the IS11 at pins (4 and 5) respectively. Audio DSP (Digital Signal Processor) DSP Unit HC4051 The Digital Signal Processor is responsible for decoding Dolby Pro-Logic, AC-3 audio and selecting the output of the audio determined by the customer’s menu. Such as Off, Matrix, Hall, etc… Control for the DSP is routed from the Microprocessor pins (15 DSPSS DSP Surround Sound Mode, 16 DSPSCK DSP Clock, 17 DSPI DSP Mode 1, 18 DSPERR Mute DSP Error Mute, and 19 DSPRST DSP Re-set). Then to the Level Shift IC I014 pins (5, 6, 8, 7, 9) respectively. These signals are then routed to the PSU2 connector pins (5, 2, 3, 6, and 1) respectively to the DSP module via the PMU1 connector pins (9, 12, 11, 8 and 13) respectively.
DSPSS
DSPSCK
DSPERR Mute
DSPI
DSPRST
DP0X CHASSIS MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT DIAGRAM
PAG
E 02-18
IOO1PSZ2
IX01Rainforest
RGB Processor
2H Video PWB
60
59
SCL2
SDA2
PSD2
Sweep Control
Surround PWB
Clock
Data
U205FLEX
&PinP
PFC1
Enable
Clock
Data
FCENAble
1
2
17
16
SCL2
SDA2
SDA2
26
27
SCL22
1I201
Main VideoChroma33
34 SDA2
SCL2
SDA2
SCL2 U2043DY/C
PYC1
2
3
2
I0143.3V -> 5VLevel Shift
3
4
5
6
7
18
17
16
15
14
13
20
21
46
15
16
18
8
9
12
11
17
19
DSPSS
DSPSCK
DSPERR Mute
DSPI
DSPRST
PSU2
5
2
6
3
1
PSU1
2
1
IS03Front
Audio ControlSCL2
SDA2
IS08Center/LFE/
Audio Control
IS10Center
Equalizer
IS05Front
Equalizer
SCL2
SDA2
SCL2
SDA2
IS01DAC3SCL2
SDA2
I403Sub VideoChroma
PST1
Deflection PWB
Signal PWB
I701
9
12
8
11
13
DSPUnit
HC4051
PMU1
5
6I401
A/V SelectSCL1
34
33
SDA1
FCEN
SCL2
SDA2
SCL2
SDA2
10
11
12
4
5
4
5
17
16
17
16
14
15
3
2
SCL1
SDA1 IOO2EEPROM
5
6
SDA1
SCL1
I004DAC2SDA1
SCL1
14
1514
15
SDA1
SCL1I003DAC1
SCL3
SDA3
58
57
SCL3 IS11Rear
Audio ControlSDA3
Terminal PWB
3
4
5
4
DSPSS
DSPSCK
DSPERR Mute
DSPI
DSPRST
FEENABLE2 43 17
U202Tuner 2
Pinp
16
Clock
Data
15Enable
6Enable
U201Tuner 1
MainFEENABLE1 44
5
Clock
Data
433
34 SDA2
SCL22
1
DP-05 & DP-05F MICROPROCESSOR DATA COMMUNICATION Description
PAGE 02-19
DP-05 and DP-05F DATA COMMUNICATIONS DESCRIPTION Refer to the DP-05 and DP-05F Microprocessor Data Communication Circuit Diagram The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 Microprocessor Data Communication Circuit Diagram is; • The DP-05 and DP-05F doesn’t have the DSP Module. Therefore, it uses a SRS Surround PWB. There is no
Rear or Center Audio, so the Serial Data Communications (SCL3 and SDA3) to the Rear Audio B+ isn’t Used.
• The Data Communications to the Level Shift IC (I014) going to the (DSP) is not used. • The Rear Audio IC, Center Audio IC and the Center Graphic EQ IC are not used. • The Front Audio Control IC designation is (IA05). • The DAC3 IC designation is (IA01). All else remains the same. (See Next page for diagram).
DP-05 and DP-05F CHASSIS MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT DIAGRAM
PAG
E 02-20
IOO1
PSZ2
IX01Rainforest
RGB Processor
2H Video PWB
60
59
SCL2
SDA2
PSD2
Sweep Control
Surround PWB���������������������������������������������������
���������������������������������������������������
���������������������������������������������������
���������������������������������������������������
���������������������������������������������������
Clock
Data
U205FLEX
&PinP
PFC1
Enable
Clock
Data
FCENAble
1
2
17
16
SCL2
SDA2
SDA2
26
27
SCL22
1I201
Main VideoChroma33
34 SDA2
SCL2
���������������������������������������������������
���������������������������������������������������
���������������������������������������������������
���������������������������������������������������SDA2
SCL2 U2043DY/C
PYC1
2
3
2 I0143.3V -> 5VLevel Shift
3
4
18
17
16
20
21
46
PSU1
2
1
IS03Front
Audio ControlSCL2
SDA2
IS10Center
Equalizer
IS05Front
Equalizer
SCL2
SDA2
IS01DAC3SCL2
SDA2
I403Sub VideoChroma
PST1
Deflection PWB
Signal PWB
I701
5
6
I401A/V SelectSCL1
34
33
SDA1
FCEN
SCL2
SDA2
SCL2
SDA2
10
11
12
4
5
17
16
17
16
14
15
3
2
SCL1
SDA1 IOO2EEPROM
5
6
SDA1
SCL1
I004DAC2SDA1
SCL1
14
1514
15
SDA1
SCL1
I003DAC1
Terminal PWBFEENABLE2 43 17
U202Tuner 2
Pinp
16
Clock
Data
15Enable
6Enable
U201Tuner 1
MainFEENABLE1 44
5
Clock
Data
433
34 SDA2
SCL22
1
ON SCREEN DISPLAY (OSD) SIGNAL PATH DESCRIPTION
PAGE 02-21
The Microprocessor is responsible for generating On Screen Display (OSD) related to the Main Menu, Volume Control, Channel Number, Closed Caption Display, Clock, etc… It also generates the OSD for the Service Menu. However there are actually two different sources for generating OSD, the Microprocessor and the Digital Conver-gence Unit, (DCU). MICROPROCESSOR AS THE SOURCE FOR OSD: The Microprocessor receives information related to timing for H. Blanking and V. Blanking. These arrive at pins (49 and 55) respectively. The Microprocessor determines the position for each display using these signals as a timing pulse. When it’s necessary, the Microprocessor generates 1uSec pulses from pins (37 Red, 38 Green and 39 Blue) that are routed through the PSZ1 connector pins (14 Red, 16 Green and 18 Blue) and then through (QX07 Red, QX08 Green and QX09 Blue) and then sent to the Rainforest IC IX01 pins (39 Red, 38 Green and 37 Blue) as OSD signals. When the OSD signals are high, they turn on the output of the Red or Green or Blue chroma amps inside the Rainforest IC and output a pulse to the CRTs to generate that particular character in the particular color. HALF TONE PIN (40): This pin is responsible for controlling the background transparency of the Main Menu. When the customer calls up the Main Menu, they can select the CUSTOM section. Within the CUSTOM section is MENU BACK-GROUND. There are three selections for this, GRAY, SHADED, and CLEAR. • CLEAR: Selection turns off any background for the Menu and video is clearly seen behind the Menu. • SHADED: Selection add a transparent background which makes the Menu easier to see and also some of the
video behind the Menu. • GRAY: Selection generates a GRAY background for the MENU blocking video behind the Menu. This is accomplished by outputting any one of three different pulses from pin (40) of the Microprocessor. This signal is then routed through the PSZ1 connector pin (20) to the Rainforest IC IX01 pin (47) as YM signal which does the following: • CLEAR: No output during the display of the Menu. • SHADED: 1/2 Vcc pulse equal to the timing of the Menu background. • GRAY: Full Vcc equal to the timing of the Menu background. OSD BLANKING PIN (51): This pin is responsible for muting the video behind each character produced by the Microprocessor. This pulse is in exact time with the character, however it is slightly longer. In other words, just before any character is pro-duced, this pin goes high and just after any character turns off, this pin turns off. This clears up the video behind the OSD character to make it easier to read. OSD Blk is produced from pin (51) of the Microprocessor. This signal is then routed through Q013, then through Q007, through the PSZ1 connector pin (19) to the Rainforest IC IX01 pin (36) as YS1 signal which mutes the video. P Blk PICTURE BLANKING PIN (56): This pin is responsible for muting the video when the Microprocessor deems it necessary. This would be during power up or power off, child lock, channel change, or selecting a video input with no video input available. P Blk is produced from pin (56) of the Microprocessor. This signal is then routed through Q007, through the PSZ1 connector pin (19) to the Rainforest IC IX01 pin (36) as YS1 signal which mutes the video. CLOSED CAPTION DISPLAY FROM THE MICROPROCESSOR SOURCE: The Microprocessor is also responsible for stripping the Closed Caption Display (CCD) from within the Vertical Sync on horizontal line 21. It receives the composite video signal at pin (28). This signal is tapped off the main video path before it arrives at I005 pin (5). See Video Path Circuit Diagram and Explanation for Details. The tapped video is routed through Q021 to the Microprocessor at pin (28). See Sync Signal Path Circuit Diagram and Explanation for Details.
(Continued on page 22)
ON SCREEN DISPLAY (OSD) SIGNAL PATH DESCRIPTION
PAGE 02-22
(Continued from page 21)
DCU AS THE SOURCE: The DCU (Digital Convergence Unit) generates it’s own OSD patterns and text. The DCU generates these characters in the same fashion as the Microprocessor. The DCU generates Digital Red from pin (11), Digital Green from pin (12) and Digital Blue from pin (10) output from the PDG and then through (QK06 Dig Red, QK07 Dig Green and QK08 Dig Blue). The DCU characters are then routed through the PSD1 connector pins (2 Red, 4 Green and 6 Blue) and then through (QX01 Red, QX02 Green and QX03 Blue) and then sent to the Rainforest IC IX01 pins (35 Analog Red In, 34 Analog Green In and 33 Analog Blue In) as Digital Con-vergence graphic signals. When the DCU is activated by pressing the Service Only switch on the Deflection PWB, the DCU outputs a BUSY signal. This signal does two things. 1. It tells the Microprocessor to ignore Infrared Remote commands. It does this by outputting the BUSY sig-
nal from pin (10) of the PDG connector and then through the PSD1 connector pin (1). Then to I004 the Analog to Digital converter. The Analog to Digital converter outputs this information in digital form through the I2C bus to the microprocessor. The I2C data is output from pin (14 SDA1 and 15 SCL1) and arrives at the Microprocessor I001 pins (2 and 3). When the Microprocessor receives this BUSY signal, it ignores all Infrared Remote commands.
2. It blanks video so that the DCU graphics can be see easily. This is accomplished by the same BUSY signal being routed from pin (10) of the PDG connector and then through the PSD1 connector pin (1). It is then routed through the PSZ1 connector pin (7) to the Rainforest IC IX01 pin (32) as YS2 signal which mutes video.
GRAPHICS PRODUCED BY THE DCU: • Cross hatch grid. • Colored Cursor which blinks indicating the adjustment point • Different text such as, Read from ROM?, Write to ROM? • Light pattern for Sensor Initialization • Light pattern for Magic Focus. • The DCU can also turn off individual colors during adjustment. Everything except Green. This is accom-
plished by not producing the particular color’s characters from the DCU.
OSD Blue
OSD Green
OSD Red
OSD YS
DP-0X CHASSIS "On Screen Display, OSD" SIGNAL CIRCUIT DIAGRAM
I001 Main uP
OSD B
OSD G
OSD R
Signal PWB
DigitalConvergence
Unit"DCU"
"Mounted onDeflection
PWB"
Deflection PWB
UKDGHC2151
PDG
10 BUSY 1
4567
321 -5V
+5V
+5V SRAM
H Blk
D SizeV Blk
IX01Rainforest
PSD1
1
QX36
QX31
To CR
Ts
B
G
R
41
42
43
QX41P Blk
OSD Blk
PZC
5
3
1
Signal SUB PWB
Dig B13 26Dig G
412 4Dig R
11 62
PAG
E 02-23
393837
56
51
3
2
28Sync for Closed Captionand V-Chip Data
30Sync2 for Closed Captionand V-Chip Data
Main
Sub
PSZ1
181614
Q00719
OSD YM40Half Tone 20
Q013
12
10
8
7
I004DAC2
15
14
SCL1
SDA1
10BUSY
373839
33
34
35
32
47
36
Analog B In
YS1
YM
Analog G In
Analog R In
B Out
G Out
R Out
YS2
Analog B In
Analog G In
Analog R In
QK08
QK07
QK06
QX03
QX02
QX01
QX09
QX08
QX07
AUDIO and VIDEO MUTE SIGNAL PATH DESCRIPTION
PAGE 02-24
V MUTE 1 EXPLANATION: There are certain times when the Microprocessor or other circuits must Mute the video or audio. The Microproc-essor is responsible for Muting the Audio/Video during Channel Change, Power On/Off, Child Lock, AVX Se-lected with no input, etc…. This is accomplished via pin (45) of the Microprocessor. When V Mute is activated, a high is routed through D028 to the base of Q022 turning it ON. The collector goes low and pulls the base of Q023 low turning it ON. The emitter of Q023 is connected to STBY +11V, so when it turns ON, it’s collector output goes HIGH. This high is now called V Mute 1. V Mute 1 is routed to two circuits, for Video Mute and for Audio Mute. FOR VIDEO MUTE: There are three different signals that mute video on the Rainforest IC, IX01 pin (25 FBP In):
1. V Mute 1 high is routed through the PSZ2 connector pin (6) to DX08. DX08 sends this high to the base of QX18 turning it OFF. The emitter of QX18 is connected to the SW +9V line and when it turns OFF the emitter pulls up HIGH. This pulls up pin (25) of IX01 the rainforest IC and Mutes the Video. Oddly enough, this high is sent into the same pin as the Flyback Pulse used for horizontal blanking. So it can be thought of as an extremely long blank pulse.
2. H Blk FC which is generated by the Flex Converter U205 at pin (12 H.BLK). This positive going blank-ing signal generated in time with Horizontal Sync from the main picture is routed through the PSZ2 con-nector pin (12) to DX09 to the base of QX18 turning it OFF with each positive going pulse. The emitter of QX18 is connected to the SW +9V line and when it turns OFF the emitter pulls up HIGH. This inputs positive horizontal blanking signals into pin (25) of IX01 the rainforest IC and Mutes the Video. This signals is used for horizontal blanking.
3. V Blk FC which is generated by the Flex Converter U205 at pin (11 V.BLK). This positive going blank-ing signal generated in time with Vertical Sync from the main picture is routed through the PSZ2 con-nector pin (13) to DX10 to the base of QX18 turning it OFF with each positive going pulse. The emitter of QX18 is connected to the SW +9V line and when it turns OFF the emitter pulls up HIGH. This inputs positive vertical blanking signals into pin (25) of IX01 the rainforest IC and Mutes the Video. This sig-nals is used for vertical blanking.
V Mute 1 FOR AUDIO MUTE: The V Mute 1 signal is also routed to the base of Q024 turning it ON. The high produced on it’s emitter is now called V Mute 2 which is routed to two places.
1. To the anode of DC04, to the base of QC03 which turn ON and grounds pin (11) of IC01 placing the Front Audio output IC into Mute.
2. To PSU1 connector pin (14) which mutes the Center and Rear audio output ICs. See the Surround Mute Circuit diagram and explanation for details.
ERRMUTE pin (18) of the Microprocessor: When the Microprocessor deems it necessary to mute the audio, it outputs a ERRMute signal from pin (18) to I014 pin (7) the Level Shift IC. This IC outputs the high from pin (13) to three places;
1. To the Audio DSP circuit via the PSU2 connector pin (6) to mute the internal functions of the DSP. See the Surround Mute Circuit diagram and explanation for details.
2. To the Surround PWB via the PSU1 connector pin (7) called Mute. Here the audio outputs for out to Hi-Fi, Transmitter out and Sub woofer are muted. See the Surround Mute Circuit diagram and explanation for details.
3. To the anode of DC01, then to the base of QC01 and QC02 which grounds the audio input to pin (4 Right audio in and 2 Left audio in) of IC01.
(Continued on page 25)
AUDIO and VIDEO MUTE SIGNAL PATH DESCRIPTION
PAGE 02-25
(Continued from page 24)
F.Spk Off FRONT SPEAKER OFF: When the customer accesses the Main Menu and selects the Front Speaker Off selection, DAC IS01 on the Sur-round PWB outputs a high from pin (6), see the Surround Mute Circuit diagram and explanation for details. This high is routed through the PSU1 connector pin (6) to the anode of two diodes;
1. To the anode of DC03, to the base of QC03 which turn ON and grounds pin (11) of IC01 placing the Front Audio output IC into Mute.
2. To the anode of DC02, then to the base of QC01 and QC02 which grounds the audio input to pin (4 Right audio in and 2 Left audio in) of IC01.
AC LOSS DETECTION: AC is monitored by the AC Loss detection circuit. The AC input from PQS1 pin (10) is rectified by DN09. This charges up C009 and through DN08 it charges C008. When AC is first applied, C008 charges slightly be-hind C009 preventing activation of Q001. If AC is lost, C009 discharges rapidly pulling the base of Q001 low, however DN08 blocks C008 from discharging and the emitter of Q001 is held high. This action turns on Q001 and produces a high. This high is routed through D029 to the base of Q022 turning it ON. The collector goes low and pulls the base of Q023 low turning it ON. The emitter of Q023 is connected to STBY +11V, so when it turns ON, it’s collector output goes HIGH. This high is now called V Mute 1. V Mute 1 is routed to two cir-cuits, see V Mute 1 explanation on the previous page. SPOT: SPOT is generated from the deflection PWB when either Horizontal or Vertical deflection is lost. This is to pre-vent a horizontal or vertical line from being burnt into the CRTs. See Horizontal and Vertical Sweep Loss De-tection circuit and explanation for details. This high is input from PSD2 pin (6), through D027 to the base of Q022 turning it ON. The collector goes low and pulls the base of Q023 low turning it ON. The emitter of Q023 is connected to STBY +11V, so when it turns ON, it’s collector output goes HIGH. This high is now called V Mute 1. V Mute 1 is routed to two circuits, see V Mute 1 explanation on the previous page.
Right Ft. Audio
Left Ft. Audio
RX52
F. Spk Off
Q023
R192
I001
DP-0X Series Chassis AUDIO and VIDEO MUTE Circuit(See also Surround Mute Circuit)
D027
2
D028
D030
D031
V. Mute 1
Micro Processor
V MUTE
IX01
25 FBPIn
"SPOT"Horizontal Sweep Loss Det.
Vertical Sweep Loss Det.(From Deflection PWB)
IC01
FRONTL&RAudioOutput
Mute
CC03
4
2
R In R Out
L In L Out
CC04
11
13
2H Video PWB
Signal PWB
PAG
E 02-26
SBY +11V
45 A5V
CC01
CC027
12
Mute = Lo
DN08
RN
15
C008
R007C009
DN09
PQS1
R00
8From I904
Pin 3AC PhotoCouplerAC Sig
Q001
10 R010
D029
R193
R194
Q022
R029
R190 R191
R198
C070
V Mute 1
R195
Q024
R196
V Mute 2
DC04
ERRMuteQC02
RC04
QC01RC03
QC03RC07DC03
RC08CC08
RC09
CC09
QX18
12
6
H Blk FC
V Blk FC DX10
DX09
DX08
RX57
SW+9V
6
8
9
7
DC02
DC01
14V Mute 2
From IS01 Pin 6
18 I0147
6
13
ERR Mute
ERRMuteLevel Shift
Mute
AudioDSP
Surround PWB
VM
ute
R01
1
PSZ2PSD3
PSU2
PSU1
10V p/p
DP-05 & DP-05F AUDIO and VIDEO MUTE SIGNAL CIRCUIT DESCRIPTION
PAGE 02-27
DP-05 and DP-05F AUDIO and VIDEO MUTE SIGNAL CIRCUIT DESCRIPTION Refer to the DP-05 and DP-05F Audio and Video Mute Circuit Diagram The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 AV Mute Circuit Diagram is; • The DP-05 and DP-05F doesn’t have the DSP Module. Therefore, it uses a SRS Surround PWB. There is no
Rear or Center Audio, so the Mute to the Rear and Center Audio ICs isn’t Used. • The (DSP) is not used. So ERRMUTE isn’t routed to the Surround PWB DSP module. All else remains the same. (See Next page for diagram).
Right Ft. Audio
Left Ft. Audio
RX52
F. Spk Off
Q023
R192
I001
DP-05 and DP-05F Series Chassis AUDIO and VIDEO MUTE Circuit(See also Surround Mute Circuit)
D027
2
D028
D030D031
V. Mute 1
Micro Processor
V MUTE
IX01
25 FBPIn
"SPOT"Horizontal Sweep Loss Det.
Vertical Sweep Loss Det.(From Deflection PWB)
IC01
FRONTL&RAudioOutput
Mute
CC03
4
2
R In R Out
L In L Out
CC04
11
13
2H Video PWB
Signal PWB
PAG
E 02-28
SBY +11V
45 A5V
CC01
CC02 7
12
Mute = Lo
DN08
RN
15
C008
R007C009
DN09
PQS1
R00
8From I904
Pin 3AC PhotoCouplerAC Sig
Q001
10 R010
D029
R193
R194
Q022
R029
R190 R191
R198
C070
V Mute 1
R195
Q024
R196
V Mute 2
DC04
ERRMuteQC02
RC04
QC01RC03
QC03RC07DC03
RC08CC08
RC09
CC09
QX18
12
6
H Blk FC
V Blk FC DX10
DX09
DX08
RX57
SW+9V
6
8
9
7
DC02
DC01
14V Mute 2
From IA01 Pin 12
18 I0147
13ERR Mute
ERRMuteLevel Shift
Mute
SRSPWB
VM
ute
R01
1
PSZ2PSD3
PSU1
10V p/p
SURROUND PWB MUTE SIGNAL PATH DESCRIPTION
PAGE 02-29
V Mute 2 FOR SURROUND MUTE: The V Mute 1 signal explained in the Audio Video Mute signal path explanation is also routed to the base of Q024 turning it ON. The high produced on it’s emitter is now called V Mute 2 which is routed to the Surround PWB via the PSU1 connector pin (14). V Mute 2 is labeled VMute on the Surround PWB. This high arrives at the anode of the following diodes;
1. DS27 which puts a high on the base of QS06 turning it ON which grounds pin (11) of IC15 placing the Center Audio output IC into Mute.
2. DS49 which puts a high on the base of QS20, turning it ON. This grounds the Sub Woofer audio output. 3. DS45 which puts a high on the bases of QS17 and QS16. Turning them ON. This grounds the Out to Hi-
Fi outputs. 4. DS37 which puts a high on the base of QS10, turning it ON. This grounds the Rear audio output
ERRMUTE PIN 7 of the PSU1 CONNECTOR: The ERRMute signal explained in the Audio Video Mute signal path explanation is routed to the Surround PWB via the PSU1 connector pin (7). See the Audio Video Mute Signal Path explanation and diagram for details con-cerning the generation of the ERRMute signal. ERRMute is labeled Mute on the Surround PWB. This high arrives at the anode of the following diodes;
1. DS24 which puts a high on the base of QS04 and QS05 turning them ON. This grounds the audio input to the Center audio output IC, IS15 at pins (4 and 2).
2. DS48 which puts a high on the base of QS20, turning it ON. This grounds the Sub Woofer audio output. 3. DS44 which puts a high on the bases of QS17 and QS16. Turning them ON. This grounds the Out to Hi-
Fi outputs. 4. DS34 which puts a high on the base of QS08 and QS09 turning them ON. This grounds the audio input
to the Rear audio output IC, IS16 at pins (4 and 2). ERRMUTE PIN 14 of the PSU2 CONNECTOR: The ERRMute signal explained in the Audio Video Mute signal path explanation is routed to the Surround PWB via the PSU2 connector pin (6). ERRMute places the DSP Audio Module into Mute when the Microprocessor deems it necessary. See the Audio Video Mute Signal Path explanation and diagram for details concerning the generation of the ERRMute signal. RSpkOff (REAR SPEAKER OFF) IS01 PIN 4: The Rear Speaker Off signal is output from IS01 pin (4). This high arrives at the anode of the following diodes;
1. DS36 which puts a high on the base of QS10 turning it ON which grounds pin (11) of IC16 placing the Rear Audio output IC into Mute.
2. DS35 which puts a high on the base of QS08 and QS09 turning them ON. This grounds the audio input to the Rear audio output IC, IS16 at pins (4 and 2).
CSpkOff (CENTER SPEAKER OFF) IS01 PIN 4: The Center Speaker Off signal is output from IS01 pin (5). This high arrives at the anode of the following diodes;
1. DS26 which puts a high on the base of QS06 turning it ON which grounds pin (11) of IC15 placing the Center Audio output IC into Mute.
2. DS25 which puts a high on the base of QS04 and QS05 turning them ON. This grounds the audio input to the Rear audio output IC, IS15 at pins (4 and 2).
FSpkOff (FRONT SPEAKER OFF) IS01 PIN 6: The Front Speaker Off signal is output from IS01 pin (6). This high is routed out the PSU1 connector pin (6) and sent to the Signal PWB into the V Mute Circuit. See the Audio Video Mute Circuit Signal Path Explanation and Diagram for more details.
Mute
Sub Woofer
SurroundDSP
Module
F. Spk Off
DP-0X Series Chassis SURROUND MUTE Circuit(See also Audio Video Mute Circuit)
IS15
CENTERAudioOutput
Mute
CSJ5
4
2
C In C Out
C In C Out
CSJ4
11
PAG
E 02-30
CSJ3
CSJ27
12
Mute = Lo
ERRMute
QS05RS04
QS04RS03
QS06
CSJ9CSK01
6
7
14V Mute 2
6ERR Mute
IS01
6
8
Mute
VMute
IS16
REARAudioOutput
Mute
CSM4
4
2
R In R Out
L In L Out
CSM3
11
CSM2CSM1
7
12
Mute = Lo
QS08RSJ5
QS09RSJ6
QS10RSJ7
RSJ8CSM8
RSJ9
CSM9
DS37
DS27
CENTER
DS26
VMute
Mute
CSpkOff
REAR R
REAR L
DS36
RSpkOff
DS35
DS34
QS20
DS24
DS48
DS25
DS49
SD50
HiFi L
QS17
DS44
SD47
HiFi R
QS16 SD46
DS45
5
4RSpkOff
F. Spk OffRSF5
RSF6
RSF7PSU1
PSU2 PMU1
DP-05 and DP-05F SRS MUTE SIGNAL CIRCUIT DESCRIPTION
PAGE 02-31
DP-05 and DP-05F SRS MUTE SIGNAL CIRCUIT DESCRIPTION Refer to the DP-05 and DP-05F SRS Mute Circuit Diagram The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 AV Mute Circuit Diagram is; • The DP-05 and the DP-05F doesn’t have the DSP Module. Therefore, it uses a SRS Surround PWB. There is
no Rear or Center Audio, so the Mute to the Rear and Center Audio ICs isn’t Used. • The (DSP) is not used. So ERRMUTE isn’t routed to the Surround PWB DSP module. All else remains the same. (See Next page for diagram).
F. Spk Off
DP-05 and DP-05F Series Chassis SRS MUTE Circuit(See also Audio Video Mute Circuit)
PAG
E 02-32
ERRMute
6
7
14V Mute 2
IA01
12
Mute
VMute
F. Spk Off
PSU1
HiFi L
QA11
HiFi R
QA12DA04 DA16
DA08 DA11
SCL2 1 2 SCL
SDA2 2 3 SDA
R100
PAGE 02-33
I001MicroProcessor
CLOCKKEY-IN1
7
1 2 PP1 Connector
Jumper
WARNING: This should only be done in extreme cases. I2C Data will be reset as well.Be sure and write down all data values before continuing.
Ø Disconnect Power to Television.Ø Remove the Back Cover.Ø Remove the two screws holding the Main chassis to the Cabinet if necessary.Ø Disconnect wiring harness clips to free up the chassis if necessary.Ø Reconnect Power to the Television and turn the set ON.Ø Locate PP1 and add a jumper between pins 1 and 2 of the PP1 connector as shown below.Ø Hold jumper in place for 5 seconds. (A beep will NOT be heard).Ø Remove the jumper.Ø Confirm EEPROM reset, Input source is now set to Air and not to Cable 1 or 2. No Child
Lock, and only channels 2 through 13 are in memory.Ø Reassemble Chassis and reinstall PTV back. Set is now ready to operate.
NOTE: All customers' Auto Programming and Set-Ups are returned to factory settings.
D024
DP-0X MEMORY INITIALIZATION PROCEDURE(EEPROM RESET)
20
R1E4
3.3V
MEMORY SWITCH SETTINGS ON SET FROM FACTORYTo Access Service Menu, press and hold INPUT then POWERNTSC SIGNAL INPUTPAGE 01 PAGE 02ADJUST MODE HP DP062b TA1300 NTSC
Sub Brit H Posi 30Service
FLEX CONTDef Reset 47 VD-Pos 3FV/P Reset UPD640813DYC Reset DYGA 09Flex Reset DCGA 06DSP Reset VAPGA 05CCD Reset VAPIN 0BFact Reset YHCOR 00Mem Init
PAGE 03 PAGE 04TA1270-M FLEX CONT NTSC
TINT (TV) 3C 39 HHPF1 00TOFFO (TV) 00 41 V-CRG 00TOFQ 00 42 H-CRG 00Sub CNT 0F 43 V-ENH 00Sub Clr 1B 44 H-ENH 00
96 YVHENH 0B100 CVHENH 12
PAGE 05 PAGE 06FLEX CONT NTSC FLEX CONT NTSC71 YV-ENH 00 97 YV NLP 0079 CV-ENH 00 98 YH NLP 0A87 YH-ENH 07 101 Y-LMT FF94 CH-ENH 0F 83 YH FTQ 0066 YV-DSB 00 91 CY FRQ 0275 CV-DSB 00 70 YV LTI 0082 YH-DSB 00 78 CV CTI 0090 CH-DSB 00 86 YH LTI 0168 YV-CLP 00 93 CH CTI 0184 YH-CLP 00
PAGE 07 PAGE 08FLEX CONT NTSC FLEX CONT NTSC69 YVDSBC 00 65 YNRRDC 0077 CVDSBC 00 74 CNRRDC 0085 YHDSBC 00 67 YNR-DC 0092 CHDSBC 00 76 CNR-DC 0095 Y-CRG 00 81 YNR-O 0099 C-CRG 00 89 CNR-O 0064 YNR-IN 04 45 CB-BLK 0773 CNR-IN 04 46 CR-BLK 0780 YNRPAS 00 27 FRMBRT 6088 CNRPAS 02 102 CLPOUT 7F
PAGE 02-34
MEMORY SWITCH SETTINGS ON SET FROM FACTORYPAGE 09 PAGE 10FLEX CONT NTSC FLEX CONT NTSC10 MPLL-S 0F 23 V-POS 1F17 SPLL-S 0F 24 VSIZ 7F12 MPLL-E 0F 50 HD-POS 3F19 SPLL-E 0F 48 VBLK-T 7F11 MVW-PH 05 49 VBLK-B 7F18 SVW-PH 05 51 HBLK-R 7F14 MHS-HP 0F 52 HBLK-L 7F21 SHS-HP 0F 40 READ-F 1013 MY-CLP 0320 SY-CLP 03
PAGE 11 PAGE 12FLEX CONT NTSC FLEX CONT NTSC35 FRMTOP-2 07 120 TV/CINE 01
FRMTOP-L 07 121 T/C DET 0736 FRMBTM-2 07 122 T/C UNL 01
FRMBTM-L 07 123 T/C LCK 0337 FRM RGT 07 126 T/C ARE 0538 FRM LFT 07 127 T/C CBR 0759 BS-TOP 07 128 T/C YBR 0760 BS-BTM 0761 BS-RGT 0762 BS-LFT 07
PAGE 13 PAGE 14TA1298 NTSC TA1298 NTSC
SHARP 0C COLOR 40APACON 06 TINT 45YNR 00 R-Y PH 02
R/B GH 01G-Y PH 00G/B GH 00Color System00
PAGE 15 PAGE 16TA1298 NTSC TA1298 NTSC
RGB BRT 50 CLRG 00RGB CNT 50 CLT 00G DRV (W) 39 YOUTG 00B DRV (W) 2D YGPNT 00SUB CLR 10 S TRK 00SUB CNT 1F RGBG 00VSM PH 05 DC PNT 00VSM GA 00 DC RAT 00OS ACL 01 DC LMT 00RGB ACL 00
PAGE 02-35
MEMORY SWITCH SETTINGS ON SET FROM FACTORYPAGE 17 PAGE 18TA1298 NTSC V CHIP RATINGS
BSP 03 POLLING 0FAPL/BS 00 TIMEOUT 05B COR 01 STATUS 02B GA 00B DET 00 AFC/CLOCK TESTDABL PN 00DABL GA 07ABL PN 07ABL GA 05
PAGE 02-36
DP-0X SERIES CHASSIS DAC 1 and DAC 2 INFORMATION
PAG
E 02-37
Detects IR from Remote for Auto Link Remote Set Up1
2
I003
YN Det
IR Det
DAC1
Detects the presents of Luminanace Sync from the Main Signal Path Active Low
3Blk Main Inputs Blanking for Main Signal to the Flex Converter
4MTS Places the Main Tuner into MTS mode if Stereo MTS Detected by Microprocessor
5F Mono Places the Main Tuner into Forced MONO mode
6ANT Switches the Antenna Switch Assembly from Antenna 1 to Antenna 2
7Blk Sub Inputs Blanking for Sub Signal to the Flex Converter
9SAP Det Receives the Low from the Main Tuner indicating SAP signal received.
10ST Det Receives the Low from the Main Tuner indicating Stereo signal received.
14SDA Serial Data from Microprocessor
15SCL Serial Clock from Microprocessor
8 Gnd
16 Vcc
11 Not Used
12 Not Used
13 Not Used
Detects Component 1 input activity1
2
I004
YUV/Det2
YUV/Det1
DAC2
Detects Component 2 input activity
3FH Det Not Used
4SEL5 Select 5 output. Controls Chromal Rotation Switch IX02 on 2H Video PWB. Hi = NTSC Lo = Y Cr/Cb
531/33 Output Deflection Frequency Control 31.5 kHz or 33.75 kHz.
6FH Det 2 Not Used
7G Power Not Used
9C/S Sel Not Used
10Busy Receives Busy from DCU stopping Microprocessor from responding to Remote commands.
14SDA Serial Data from Microprocessor
15SCL Serial Clock from Microprocessor
8 Gnd
16 Vcc
11 Not Used
12 Not Used
13 Not Used
SECTION 3
POWER SUPPLY INFORMATION
POWER SUPPLY ON AND OFF (STAND-BY) OPERATION EXPLANATION
PAGE 03-01
Use the DP-0X Series Power On and Off Diagram along with this explanation: The power supply in the DP-0X chassis works very similar to the previous models, with only a few exceptions. This power supply runs all the time when the AC is applied. The use of the power supply creating Stand By Volt-age supplies eliminates the need for a Stand-By transformer. The following explanation will describe the Turning ON and OFF of the projection television. The Microprocessor I001 generates the ON-OFF control signal from pin (53). The logic states of this pin are High = On and Low = Off. When the set is turned On, the high from pin (53) is routed to the Relay Driver Q002 base. This turns on Q002 and it’s collector goes low. This On/Off from the Relay Driver Q002 will perform the following : • Turns on the SW5+V I907 and SW+12V I908 regulators. Which do not operated in Standby. • Turns on the Shut Down “Power Shorted” detection circuit, Q908 and Q909. • Turns on the Horizontal Vcc supply to the Horizontal and Vertical drive IC, I701. • Turns on the Relay providing AC to the Deflection Power Supply on the Power/Deflection PWB. TURNING ON and OFF THE HORIZONTAL DRIVER B+ CIRCUIT: (See Figure When the power supply goes into Stand-By mode (TV Off), the Horizontal Drive signal for deflection is shut off. This is accomplished by Q002 and QP04. The Low produced from the Power On/Off pin (53) of the Microproc-essor is inverted by Q002 located on the Signal PWB. This High is sent through the PQS1 connector pin (8) to the Sub Power Supply PWB and then through PQD2 connector pin (1) and sent to the Deflection PWB. This High is detected by the base of QP04 turning it Off and the SBY +11V connected to the emitter is not available at the collector. The collector is routed through DP35 and DP36 and connected to the Deflection B+ pin of the Horizontal and Vertical Drive IC, I701 at pin (8). This action stops I701 from producing a horizontal deflection drive signal.
C705
Signal PWB
115
8 Def.B+
Hoz. Out
To Horz.DriveTransistor QH01
Deflection PWBPQD2SBY +11V
QP04
53
PowerOn/Off
I001
Micro
BB
Q002C E
C
I701H/V Driver IC
OFF = LowOn = High
3
OFF = HighOn = Low
8
PQS1
Sub PowerSupply PWB
DP35
DP36
Figure 1
Continued on Next Page
POWER SUPPLY ON AND OFF (STAND-BY) OPERATION EXPLANATION
PAGE 03-02
I907SW+5V Reg
I908SW+12V RegPQS1
8
Q903
R951
R937
A9.65V
OFF = Lo0V
SW+5V
SW+12V
0V
+28V
5
1
1
5
2
2
3
3
53PowerOn/Off
I001 Micro
ON = Hi3.3V Q002
Figure 3
I902Regulation
Photocoupler2 3
Cold Gnd. Hot Gnd.
D923
Normal Freq. 80 ~ 100KHzPin 4 > 1.4V = Normal
Pin 4 < 1.4V = 200KHz.
I901
Freq. Control &
Power SupplyDriver & Output IC
Inhibit PC Line 2
R912
Raw B+150V
28V Line
1
3
Q902
R946
R947
R948
R918R919R9200.22each
Figure 2
SW+12V AND SW+5V REGULATOR OPERATION IN STAND-BY: (See Figure 3) Both of these ICs as well as the STY+11V and the STY+7V regulators are DC to DC converters just like last year. This is because of the wide range of input voltages from Stand-By to Normal operation of the Power Sup-ply. The SW+12V regulator (I908) and the SW+5V regulator (I907) are shut off during Stand-By mode. This is accomplished by Q002 and Q903. The Low from the Power On/Off at pin (53) of the Microprocessor is in-verted by the relay driver Q002 to a High and routed through the PQS1 connector pin (8). It is detected by Q903 base. The collector will go Low and pull pin (5) of I907 and I908 Low, turning off the two DC to DC converters.
POWER SUPPLY OPERATIONAL FREQUENCY DURING STAND-BY: (See Figure 2) When the Horizontal deflection is defeated, the power supply no longer has a deflection load. This low current demand is detected by the three resistors connected to the source of the internal Switch MOS FET inside I901 via pin (2). Pin (1) of I901 is the over current detection pin, however it is also the current demand sensing pin. When the current demand is low due to horizontal defeat, pin (1) will be less than 1.4V and the internal fre-quency will switch to 200Khz. This is caused by the Quasi Resonant circuit operation. This reduction of power supply frequency will move the frequency above the Bell of the power supply trans-former and all secondary voltages will reduce to approximately 1/2 of their normal voltage. Due to the fact that the power supply is still operating at 1/2 voltage output, the Green LEDs used for visual trouble sensing will reduce in intensity, however they will remain lit. With the exception of the SW+12V and SW+5V regulator. Which are turned off in Stand By. See Figure 2.
Continued on Next Page
Continued From Previous Page
POWER SUPPLY ON AND OFF (STAND-BY) OPERATION EXPLANATION
PAGE 03-03
TURNING ON THE DEFLECTION POWER SUPPLY: (See Figure 5) When the Projection Television is turned On, the Microprocessor outputs a high from Pin (53) which is in-verted by Q002. This Low is routed through the connector PQS1 pin (8) on the signal PWB to the Sub Power Supply PWB. This Low is routed to Q903s Base and its collector will go High. This will pull up pin (5) of I907 and I908, turning ON the two DC to DC converters. The output of both DC to DC converters I907 and I908, are used by the relay which supplies AC voltage to the Deflection Power Supply on the Power/Deflection PWB. The output of I907 SW+5V Regulator supplies B+ for pin (3) of the relay S901. The output of I908 SW+12V Regulator drives the base of Q911 turning it On and grounding pin (4) of the re-lay S901. The relay now provides AC to the bridge rectifier on the Deflection Power Supply.
Q903R957
R958
Q908 Q909D946
To Gate ofQ914
ShutdownSCRR959
6 Shutdown Inputs,Active Low
+28V
C948
C949
Power/Deflection PWB
D945
PQS1
8On = LoOff = Hi
35PowerOn/Off
I001 Micro
Q002R951
R950
Figure 4
Off
I001Micro-
processor
53 PQS1
8
PowerOn/Off
+28VON = HiOFF = Lo
I907SW+5V Reg IC
5
1
I908SW+12V Reg IC
1
5
2
2
3
3
Q002
D928
D948
Q903R951
On
Q9114
3
1
2
S-901 Def. PowerSupply RelayAC In
PQD1
1AC for Def. PowerSupply 2
SW+12V
SW+5V
SW+12V
SW+5V
Power/Deflection PWB Sub Power Supply PWB
Signal PWB Figure 5
SOME SHUT-DOWN DETECTION CIRCUITS SHUT OFF DURING STAND-BY: (See Figure 4) During Stand-By, all of the secondary voltages produced by the Switching Transformer (T901) are reduced to approximately 50% of their normal voltage, except the STBY voltages after regulation. This could cause a po-tential problem with the Short Detection circuits for shutdown. To avoid accidental shut down, Q903 also con-trols the activity of Q908 and Q909. During Stand-By, the output from the Microprocessor On/Off pin (35) is Low. This Low is inverted by Q002 and this High is routed to the base of Q903 turning it On. This allows the Base of Q908 to be pulled Low through D945. This action turns off Q908. When Q908 is off, it doesn’t supply emitter voltage to the collector of Q909. The base of Q909 is connected to 6 Low Detection inputs, (See the Sub Power Supply Shut Down Circuit explanation and diagram for further details). When the power supply operates at 50%, the Short Detection circuit could activate. By turning off Q909, no accidental shut down op-eration can occur.
Continued From Previous Page
Off
Power On/Off
DP-0X SERIES "POWER ON & OFF" DIAGRAM
I001Microprocessor
53 PQS1
8
R958D946
To Gate of Q905(Shutdown SCR)
R959
6 ShutdownInputs,
Active Low
PowerOn/Off
+28V
C948
C949
ON = HiOFF = Lo
Sub Power PWB
Signal PWB
RP36
CP44
HVcc
CP45
Power/Deflection PWB
I701H Drive IC
15 8Def.B+Hoz. Out
Signal Sub PWB
C701
2.35V
I907SW+5V Reg IC
5
1
I908SW+12V Reg IC
1
5
2
2
3
3
VDD3.3V
L004Q026
R029
D034C075
1
C074
STB
Y+5V
3.3V
3.9V
3.3V
61 54
Reset
I006Reset
2
3
1
SBY11V
3.3V3.3V
C032
R053
I905STBY+7V
2
D035
PAG
E 03-04
Q002
I008STBY+5V
13
2
STBY +7V
PQS2
D928
D948
R949
R950
+28V
D947
PQD2
1DP21
RP38
RP37
QP04DP35
DP36
3
L701
I906STBY+11V
2
2
3
Q909Q908
R957
D945
Q903R951
Off On
On
Q9114
3
1
2
S-901 Def. PowerSupply Relay
AC InPQD1
1AC for Def.Power Supply 2
SW+12V
SW+5V
SW+12V
SW+5V
Power/Deflection PWB
C705
11.1V
10.4V
11.1V11.55V
7.28V
25.96V
11.9V
25.96V
25.25V
5.78V
BOTH OFF IN STBY
OV in STBY
OV in STBY
OV in STBY
OFF IN STBY
11.1V STBY
LEDs USED FOR VISUAL TROUBLE SHOOTING DESCRIPTION
PAGE 03-05
SUB POWER SUPPLY VISUAL LEDs. DP-0X Chassis has 5 Green and 1 Red LED on Sub Power Supply PWB. This chassis utilizes 5 Green LED’s in the power supply cold side and a Red LED in the HOT side. The power supply operates it two different modes, Standby and Projection On mode. STANDBY MODE: 4 Green LED’s and the Red LED are lit in the standby mode with the AC applied and the TV OFF; • D903 Indicating Vcc applied to the Power Supply Driver IC Color RED • Audio Front 29V Regulator SW+29V indicated by D912 Color GREEN • Audio Rear and Center 29V Regulator SW+29V indicated by D913 Color GREEN • STBY+11V Regulator I906 indicated by D949 Color GREEN • STBY+7V Regulator I905 indicated by D927 Color GREEN POWER ON MODE: When the Power is turned ON, the other LED lights and the Red LED remains lit as well; • D903 Indicating Vcc applied to the Power Supply Driver IC Color RED • SW+5V Regulator I907 indicated by D931 LED USAGE: The Visual LEDs are very useful in Trouble Shooting. Without removing the back cover, some diagnostics can be made. By observing the operation of the Red and Green LEDs, the technician can determine if the Sub Power Supply is running or not. The following will examine each LED and how they are lit. D903 Indicating Vcc applied to the Power Supply Driver IC Color RED This LED indicates any of three different scenarios, 1. Is there B+ (Vcc) available to the Sub Power Supply Driver IC? LED will be ON 2. Is the B+ (Vcc) available to the Sub Power Supply Driver IC missing? LED will be OFF 3. Is the Set in Shut Down? LED will be OFF As can be see, there are two different scenarios that can cause D903 to be off, Missing Start up voltage for the Driver IC and/or the Sub Power Supply is in Shut Down. B+ GENERATION FOR THE SUB POWER SUPPLY DRIVER IC. See Figure 1 Vcc for the Driver IC is first generated by the AC input. This voltage is called Start Up Voltage. I901 requires 21V DC to operate normal. However, it will begin operation between 9~10V DC on pin (4) of I901. When AC is applied, AC is routed through the main fuse F901 (a 5 Amp fuse), then through the Line filters L901, 902, 903 and 904 to prevent any internal high frequency radiation for radiating back into the AC power line. Af-
(Continued on page 6)
Hot
SwitchingTransformer
T901
FUSEF901 5A
AC InputNoise FilterL901,2, 3,4
RectifierD901
Cold
SwitchingControl
I901
ProtectSCR Q901
D903 ProtectPhotocoupler
I903
RectifierD901
4
3
Figure 1
LEDs USED FOR VISUAL TROUBLE SHOOTING DESCRIPTION
PAGE 03-06
(Continued from page 5)
ter passing the filters it arrives at the main full wave bridge rectifier D901 where it is converted to DC voltage. One leg of the AC is routed to a half wave rectifier D902 where it is rectified, routed through R905 and R906 (both a 5.6K ohm resistor), filtered by C907, clamped by a 30V Zener D904 and made available to pin (4) of I901 as start up voltage. The Red LED D903 is illuminated by this power supply. When this voltage reaches 9~10 Vdc, the internal Regulator of I901 is turned On and begins the operation of I901. Figure 2 is a simplified diagram of the main Power Supply used in the DP-0X series Projection Television chassis. The primary control element of the power supply is I901 (the Switching Regulator IC), in conjunction with transformer T901. These two components, along with the supporting circuitry, comprise a closed loop regulation system. Unlike previous Pulse Width Modulated (PWM) Switch Mode Hitachi power supplies, the regulation system in the this chassis utilizes Frequency Control Modulation with an operational frequency of 105KHZ. Primary regulation is provided by Q902, I902 and Q910, regulating the switching frequency at pin (3) of I901 via pin 1, the regulation input to the IC.
Three primary voltages are developed that are needed to sustain run, maintain regulation, and support shutdown circuitry; Run Voltage generated from pin (8 and 9) of T901, +28V used for regulation, and STBY +11V, respectively. The “STBY” represents “always on”, designating a supply that is active when the unit is connected to AC power. The Power Supply utilizes a Shutdown circuit that can trigger Q905 from 16 input sources. (6 of these are not op-erational in Stand By mode). I903 is activated by Q905, applying gate voltage to Q901, which grounds out the Vcc at pin (4) of I901, disabling the power supply. Audio Front 29V Regulator SW+29V indicated by D912 The Audio Front 29V supply is generated from pin (17) of T901. This output is protected by E992, rectified by D910 and filtered by C918. This supply is routed to the Rear Audio Output IC IC01. This voltage is what illuminates the Green Visual Trouble Shooting LED, D912.
(Continued on page 7)
T901Switch ModeTransformer
I902Opti-Coupler
I903Opti-Coupler
Q910Buffer
Q905SCR
28V
ShutdownInputs
AC
1
3DrainI901SwitchMode
ICRegulate
Q901SCR
4
Q902Buffer
Raw 150V
Run V
Figure 2
LEDs USED FOR VISUAL TROUBLE SHOOTING DESCRIPTION
PAGE 03-07
(Continued from page 6)
Audio Rear and Center 29V Regulator SW+29V indicated by D913 (Not in the DP-05F Chassis)/. The Audio Rear and Center 29V supply is generated from pin (16) of T901. This output is protected by E993, rectified by D911 and filtered by C917. This supply is routed to the Rear Audio Output IC IS16 and Center Audio Output IC IC15. This voltage is what illuminates the Green Visual Trouble Shooting LED, D913. STAND BY +11V REGULATOR: STBY+11V Regulator I906 indicated by D949 (Not on in Stand By mode.) The STBY+11V supply is generated from pin (11) of T901. This output is rectified by D918 and filtered by C928. This supply is routed to the Stand By +11 Regulator I906 pin (1). This voltage is what illuminates the Green Visual Trouble Shooting LED, D949. STAND BY +7V REGULATOR: STBY+7V Regulator I905 indicated by D927 The STBY+7V supply is generated from pin (11) of T901. This output is rectified by D918 and filtered by C928. This supply is routed to the Stand By +7 Regulator I905 pin (1). This voltage is what illuminates the Green Visual Trouble Shooting LED, D927.
65V
R907
I901Driver/Output IC
I903
100% Dead Time &IC B+ Detection
4
Osc B+
4R908
I903 ShutdownPhotocoupler
Q905Shutdown
SCR
D903 is a RED L.E.D.Off = No I901 B+
On = I901 Run Voltage OK
R933
Stby+11V
R930
Stby+7V
AudioFront 29V
Sw+5V
DP0X CHASSIS L.E.D. (VISUAL TROUBLE DETECTION) DIODES(SUB POWER PWB) SIGNAL POWER SUPPLY 5 GREEN L.E.D.s and 1 RED L.E.D.
(6 Total L.E.Ds. for visual trouble sensing observation)
3
1
2
Vcc
ALL GREEN L.E.D.s
16 Shut DownInputs
Run
11.97V Stby12.56V Run
AudioRear/C 29V
PAG
E 03-08
D913
D949 D927
D912
D931
Q901 Shutdown SCR
D903
Start Up
R905 R906
Not InDP05F
R926
R936
Not OnIn Stby
165KHz Stby105KHz
11.9V Stby13.56V Run
0V Stby0V Run
11.9V Stby12.23V Run
11.17V Stby11.55V Run
D905
From Pin 8 T901
D904C907
8.0V Stby30.67V Run
11.8V Stby11.9V Run
7.28V Stby7.39V Run
0.0V Stby5.78V Run
D902
LEDs USED FOR VISUAL TROUBLE SHOOTING DESCRIPTION
PAGE 03-09
DP-05 and DP-05F SUB POWER SUPPLY LEDs USED FOR TROUBLE SHOOTING Refer to the DP-05 and DP-05F LEDs used for Trouble Shooting Diagram The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 Sub Power Supply LEDs used for Trouble Shooting is that the DP-05 and DP-05F doesn’t have the DSP Module. Therefore, it uses a SRS Surround PWB. There is no Rear or Center Audio, so the LED for monitoring the Rear Audio B+ isn’t there. (D913) is not used. So there will only be (4) Green LEDs and (1) Red LED on the Sub Power Supply. All else remains the same. (See Next page for diagram).
65V
R907
I901Driver/Output IC
I903
100% Dead Time &IC B+ Detection
4
Osc B+
4R908
I903 ShutdownPhotocoupler
Q905Shutdown
SCR
D903 is a RED L.E.D.Off = No I901 B+
On = I901 Run Voltage OK
R933
Stby+11V
R930
Stby+7V
AudioFront 29V
Sw+5V
DP-05 and DP-05F CHASSIS L.E.D. (VISUAL TROUBLE DETECTION) DIODES(SUB POWER PWB) SIGNAL POWER SUPPLY 4 GREEN L.E.D.s and 1 RED L.E.D.
(5 Total L.E.Ds. for visual trouble sensing observation)
3
1
2
Vcc
ALL GREEN L.E.D.s
16 Shut DownInputs
Run
11.97V Stby12.56V Run
PAG
E 03-10
D949 D927
D912
D931
Q901 Shutdown SCR
D903
Start Up
R905 R906
R926
R936
Not OnIn Stby
165KHz Stby105KHz
11.9V Stby13.56V Run
0V Stby0V Run
11.9V Stby12.23V Run
11.17V Stby11.55V Run
D905
From Pin 8 T901
D904C907
8.0V Stby30.67V Run
11.8V Stby11.9V Run
7.28V Stby7.39V Run
0.0V Stby5.78V Run
D902
SUB POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
PAGE 03-11
Use this explanation in conjunction with the Sub Power Supply Shutdown diagram. The sub power supply in the DP-0x chassis works very similar to the previous models, with some very significant exceptions. This power supply runs at 50% efficiency when the AC is applied and the set is OFF. The use of the power supply creating the SBY+11V supply eliminates the need for a Stand-By transformer. The following explanation will describe the Turning ON and OFF of the projection television. Power Supply Frequency of Operation During Run and Stand By: When the Horizontal deflection is in operation, the power supply frequency fluctuates in accordance to current demands. The normal operational range for the power supply is 105 KHz. During Stand-By, it operates at 165KHz. Power Supply Shutdown Explanation This chassis utilizes I901 as the Osc.\Driver \Switch for the sub power supply, just as the previous chassis have done. This IC is very similar to the previous versions, however it does differ in Frequency, (described previously) and in Stand-By detection. The Shutdown circuit, (cold ground side detection), is routed to I901 via the following circuit, Q905 (the Shutdown SCR), I903 (the Photo Coupler), which isolates the Hot ground from the Cold ground and couples the Shutdown signal to the Hot Ground side, Q901 the hot ground side SCR and I901 pin (4) (the Vcc pin). The Power Supply utilizes a Shutdown circuit that can trigger Q905 from 16 input sources. (6 of these are not op-erational in Stand By mode). I903 is activated by Q905, applying gate voltage to Q901, which grounds out the Vcc at pin (4) of I901, disabling the power supply. All of the Power Supply Shutdown circuitry can be broken down into the following groups; • Voltage Missing Detection • Excessive Current Detection • Voltage Too High Detection In the following explanation, the Shutdown circuits will be grouped. This will assist the Service Technician with trouble shooting the Chassis, by understanding these circuits and having the associated circuit routs, the technician can then “Divide and Conquer”. Commonly Used Shutdown Detection Circuits Excessive Current Detection. (See Figure 1) One very common circuit used in many Hitachi television products is the B+ Excessive Current Sensing circuit. In this circuit is a low ohm resistor in series with the particular power supply, (labeled B+ in the drawing). The value of this resistor is determined by the maximum current allowable within a particular power supply. In the case of Figure 1, the value is shown as a 0.47 ohm, however it could be any low ohm value. When the current demand increases, the voltage drop across the resistor increases. If the voltage drop is sufficient to reduce the voltage on the base of the transistor, the transistor will conduct, producing a Shutdown signal that is directed to the appropriate circuit. Voltage Loss or Excessive Load Detection (See Figure 2 on next page) The second most common circuit used is the Voltage Loss Detection circuit. This is a very simple circuit that detects a loss of a particular power supply and supplies a Pull-Down path for the base of a PNP transistor.
(Continued on page 12)
0.47B+
Shut-Down Signal
Current Detection Resistor
Figure 1
Any PositiveB+ Supply
B+
Q1
Shut-DownSignal
VoltageLoss
Detector
Figure 2
SUB POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
PAGE 03-12
(Continued from page 11)
This circuit consist of a diode connected by its cathode to a positive B+ power supply. Under normal conditions, the diode is reversed biases, which keeps the base of Q1 pulled up, forcing it OFF. However, if there is a short or excessive load on the B+ line, the diode in effect will have a LOW on its cathode, turning it ON. This will allow a current path for the base bias of Q1, which will turn it ON and generates a Shutdown Signal. B+ Voltage Too High Detection. (See Figure 3) In this circuit, a Zener diode is connected to a voltage divider or in some cases, directly to a B+ power supply. If the B+ voltage increases, the voltage at the voltage divider or the cathode of the zener diode will rise. If it gets to a predetermined level, the zener will fire. This action creates a Shutdown Signal. Negative Voltage Loss Detection. (See Figure 4) The purpose of the Negative Voltage Loss detection circuit is to compare the negative voltage with its’ counter part positive voltage. If at any time, the negative voltage drops or disappears, the circuit will produce a Shutdown signal. In Figure 5, there are two resistors of equal value. One to the positive voltage, (shown here as +12V) and one to the negative voltage, (shown here as -12V). At their tie point, (neutral point), the voltage is effectually zero (0) volts. If however, the negative voltage is lost due to an excessive load or defective negative voltage regulator, the neutral point will go positive. This in turn will cause the zener diode to fire, creating a Shutdown Signal. DP-0X Shutdown Circuit There are a total of 16 individual Shutdown inputs. In addition, there are also two Shutdown inputs that are specifically detected by the main power driver IC, I901 that protect it from excessive current or over voltage. All of the Shutdown detection circuits can be categorized by the four previously described circuits Voltage Loss Detection • Shorted SW+2.5V on Signal PWB through Protect 1 to (D957) on Sub Power Supply PWB • Shorted SW+9V (D015) on Signal PWB through Protect 1 to (D959) on Sub Power Supply PWB • Shorted SW+5V (D014) on Signal PWB through Protect 1 to (D959) on Sub Power Supply PWB • Shorted SW+3.3V (D016) on Signal PWB through Protect to (D959) on Sub Power Supply PWB • Shorted Stby+3.3V on Signal PWB through Protect 2 to (D959) on Sub Power Supply PWB • Shorted Stby+5V (D032) on Signal PWB through Protect 2 to (D959) on Sub Power Supply PWB • Shorted Stby+9V (D007) on Signal PWB through Protect 2 to (D959) on Sub Power Supply PWB • Shorted Stby+3.3V (D016) on Signal PWB through Protect 2 to (D959) on Sub Power Supply PWB • SW+5V (D943) • SW+12V (D944) • Stby+7V (D955) • Stby+11V (D952)
(Continued on page 13)
Any PositiveB+ Supply
Voltage Too HighDetector
Shut-Down Signal Figure 3
NegativeVoltage
LossDetector
+12V -12V
Shut-Down Signal
Figure 4
SUB POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
PAGE 03-13
(Continued from page 12)
Negative Voltage Loss Detection • SW-12V Loss Detection (D939, D940) Excessive Current Detection • Not used in the Sub Power Supply. Voltage Too High Detection • SW+12V (D935, D936) • SW+5V (D932, D933) • Stby+11V (D941) • Stby+7V (D938) If any one of these circuits activate the power supply will STOP, and create a Power Supply Shutdown Condition. SOME SHUTDOWN CIRCUITS ARE DEFEATED IN STANDBY MODE. (Set Off). As indicated in the Power On/Off circuit diagram explanation, 6 of the 16 shut down inputs are not active when the set is in standby. • Shorted SW+2.5V on Signal PWB through Protect 1 to (D957) on Sub Power Supply PWB • Shorted SW+9V (D015) on Signal PWB through Protect 1 to (D959) on Sub Power Supply PWB • Shorted SW+5V (D014) on Signal PWB through Protect 1 to (D959) on Sub Power Supply PWB • Shorted SW+3.3V (D016) on Signal PWB through Protect to (D959) on Sub Power Supply PWB • SW+5V (D943) • SW+12V (D944) These SW voltage loss sensing circuits are defeated because the SW (Switched) power supplies are turned off in standby to prevent misoperation of the shutdown circuit. Q909 supplies the high for shutdown if any of the voltage loss circuits become activated. Q909 requires emitter voltage to operated. Emitter voltage is supplied from the emitter of Q908. Q908’s base is connected to Q903 which in turn is connected to the power on/off line. When the set is not on or turned off, the power on/off line goes high. This high is inverted to a low by Q903 and pulls the cathode of D945 low, removing the base voltage of Q908 turning it OFF. This removes the emitter voltage from Q909 and this circuit can’t function. SHUT DOWN CIRCUIT: Shut down occurs when the shutdown SCR Q905 is activated by gate voltage. When Q905 receives gate voltage of 0.6V, the SCR fires and give a ground path for the emitter of the LED inside I903. The light produced by turn-ing on this LED turns on the internal photo receiver and generates a high out of pin (3). This high is routed to the gate of Q901 turning it on. This grounds pin (4) of I901 removing Vcc and the power supply stops working. The reason for the photo sensor I903 is to isolate hot and cold ground. B+ GENERATION FOR THE SUB POWER SUPPLY DRIVER IC: Vcc for the Driver IC is first generated by the AC input. This voltage is called Start Up Voltage. I901 requires 12.7V DC to operate normal. However, it will begin operation at 9~!0V DC on pin (4) of I901. When AC is applied, AC is routed through the main fuse F901 (a 5 Amp fuse), then through the Line filters L901, 902, 903 and 904 to prevent any internal high frequency radiation for radiating back into the AC power line. Af-ter passing the filters it arrives at the main full wave bridge rectifier D901 where it is converted to Raw 150V DC voltage to be supplied to the power supply switching transformer T901 pin (1). However, one leg of the AC is routed to a half wave rectifier D902 where it is rectified, routed through R905 and R906 (both a 5.6K ohm resistor), filtered by C907, clamped by a 30V Zener D904 and made available to pin (4) of I901 as start up voltage. The Red LED D903 is illuminated by this power supply. When this voltage reaches 9~10VDC, the internal Regulator of I901 is turned On and begins the operation of I901. When the power supply begins to operate by turning on and off the internal Switch MOS FET, the Raw 150V DC routed through T901, in on pin 1 and out on pin 2 which is connected to pin (3) of I901 which is the Drain. The
(Continued on page 14)
SUB POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
PAGE 03-14
(Continued from page 13)
Source of the internal Switch MOS FET is routed out of pin (2) through three low ohm resistors to hot ground. This on and off action, causes the transformer to saturate building up the magnet field. When the internal Switch MOS FET turns off, the magnet field collapses and the EMF is coupled over to the secondary windings, as well as the drive windings. The drive windings at pin (8 and 9) produce a run voltage pulse which is rectified by D905, filtered by C908 then routed through R908, clamped by D904 and now becomes run voltage (12.7V) for I901.
I901Power
IC
4
R906R905D902
D904C907
R908 D905
C908
8
9
T901
AC
R909
Q901
C910R910
1
23
I903
4
28V
R945
R911
Sw+12V
Q905
C947
R955
Sw +12V
Sw +5V
Stby +7V
R941 R942
Sw-12V
D940 D939
D936 D935
D933 D932
D938
Stby +11VD941
D921
Q909
C949R959
Q908
R958
+28V
R957
D945Q903
On/Off
OnOff On
Off
D946
R960D944Sw +12V
D943Sw +5V
D957
D958Protect 1PQS2R198
Pin 10
D015Sw +9V
D014Sw +5V
D016Sw +3.3V
Sw +2.5V
Q912
C956R969
D951
R960D952
Stby +11V
D955
Stby +7V
D959
D960
Protect 2PQS2R014
Pin 11D032
Stby +5V
D007Stby +9V
Stby +3.3V
D954
D953
R968
R967 D956
11
12
DP-0X SIGNAL POWER SUPPLY (Low Voltage) SHUT-DOWN CIRCUIT
VinR960
D903
PAGE 03-15
LEDs USED FOR VISUAL TROUBLE SHOOTING DESCRIPTION
PAGE 03-16
DEFLECTION POWER SUPPLY VISUAL LEDs. DP-0X Chassis has 1 Green and 1 Red LED on Deflection Power Supply PWB. This chassis utilizes 1 Green LED in the power supply cold side and a Red LED in the HOT side. The power supply operates it two different modes, Standby and Projection On mode. POWER ON MODE: When the Power is turned ON, the LEDs lights; • DP37 Indicating Vcc applied to the Power Supply Driver IC IP01 Colored RED • DP29 Indicating 120V Deflection B+ is available Colored GREEN LED USAGE: The Visual LEDs are very useful in Trouble Shooting. Without removing the back cover, some diagnostics can be made. By observing the operation of the Red and Green LEDs, the technician can determine if the Deflection Power Supply is running or not. Remember, this power supply doesn’t operate when the set is in Standby. The following will examine each LED and how they are lit. DP37 Indicating Vcc applied to the Power Supply Driver IC IP01 Colored RED This LED indicates any of three different scenarios, 1. Is there B+ (Vcc) available to the Deflection Power Supply Driver IC? LED will be ON 2. Is the B+ (Vcc) available to the Deflection Power Supply Driver IC missing? LED will be OFF 3. Is the Set in Shut Down? LED will be OFF As can be see, there are two different scenarios that can cause DP37 to be off, (1) Missing Start up voltage for the Driver IC and/or (2) the Deflection Power Supply is in Shut Down. B+ GENERATION FOR THE DEFLECTION POWER SUPPLY DRIVER IC. See Figure 1 Vcc for the Driver IC is first generated by the AC input. This voltage is called Start Up Voltage. IP01 requires 10.7V DC to operate normal. However, it will begin operation at 9~10V DC on pin (4) of IP01. When AC is applied by the relay on the Sub Power Supply R901, AC is routed through the connector PQD1. Then it arrives at the main full wave bridge rectifier DP01 where it is converted to DC voltage. One leg of the AC is routed to a half wave rectifier DP02 where it is rectified, routed through RP02 and RP03 (both a 5.6K ohm re-sistor), filtered by CP05, and made available to pin (4) of IP01 as start up voltage. The Red LED DP37 is illumi-nated by this power supply. When this voltage reaches 9~10Vdc, the internal Regulator of IP01 is turned On and begins the operation of IP01.
(Continued on page 17)
4
Sub Power Supply Hot
SwitchingTransformer
TP91
AC InputRectifier
DP01
Cold
SwitchingControl
IP01DP37
RelayR901
ConnectorPQD1
Power/Deflection PWB
RectifierDP02
3
Figure 1
LEDs USED FOR VISUAL TROUBLE SHOOTING DESCRIPTION
PAGE 03-17
(Continued from page 16)
Figure 2 is a simplified diagram of the main Power Supply used in the DP-0X series Projection Television chassis. The primary control element of the power supply is IP01 (the Switching Regulator IC), in conjunction with transformer TP91. These two components, along with the supporting circuitry, comprise a closed loop regulation system. Unlike previous Pulse Width Modulated (PWM) Switch Mode Hitachi power supplies, the regulation system in the this chassis utilizes Frequency Control Modulation with an operational frequency of 60KHZ to 85KHZ, corresponding to full load and no load conditions, respectively. Primary regulation is provided by IP03, IP04 and into IP01, regulating the switching frequency at pin (3) of I901 via pin 1, the regulation input to the IC. Two primary secondary voltages are developed that are needed to sustain run and maintain regulation; 1. Run Voltage generated from pin (8 and 9) of TP91 rectified by DP03 and supplies run voltage to IP01 pin
(4) and 2. 120V Deflection Voltage generated from pin (13) of TP91, rectified by DP11 used for regulation and power-
ing the Deflection and regulation circuitry.
GREEN LED: 120V Deflection B+ DP29 The Deflection B+ 120V supply is generated from pin (13) of TP91. This output is rectified by DP11 and filtered by CP17. This supply is routed to the Horizontal Drive Circuit and the High Voltage generation circuit. This voltage is what illuminates the Green Visual Trouble Shooting LED, DP29.
TP91Switch ModeTransformer
IP04Opti-Coupler
120VDeflection B+
AC
1
3DrainIP01SwitchMode
ICRegulate
4
Raw 150V
Run V
IP03Regulator IC
DP29
DP37HOT COLD
Figure 2
DP0X CHASSIS L.E.D. (VISUAL TROUBLE DETECTION) DIODESDEFLECTION PWB 1 GREEN L.E.D.s and 1 RED L.E.D.
(2 Total L.E.Ds. for visual trouble sensing observation)
GREEN L.E.D.
120V Deflection B+
PAG
E 03-18
RP29
RP28
DP29
RP42
IP01Driver/Output IC
IP044
Osc B+
4
IP04 RegulatorPhotocoupler
DP37 is a RED L.E.D.OFF = IP01 B+ MissingMay be caused by Shut Down or Faulty Start up Circuit.ON = IP01 B+ OK
3
1
2
Vcc
17.5V
DP37
Start Up
RP02
RP03
1
IP03
2
IP03 Regulator
85KHz Blk Screen70KHz Pic Screen60KHz White Screen
17V
11.9V
10.7V3V
Run
DP03
From Pin 8 TP91
CP05
DP02 65V
2.1V
RP09
10.7V
DEFLECTION POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
PAGE 03-19
Use this explanation in conjunction with the Deflection Power Supply Shutdown diagram. POWER SUPPLY FREQUENCY OF OPERATION DURING RUN When the Horizontal deflection is in operation, the power supply frequency fluctuates in accordance to screen brightness, causing differing demands for High Voltage replacement. The normal operational range for the power supply is between 80 KHz to 100 KHz. The lower the frequency, the higher the current supplied to the load. During Stand-By, it operates at 200KHz. POWER SUPPLY SHUTDOWN EXPLANATION This chassis utilizes IP01 as the Osc.\Driver \Switch for the Deflection power supply, just as the previous chassis have done. This IC is very similar to the previous versions, however it does differ in Frequency, (described previously). The Shutdown circuit, (cold ground side detection), is used to turn off the Relay S901 via the follow-ing circuit, QP01 (the Shutdown SCR), Connector PQD2, Q911 the Relay Driver and the Relay S901. The Power Supply utilizes a Shutdown circuit that can trigger QP01 from 14 input sources. When any of these inputs cause a high on the gate of QP01, the relay disengages, disabling the deflection power supply. All of the Power Supply Shutdown circuitry can be broken down into the following groups; • Voltage Missing Detection • Excessive Current Detection • Voltage Too High Detection In the following explanation, the Shutdown circuits will be grouped. This will assist the Service Technician with trouble shooting the Chassis, by understanding these circuits and having the associated circuit routs, the technician can then “Divide and Conquer”. COMMONLY USED SHUTDOWN DETECTION CIRCUITS EXCESSIVE CURRENT DETECTION. (See Figure 1) One very common circuit used in many Hitachi television products is the B+ Excessive Current Sensing circuit. In this circuit is a low ohm resistor in series with the particular power supply, (labeled B+ in the drawing). The value of this resistor is determined by the maximum current allowable within a particular power supply. In the case of Figure 1, the value is shown as a 0.47 ohm, however it could be any low ohm value. When the current demand increases, the voltage drop across the resistor increases. If the voltage drop is sufficient to reduce the voltage on the base of the transistor, the transistor will conduct, producing a Shutdown signal that is directed to the appropriate circuit. VOLTAGE LOSS OR EXCESSIVE LOAD DETECTION (See Figure 2) The second most common circuit used is the Voltage Loss Detection circuit. This is a very simple circuit that detects a loss of a particular power supply and supplies a Pull-Down path for the base of a PNP transistor. This circuit consist of a diode connected by its cathode to a positive B+ power supply. Under normal conditions, the diode is reversed biases, which keeps the base of Q1 pulled up, forcing it OFF. However, if there is a short or excessive load on the B+ line, the diode in effect will have a LOW on its cathode, turning it ON. This will allow a current path for the base bias of Q1, which will turn it ON and generates a Shutdown Signal.
(Continued on page 20)
0.47B+
Shut-Down Signal
Current Detection Resistor
Figure 1
Any PositiveB+ Supply
B+
Q1
Shut-DownSignal
VoltageLoss
Detector
Figure 2
DEFLECTION POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
PAGE 03-20
(Continued from page 19)
B+ VOLTAGE TOO HIGH DETECTION. (See Figure 3) In this circuit, a Zener diode is connected to a voltage divider or in some cases, directly to a B+ power supply. If the B+ voltage increases, the voltage at the voltage divider or the cathode of the zener diode will rise. If it gets to a predetermined level, the zener will fire. This action creates a Shutdown Signal. NEGATIVE VOLTAGE LOSS DETECTION. (See Figure 4) The purpose of the Negative Voltage Loss detection circuit is to compare the negative voltage with its’ counter part positive voltage. If at any time, the negative voltage drops or disappears, the circuit will produce a Shutdown signal. In Figure 5, there are two resistors of equal value. One to the positive voltage, (shown here as +12V) and one to the negative voltage, (shown here as -12V). At their tie point, (neutral point), the voltage is effectually zero (0) volts. If however, the negative voltage is lost due to an excessive load or defective negative voltage regulator, the neutral point will go positive. This in turn will cause the zener diode to fire, creating a Shutdown Signal. DP-0X SHUTDOWN CIRCUITS FOR THE DEFLECTION POWER SUPPLY There are a total of 14 individual Shutdown inputs. In addition, there are also two Shutdown inputs that are specifically detected by the main power driver IC, IP01 that protect it from excessive current or over voltage. All of the Shutdown detection circuits can be categorized by the four previously described circuits VOLTAGE LOSS DETECTION 1. Shorted 220V (DP31 and DP32) Inverted by QP03 then through DP22 2. Shorted SW+8V (DP33) Inverted by QP03 then through DP22 3. Shorted 28V (DP30) Inverted by QP03 then through DP22 4. Shorted Side Pin Cushion Circuit (D760 and Q754) then through DP34 5. Shorted Deflection Transformer or Misoperation (D756 and Q754) then through DP34 6. Heater Loss Detection (DH26, DH27,QH07 and DP34) This voltage does not go to the CRTs. NEGATIVE VOLTAGE LOSS DETECTION 7. -M28V Loss Detection (DP23, DP24) 8. SW-8V Loss Detection (DP28, DP29) EXCESSIVE CURRENT DETECTION 9. 120V Deflection Power Supply (RP17, QP02, DP15, DP16 and DP18) 10. 28V Vertical IC I601 Power Supply (R645, Q609, D615, and DP34)
(Continued on page 21)
Any PositiveB+ Supply
Voltage Too HighDetector
Shut-Down Signal Figure 3
NegativeVoltage
LossDetector
+12V -12V
Shut-Down Signal
Figure 4
DEFLECTION POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
PAGE 03-21
(Continued from page 20)
Voltage Too High Detection 11. Excessive High Voltage Detection (DH31, RH54, RH55 and DH24). Sensed from the Heater Voltage gener-
ated from pin (5) of the Flyback Transformer TH01. Also, (DH42) sends a high command to the Horizontal Driver IC IH02, to defeat Horizontal Drive Output.
12. Side Pincushion failure generating a High. (D754, and D753). 13. Deflection B+ Too High. (DP17, RP21 and RP22). 14. Heater Voltage from the Deflection Power Supply Too High Detection. (DP27 and DP28) If any one of these circuits are activated, the power supply will STOP, and create a Power Supply Shutdown Condition. SHUT DOWN CIRCUIT: Shut down occurs when the shutdown SCR QP01 is activated by gate voltage. When QP01 receives gate voltage of 0.6V, the SCR fires and give a ground path for the pin (5) of Connector PQD2 called PROTECT. This Low is routed to the Sub Power Supply PWB and is impressed on the base of the Relay Driver Transistor Q911 turning it Off. When Q911 turns Off the Relay S901 will disengage and remove the AC source from the Deflection Power Supply. DESCRIPTION OF EACH SHUT DOWN CIRCUIT: Please use the Commonly Used Shutdown Detection Circuits for the description of how the circuit works. VOLTAGE LOSS DETECTION 1. Shorted 220V (DP31 and DP32) Inverted by QP03 then through DP22
The cathode of DP31 is connected directly to the 220V line. If it shorts this circuit is activated and pulls the base of QP03 low. This output High is routed through DP22 to the gate of the Shut Down SCR QP01.
2. Shorted SW+8V (DP33) Inverted by QP03 then through DP22 The cathode of DP33 is connected directly to the SW+8V line. If it shorts this circuit is activated and pulls the base of QP03 low. This output High is routed through DP22 to the gate of the Shut Down SCR QP01.
3. Shorted 28V (DP30) Inverted by QP03 then through DP22 The cathode of DP30 is connected directly to the 28V line. If it shorts this circuit is activated and pulls the base of QP03 low. This output High is routed through DP22 to the gate of the Shut Down SCR QP01.
4. Shorted Side Pin Cushion Circuit (D760 and Q754) then through DP34 The Side Pin Cushion circuit is comprised of I651, Q652 through Q657 If a problem occurred in this circuit that creates a Low on the cathode of D760, the low will be routed to the base of Q754, turning it Off. This output High is routed through DP34 to the gate of the Shut Down SCR QP01.
5. Shorted Deflection Transformer or Misoperation (D756 and Q754) then through DP34 The Deflection circuit generates the actual Drive signal used in the High Voltage section. If a problem occurs in this circuit, the CRTs could be damaged or burnt. D757 is connected to D759 which is nor-mally rectifying pulses off the Deflection Transformer T753. This rectified voltage is normally sent through D757, D756 to the base of Q754 keeping it On and it’s collector Low. If the Deflection circuit fails to produce the pulses for rectification, the base voltage of Q754 disappears and the transistor turns Off generating a High on its collector. This output High is routed through DP34 to the gate of the Shut Down SCR QP01.
(Continued on page 22)
DEFLECTION POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
PAGE 03-22
(Continued from page 21)
6. Heater Loss Detection (DH26, DH27,QH07 and DP34) This voltage does not go to the CRTs.
The Flyback Transformer TH01 generates a pulse called Heater. (Note: This does not go to the CRTs as heater voltage, its used for Excessive High Voltage Detection. If a problem occurs in this circuit, the Ex-cessive High Voltage Detection circuit wouldn’t operate. So it would be possible for there to be High Voltage but the circuit detecting Excessive High Voltage couldn’t work. DH26 is connected to DH24 which is normally rectifying pulses off the Flyback Transformer TH01. This rectified voltage is nor-mally sent through DH26, DH27 to the base of QH07 keeping it On and it’s collector Low. If the Heater Pulse fails to produce the pulses for rectification, the base voltage of Q754 disappears and the transistor turns Off generating a High on its collector. This output High is routed through DH30 to the anode of DP34 to the gate of the Shut Down SCR QP01.
NEGATIVE VOLTAGE LOSS DETECTION Please use the Commonly Used Shutdown Detection Circuits for the description of how the circuit works. 7. -M28V Loss Detection (DP23, DP24)
RP31 (18K ohm) is connected to the negative –M28V line and RP30 (22K ohm) is connected to the positive +29V line. The Cathode of DP23 monitors the neutral point where these two resistors are con-nected. If the negative voltage disappears, the zener DP23 fires. This high is routed through DP24 to the gate of the Shut Down SCR QP01 and Shut Down occurs.
8. SW-8V Loss Detection (DP28, DP29) RP26 (3.3K ohm) is connected to the negative SW-8V line and RP25 (3.3K ohm) is connected to the positive SW+8V line. The Cathode of DP28 monitors the neutral point where these two resistors are connected. If the negative voltage disappears, the zener DP28 fires. This high is routed through DP29 to the gate of the Shut Down SCR QP01 and Shut Down occurs.
EXCESSIVE CURRENT DETECTION Please use the Commonly Used Shutdown Detection Circuits for the description of how the circuit works.
9. 120V Deflection Power Supply (RP17, QP02, DP15, DP16 and DP18)
If an excessive current condition of the Deflection B+ is detected by RP17 a 0.47 ohm resistor, the base of QP02 would drop. This would turn on QP02 and the high produced at the collector would fire zener DP15. This High would be routed through DP16 through DP18 to the gate of the Shut Down SCR QP01 and Shut Down occurs.
10. 28V Vertical IC I601 Power Supply (R645, Q609, D615, and DP34) If an excessive current condition of the Vertical B+ is detected by R645 a 0.68 ohm resistor, the base of Q609 would drop. This would turn on Q609 and the high produced at the collector would be routed through D615 through DP34 to the gate of the Shut Down SCR QP01 and Shut Down occurs.
(Continued on page 23)
DEFLECTION POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
PAGE 03-23
(Continued from page 22)
VOLTAGE TOO HIGH DETECTION Please use the Commonly Used Shutdown Detection Circuits for the description of how the circuit works. 11. Excessive High Voltage Detection (DH31, RH54, RH55 and DH24). Sensed from the Heater Voltage
generated from pin (5) of the Flyback Transformer TH01. Also, (DH42) sends a high command to the Horizontal Driver IC IH02, to defeat Horizontal Drive Output
The Flyback Transformer TH01 generates a pulse called Heater. (Note: This does not go to the CRTs as heater voltage, its used for Excessive High Voltage Detection). If this voltage goes too high indicating an excessive High Voltage condition, the voltage divider comprised of RH54 and RH55 would impress a high on the cathode of DH31. This high is routed through DH34 to the gate of the Shut Down SCR QP01 and a Shut Down occurs.
12. Side Pincushion failure generating a High. (D754, and D753) The Side Pin Cushion circuit is comprised of I651, Q652 through Q657 If a problem occurred in this circuit that creates a High on the cathode of D754, the High will be routed through D753 to the gate of the Shut Down SCR QP01.
13. Deflection B+ Too High. (DP17, RP21 and RP22
RP21 and RP22 form a voltage divider. The top side of RP22 is monitored by DP17. If this voltage goes too high, the zener DP17 will fire. This high is routed through DP18 to the gate of the Shut Down SCR QP01 and Shut Down occurs.
14. Heater Voltage from the Deflection Power Supply Too High Detection. (DP27 and DP28) The Heater Voltage for the CRTs filament is generated in the Deflection Power Supply. This voltage is monitored by DP27. If this voltage goes too high, the zener DP27 will fire. This high is routed through DP28 to the gate of the Shut Down SCR QP01 and Shut Down occurs.
Pin 10I601
DP0X DEFLECTION POWER SUPPLY SHUTDOWN DIAGRAM
PAGE 03-24
QP01ShutDown
S.C.R.
DP18
DP34 HeaterLoss Det.
Excessive HighVoltage Det.
Side Pin FailureHigh Det.
Side PinFailure
Low Det.
PreventsProtect
Misoperation
Deflection TransformerInoperative Det.
DP22X-RAY
PROTECT
QP03
DP23
DP24
-M28V
RP31 RP30
+28V
DP28
DP29
SW-8V
RP26 RP25
SW+8V
DP27
DP28
RP27
Heater from Def. Power Supply.Goes to CRT's
DP32DP31
DP33SW+8V
DP30
DP11
CP33
DP15 DP17
13
TP91
Deflection B+ (120V)Excessive Voltage Det.
Deflection B+ 120V
QP02
RP21
RP22
RP170.47
Deflection B+ (120V)Excessive Current Det.
Q609
R6450.68
FlybackTH01
Vertical CircuitExcessive Current Det.
5 5OPDH24
DH26
QH07
DH30
QH08
D753
Q754
1
6 7
8
Deflection B+ 120V V1
Q777
D759
C769
H.Blk
D757 D756
D760
T752
-28V Loss Det. SW-8V Loss Det. Heater Too High Det.
220V Short Det.
28V Short Det.
SW+8V Short Det.
DP16
DH27
Doesn'tgo toCRT's
S12V
Q911
5
PQD2
SpotKiller Off On
28V
D615
SW+12V
D754
SW+5V
4
3
1
2
S-901Def. Power
Supply Relay
AC In
PQD1
1 AC for Def.Power Supply2
220V
28V
RH54
RH55
DH42
DH31
IH02 7OVP
9.46V
9.36V
9.01V
29.01V
23V
SECTION 4
VIDEO INFORMATION
I401 - Luminance Audio Selector IC Main Tuner (TV1V) in pin 63 Sub Tuner (TV2V) in pin 60
Video 1 in from Terminal PWB pin 8 S-Video 1 (Y) from Terminal PWB pin 10 S-Video 1 (C) from Terminal PWB pin 12
Video 2 in from Terminal PWB pin 1 S-Video 2 (Y) from Terminal PWB pin 3 S-Video 2 (C) from Terminal PWB pin 5
Video 3 in from Front Control PWB pin 15 S-Video 3 (Y) from Front Control PWB pin 17 S-Video 3 (C) from Front Control PWB pin 19
Yin1 PinP Luminance from 2L Comb filter pin 49 Cin1 PinP Chroma from 2L Comb filter pin 51 VOut1 PinP Video to 2L Comb filter pin 53 YOut1 PinP (Y) to Sub video processor pin 56 COut1 PinP (C) to Sub video processor pin 58
V/YOut2 Main Video or S-Video (Y) to 3DYC pin 44 COut2 S-Video (C) to 3DYC pin 47
VOut3 Video out to Monitor pin 41 YOut3 S-Video (Y) out to Monitor pin 39 COut3 S-Video (C) out to Monitor pin 37
I201 - Main Video Chroma Processor IC Main video in (Y) pin 40 Main video in (C) pin 6
Y out pin 37 R-Y Out pin 48 B-Y Out pin 47
I403 - Sub Video Chroma Processor IC Sub video in (Y) pin 40 Sub video in (C) pin 6
Y out pin 37 R-Y Out pin 48 B-Y Out pin 47
2 Line Comb Filter (PinP) Video In pin 4 Y Out pin 1 C Out pin 3
3DYC Comb Filter (Main) Video/Y in pin 11 C in pin 13 Y Out pin 9 C Out pin 7
Video Circuit Block Diagram Explanation
Page 04-01
U2043DYC
PinP VY
PinP C
S-Y1S-C1
PinP TUNER (Mono)Always PinP
DP-0X SERIES CHASSIS VIDEO SIGNAL PATH (Main & Terminal)
I401
53
49
Lum/Audio Selector IC
23
103V
VOut1
U202
Avx 3 In
PinPVideo
17
15
60
Terminal PWBSignal PWB 1 of 2
Front Control PWB
19
MainVideoNTSC
Aux Input 3
V1 810
Aux Inputs
U201Main Tuner
63Q205
53
S-Y3S-C3
19S-3 In
S-1 In12
S-Y2S-C2
V2 13
S-2 In5
YIn1
2Line
CombFilter
V In
Y Out
C Out
S Det.
S Det.
S Det.56
PinP Yout1
18
Q206
14TV1V
TV2V
4
1
351CIn1
41Vout3
Q409 Monitor Out
58PinP C Cout1
39
37
Q410 Q411
Y/S Monitor Out
Yout3
Cout3
Q405
Q404
I40340
6
V3V
PST1
Q403
Q406
Q408
3748
47
YR-Y
B-Y
See Component Signal FlowDiagram for Continuation
44Q402
47Q401
V/Yout2
Cout2
Main Y/Video
13
9
Main C
PST2
5
7
I201
40
6
37
48
Q216
Q213
Q235
Q214
Main Y/Video
PFT
Sub Video Route
PAG
E 04-02
PYC1
11
7
Main Y/Video
Main C
MainVideo/
Chroma
Signal PWB 2 of 2Terminal PWB
47
B-Y/CB Out
R-Y/CROut
Y
CB
CR
I401 - Luminance/Audio Select IC VIn4 Comp 1 (Y) When component video is 480i this is used for CCD, as well as the Auto Link function. VIn5 Comp 2 (Y) When component video is 480i this is used for CCD, as well as the Auto Link function. I406 - Main Component 1 / Component 2 Select IC Selects either Component 1 or Component 2 (Y/CbPb/CrPr). Outputs to I205. I205 - Main Video / Component Select IC Selects either Component 1 or 2 (Y/CbPb/CrPr) from I406 and Main (R-Y/B-Y/Y) from I201. Outputs to Flex Converter Main inputs. I407 - Sub Component 1 / Component 2 Select IC Selects either Component 1 or Component 2 (Y/CbPb/CrPr). Outputs to I404. I404 - Sub Video / Component Select IC Selects either Component 1 or 2 (Y/CbPb/CrPr) from I407 and Sub (R-Y/B-Y/Y) from I403. Outputs to Flex Converter Sub inputs. Flex Converter Receives Main R-Y/B-Y/Y from I205 and Sub R-Y/B-Y/Y from I404. Combines the two sets of signals (Main and Sub). Converts output signals to 2H (31.75kHz) YCbCr unless signals are already 31.75kHz or higher. YCbCr to YIQ Converter Level/phase shifts color difference signals. IX02 - YCbCr / YIQ Select IC Selects either YCbCr or YIQ color difference signals. YIQ is selected by microprocessor via I004 DAC2 sensing NTSC input on Comp 1 or 2. Outputs to IX01. IX01 - Rainforest IC Receives the three color difference signals from IX02. Outputs to the three CRT PWBs.
Component Video Circuit Block Diagram Explanation
Page 04-03
Sub B-Y Cb Out
Sub Y Out
Sub R-Y Cr Out
Main B-Y Cb Out
Main Y Out
Main R-Y Cr Out
DP-0X SERIES CHASSIS COMPONENT SIGNAL PATH (Main & Terminal)Lum/Audio Selector IC
Terminal PWB
Component 1Inputs
Cr/Pr
Cb/Pb
Y
Component 2Inputs
Y
Cb/Pb
Cr/Pr
30
22
Comp 2 forAuto Link
Comp 1forAuto Link
161
3
1114
5
98
6
I4061
21
21
2
Q439
Q438
Q437
Q434
Q435
Q436
I401
Y
Cb/Pb
Cr/Pr Q427
Q426
Q425
71
21
93
19
115
15
I2051
21
21
2
Q232
233 Q23413Q229
Q230 Q23111Q226
Q227 Q2289
PST2
13
145
86
I4071
21
21
2
Y
Cb/Pb
Cr/Pr
17
21
39
19
511
15
I4041
21
21
2
Q416
Q417 Q418Q419
Q420 Q421Q422
Q423 Q424
PST2
5
4
3
U205
PFC1
19
17
15
48
47
37
I403
19
18
17
Sub B-Y Cb Out
Sub Y Out
Sub R-Y Cr Out
FL
EX
CO
NV
ER
TE
R
I20148
47
37
TerminalPWB
Signal PWB
Signal PWB
11
16
Cr/Pr1
Cr/Pr2
Cb/Pb2
Y2
Y1
9
Q440
Q441
Q442
16
18
20
PFC2
15
17
19
PSZ22H Y
2H B
2H R
2H Y
2H CB
2H CR
PAG
E 04-04
PZC 2H Video PWB
To CRT PWB
IX01
Rainforest
Y2 In
CB/Q
CR/I
5242QX36
3G
5343QX31
1R
QX21
5141QX41
5B
YCBCR to YIQCONVERTER
Q22~27 & 54,55
IX02YCBCR/YIQSELECTOR
See Chroma After Flex Converter Sig. Diagram
Q414
Q413
Q412
Main PicturePreparation IC
Sub PicturePreparation IC
DP-05 & DP-05F COMPONENT VIDEO CIRCUIT BLOCK DIAGRAM
PAGE 04-05
DP-05 and DP-05F COMPONENT VIDEO CIRCUIT BLOCK DIAGRAM DESCRIPTION Refer to the DP-05 and DP-05F Component Signal Path (Main & Terminal) Circuit Diagram The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 Component Video Circuit Diagram is; • The DP-05 and DP-05F PinP circuit doesn’t route the Component inputs to the PinP Signal route into the
Flex Converter. Therefore, the PinP in the DP-05 and DP-05F only produces NTSC inputs routed through the Selector IC.
• The Sub Component Selector IC (I407) is not used. • The Sub Component/NTSC Signal Selector IC (I404) is not used. All else remains the same. (See Next page for diagram).
Sub B-Y Cb Out
Sub Y Out
Sub R-Y Cr Out
Main B-Y Cb Out
Main Y Out
Main R-Y Cr Out
DP-05 and DP-05F SERIES CHASSIS COMPONENT SIGNAL PATH (Main & Terminal)Lum/Audio Selector IC
Terminal PWB
Component 1Inputs
Cr/Pr
Cb/Pb
Y
Component 2Inputs
Y
Cb/Pb
Cr/Pr
30
22
Comp 2 forAuto Link
Comp 1forAuto Link
161
3
1114
5
98
6
I4061
21
21
2
Q439
Q438
Q437
Q434
Q435
Q436
I401
Y
Cb/Pb
Cr/Pr Q427
Q426
Q425
71
21
93
19
115
15
I2051
21
21
2
Q232
233 Q23413Q229
Q230 Q23111Q226
Q227 Q2289
PST2
Q416
Q417 Q418Q419
Q420 Q421Q422
Q423 Q424
PST2
5
4
3
U205PFC1
19
17
15
48
47
37
I403 19
18
17
Sub B-Y Cb Out
Sub Y Out
Sub R-Y Cr Out
Sub PicturePreparation IC
Main PicturePreparation IC
FLEX C
ON
VER
TER
I2014847
37Terminal
PWB
Signal PWB
Signal PWB
Cr/Pr1
Cr/Pr2
Cb/Pb2
Y2
Y1
16
18
20
PFC2
15
17
19
PSZ22H Y
2H B
2H R
2H Y
2H CB
2H CR
PAG
E 04-06
PZC 2H Video PWB
To CRT PWB
IX01
Rainforest
Y2 In
CB/Q
CR/I
5242QX36
3G
5343QX31
1R
QX21
5141QX41
5B
YCBCR to YIQCONVERTER
Q22~27 & 54,55
IX02YCBCR/YIQSELECTOR
See Chroma After Flex Converter Sig. Diagram
Q414
Q413
Q412
U205 - Flex Converter Receives Main R-Y/B-Y/Y from I205 and Sub R-Y/B-Y/Y from I404. Combines the two sets of signals (Main and Sub). Converts output signals to 2H (31.75kHz) Y/Pb/Pr unless signals are already 31.75kHz or higher. YCbCr to YIQ Converter Consists of QX22-QX27, QX52-QX55 Level/phase shifts color difference signals. IX02 - YCbCr / YIQ Select IC Selects either YCbCr or YIQ color difference signals. YIQ is selected by microprocessor via I004 DAC2 sensing NTSC input on Comp 1 or 2. Outputs to IX01. IX01 - Rainforest IC Receives the three color difference signals from IX02. Outputs to the three CRT PWBs. Note: Three Color Difference signals can be: RGB R-Y/B-Y/Y CrCbY PrPbY YIQ YUV (U, Q, and Blue all rhyme)
Chroma After Flex Converter Block Diagram Explanation
Page 04-07
DP-0X CHROMA ROTATION CIRCUIT EXPLANATION
PAGE 04-08
(I)1230
(U)00
(Q)330
(V)900
330
QUESTION: What is the function of QX22, QX23, QX24, QX25, QX26 and QX27 on the output of the 3D Y/C Comb filter. See Chroma After Flex Converter Diagram schematic for details. FROM: Alvie Rodgers C.E.T. Technical Trainer. ANSWER: The RGB Processor IX01 (TA1298AN) has a function called Skin Tone correction. This circuit is also named “Auto Color or Auto Flesh Tone”. The Auto Color function works only with Y/I-Q signals. The YUV signal out of the Comb filter must be converted to YIQ before entering IX01 (Rainforest IC) in order to use “Auto Color”. Y Pr/Pb YUV signals must be converted. IQ signals are made from UV signal by giving them a 330 phase shift. See figure below for details. The Switching IC IX02 shown on the Chroma After Flex Converter Diagram selects either the NTSC Y/IQ signal without rotation or the Y Pr/Pb with rotation as deter-mined by the control signal Select 5 (SEL5). Select 5 logic: High = Y/IQ (NTSC) and Low = YUV (Y/Pr/Pb). Not shown is the input pin for Select 5 (SEL5) control signal. This control signal is in-put via pin (5 and 12).
The V Signal is rotated 33 degrees to Convert it to an I signal.
The U Signal is rotated 33 degrees to Convert it to a Q signal.
DP-0X SERIES CHASSIS CHROMA AFTER FLEX CONVERTER SIGNAL PATH
PAG
E 04-09
CB/Q
CR/I
18
20
PFC2
17
19
PSZ2
2H B
2H R
2H CB
2H CR
QX25
QX23
QX22
2H CB
2H CB
2H CR
2H CRQX24
QX54
QX26
QX55
QX27
2H C
R 2H C
B
I
Q
11
IX021
21
2
14
1
QX52
QX53 Q
II
Q16
2H CB
51
52
IX01
5
3U/Q In
V/I In
Rainforest ICRGB Processor
YCBCR/YIQSelector
YCBCR YIQCONVERTER
FL
EX
CO
NV
ER
TE
R
U205
Signal PWB
2H VIDEO PWB
2
12SEL5 High = NTSC Low = Y Pr/Pb
I401 - Luminance Audio Selector IC VOut1 PinP (Sub) Video to I005 Main/Sub Select IC and also to I001 microprocessor for Sub CCD. V/YOut2 Main Video or S-Video (Y) to I005 Main/Sub Select IC and also to I001 microprocessor for Main CCD. VIn4 Component 1 Y in for CCD (480i only) and Auto Link. VIn5 Component 2 Y in for CCD (480i only) and Auto Link. Component Inputs (Y) Component 1 (Y) to I015 Component 1 Sync Separator IC. Component 2 (Y) to I016 Component 2 Sync Separator IC. I015 - Component 1 Sync Separator IC Vertical sync out goes to I001 microprocessor IC Comp 1 VFDet. Horizontal sync out goes to I005 Main/Sub Select IC. I016 - Component 2 Sync Separator IC Vertical sync out goes to I001 microprocessor IC Comp 2 VFDet. Horizontal sync out goes to I005 Main/Sub Select IC. I005 - Main/Sub Select IC Select control from I001 microprocessor SD Sel (Station Detect) Low = Main, High = Sub Three separate sets of inputs/outputs, (only first two shown in graphic) pin 3 Sub Video (In) pin 5 Main Video (In) pin 4 Sub/Main SD Det (Out) pin 2 Comp 1 H sync (In) pin 1 Comp 2 H sync (In) pin 15 Comp 1/2 HFDet (Out) pin 12 Sub AFC (In) pin 13 Main AFC (In) pin 14 Sub/Main AFC (Out) I001 - Microprocessor IC Sub video in on pin 30 for CCD. Main video in on pin 28 for CCD. Component 1 vertical frequency detect on pin 10, from I015. Component 2 vertical frequency detect on pin 11, from I016. Component 1/2 horizontal frequency detect on pin 22, from I005. SD Select out on pin 50 to control I005 during Sub picture changes; example PinP CH up or down. Main/Sub SD detect in on pin 24 from I005.
Sync Circuit Block Diagram Explanation
Page 04-10
TV1V
TV2V
S-Y1S-C1
PinP TUNER (Mono)Always PinP
DP-0X SERIES CHASSIS SYNC SIGNAL PATH
I401
Lum/Audio Selector IC
23
103V
VOut1
U202
Avx 3 In
PinPVideo
17
15
60
Terminal PWB
Signal PWB 2 of 2
Front Control PWB
19
MainVideoNTSC
Aux Input 3
V1 810
Aux Inputs
U201Main Tuner
63Q205
53
S-Y3S-C3
19S-3 In
S-1 In12
S-Y2S-C2
V2 13
S-2 In5
S Det.
S Det.
S Det.
18
Q206
14
V3V
PST1
PFT
PAG
E 04-11
3
PST2
Sub Video
VOut2
5
Main Y/Video
I005Z1
Z0
3
5
Q210
Q208
I001
Q019 Q018
4
24
Main SubSD Det
I003
53
44
Q403
Q402
Q02128
Main forCCD
30
Sub for V. ChipData
Q031
Q017
2
Q016
YN Det
SDA1
SCL1
SCL1
SDA1
2
3
15
14
SIGNAL PWB 1 of 2
Composite 2
Composite 1
I015Comp 11 4 10
I016Comp 21 4 11
PST1
8
9
Q434
Q437
Q431
Q433
Component 1 Y
Component 2 Y
Sync Sep Comp 1
Sync Sep Comp 2
Composite 3
Aux Input 1
Aux Input 2
Also, see Main/Component SyncSeparation Circuit Diagram
MicroProcessor
Lo = MAINHi = SUB
Lo
Hi
Vert FreqDet Comp1
Vert FreqDet Comp2
Y0
Y1
15
Q046
22
2
2
Com
p 1
H O
ut
Com
p 2
H O
ut
2
1
Comp1/2FHDet
DAC1
22
30
For 480iComp
Only CCD& V Chip
Comp1 In
Comp2 In
I406 - Main Component 1 / Component 2 Select IC Selected Y output on pin 6. I207 - Main Component Sync Separator Y in on pin 1 H out on pin 2 V Out on pin 4 I203 - Sync Inverter H sync from I207 is inverted and applied to I202. I201 - Main Video Chroma Processor (NTSC) Main Video in (Y) on pin 40 Vertical sync out on pin 13 Horizontal sync out on pin 14 I202 - Main Sync Selector Selects either Main NTSC H and V sync or Main Component H and V sync. Select 3 controlled by DAC2 line from I201 Main Video Chroma Processor IC. Outputs selected H and V sync to I203 Sync Inverter IC. I407 - Sub Component 1 / Component 2 Select IC Selected Y output on pin 6. I408 - Sub Component Sync Separator Y in on pin 1 H out on pin 2 V Out on pin 4 I409 - Sync Inverter H sync from I408 is inverted and applied to I405. I403 - Sub Video Chroma Processor (NTSC) Main Video in (Y) on pin 40 Vertical sync out on pin 13 Horizontal sync out on pin 14 I405 - Sub Sync Selector Selects either Sub NTSC H and V sync or Sub Component H and V sync. Select 4 controlled by DCOut line from I401 Luminance Audio Select IC. Outputs selected H and V sync to I203 Sync Inverter IC. I203 - Sync Inverter Inverts incoming signals Outputs (Main H, Main V, Sub H, Sub V) go to Flex Converter for PinP timing purposes. Main H labeled MHW at Flex Converter Main V labeled MVW at Flex Converter Sub H labeled SHW at Flex Converter Sub V labeled SVW at Flex Converter
Component Sync Separation Block Diagram Explanation
Page 04-12
SHW
I406 See VideoSignal PathV.Out
H.Out
I409
DP-0X SERIES CHASSIS MAIN/COMPONENT SYNC SEPARATION SIGNAL PATH
See ComponentSignal Path (Main)
PAG
E 04-13
PTS2
Q223
I207
1
4
2
V.Sync Out
H.Sync Out
2
3
I2021
2
1
2
1
I2035 6
I201MainVideo/
Chroma
13
14
Q224
5
10 11
4
5
12 13
10
9
2 1
4 3
U2058
7
15
14
PTS3
3
1Sub H. Sync
Sub V. Sync
I4051
2
1
2
15
10
9
4
Q428
2
I403
4 2
14
40
13
H.Out
V.Out
3
I4084
2
5
Q415Q442
1
TERMINAL PWB
SIGNAL PWB
Flex C
onverter
MHW
MVW
SVW
Sub Video/
Chrom
a
Select 3Hi : Main NTSCLo : Main Component
Select 4Hi : Sub NTSCLo : Sub Component
Select 3
Select 4
SyncSep.
SubSyncSel.
Select 4
1
Q425
9
6
I4076See Component
Signal Path (Sub)
Select 340
See VideoSignal Path
16
18
20
SeeComponentSignal Path
DP-05 & DP-05F COMPONENT SYNC SEPARATION BLOCK DIAGRAM
PAGE 04-14
DP-05 and DP-05F COMPONENT SYNC SEPARATION BLOCK DIAGRAM EXPLANATION
Refer to the DP-05 and DP-05F Component Sync Separation Circuit Diagram The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 Component Sync Separation Circuit Diagram is; • The DP-05 and DP-05F PinP circuit doesn’t route the Component inputs to the PinP Signal route into the
Flex Converter. Therefore, the PinP in the DP-05 and DP-05F only produces NTSC inputs routed through the Selector IC.
• The Sub Component Selector IC (I407) is not used. • The Sub Component Sync Separator IC (I408) is not used. • The Sub Component or Main NTSC Sync Selection IC (I405) is not used. All else remains the same. (See Next page for diagram).
SHW
I406See Sub Video
Signal Path
DP-05 and DP-05F SERIES CHASSIS MAIN/COMPONENT SYNC SEPARATION SIGNAL PATH
PAG
E 04-15
PTS2
Q223
I207
1
4
2
V.Sync Out
H.Sync Out
2
3
I2021
2
1
2
1
I2035 6
I201MainVideo/
Chroma
13
14
Q224
5
10 11
4
5
12 13
10
9
2 1
4 3
U2058
7
15
14
PTS3
3
1Sub H. Sync
Sub V. Sync
I40314
4013
H.Out
V.Out
TERMINAL PWB
SIGNAL PWB
Flex Converter
MHW
MVW
SVWSub Video/
ChromaPreparation
IC
Select 3Hi : Main NTSCLo : Main Component
Select 4Hi : Sub NTSCLo : Sub Component
Select 3
Q425
9
6
Select 340
See VideoSignal Path
16
18
20
SeeComponentSignal Path
See Main ComponentSignal Path
The ABL voltage is generated from the ABL pin of the Flyback transformer, TH01. The ABL pull-up resistors are RH58 and RH59. They receive their pull up voltage from the B+ 120V(V2 ) for Deflection line generated from the Power Supply via TP91 pin 13, rectified by DP11, filtered by CP33 and then routed through the excessive current sensing resistor RP17. ABL VOLTAGE OPERATION The ABL voltage is determined by the current draw through the Flyback transformer. As the picture brightness becomes brighter or increases, the demand for replacement of the High Voltage being consumed is greater. In this case, the flyback will work harder and the current through the Flyback increases. This in turn will decrease the ABL voltage. The ABL voltage is inversely proportionate to screen brightness. Also connected to the ABL voltage line is DH33. This zener diode acts as a clamp for the ABL voltage. If the ABL voltage tries to increase above 12V due to a dark scene which decreases the current demand on the flyback, the ABL voltage will rise to the point that DH33 dumps the excess voltage into the 12 line. ACCL TRANSISTOR OPERATION The ABL voltage is routed through the PSD3 connector, through the PSZ2 connector, to the base of QX13. Under normal conditions, this transistor is nearly saturated. QX13 determines the voltage being supplied to the cathode of DX05, which is connected to pin 45 of the Rainforest IC, IX01. During an ABL voltage decrease, due to an excessive bright circumstance, the base of QX13 will go down, this will drop the emitter voltage which in turn drops the cathode voltage of DX05. This in turn will pull voltage away from pin 45 of the Rainforest IC, IX01. Internally, this reduces the contrast and brightness voltage which is being controlled by the I2C bus data communication from the Microprocessor arriving at pin 27 and 28 of the Rainforest IC and reduces the overall brightness, preventing blooming. SUB BRIGHTNESS ADJUSTMENT - I2C Alignment The purpose for the Sub Brightness Adjustment alignment is to set up the Lowest DC level to which the Brightness control voltage can be set. Again, this voltage is controlled internally within IX01 via I2C bus data. The adjustment is performed within the Service Menu. To enter this adjustment menu, with the set turned off, press and hold the Input button, then press the Power button. This will bring up a Service Menu. Under the P.01 menu, the 1st selection is Sub Bright Adj. Selection is made using the pq buttons and adjusting the data values are made using the tu buttons.
Automatic Brightness Limiter (ABL) Circuit Block Diagram Explanation
Page 04-16
CX31
SignalPWB
DP0X CHASSIS A.B.L. CIRCUIT DIAGRAM
DX05 RX37
CX19
45
3
B+
ToFocus
CH25
C
RH59RH58
High Voltage B+ 120V V2
Sw +12V
SW +9V
RX33 RX35
IX01Rainforest
ICABL
SDA2
PSZ2
SDA216
To Anodes
ABLTo QH01Collector of High Voltage
Output Transistor
2H VideoPWB
orSignal Sub
PWB
Deflection PWB
Clamp
ABL Pull-Up Resistors
As Brightness goes Up, ABL Voltage goes Down. (Inverse Proportional)
[ Current Path ]
QX13RX34
RX36
5
27
See uPData
SignalPath
PAG
E 04-17
DH33
RH56Deflection B+ 120V V1
PSD3
1
DX03 CX32
CX34PSZ1
SCL2SCL2
17 28
TH01
RH67
LH03
CH31
RX32
The key component in the Sweep Loss Detection circuit is QN04. This transistor is normally biased off. When the base becomes more negative, it will be turned on, causing the Standby 11V to be applied to two different circuits, the Spot circuit and the High Voltage Drive circuit. SPOT CIRCUIT When QN04 is turned on, the 11V standby will be applied to the anode of DN11, forward biasing it. This voltage will then pass through DN11, get zenered by DN09, and go to pin 2 of PSD3, where it will activate the Video Mute circuitry Q022 - Q024 on the Signal PWB. This is done to prevent CRT burn. Another input to this circuit is the I701 DAC3 line. This will activate when accessing certain adjustment parameters in the service mode; i.e. turning off vertical drive for making CRT drive or cut-off adjustments. HIGH VOLTAGE DRIVE CIRCUIT When QN04 is turned on, the 11V standby will also be applied to the High Voltage Drive IC IH02 pin 14 via RN15 and DN13. When this occurs, the IC will stop generating the drive signal that is used to produce High Voltage via QH08, the High Voltage Driver. Again, this is done to prevent CRT burn, especially during sweep loss. CONCERNING QN04 There are several factors that can affect the operation of QN04; namely loss of vertical or horizontal blanking and spot killer or spot protect from a shutdown in the deflection power supply. Loss of Vertical Blanking When the 24Vpp positive vertical blanking pulse is missing from the base of QN01, it will be turned off, which will cause the collector to go high. This in turn will cause QN02 to turn on, creating an increase of current flow from emitter to collector and up through RN07, (which is located across the emitter base junction of QN04), to the 11V standby supply. This increase of current flow through RN07 will bias on QN04 and the events described previously will occur. Loss of Horizontal Blanking When the 11.6Vpp positive horizontal blanking pulse is missing from the base of QN05, it will be turned off, which will cause the collector to go high. This in turn will cause QN03 to turn on, creating an increase of current flow from emitter to collector, through RN06, and up through RN07. Again, this increase of current flow through RN07 will bias on QN04 and the events described previously will occur. SPOT PROTECT or SPOT KILLER As mentioned earlier, when the deflection power supply goes into shutdown for whatever reason, a low potential will be felt at the cathode of DN14, forward biasing it and causing current flow through RN07. Once again, this increase of current flow through RN07 will bias on QN04 and the events described previously will occur.
Sweep Loss Detection Block Diagram Explanation
Page 04-18
Prevents CRT Burn
DP0X SWEEP LOSS DETECTION CIRCUIT
DN01
DN02
RN04
DN03
CN02
CN01
RN01V. Blk.
24V P/P
H. Blk.
CN04
RN11
RN12
DN06
RN13
RN09
CN03 DN04 RN06
RN07Stby 11V
RN08
DN1111.6V P/P
SW+12V
SPOT
RN02
RN03RN05
RN10
VerticalBlanking
FromPin 11 I601
HorizontalBlanking
FromQ755 Emitter
PAGE 04-19
QN05
QN03
QN04
QN02
QN01
IH02
1 Drive
High VoltageDriver IC
2
I701
DAC3
Horizontaland
VerticalDrive IC
R718HVcc
Spot Inhibit
DN12
When Vertical Driveis turned Off duringadjustment, I 2C.
DN13
DN09
QN07
DN05
QN08
SW+12V
14RN15
StopsDrive
RN14
RH60
Stops High VoltageDrive Signals Frombeing producedwhen Sweep Loss isdetected.
High VoltageH Drive
QH08
See DeflectionPower Supply
Circuit Diagram
RN10
SPOTPROTECT
DN14
DN15
PSD3
24
I401 - Luminance Audio Selector IC Main Tuner (TV1V) in pin 63 Sub Tuner (TV2V) in pin 60
Video 1 in from Terminal PWB pin 8 S-Video 1 (Y) from Terminal PWB pin 10 S-Video 1 (C) from Terminal PWB pin 12
Video 2 in from Terminal PWB pin 1 S-Video 2 (Y) from Terminal PWB pin 3 S-Video 2 (C) from Terminal PWB pin 5
Video 3 in from Front Control PWB pin 15 S-Video 3 (Y) from Front Control PWB pin 17 S-Video 3 (C) from Front Control PWB pin 19
Yin1 PinP Luminance from 2L Comb filter pin 49 Cin1 PinP Chroma from 2L Comb filter pin 51 VOut1 PinP Video to 2L Comb filter pin 53 YOut1 PinP (Y) to Sub video processor pin 56 COut1 PinP (C) to Sub video processor pin 58
V/YOut2 Main Video or S-Video (Y) to 3DYC pin 44 COut2 S-Video (C) to 3DYC pin 47
VOut3 Video out to Monitor pin 41 YOut3 S-Video (Y) out to Monitor pin 39 COut3 S-Video (C) out to Monitor pin 37
I201 - Main Video Chroma Processor IC Main video in (Y) pin 40 Main video in (C) pin 6
Y out pin 37 R-Y Out pin 48 B-Y Out pin 47
I403 - Sub Video Chroma Processor IC Sub video in (Y) pin 40 Sub video in (C) pin 6
Y out pin 37 R-Y Out pin 48 B-Y Out pin 47
2 Line Comb Filter (PinP) Video In pin 4 Y Out pin 1 C Out pin 3
3 Line Comb Filter (Main) All discreet components IJ01 Video In, Y and C out IJ02 Selects either incoming S-video or IJ01 Y and C outputs
ZP-04 (Zenith) Video Circuit Block Diagram Explanation
Page 04-20
MainY
/Video
IJ01
PinP VY
PinP C
S-Y1S-C1
PinP TUNER (Mono)Always PinP
ZP-04 SERIES CHASSIS VIDEO SIGNAL PATH (Main & Terminal)
I401
53
49
Lum/Audio Selector IC
23
103V
VOut1
U202
Avx 3 In
PinPVideo
17
15
60
Terminal PWBSignal PWB 1 of 2
Front Control PWB
19
MainVideoNTSC
Aux Input 3
V1 810A
ux Inputs
U201Main Tuner
63Q205
53
S-Y3S-C3
19S-3 In
S-1 In12
S-Y2S-C2
V2 13S-2 In5
YIn1
2Line
CombFilter
V In
Y Out
C Out
S Det.
S Det.
S Det.56
PinP Yout2
18
Q206
14TV1V
TV2V
4
1
351CIn1
41Vout3
Q409 Monitor Out
32PinP C Cout2
39
37
Q410 Q411
Y/S Monitor Out
Yout3
Cout3
Q405
Q404
I403SUB
VIDEO
40
6
V3V
PST1
Q403
Q406
Q408
374847
Y-OutR-Y/CR Out
B-Y/CB Out
See Component Signal FlowDiagram for Continuation
44Q402
47Q401
V/Yout2
Cout2
13
9
Main C
PST2
5
7
I201
40
6
Q216
Q213
Q235
Q214
B-Y/CB Out
Main Y/Video
PFT
Sub Video Route
Page 04-21
PYC1
11
7
MainY
/Video
Main C
MainVideo/
Chroma
Signal PWB 2 of 2
Terminal PWB
5S-CIn
38 1
QJ09
QJ10
6
IJ02
QJ11QJ12
8 25QJ08 QJ07
QJ06QJ05
1025
QJ04
QJ03
QJ02QJ01
3 Line Comb Filter
Video In
37
48
47
CB
R-Y/CR OutCR
YAux Input 1
Aux Input 2
SECTION 5
AUDIO INFORMATION
I401 - Luminance Audio Selector IC Main Tuner TV1 Left in pin 62 Main Tuner TV1 Right in pin 64 Sub Tuner Mono in pin 59 and 61 Aux 1 Left in from Terminal PWB pin 9 Aux 1 Right in from Terminal PWB pin 11 Aux 2 Left in from Terminal PWB pin 2 Aux 2 Right in from Terminal PWB pin 4 Aux 3 Left in from Front Control PWB pin 16 Aux 3 Right in from Front Control PWB pin 18 Monitor Left out pin 38 Monitor Right out pin 40 Main (Selected) Out Left to Surround Sound PWB pin 43 Main (Selected) Out Right to Surround Sound PWB pin 45 Serial Clock 1 pin 33 Serial Data 1 pin 34 IC01 - Front Audio Output IC Front Left in from Surround PWB pin 2 Front Right in from Surround PWB pin 4 Mute Line pin 11
Audio Circuit Block Diagram Explanation
Page 05-01
Select L
DP-0X CHASSIS AUDIO SIGNAL PATH(Main, Terminal & Audio Output)
Main Audio
11
12
I401
43
45
Lum/AudioSelector IC
8
7
3L
3R
Main Audio
(See
Sur
roun
d A
udio
Sig
nal P
ath)
Avx 3 In
F L Out
F R Out
Front Left
Front Right
IC01 2
4
Select R
11
12
18
16
12
72
TerminalPWB
Signal PWB 2 of 2
Signal PWB 1 of 2
Front Control PWB
PR
PST1
PFV
Terminal PWB
TunerAudio
PAG
E 05-02
Aux Input 3
QC0311
DC03
Front Speaker Off
VMute2
SCL1
SDA1
33
34
6
5
64
62
PST3
I001Microprocessor
SCL1
SDA1
PST1
PinP Tuner
Mono PinP55
61
PinPAudio
In
Left Select
Right Select
U201Main Tuner
PSU1
Front Right
8
9
Front Output IC
TV 1 Left
TV 1 Right
16
17
27
261 of 2
2 of 2
U202
9
11
2
4
AVX 1
AVX 2
51
49AVX 3
1L
2L
2R
1R
Aux Inputs
3L
3R
Left Monitor Out
Right Monitor Out
FL
FR
3
2
38
40
PST2
DC044
Woofer
Tweet
2
PLFront Left
4
Woofer
Tweet
QC02
DC02
DC01QC01ERRMute
1
20
IS19 - Perfect Volume IC This IC receives main selected Left and Right audio and if the perfect volume feature is enabled via customer controls, will act as a limiter/compressor to keep sound levels at the same relative level. Output is sent to the DSP Module as well as to IS03 Front Audio Control IC. Digital Signal Processor (DSP) This Module is located on the Signal PWB. It receives Left and Right audio in from the Perfect Volume IC and creates the following outputs; Front Right, Front Left, Rear Right, Rear Left, Center, and Sub. It also is capable of receiving and processing a digital audio input signal, via either coaxial or optical inputs. IS02 - Buffer IC This IC receives the Front Left and Front Right signals from the DSP on it’s non-inverting inputs and outputs them to the Front Audio Control IC. IS03 - Front Audio Control IC This IC receives both the non-DSP processed Left and Right signals as well as the DSP Front Left and Front Right signals. Serial clock and data lines control various functions such as level and balance. IS04 - Buffer IC This IC receives the Front Left and Front Right signals from the Front Audio Control IC on it’s inverting inputs and outputs them to the Front Audio Graphic Equalizer IC. IS05 - Front Audio Graphic Equalizer IC This IC receives the Front Left and Front Right signals from the Buffer IC IS04. Serial clock and data lines control frequency response via the customer control interface. The output is sent back to the Signal PWB via the PSU1 connector to the Front Audio Output IC. This output is also sent to QS12 - QS15 buffer stages to be available as the HiFi outputs. IS08 - Center Channel & Sub Woofer Audio Control IC This IC receives the processed Center Channel and Subwoofer signals from the DSP. Serial clock and data lines control various functions such as level and balance. IS09 - Buffer IC This IC receives each of the processed Center Channel and Subwoofer signals from IS08 on it’s inverting inputs. The Subwoofer output is routed to QS18 and then on to the Subwoofer output connector. The Center Channel output is sent to the Center Channel Graphic Equalizer IC IS10. IS10 - Center Channel Graphic Equalizer IC This IC receives the Center Channel signal from the Buffer IC IS09. Serial clock and data lines control frequency response via the customer control interface. The output is sent to the Center Channel Audio Output IC IS15. IS15 - Center Channel Output IC This IC receives a paralleled input and amplifies the signal (s) to be sent to the pair of center channel speakers. There is also a mute line control input. IS11 - Rear Audio Control This IC receives the processed Rear Left and Rear Right signals from the DSP. Serial clock and data lines control various functions such as level and balance. IS12 - Buffer IC This IC receives the Rear Left and Rear Right signals from the Rear Audio Control IC on it’s inverting inputs and outputs them to the Rear Audio Output IC. IS16 - Rear Audio Output This IC receives the input from the Buffer IC IS12 and amplifies the signals to be sent to the rear speaker output connector SP. There is also a mute line control input.
Surround Sound Circuit Block Diagram Explanation
Page 05-03
IS15Cent
AudioOutput
IC
DP0X CHASSIS SURROUND AUDIO SIGNAL PATH
PAG
E 05-04
11
12
See
Aud
io S
igna
l Pat
h (M
ain
& T
erm
inal
)
L
R
PSU1
1
10
IS19PerfectVolume
3
8
2011
IS03
FrontAudio
Control
3
PMU4
4
3
FL
FR
SL
SR
IS02-+
65
+-
32
1
2
FLFR
DigitalBoard
HC4051
17
14
FL
FR
PMU3
IS04-+
65
+-
32
FL
FR29
IS05Front
GraphicEQ
1
30
12
19
8
9FL
FR FR
FL
IS11RearAudio
Control
17
14
IS12-+
65
+-32
SL
SR29
IS16RearAudio
OutputIC
2
4
12
7
7
1
1
2
SP
IS08
Center/Sub
WooferAudio
Control17
IS09
-+
65
+-32
CL2
9
IS10Cent.
GraphicEQ
121
5C
7
1
SW QS18 Sub Woofer
Center
14
6SWSub Woofer
IS07
+- 3
1
65
7Gnd
2
Gnd
GS
DSW Sel 1
+-
IS065
+-
Gnd
67
+-
32
1
SW Sel 2
PCR
2
4
12
7
1
2
PCL
Center
QS01
QS01
Out to Hi-Fi
Coaxial Input
IS18
11
8
IS17
3
5
JS03
Optical Input
12
3
FPFRX
Digital Outputto DSP
PMU2
3
1
Actual Input Coax
Invert 1
Invert 2
Optical Input Good, no Invert
2XInvert
QS12QS13 FROut to Hi-Fi
FL
11 11
DS37
DS36Rear Spk Off
V MuteDS27
DS26Cent Spk Off
QS10 QS06MuteMute
QS15QS14
7
1
IA02 - Perfect Volume IC This IC receives main selected Left and Right audio and if the perfect volume feature is enabled via customer controls, will act as a limiter/compressor to keep sound levels at the same relative level. Output is sent to the SRS IC IA03. IA03 - SRS Processor (Sound Retrieval System) IC This IC is controlled by logic modes from the DAC IC IA01. It receives Left and Right audio in from the Perfect Volume IC and creates Front Right and Front Left signals. The two Modes control whether SRS is activated or not and whether its producing a monaural or stereo output. IA05 - Front Audio Control IC This IC receives the SRS processed Left and Right signals. The output is sent to the Buffer IC IA06. This output is also sent to QA07 - QA10 buffer stages to be available as the HiFi outputs. Serial clock and data lines control various functions such as level, tone, and balance. IA06 - Buffer IC This IC receives the Front Left and Front Right signals from the Front Audio Control IC on it’s inverting inputs and the outputs are sent back to the Signal PWB via the PSU1 connector to the Front Audio Output IC.
DP-05, DP-05F and ZP-04 (Zenith) SRS Circuit Block Diagram Explanation
Page 05-05
PAG
E 05-06
DP-05 AND DP-05F CHASSIS SRS AUDIO SIGNAL PATH
11
12
See
Audi
o Si
gnal
Pat
h (M
ain
& T
erm
inal
)
L
R
PSU1
1
10
IA02PerfectVolume
IA05
FrontAudio
Control
2
21
FL
FR
IA06
-+65
3
FL
8
9FR
FL
21
22
IA03SRS
14
13+-2
FR
QA07 QA08Out to Hi-Fi
FL
QA09 QA10Out to Hi-Fi
FR
SRS LOGICMODE
BYPASS (SRS Off)SRS SOUND
MODE 1L
MODESRS STEREOSRS MONAURAL
3
8
7
1
1
2
SCL2
SDA2
2
3
IA01DAC3
4
5
SRS1
SRS2
11 1210 11
HMODE 2
LH
18
5
SECTION 6
DIGITAL CONVERGENCE INFORMATION
DIGITAL CONVERGENCE INTERCONNECT DESCRIPTION
PAGE 06-01
Use this explanation in conjunction with the Digital Convergence Interconnect circuit diagram. The Digital Convergence circuit is responsible for maintaining proper convergence of all three colors being pro-duced by the CRTs. Many different abnormalities The Digital convergence Interconnect Diagram depicts how the Digital Convergence Circuit is interfaced with the rest of the Projection’s circuits. The main components and/or circuits are; • THE DIGITAL CONVERGENCE UNIT (DCU) • INFERRED REMOTE RECEIVER • ON SCREEN DISPLAY PATH • CONVERGENCE OUTPUT STKs • CONVERGENCE YOKES • MAGIC FOCUS SENSORS AND INTERFACE • MICROPROCESSOR • RAINFOREST IC (Video Processor). • SERVICE ONLY SWITCH • MAGIC FOCUS SWITCH THE DIGITAL CONVERGENCE UNIT (DCU) The DCU is the heart of the Digital convergence circuit. Held within are all the necessary components for gener-ating the necessary waveforms for correction, and associated memories for the adjustment data and Magic Focus Data.
The Block above shows the relationship of the DCU to the rest of the set. Note that the light being produced by the CRTs is what is used by the sensors for Magic Focus. This allows the DCU to make adjustments regardless of circuit changes, by actually using the light on the screen to make judgments. EEPROM AND SRAM SHOWN IN FIGURE 1: Each color can be adjusted in any one of 117 different locations. The internal workings of the DCU can actually make 256 adjustment points per color. These adjustment points are actual digital data stored in memory. This data
(Continued on page 2)
DIGITALCONVERGENCECIRCUIT
INTERPOLATION
X6 X6 X6X6X1
CY CLAMP
CRT
RG
B
H
V
117 Points Per/Color
Light
Sensors (X8)
Sensor PWBA/DData Comparator Serial-Parallel
Converter
TimingController
Stored Light Sensor Data
Technician's Eye
Error Data
EEPROM2K Bit
MIRROR
AC Applied, Copy from EEPROM, then caculations will be made. Time, approx. 20 sec.
Calculation of other 139 points per/color
Back Up
To Video Circuits
Addressableby
Technician
Also available;35 Adjustment Points9 Adjustment Points
PointsPer/Color
Via O.S.D.
117 Points Per/Color D/A Conv.Static Centering
Stored during Initialize
between stored dataand light sensor data
One Chip CPU
Infra-Red Decoder
Digital CrossHatch Gen. Timing
Controler
Serial/ParallelConverter
Gate Array 4000 gates
S-RAM(256Kbit)
FAST
EEPROM(2Kbit)
SLOW
8 bit128 Kbit
D/A
1st S
/H
2nd
S/H
LPF
CLA
MP
256 Adjusted
Displays CrossHatch
SCREENAdjust through observation
RemoteControl
Figure 1
DIGITAL CONVERGENCE INTERCONNECT DESCRIPTION
PAGE 06-02
(Continued from page 1)
represents a specific correction signal for that specific location. When the Service Technician makes any adjust-ment, the new information must be stored in memory, EEPROM. The EEPROM only stores the 117 different ad-justment points data, the SRAM interpolates to come up the additional 139 adjustment points for a total of 256 per color. The EEPROM data is slow in relationship to the actual deflection raster change. The SRAM is a very fast memory. So, during the first application of AC power, the EEPROM data is read and the SRAM makes the inter-polation and as long as power remains, interpolation no longer has to be made. This can be seen during an adjustment. If the Interpolation key is pressed on the remote control, what is happen-ing is that the SRAM must make those additional calculations beyond the 117 made by the Servicer and this is all placed into memory. INFERRED REMOTE CONTROL INPUT SHOWN IN FIGURE 1: As can be seen in Figure 1, the Inferred Remote control signals actually manipulate the internal data when the Service Only Switch is pressed on the Deflection PWB. This process actually prevents the Microprocessor from responding to Remote commands, via a Busy line output from the DCU. (See Microprocessor Port Description page for further details.) INTERNEAL CONTROLLER, D/A CONVERTERS SHOWN IN FIGURE 1: The internal controller, takes the stored data and converts it to a complicated Convergence correction waveform for each color. The Data is converted through the D/A converter, 1st and 2nd sample and hold, the Low Pass Fil-ter that smoothes out the parasitic harmonic pulses from the digital circuit and the output Clamp that fixes the DC offset level. The DC offset voltage is adjusted by several things. • Raster Centering. The Raster Centering adjustment actually moves the DC offset voltage for Horizontal and
Vertical direction. This Offset voltage will move the entire raster Up or Down, Left or Right. • Static Centering. This is accessed by holding down the Magic Focus button on the front control panel for
more that 10 Seconds. The word Static will come up on the screen, generated by the DCU, and using the re-mote controls up/down/left or right cursor buttons, the Red or Blue raster can again be moved up/down/left or right. This allows adjustment of the entire raster for Red or Blue to match the Green Raster.
By holding down the Magic Focus button for more that 5 seconds, but not more than 10, the word Center comes up on screen. Again generated from the DCU. This adjustment only moves the center 60% of the raster for Red or Blue. The assumption for this adjustment was related to the location of the Magic Focus sensors located on the outside perimeter of the inside cabinet. It was assumed possible that the outside could have been corrected, but the inside middle might not. This adjustment is rarely necessary if at all. MAGIC FOCUS MEMORY SHOWN IN FIGURE 1: NOTE: This set has two Digital Convergence Memories. On for Progressive display mode and one for HD dis-play mode. NOTE: This set has two Magic Focus Memories. On for Progressive display mode and one for HD display mode. Progressive requires a complete Digital Convergence adjustment procedure along with Magic Focus Sensor Ini-tialization and HD Mode does too! When a complete Digital Convergence procedure has been performed and the adjustment information stored in memory by pressing the PROG button twice (2), it is mandatory to run Sensor Initialization. This is done by pressing the PROG button or the remote once (1), then pressing the PinP Ch button. This begins a prepro-grammed production of different light patterns. Magic Focus memorizes the characteristics of the light pattern produced by the digital convergence module. If a convergence touchup is required in the future, the customer simply presses the Magic Focus button on the front panel and the set begins another preprogrammed production of different light patterns. This automated process that duplicates the same light pattern it memorized from the initialization process, re-aligns the set to the memorized convergence condition.
(Continued on page 3)
DIGITAL CONVERGENCE INTERCONNECT DESCRIPTION
PAGE 06-03
(Continued from page 2)
MAGIC FOCUS SENSORS SHOWN ON FIGURE 1: This process is a joint effort between the digital convergence module and 8 Photo-sensors, physically located on the edge of the cabinet, just behind the screen. The physical placement of the sensors assures that they will not produce a shadow on the screen that can be seen by the customer. Magic Focus is activated when the set is on and by pressing the Magic Focus button inside the front control panel door. An on-screen graphic will be displayed to confirm that the automatic convergence mode (Magic Fo-cus) has begun. The digital convergence module produces different patterns for each CRT, and the sensors pick up the transmitted light, generate a DC voltage. This voltage is sent to the DCU and converted to digital data and compared with the memorized sensor initialization data. Distinct patterns will be generated in each primary color. As the process continues, the digital module manipulates the convergence correction waveforms that it is producing to force the convergence back into the original memorized configuration. When all cycles have been completed, the set will return to the original signal and the convergence will be corrected. In most cases, activating the Magic Focus will allow the set to correct itself, without further adjustments. EXPLANATION OF THE DIGITAL CONVERGENCE INTERCONNECT DIAGRAM: INFRARED RECEIVER: During normal operations, the IR receiver directs it signal to the Main Microprocessor where it interprets the in-coming signal and performs a predefined set of operations. However, when the Service Only Switch is pressed, the Main Microprocessor must ignore remote control commands. Now the DCU receives theses commands and interprets them accordingly. The Microprocessor is notified when the DCU begins it’s operation by the BUSY line. As lone as the BUSY line is active, the Main Microprocessor ignores the IR signal. ON SCREEN DISPLAY PATH: MICROPROCESSOR SOURCE FOR OSD: The On Screen Display signal path is shown with the normal OSD information such as Channel Numbers, Vol-ume Graphic Bar, Main Menu, etc… sent from the Main Microprocessor to the Rainforest IC IX01 pins 14, 16 and 18. These are positive going pulses, about 5 V p/p and about 3uS in length dependant upon there actual hori-zontal time for display. (See the On Screen Display Path Circuit Diagram Explanation for further details). DCU SOURCE FOR OSD: The DCU has to produce graphics as well. When the Service Only switch is pressed, the Main Microprocessor knows the DCU is Busy as described before. Now the On Screen Display path is from the DCU to the Rainforest IC IX01 pins 8, 10 and 12. The output for the DCU OSD characters is pin (11 Dig Red, 12 Dig Green and 13 Dig Blue). These are routed through their buffers (QK06 Dig Red, QK07 Dig Green and QK08 Dig Blue) to (QX01 Dig Red, QX02 Dig Green and QX03 Dig Blue). Then it arrives at the Rainforest IC IX01 at pins (8 Dig Red, 10 Dig Green and 12 Dig Blue). When a character pulse arrives at any of these pins, the internal color amp is saturated and the output is generated to the CRTs. Any combination for these inputs generates either the primary color Red, Green or Blue or the complementary color Red and Green which creates Yellow, Red and Blue which creates Magenta or Green and Blue which creates Cyan. (See the On Screen Display Path Circuit Diagram Explanation for further details). OUTPUT STKs: These are output amplifiers that take the correction waveforms generated by the DCU and amplify them to be used by the Convergence Yoke assemblies for each color. RV is Red Vertical Convergence correction. Adjust the location either up or down for Red. RH is Red Horizontal Convergence correction. Adjust the location either left or right for Red. GV is Green Vertical Convergence correction. Adjust the location either up or down for Red. GH is Green Horizontal Convergence correction. Adjust the location either left or right for Red. BV is Blue Vertical Convergence correction. Adjust the location either up or down for Red. BH is Blue Horizontal Convergence correction. Adjust the location either left or right for Red.
(Continued on page 4)
DIGITAL CONVERGENCE INTERCONNECT DESCRIPTION
PAGE 06-04
(Continued from page 3)
CONVERGENCE YOKES: Each CRT has a Deflection Yoke and a Convergence Yoke assembly. The Deflection manipulates the beam in accordance to the waveforms produced within the Horizontal Deflection circuit or the Vertical Deflection circuit. The Convergence Yoke assembly manipulates the Beam in accordance with the correction waveforms produced by the DCU. MAGIC FOCUS SENSORS AND INTERFACE: Each of the eight photo cells, called solar batteries in the service manual, have their own amps which develop the DC potential produced by the cells. Each amp is routed through the PDS1 connector and arrives at the PDS con-nector on the DCU where the DCU converts this DC voltage to Digital signals. These digital signals are used only when the Magic Focus Button is pressed and Magic Focus runs. MICROPROCESSOR: The Microprocessor is only involved in the Digital Convergence circuit related to IR (Inferred Remote Control Signals). When the DCU is put into the Digital Convergence Adjustment Mode, DCAM, the Microprocessor ig-nores IR pulses. This is accomplished by the Busy signal from the DCU. RAINFOREST IC (Video Processor). The Rainforest IC, IX01 is only involved with the Digital Convergence circuit related to OSD.\ SERVICE ONLY SWITCH: The Service Only Switch is located just in front of the Flyback Transformer on the Deflection PWB. If the front speaker grills are removed and the front access panel is opened, the switch will be on the far left hand side. When this button is pressed with the TV ON, the DCU enters the Digital Convergence Adjustment Mode. If the button is pressed and held down with the TV OFF and the power button is pressed, the Digital Convergence RAM is cleared. This turns off any influence from the DCU related to beam deflection. Magnetic centering is per-formed in the mode as well as the ability to enter the 3X3, (9 adjustment points) mode. MAGIC FOCUS SWITCH: When this button is pressed with the Set ON, the DCU enters the Magic Focus adjustment mode described earlier. When this button is pressed with the Set ON and held for; • 5 Seconds, the word CENTER comes up on screen and if the button is released, the center 60% of the raster
can be adjusted for Red and Blue up/down/left and right using the Remote control Cursor Buttons. • 10 Seconds, the word STATIC comes up on screen and if the button is released, the entire raster can be ad-
justed for Red and Blue up/down/left and right using the Remote control Cursor Buttons. NOTE: This set has two Digital Convergence Memories. On for Progressive display mode and one for HD dis-play mode. Both have to be adjusted independently. NOTE: This set has two Magic Focus Memories. On for Progressive display mode and one for HD display mode. Progressive requires a complete Digital Convergence adjustment procedure along with Magic Focus Sensor Ini-tialization and HD Mode does too! The Magic Focus button will correct for either mode.
DigitalConvergence
Unit"DCU"
"Mounted onDeflection
PWB"
DP-0X CHASSIS "DIGITAL CONVERGENCE" INTERCONNECTION CIRCUIT DIAGRAM
+5V
N/C
Gnd
Gnd
S7
S6
S5
S4
S3
S2
S1
S0
PDS1
1
2
3
4
5
6
7
8
9
10
11
12
1 of 2 PDS
1
2
3
4
5
6
7
8
9
Gnd
S7
S6
S5
S4
S3
S2
S1
S0
PDG
4
5
6
7
8
9
10
11
12
13
14
15
3
2
1PDC
1
2
4
5
7
8
9
BV
BH
GH
RV
RH
Mute
8 7
5
10
+33V
+28P
4
-33V-28P
+ -
14 13
11
+ -
16
18
+ -
6 7
9
4
10 5
+28P +33V
+ -
14 13
11
+ -
6 7
8
+ -
IK04
GH
RV
RH
IK05
BV
BH
GV
15
PCB2
1
3
PCG
1
3
4
PCR
2
1
4
3
9
4
2
CYV+
CYV-
CYH+
CYH-
CYH+
CYH-
CYV-
CYV+
CYV+
CYV-
CYH+
CYH-
+28VIK02 21
3
To Blue Convergence Yokes
To Green C
onvergence YokesTo R
ed Convergence Yokes
HBlk
D Size
V SyncDig R
BUSY
IR-In
Dig G
Dig B
"DCAM" DigitalConvergence Mode
QK07
QK06
QK08
PSD1
4
5
6
7
3
2
1PFS
IX01Rainforest
PZC
5
3
1
41
42
43
37
39
38
OSD B
OSD G
OSD R
OSD B
OSD G
OSD R
Dig OSD R
Dig OSD G
Dig OSD B
PSZ114
16
18
To CR
Ts
B
G
R
Deflection PWB
Ft. ControlPWB
SignalPWB
SDA1
Deflection PWB
Signal PWB
HMO1
QM01
1
IR Receiver
2
IR O
ut
SK01
SensorPWB
LEDS0-S78 Total
Sensors
UKDGHC2151
QX07
QX36
QX31
QX41
Normal "Lo"PAGE 06-05
817 12
10
11
28
SCL1
Stby +5V
IR In
I002
Memory
817 12
3
3
1 IR
5
6
SDA 1
SCL 1
MAG SW
3
SM09
GV
6 31/33
+5V SRAM
+5V
-5V
+5V SRAM
MAG SW
9
5
Magic Focus
IR-In2
I004DAC2
14
15
10
QX08
QX09
QX01
QX02
QX03
I001
MainUp 10
12
14
16
18
8
10
12
2H Video PWB
Deflection PWB
MUTE RECALLSVCS
VCR PLUS+ INFO GUIDE/TVSCHD
PIP CHPIP FRZ
PIP-MODE SWAP
PROG TV/VCR SLOW
REC
HITACHICLU-572TSI
SELECTVOL CH
MENU EXIT
C.S.HELP
INPUT
0 LASTCH
SLEEP
7 8 9
1 2 3
4 5 6
DVD AV1 AV2 AV3
SATCBLVCRTV
SOURCEWIZARD
000
POWER
CURSOR LEFT
BLUE (13X9)
REMOVECOLOR
CALCULATE
INITIALIZEPIP MODE +
PIP CH
WRITE TOROM
PRESS(2X)
READ OLDROM DATAPRESS (2X)
CENTERING
GREEN (3 X 3)
CORRECTIONBUTTONS
CROSSHATCHVIDEO
RASTER PHASE
RED (7 X 5)
DP-05, DP-05F, DP-06, DP-07 REMOTE CONTROL CLU-572 TSI
PAGE 06-06
C.C. ASPECT
CURSOR UP
CURSOR RIGHT
CURSOR DOWN
Used with43FDX01B, 53FDX01B,53SDX01B, 61SDX01B,
53SWX01W, 65DMX01W
MUTE RECALLSVCS
VCR PLUS+ INFO GUIDE/TVSCHD
PIP CHPIP FRZ
MOVE SWAP
PROG TV/VCR SLOW
REC
HITACHICLU-573TSI
SELECTVOL CH
MENU EXIT
C.S.HELP
INPUT
0 LASTCH
SLEEP
7 8 9
1 2 3
4 5 6
DVD AV1 AV2 AV3
SATCBLVCRTV
SOURCEWIZARD
000
POWER
CURSORPOSITIONBUTTONS
BLUE13X9
REMOVECOLOR
CALCULATE
INITIALIZE
WRITE TOROM
READ FROMROM
CENTERING
GREEN3 X 3
CORRECTIONBUTTONS
CROSSHATCHVIDEO
RASTERPHASE
RED7 X 5
AP-93R REMOTE CONTROL CLU-573 TSI
PAGE 06-07
Used with53SBX01B, 61DSBX01B
"MOVE" = "RASTER ADJ"Used to align Red and Blue
raster with Green.
(2 Additional lines will Appear)
DP85 SERIES CHASSIS "CLU-614MP" REMOTE CONTROLREMOTE PERSONALITY WHILE IN THE
DIGITAL CONVERGENCE ADJUSTMENT MODE D.C.A.M.
V O L C H
M U T E
LAST
TV / CABLE / SAT
V C R
AUDIO
FAVCH
FAVCH
MENU
GUIDE
INFO EXIT
REC SELECTSVCS SCHED
USER HELP
1
4
7
2
5
8
3
6
9
0
HITACHICLU-614MP
LIGHT
T V S A TCABL E
DTV/ S A T S W A PP I P
PIP CH M O V EA N T
P O W E R
C.S.INPUT
"PIP" = "ROM READ"Reads old R.O.M. data.
(Last data stored in R.O.M.
(Press 2 times)
"SWAP" = "ROM WRITE"(STORE)
Stores data into R.O.M..
(Press 2 times)
"PIP CH" = "INITIALIZE"Perform after
STORE & before EXIT[SWAP + PIP CH]
"MENU" = "REMOVE COLOR"Removes color
not being adjusted.
(Will NOT remove GREEN )
"USER" ="GREEN adjust"Digital Cursor Blinks GREEN
3x3 adjustment mode
(Press 5 times), can only be
entered when R.A.M. is cleared.
"CURSOR KEYS" ="(ADJUSTMENT)"
Adjust the selected color at
the current stopping position.
Up
Down
Left
Right
"MOVES DIGITAL CURSOR"Moves Adjustment Point
(2) Up, (4) Left,
(5) Down, (6) Right
"INPUT" = "BLUE adjust"Digital Cursor Blinks BLUE
13 x 9 adjustment mode
(Press 5 times)
" 0 " = "RED adjust"
Digital Cursor Blinks RED
7x5 adjustment mode
(Press 5 times)
"ANT" = "PHASE" (Aligns Cursor to Grid)
"INFO" = "CALCULATION" (Calculates mid-points)
"EXIT" = "ENTER & EXIT"Enter or Exit the D.C.A.M.
Must initially enter D.C.A.M. with
Service Button on chassis.
(Press 5X)
Toggles between External Video
and Internally generated Cross
hatch. After exiting the DCAM,
set can change channels or
external video source.
To Clear R.A.M. data.Turn set OFF.Press and hold the Service Button ondeflection P.W.B. Then PowerButton.
*
*
*
PAGE 06-08
D.C.A.M.Digital convergence adjustmentmode
RECALL:
Green Adjust
(3 X 3 Mode)M U T E
P O W E R
LIGHI
LST-CH
T V V C RCABL E
HELP PIP CH TV/VCR
PIP S W A P M O V E FR Z
CURSOR CONTROL
STO P
R E C PAUSE
VOL CH
CLU-436UI REMOTE CONTROL FOR AP-91 and AP-01 CHASSIS
H I T A C H I
CLU-436UI
1
4
7
2
5
8
3
6
9
0SLEEPINPUT
INPUT EXIT
FRZ: Raster Posit ion
MOVE: ROM Write
(Store)
2: Cursor Up
6: Cursor Right
0 :
Red Adjust
(7 X 5 Mode)
4: Cursor Left
5: Cursor Down
INPUT:
Blue Adjust
(13 X 9 Mode)
S W A P :
ROM Read
HELP :
Phase
PAGE 06-09
Used With50DX01B, 50EX01B,60EX01B, 43GX01B,46GX01B, 50GX20B
DP-05 and 05F DIGITAL CONVERGENCE CIRCUIT DIAGRAM EXPLANATION
PAGE 06-10
Refer to the DP-05 and 05F Digital Convergence Circuit Diagram The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 Digital Convergence Circuit Diagram is; • The DP-05 and 05F doesn’t have Magic Focus. • There are no sensors around the inside of the cabinet behind the screen. • There is no Magic Focus Switch on the front control panel. • There is a Static Convergence Switch on the front control panel. • When performing adjustment, there is no need for Sensor Initialization in either Progressive or HD mode. All else remains the same. (See Next page for diagram).
DigitalConvergence
Unit"DCU"
"Mounted onDeflection
PWB"
DP-05 and 05F CHASSIS "DIGITAL CONVERGENCE" INTERCONNECTION CIRCUIT DIAGRAM
PDG
4
5
6
7
8
9
10
11
12
13
14
15
3
2
1 PDC
1
2
4
5
7
8
9
BV
BH
GH
RV
RH
Mute
8 7
5
10
+33V
+28P
4
-33V-28P
+ -
14 13
11+ -
16
18+ -
6 7
9
4
10 5
+28P +33V
+ -
14 13
11+ -
6 7
8+ -
IK04
GH
RV
RH
IK05
BV
BH
GV
15
PCB2
1
3
PCG
1
3
4
PCR2
1
4
3
9
4
2
CYV+
CYV-
CYH+
CYH-
CYH+
CYH-
CYV-
CYV+
CYV+
CYV-
CYH+
CYH-
+28VIK02 21
3
To Blue Convergence YokesTo Green Convergence Yokes
To Red Convergence Yokes
HBlk
D Size
V SyncDig R
BUSY
IR-In
Dig G
Dig B
"DCAM" DigitalConvergence Mode
QK07
QK06
QK08
PSD1
4
5
6
7
3
2
1PFS
IX01Rainforest
PZC
5
3
1
41
42
43
37
39
38
OSD B
OSD G
OSD R
OSD B
OSD G
OSD R
Dig OSD R
Dig OSD G
Dig OSD B
PSZ1
14
16
18
To CRTs
B
G
R
Deflection PWB
Ft. ControlPWB
SignalPWB
SDA1
Deflection PWB
Signal PWB
HMO1
QM011IR Receiver
2 IR O
ut
SK01 UKDGHC2151
QX07
QX36
QX31
QX41
Normal "Lo"
PAGE 06-11
817 12
28
SCL1
Stby +5V
IR In
I002
Memory
817 12
3
3
1 IR
56
SDA 1
SCL 1
MAG SW
3
SM09
GV
6 31/33
+5V SRAM+5V
-5V
+5V SRAM
MAG SW
9
5
Static Conv.
IR-In2
I004DAC2
14
15
10
QX08QX09
QX01QX02
QX03
I001Main Up
10
12
14
16
18
8
10
12
2H Video PWB
Deflection PWB
No Magic Focus
SECTION 7
DEFLECTION CIRCUIT
INFORMATION
DEFLECTION DRIVER IC (I701) B+ GENERATION DESCRIPTION
PAGE 07-01
DEFLECTION DRIVER IC B+ GENERATION CIRCUIT: (See the Deflection Vcc Production Circuit Diagram for Details) EXPLANATION: The B+ for the Deflection Driver IC (I701) is switched On and Off with the TV. Control for this process is pre-formed by the Microprocessor On/Off (Power On/Off) pin. The Power On/Off pin (53) of the Microprocessor I001 is High when the set is turned On. This High is sent to the low voltage Power Supplies on the Signal PWB via Q003 and Q004. This turns on the +9V Regulator I009, the SW+5V Regulator I010 and the +5V Regulator IS13 on the Surround PWB. The High from the Microprocessor is also routed through the Relay Driver transistor Q002 and inverted to a Low, then through the connector PQS1 pin (8), to the Sub Power Supply. (Also called the Low Voltage Power Supply PWB). Here it turns on the necessary circuits for the Sub Power Supply. (See the Power On/Off Circuit Descrip-tion for detail). This Low is now routed through the connector PQD2 pin (1), to the Deflection PWB. The Low forward biases DP21 and pulls the base of QP04 Low which turns it On. The emitter of QP04 is connected to the Stby +11V power supply via the connector PQD2 pin (3). When QP04 turns On, the collector goes high and is routed through DP35 and DP36 to pin (8) of I701, the Horizontal Driver IC. When B+ is applied, the Driver IC begins producing Horizontal Drive for the Deflection Circuit. (See Deflection Circuit description for more details).
QP04I001
MicroProcessorPower On/Off 53
Q002
PQS1
8
Stby +11V
I7018HVcc
Power ONDriver
(Relay Driver)
SIGNAL PWB SUB POWER PWB DEFLECTIONPWB
SUB DEFLECTIONPWB
DP0X DEFLECTION Vcc PRODUCTION CIRCUIT
PAGE 07-02
Other PowerOn/Off Circuits
From I906 Stby +11VReg.
PQD2
3
1
STBY +11V
Start Up Power
DP21
Power On byRemote Control orFront Power Key
Press
DP35
DP36
Q003 Q004
Turns on I009 SW +9V Reg.,IS13 +5V Reg on Surround PWB
and I010 SW+5V Reg. Signal PWB
Horizontal Drive IC
HORIZONTAL DRIVE CIRCUIT DESCRIPTION
PAGE 07-03
HORIZONTAL DRIVE CIRCUIT DIAGRAM DESCRIPTION: (Use the Horizontal Drive Circuit Diagram for details) CIRCUIT DESCRIPTION When B+ arrives at the Horizontal Driver IC I701 pin (8), horizontal drive is output from pin (15). The drive sig-nal is routed to the Horizontal Driver Transistor Q751. This transistor switches the ground return for pin (8) of the Driver transformer (T751). 28 volts is supplied to pin (5) and this switching allows EMF to develop. As this sig-nal collapses, it creates a pulse on the output pin of (T751) at pin (4) to the base of the Deflection Horizontal out-put transistor Q777. This transistor switches the primary windings of the Deflection Transformer T752. This transformer produces the following output pulses; • Deflection Pulse from pin (7): This pulse is used by;
1. The Side Pin Cushion Circuit: The Side Pin Cushion circuit for pin cushion correction. 2. The DF OUT Circuit: Generated from the Horizontal Blanking pulse. A Dynamic Focus waveform is
created. This is a parabolic waveform that is superimposed upon the static focus voltage to compensate for beam shape abnormalities which occur on the outside edges of the screen because the beam has to travel further to those locations.
3. To X-Ray Protect: This signal is monitored by the X-Ray Protect circuit to place the power supply into shut down if the Deflection circuit doesn’t operate.
• +28V, M26V and RETRACE PULSE +28P and M28P: The positive 28V and the negative 28V is routed to the Deflection transformer I752. They enter the transformer as a pure DC voltage then a 7.5V P/P horizon-tal pulse is added to the DC voltage and leaves as +28P and M28P. From here these voltages are routed to the Convergence output section and they are rectified. They become +33V and -33V respectively. This process prevents the need for another power supply. (Note: the M stands for Minus voltage.)
Deflection Pulse from pin (7): The Horizontal Pulse is also routed to the Horizontal Blanking generation transis-tor Q755. This transistor generates the 13V P/P called H Blk. This signal goes to the following circuits; • To pin (10) of I701 as FBP In. Here this signal is used as a comparison signal. It is compared to the refer-
ence signal coming in at pin (3) Horizontal Sync. If there are any differences between these two signals, the output Drive signal from pin (15) is corrected.
• To the Convergence circuit for correction waveform generation. • Sweep Loss Circuit to shut off the CRTs if Horizontal deflection is lost. • Through the connector PSD3 pin (6): The H Blk signal is routed from here to the Signal PWB to be used by
different circuits. The Microprocessor uses this signal for OSD positioning and for Station Detection during Auto programming within the coincidence detector. The PinP unit uses this signal for switching purposes. Like the read/write clock, positioning, etc…
The Horizontal Blanking signal H Blk from Q755 is also sent to the High Voltage Driver IC IH01 pin (3). This IC uses this signal as its reference signal to produce the High Voltage Drive waveform output from pin (1). This output is routed to the driver transistors, QH08, QH09 and QH10. Then to the High Voltage Horizontal Output Transistor QH01. This transistor switches the primary of the Flyback transformer TH01. 120V2 is sent through pin (2) and output pin (10) to the collector of the Horizontal Output Transistor QH01. A sample of the High Voltage is output from the Flyback transformer TH01 pin (12). This voltage is sent to pin (9) of the High Voltage Driver IC IH01. This voltage is compared to the reference voltage available at pin (12). If there is a difference between the two voltages, an error voltage is generated and output from pin (10) and input again at pin (11) where it manipulates the PWM (Pulse With Modulation) signal producing the Horizontal Drive signal output from pin (1). It’s important to notice that the High Voltage circuit can not function without the Horizontal Deflection circuit providing a drive signal.
HORIZONTAL DRIVE CIRCUIT DESCRIPTION
PAGE 07-04
GENERAL INFORMATION: The DP-0X deflection circuit differs from conventional Hitachi product. It utilizes in a sense, two horizontal out-put circuits. One for Deflection and one for High Voltage. There are many terms around the Horizontal circuit that are not shown on the Diagram. Some of these terms are explained first: CUT OFF: Cut of collapses the Vertical circuit during I2C Bus alignments, during CRT Set Up. I2C: Communication from the Microprocessor I001 to I701 during sweep variations due to Standard/NTSC 480P (Progressive mode) and 1080I High Definition mode, (HD) and Service Adjustments. ABL: ABL voltage is generated by monitoring the current through the Flyback transformer. This voltage will fluctuate down when the scene is bright and up when the scene is dark. The ABL voltage will manipulate the screen bright-ness and contrast to prevent blooming under these conditions. HV SYNC: The composite sync is routed to the Sync processor inside the Horizontal Driver IC I701 which determines the sweep frequency for the signal being provided. (Everything but HD is 31.5KHz and HD is 33.75KHz). H and V BLK: • H Blk: Horizontal and Vertical Blanking is developed within the Deflection circuit. The Horizontal Blanking
pulse operates around 13V P/P and is produced by taking a sample pulse from the Deflection transformer T752.
• V Blk: The Vertical Blanking pulse is generated from the Vertical output IC, I601 pin (11). This pulse nor-mally operates at 23V P/P.
IR: The Infrared Pulses coming from the remote control are routed through the Deflection PWB to the Digital Con-vergence Unit. During DCAM (Digital Convergence Adjustment Mode), the Remote Control provides manipula-tion pulses for the DCU. DIG RGB BUSY: This indicates Digital RGB and BUSY. • Digital RGB represents the On Screen Characters produced by the DCU for generating the Digital Conver-
gence adjustment grid and text produced during certain conditions such as Magic Focus, Sensor Initialization, Data Storage, etc…
• Busy notifies the sub Microprocessor I901 which in turn notifies the DM-1 module that the DCU has entered the DCAM. During this time, the DM-1 module ignores the remote control commands.
MAGIC SW: When the customer presses the Magic Focus button on the front of the set, it produces a command for the DCU to begin the Magic Focus process.
(Continued on page 5)
HORIZONTAL DRIVE CIRCUIT DESCRIPTION
PAGE 07-05
(Continued from page 4)
D SIZE: Digital Size is a control signal for raster enlargement when MAGIC FOCUS is operated. Raster enlargement is required for the MAGIC FOCUS PATTERN to hit the photo sensors. This signal is output from DCU and routed to the base of Q613 for enlarging horizontal size through the Pin Cushion circuit and through Q608 to the Vertical Output IC I601 pin (4) to enlarge the vertical size. In case of AP-85, this control signal is called "A.SIZE". It's the same function between DIG.SIZE and A.SIZE. 31/33: 31/33 represents the actual Deflection Frequency; 31 = 31.5KHz and 33 = 33.75KHz. The microprocessor knows the actual frequency of the incoming signal via Sync supplied. • To the Horizontal Driver IC I701: This tell the Driver IC what output frequency to operate at. • To the DCU: This signal is sent to the DCU to tell it what frequency the Deflection circuit is running at so it
will know what memory to use. The DCU has two different memory modes. One for Progressive mode 31.5KHz and one for HD mode 33.75KHz.
• To the Dynamic Focus Circuit: This signal is also sent to the Dynamic Focus circuit Horizontal Parabola generation circuit to compensate for the higher frequency.
TO CONVERGENCE YOKES: The DCU provides compensation signal for deflection abnormalities to the convergence output IC. The Conver-gence output IC in turn, amplify the signals and rout them to the convergence yokes. +B 120V1: The Deflection transformer receives the 120V V1 DC source. +B 120V2: The High Voltage Transformer TH01 (Flyback) receives the 120V V2 DC source. HV PARABOLA: See DF Out. SCREEN 700V: 700V Supplied to the screen grids on the CRT’s. FOCUS 9KV: Focus voltage supplied to the CRT’s. 30Kv HV: 32,000 volts DC supplied to the CRT’s anodes. TO DEFLECTION YOKES: Horizontal and Vertical deflection wave forms driving the deflection yokes.
HV Sample
I70110 8
H Out15
FBP InHVCCSwitched AVCC
7Osc.
3 H. Sync In
6
1 78
120V V1
1112
Def.H Pulse
+28V
+28P
Q751
5
8
28V
Q777T751
H. Def. Yoke G
H. Def. Yoke B
H. Def. Yoke R
T752
1
4
Q755PSD3
6To I001 OSDPosition
To PinPUnit
H.Blk.
To Convergence Circuit
To Sweep Loss Det. Circuit QN05
IH023 Gen
1
Error10
Clamp
11 12
9
Drive
9
10
HighVoltage
TH01
QH08
QH01
QH10
120V V2
12
FBP In
Ref. V.
PAG
E 07-06
To Side Pin Circuit
To Dynamic Focus
To X-Ray Protect
910
M28V
M28P
HVCO
VCC
HD
QH09
DP0X SERIES CHASSIS HORIZONTAL DRIVE CIRCUIT
SECTION 8
ADJUSTMENT INFORMATION
PAGE 08-01
DP-0X CHASSIS FACTORY RESET CONDITION
USER CONTROL INITIALIZE (FACTORY RESET)
FUNCTION INITIAL DATA/CONDITION 4 EVENT PROGRAM Not Registered AI OFF ASPECT RATIO 4 X 3 AUTO COLOR ON AUTO LINK OFF BRIGHTNESS ADJUST MODE CCD CHANNEL CHANNEL 1 CCD MODE CAPTION CCD ON/OFF OFF CHANNEL ID Not Registered CHANNEL MEMORY Not Registered CLOCK SET Not Registered COLOR ADJUST MODE COLOR SYSTEM NTSC COLOR TEMPERATURE COOL CONTRAST ADJUST MODE FAMILY FAVORITES Not Registered INPUT ANT A MENU BACKGROUND SHADED MENU LANGUAGE ENGLISH MULTI WINDOW MODE OFF NOISE REDUCTION OFF NTSC Channel (Main, Sub) Channel 03 PARENTAL CONTROL Not Registered SHARPNESS ADJUST MODE SIGNAL SOURCE AIR TINT ADJUST MODE V POSITION 0
AUDIO
MTS Mode STEREO PERFECT VOLUME OFF AUTO NOISE CANCEL OFF LOUDNESS OFF DYNAMIC BASS OFF THEATER MODE SPORTS
FDX CHASSIS BASS 1/2 TREBLE 1/2 BALANCE 1/2 SRS OFF
Continued on Next Page
PAGE 08-02
USER CONTROL INITIALIZE (FACTORY RESET)
FUNCTION INITIAL DATA/CONDITION SWX CHASSIS
SCREEN FORMAT NORMAL SDX and SWX MODELS
GRAPHIC EQUALIZER ALL 0dB (Reset) SURROUND MODE STEREO BALANCE (OFF/PCM) 1/2 MASTER VOLUME 20th STEP VOLUME (FRONT L-STADIUM) 1/2 VOLUME (FRONT R-STADIUM) 1/2 VOLUME (L-ROCK ARENA) 1/2 VOLUME (R-ROCK ARENA) 1/2 VOLUME (L-JAZZ CLUB) 1/2 VOLUME (R-JAZZ CLUB) 1/2 VOLUME (L-DOLBY PRO-LOGIC) 1/2 VOLUME (R-DOLBY PRO-LOGIC) 1/2 VOLUME (L-DOLBY DIGITAL) 1/2 VOLUME (R-DOLBY DIGITAL) 1/2 VOLUME (CENTER-STADIUM) 1/2 VOLUME (CENTER-ROCK ARENA) 1/2 VOLUME (CENTER-JAZZ CLUB) 1/2 VOLUME (CENTER PRO-LOGIC) 1/2 VOLUME (CENTER-DOLBY DIGITAL) 1/2 VOLUME (SURROUND L-STADIUM) 1/2 VOLUME (SURROUND R-STADIUM) 1/2 VOLUME (SURROUND L-ROCK ARENA) 1/2 VOLUME (SURROUND R-ROCK ARENA) 1/2 VOLUME (SURROUND L-JAZZ CLUB) 1/2 VOLUME (SURROUND R-JAZZ CLUB) 1/2 VOLUME (SURROUND L-DOLBY PRO-LOGIC) 1/2 VOLUME (SURROUND R-DOLBY PRO-LOGIC) 1/2 VOLUME (SURROUND L-DOLBY DIGITAL) 1/2 VOLUME (SURROUND R-DOLBY DIGITAL) 1/2 VOLUME (SUB WOOFER-STEREO/PCM) 1/2 VOLUME (SUB WOOFER-STADIUM) 1/2 VOLUME (SUB WOOFER-ROCK ARENA) 1/2 VOLUME (SUB WOOFER-JAZZ CLUB) 1/2 VOLUME (SUB WOOFER-DOLBY PRO-LOGIC) 1/2 VOLUME (LFE-DOLBY DIGITAL) 1/2 TEST TONE OFF SPEAKER SET UP INTERNAL INTERNAL External SP W/ SURROUND YES SUB WOOFER YES LISTENING POSITION MID LISTENING MODE STANDARD INPUT SOURCE VID1 OPTICAL VID2 COAXIAL
DP-0X CHASSIS FACTORY RESET CONDITION
DP0X CHASSIS SIGNAL PWB
QS4
U2043D/YC
REARVIEW
PAGE 08-03
U205FLEXConv.andPinPUnit
U201MainTuner
U202PinP
Tuner
PP1
I001
PFS
SURROUND PWB
2HVIDEOPWB
TERMINAL PWB
MICROPROCESSOR
I010
I011
I012
PR
PL
IC01
DIGITAL BOARDHC4051
I007
DP0X CHASSIS DEFLECTION PWB
DigitalConvergence Unit
I601
DP29+B 120V Green LED
QH01
PCB PDF
RH44
High Voltage ADJ.RH44
TP91
PMB
PMR
PMG
YOKE PLUGS
SK01:SERVICESWITCH
PSD1
CONVERGENCEHEAT SINK
FBT
TH
01 REARVIEW
PAGE 08-04
R630V.SizeAdj.
R683H.SizeAdj.
R686H.Size
Adj. HD
DP37Red LED
DP01
IP01
PQD1
Q701
D752 Q777
Q657
D657
D656
IK01
QK01
QF06
PCGPCR
PQD2
PDC1
IK04 IK05
PSD1 PSD2 PSD3
DP0X CHASSIS CONTROL PWB
PAGE 08-05
DP0X CONTROL SUB P.W.B.
POWERLED
DM09HM01
EFC1
FT
MO1
DP0X CONTROL PWB
R L V S
AUTO DIGICON(MAGIC FOCUS)
FS
DIMMER CONTROLLIGHT RECEIVER
REMOTE CONTROLLIGHT RECEIVER
CH -
CH +
VOLUP
VOLDOWN
INPUT
MENU/SELECT
EFC1
POWER
QM02
DP0X CHASSIS SUB POWER PWB
PAGE 08-06
D903IC POWER
MONITOR RED
T901
SWITCHINGTRANSFORMER
REARVIEW
PQD2PQS1PQU1
PQS2 PQU2
D949STBY +11VGREEN
D931SW +5VGREEN
D927STBY +7VGREEN
D912Audio F SW +29VGREEN
D913Audio R/C SW +29VGREEN
= RED or GREEN LED USED FOR VISUAL TROUBLESHOOTING
D901
I901
S901
S904
S903
S902
PQD1
PQS4
PA
F9016 Amp
I906
I907
I905
1 9 1 10
1 11
7 1
1 8
2 1 2 1
1
3
DP-0X CHASSIS CRT PWB
P851R879
P852Cathode
GREEN
E831
P801
R829
P802Cathode
RED
BLUE
E8A1
PAGE 08-07
P8A1
PTSB
P8A2CATHODE
PVB
GND
SHORT TOKILL THECOLOR
PRV
GND
SHORT TOKILL THECOLOR
PGV
GND
SHORT TOKILL THECOLOR
PTSR
E801
W801
W801
PTSG
PAGE 08-08
DP-0X CHASSIS CLOCK SPEED ACCELERATION PROCEDURE AND CHECK
Use the Clock Speed acceleration to confirm, clock advancement, On/Off Timer, etc. 1) Select Set Up from the Main Menu the Cursor Left and Cursor Right Buttons.
2) Select Clock Set using the Cursor Up and Cursor Down Buttons.
3) Press the Cursor Right button to select Clock Set
4) Set the clock using the Cursor Up, Cursor Down, Cursor Right buttons. The clock is started when
the Cursor Left button is pressed.
5) Connect the JIG (Diode) shown below between I001 Pins 13 and 35.
6) Check that the clock indicaiton is displayed using the RECALL button and the clock is advancing
1 minute per second.
I001MicroProcessor
I RefDSP SO
13 35
Diode
PAGE 08-09
DP-0X CHASSIS HIGH VOLTAGE ADJUSTMENT PROCEDURE
1) Connect High Voltage meter to FBT High Voltage output. Connect Ground of High Volt-age meter to CRT Ground or FBT Ground.
2) Check that the High Voltage adjustment VR (RH44) is set to it’s mechanical center on the Deflection PWB. This VR is located just behind the Flyback transformer as viewed from the Front of the set. (See diagram below)
3) Receive an NTSC generator signal. (Picture should be sta-tionary for this adjustment.
4) Video Controls should be set to Factor Settings.
5) Adjust the High Voltage to the following specifications by turning RH44 slowly.
• ADJ. SPEC. = 31.5 kV +/ - 0.5 kV for (DP07)
• ADJ. SPEC. = 30.0 kV +/ - 0.5 kV for (DP05/DP05F and DP06)
6) Lock Paint the control. If avail-able.
RH44
High Voltage ADJ.
CO
NV
ERG
ENC
EH
EAT SIN
K
FBT
TH01
DEFLECTION PWB FRONT
PAGE 08-10
DP-0X CHASSIS HIGH VOLTAGE LIMITER CHECK
Check Preparation: 1) The set can face any di-
rection. 2) Receive the Cross-Hatch
Signal 3) VIDEO CONTROLS:
Factory Preset. 4) SCREEN FORMAT:
Should be PROGRES-SIVE mode.
5) Attach the JIG (1k ohm
1/8W resistor) to both ends of DH31 as shown in the diagram below. (See Diagram Below)
Checking Procedure : 1) Check that the picture is
turned off and the hori-zontal deflection circuit stops operation.
After Checking: 1) Unplug set and Remove
Jig. Allow set to remain in the off condition for at least 15 seconds.
2) Apply AC and confirm the set returns to normal operation.
RH54
RH55
CH30
DH31
DH24
+50V Pulse Add JIG to check HiVolt Limit Circuit
JIG = 1k ohm 1/8W
PAGE 08-11
DP-0X CHASSIS FLYBACK PROTECTION CIRCUIT CHECK
Check Preparation: Check number (1): 1) The set can face any di-
rection. 2) Receive the Cross-
Hatch Signal 3) VIDEO CONTROLS:
Factory Preset. 4) SCREEN FORMAT:
Should be PROGRES-SIVE mode.
5) Attach a 100 K ohm 1/16W ~ 1/8W resistor between QP04 base and Gnd. (SD4 connector Pin 4).
Check number (2): 1) The set can face any di-
rection. 2) Receive the Cross-
Hatch Signal 3) VIDEO CONTROLS:
Factory Preset. 4) SCREEN FORMAT:
Should be PROGRES-SIVE mode.
5) Attach a 100 K ohm 1/16W ~ 1/8W resistor between QH03 base and Gnd.
Checking Procedure : 1) Check that the picture is
turned off and the hori-zontal deflection circuit stops operation.
After Checking: 1) Unplug set and Remove
Jig. Allow set to remain in the off condition for at least 15 seconds.
2) Apply AC and confirm the set returns to nor-mal operation.
PAGE 08-12
DP-0X CHASSIS SWEEP LOSS DETECTION CIRCUIT CHECK
Check Preparation: Check Number (1): 1) The se t can f a ce any
d i rec t ion . 2) Rece i ve t he C ro s s-
Ha t ch S igna l 3) VIDEO CONTROLS:
Fac to ry P rese t . 4) SCREEN FORMAT:
Shou ld be PROGRE S-SIVE mode .
5) A t t a ch t he J IG (A ) ( 1 00 ohm 1 / 8W r e s i s-tor) to r ight hand s ide o f RN01 and t o G r ound a s s hown i n the d i ag ram be low . (See J ig (A) D iagram Be l ow )
Check Number (2): 1) The s e t can f a ce any
d i rec t ion . 2) Rece i ve t he C ro s s-
Ha t ch S igna l 3) VIDEO CONTROLS:
Fac to ry P rese t . 4) SCREEN FORMAT:
Shou ld be PROGRE S-SIVE mode .
5) A t tach the J IG (B) ( 1 00 ohm 1 / 8W r e s i s-tor) to r ight hand s ide o f RN11 and t o G r ound a s s hown i n the d i ag ram be low . (See J ig (B) D iagram Be l ow )
Checking Procedure : 1) C heck tha t the p i c tu re
i s turned of f in e i ther check .
After Checking: 1) Remove J i g a f t e r e a ch
check . 2) Con f i rm the se t re-
turns to normal opera-t ion.
QN01 RN01CN01
RN02
Add JIG to check HiVolt Limit Circuit
JIG = 100 ohm 1/8W
A
QN05 RN11CN04
RN12
Add JIG to check HiVolt Limit Circuit
JIG = 100 ohm 1/8W
B
PAGE 08-13
DP-0X CHASSIS VOLTAGE CHECK
POWER SUPPLY VOLTAGE CHECKS.
Set the AC input power supply to 120 Vac +/-1V.
Receive NTSC CrossHatch Signal
Set the Contrast and Brightness to MAX.
Measure after 30 Seconds of Set Operation.
Audio: MUTE
Measuring Point NTSC CrossHatch Stand-By Mode
No. Description + Side Pin - Side Pin Voltage +/- Current Voltage +/- 1 SW +35 PQS1 1 PQS1 2 32.66 1.5 0.003
2 STBY +11V PQS1 3/4/5 PQS1 6/7 11.3 1.0 1.30 11.3 1.0
3 STBY +7V PQS2 1/2/3 PQS2 4/5/6 7.20 1.0 0.80 7.3 1.0
4 SW +5V PQS2 7/8 PQS2 9 5.6 0.5 0.66
5 SW +29V AQU1 1/2 AQU1 3/4 31.60 1.5 0.14
6 SW +29V AQU1 5/6 AQU1 3/4 32.20 1.5 0.06
7 SW +12V PQU2 1 PQU2 2 12.30 0.5 0.04
8 SW -12V PQU2 3 PQU2 2 -12.80 0.5 0.11
9 STBY +7V PQU2 5/6 PQU2 7/8 7.72 1.0 0.14 7.3 1.0
10 STBY +11V PQU2 3 PQU2 2 11.44 1.0 0.06 11.3 1.0
11 SW -12V PQU2 6 PQU2 4 -12.80 0.5 0.00
12 SW +12V PQU2 7 PQU2 4 12.20 0.5 0.09
POWER SUPPLY PWB
Measuring Point NTSC CrossHatch Input Stand-By Mode
No. Description + Side Pin - Side Pin Voltage +/- Current Voltage +/- 1 +200V PDC1 1 PDC1 4 223.0 2.0 0.12
2 +28V PDC1 3 PDC1 4 27.3 0.5 0.11
3 HEATER PDC1 5 PDC1 4 6.22 0.5 0.67
4 STBY+11V PQD2 3 PQD2 2 11.26 1.0 0.06 11.3 1.0
5 SW-12V PQD2 6 PQD2 4 -12.00 0.5 0.00
6 SW+12V PQD2 7 PQD2 4 12.3 0.5 0.00
7 SW+8V CP31 + CP31 - 8.77 0.5 0.24
8 SW-8V CP32 + CP32 - -9.12 0.5 0.13
9 +B CP33 + CP33 - 119.74 1.0 0.72
10 +28V CP40 + CP40 - 27.75 1.0 1.25
11 -28V CP41 + CP41 - -23.11 1.0 0.48
DEFLEC-TION PWB
PAGE 08-14
DP-0X MAGNET AND YOKE LOCATION
(5) Beam Alignment magnets(6) Focus Block Assembly
RED, GREEN & BLUE FOCUS CONTROLSAlso: SCREEN CONTROLS for RED, GREEN & BLUE
(1) Centering magnet RED(2) Centering magnet GREEN(3) Centering magnet BLUE(4) Beam Form Magnets
DP-0X MAGNETSAdjustment Points
RED CRT GREEN CRT BLUE CRT
21 3
4
5
6
4
4
5
5
FRONT
PAGE 08-15
DP-0X CHASSIS ADJUSTMENT ORDER
It is necessary to follow an order when doing adjustments in the DP-0X chassis.
DP-0X SERVICE ADJUSTMENT ORDER “PREHEAT BEFORE BEGINNING”
Order Adjustment Item Screen Format Signal DCU Data Pre HEAT (30 Minutes) N/A NTSC N/A
2 Pre Focus Lens and Static Progressive NTSC
3 DCU Phase Data Setting Progressive NTSC
4 DCU Phase Data Setting HD 2.14H
5 Horz. Position Adj. (Coarse) Progressive NTSC
6 Horz. Position Adj. (Coarse) HD 2.14H
7 Raster Tilt Progressive NTSC CLEAR
8 Beam Alignment Progressive NTSC
9 Raster Position Progressive NTSC CLEAR
10 Horz. Size Adjust Progressive NTSC CLEAR
11 Vertical Size Adjust Progressive NTSC CLEAR 12 Beam Form Progressive NTSC
13 Lens Focus Adjust Progressive NTSC
14 Static Focus Adjust Progressive NTSC
15 Blue Defocus Progressive NTSC
16 White Balance Adjustment Progressive NTSC 17 Sub Brightness Adjustment Progressive NTSC Color Bar
18 Horz. Position Adjustment (Fine)
Progressive NTSC
19 Horz. Position Adjustment (Fine)
HD 2.14H
20 Convergence Alignment Progressive NTSC CLEAR to start
21 Convergence Alignment HD 2.14H
22 Magic Focus Initialize Progressive NTSC
23 Magic Focus Initialize HD 2.14H
It is necessary to follow the order when performing an alignment on the DP-0X chassis.
1 Cut Off Progressive NTSC
PAGE 08-16
DP-0X CHASSIS PRE-HEAT RUN ADJUSTMENTS
PRESET EACH ADJUSTMENT VR TO CONDITION AS SHOWN: A) Before Pre Heat Run. 1) Red and Green Drive VR
on the CRT PWB. (Not on Blue CRT). Pre set between the 12 o’clock and 2 o’clock position.
2) SCREEN VR ON FOCUS PACK. Pre Set fully counter clockwise.
3) Focus VR on focus pack Pre Set fully clockwise.
Allow set to operate at least 30 Minutes before beginning adjustments.
12~2
DRIVE VR
SCREEN VR
FOCUS VR
Projection Front View
R G B
R G B
Screen VR
Focus VR
FOCUS PACK
RED CRT GREEN CRT BLUE CRT
PAGE 08-17
DP-0X CHASSIS CUT-OFF (SCREENS) ADJUSTMENT
ADJUSTMENT PREPARATION: A) Pre Heat Run should be finished. ADJUSTMENT PROCEDURE: 1) Go to I2C ADJ. Mode.
(With power ON, press the TV/SAT and the CURSOR DOWN [q] button. The Service Menu is displayed.)
2) Choose SERVICE item [2] of I2C ADJ. Mode. (Select CURSOR RIGHT [u] and the Vertical will collapses).
3) Adjust any Screen VR. Screen VR should be turned clockwise gradually until that particular color is barely visible.
4) Repeat for the other two colors.
Projection Front View
R G B
R G B
Screen VR
Focus VR
FOCUS PACK
RED CRT GREEN CRT BLUE CRT
PAGE 08-18
DP-0X CHASSIS PRE-FOCUS ADJUSTMENT
ADJUSTMENT PREPARATION: A) Pre Heat Run should be finished. FOCUS ADJUSTMENT: 1) Short the 2pin sub-
miniature connector on the CRT PWB (TS), to remove any color not being adjusted and adjust one color at a time. (The adjustment order of R, G and B is just an example.)
2) Adjust the Focus VR for Red until Focus is achieved. (A Fine Adjust-ment will be made later.)
3) Repeat for Blue and Green.
4) To Return to Service Menu, press the CURSOR RIGHT [u] key on re-mote.
Projection Front View
R G B
R G B
Screen VR
Focus VR
FOCUS PACK
RED CRT GREEN CRT BLUE CRT
PAGE 08-19
DP-0X CHASSIS DCU CROSSHATCH PHASE ADJUSTMENT
Adjustment Preparation: 1) Cut Off adjustment should
be finished. 2) Video Control: Brightness
90%, Contrast Max. 3) Adjustment Procedure: 1) Receive any NTSC signal. 2) Screen Format is Progres-
sive 3) Press and Hold the
SERVICE ONLY switch on the deflection PWB.
4) Press the HELP key on the Remote, then press the EXIT key. (This is the Phase adjustment mode).
5) Adjust data value using the keys indicated in the chart, until the data matches the values indi-cated in the chart.
Exiting Adjustment Mode: 6) Press Help key on remote
control. 7) Press SWAP key
TWICE to store the information.
8) When Green dots are displayed, press the 8 key on remote.
9) Press the SERVICE ONLY switch to return to normal mode.
HD Mode Adjustment Mode: 10) Change the Display
Format to HD 2.14H Mode.
11) Repeat steps 3 through 9 for the HD 2.14H mode.
PHASE MODE
Display Format PROGRESSIVE
ADJUST USING Address Data Value Address Data Value
4 and 6 keys on Remote PH-H BB PH-H BB
2 and 5 keys on Remote PH-V 0C PH-V 07
Cursor Left t and Right u on Remote CR-H 4C CR-H 4C
Cursor Up p and Down q on Remote CR-V 00 CR-V 0C
Display Format HD
PAGE 08-20
DP-0X CHASSIS HORIZONTAL PHASE (COARSE) ADJUSTMENT
Adjustment Preparation: 1) Cut Off, DCU Phase ad-
justments should be fin-ished.
2) Video Control: Brightness 90%, Contrast Max.
Adjustment Procedure PROGRESSIVE MODE: 1) Receive any NTSC cross-
hair signal. 2) Screen Format is PRO-
GRESSIVE. 3) Press the SERVICE
ONLY switch on the de-flection PWB and display the Digital Convergence Crosshatch pattern.
4) Mark the center of the Digital Convergence Crosshatch Pattern with finger and press the SER-VICE ONLY switch to return to normal mode.
5) Enter the I2C Bus align-ment menu and select Item [12] H POSI and ad-just the data so that the center of Video matches the location of the Digital Crosshatch pattern noted in step {4}.
6) Exit from the I2C Menu. HD Mode Adjustment: 1) Receive any 2.14H signal. 2) Screen Format is HD. 3) Press the SERVICE
ONLY switch on the de-flection PWB and display the Digital Convergence Crosshatch pattern.
4) Mark the center of the Digital Convergence Crosshatch Pattern with finger and press the SER-VICE ONLY switch to return to normal mode.
5) Enter the I2C Bus align-ment menu and select Item [12] H POSI and ad-just the data so that the center of Video matches the location of the Digital Crosshatch pattern noted in step {4}.
6) Exit from the I2C Menu.
PAGE 08-21
DP-0X CHASSIS TILT (RASTER INCLINATION) ADJUSTMENT
Adjustment Preparation: 1) The set can face any direc-
tion. 2) Receive the Cross-Hatch
Signal 3) VIDEO CONTROLS:
Factory Preset. 4) SCREEN FORMAT:
should be PROGRES-SIVE mode.
5) The lens focus should have been coarse adjusted.
6) The electrical focus should have been coarse adjusted.
7) The Digital Convergence RAM should be cleared. (Turn power off, press and
hold the SERVICE ONLY switch, then press the POWER button). The Service Only switch is on the Deflection PWB.
Adjustment Procedure : GREEN: 1) Apply covers to the RED
and BLUE lenses or short the 2P Sub Mini connector [TS] on each CRT PWB to produce only GREEN.
2) Turn the Green deflection yoke and adjust the TILT until the green is level.
3) [+/- 2mm tolerance]. See diagram.
RED: 1) Remove cover from RED
CRT and align RED with GREEN.
2) [+/- 1mm tolerance when compared to Green]
BLUE: 1) Remove cover from
BLUE and cover the RED CRT. Align BLUE with GREEN.
2) [+/- 1mm tolerance when compared to Green]
3) REMOVE ALL COV-ERS.
4) Turn the power off.
l =< 2mm
Vertical Center axis of Cross-Hair signal
l
PAGE 08-22
DP-0X CHASSIS BEAM ALIGNMENT ADJUSTMENT
Preparation for adjustment: 1) Pre Heat, Pre-optical focus,
DCU Phase Data, H. Pos Course and Raster Tilt adjust-ment should be completed.
2) Brightness: 90% Contrast Max.
4) Receive cross hatch signals, or dot pattern RASTER TILT adjustment should be finished.
5) SCREEN FORMAT should be PROGRESSIVE mode.
Adjustment procedure: 1) Green (G) tube beam alignment
adjustment: Short-circuit 2P subminiature connector plug pins of Red (R) and Blue (B) on the CRT boards and project only Green (G).
2) Put Green (G) tube beam align-ment magnet to the cancel state as shown in Figure 1 . (See Fig-ure 1.)
3) Turn the Green (G) static focus VR counterclockwise all the way and make sure of position of cross hatch center on screen.
4) Turn Green (G) static focus VR clockwise all the way.
5) Turn two Beam alignment mag-net in any desired direction and move cross hatch center to posi-tion found in step (3). (See Fig-ure 2 below).
6) If image position does not shift when Green static focus VR is turned, adjustment complete.
7) If image position does move, repeat steps [2] through [6].
8) Conduct beam alignment for Red and Blue in the same way.
9) Red (R) focus on focus pack. 10) Blue (B) focus on focus pack. 11) Upon completion of adjust-
ment, place a small amount of white paint on the beam align-ment magnets, to assure they don’t move. (If available).
T h e f i g u r e s h o w s t h a t t h e l o n g a n d
s h o r t k n o b s o f t h e 2 P m a g n e t a r e
a l i g n e d , t h i s i s t h e c a n c e l s t a t e .
Figure 1
(NO ADJUSTMENT)ZERO FIELD SPACER
PICTURE TUBE SIDE
4-POLE BEAM SHAPECORRECTION MAGNET
2-POLE BEAMALIGNMENT MAGNET
ADJUSTMENTTABS BEAM SHAPE &
ALIGNMENT MAGNET
F i g u r e 2
PAGE 08-23
DP-0X CHASSIS RED AND BLUE RASTER OFF SET ADJUSTMENT
INFORMATION: Raster Off set is necessary to conserve Memory allocation. It is very important to remember that the Red is off-set Left of Center and Blue is off-set Right of center. Please use the following information to accurately offset Red and Blue from center. Also see Overlay Dimensions for further details.
MODEL NUMBER RED OFFSET LEFT OF CENTER
BLUE OFFSET RIGHT OF CENTER
ASPECT
43FDX01B 20mm 35mm 4X3
53FDX01B 15mm 25mm 4X3
53SDX01B 15mm 25mm 4X3
53SWX01B 15mm 25mm 16X9
61SDX01B 15mm 25mm 4X3
61SWX01B 15mm 25mm 16X9
Red Blue
Geometric Center
PAGE 08-24
DP-0X HORIZONTAL SIZE ADJUSTMENT
HORIZONTAL SIZE: (Display Mode PROGRES-SIVE or HD as Depicted) • Install the correct Overlay
dependant upon the Dis-play Mode being adjusted.
• Input any NTSC Signal. • Digital Convergence
RAM should be cleared. With Power Off, press and hold the Service Only Switch on the Deflection PWB, then press Power.
• Project only the Green raster.
FOR PROGRESSIVE MODE 1) Adjust R683 (Horz. Size
Adj. VR) to match marks on the Overlay.
FOR HD MODE 2) Adjust using R686 (Horz.
Size Adj. VR) to match marks on the Overlay. (See Figure Below)
3) Press “Power Off” to exit Service Menu.
Alternate Method: Adjust Horizontal Size until the size matches the chart be-low.
L= DP06 DP06 DP05/05F DP05/O5F DP07 DP07
Progressive Mode
HD Mode Progressive Mode
HD Mode Progressive Mode
HD Mode
Size of Screen
Distance of l Distance of l Distance of l Distance of l Distance of l Distance of l
61 Inch 1200 +/- 5mm 1200 +/- 5mm - - 1305 +/- 5mm 1305 +/- 5mm
60 Inch - - 1190 +/- 5mm 1190 +/- 5mm - -
53 Inch 1050 +/- 5mm 1050 +/- 5mm 1050 +/- 5mm 1050 +/- 5mm 1135 +/- 5mm 1135 +/- 5mm
50 Inch - - 995 +/- 5mm 995 +/- 5mm - -
46 Inch - - - - - -
43 Inch - - 860 +/- 5mm 860 +/- 5mm - -
lBetween Outside Lines
HORIZONTAL SIZE
PAGE 08-25
DP-0X VERTICAL SIZE ADJUSTMENT
VERTICAL SIZE: (Display Mode PROGRES-SIVE or HD) Vertical rate stays the same. 1) Adjust using R630
(Vertical Size Adj. VR) to match marks on the Over-lay. (See Figure Below)
2) Press “Power Off” to exit Service Menu.
NOTE: Centering magnet may be moved to facilitate. Distance is important, not centering.
NOTE: The Vertical Fre-quency is shared between Progressive and HD modes. Alternate Method: Adjust Vertical Size until the size matches the chart below.
l
VERTICAL SIZE
L= DP06 DP05/05F DP07
Progressive Mode
Progressive Mode
Progressive Mode
Size of Screen Distance of l Distance of l Distance of l
61 Inch 775 +/- 5mm - 635 +/- 5mm
60 Inch - 770 +/- 5mm -
53 Inch 670 +/- 5mm 670 +/- 5mm 550 +/- 5mm
50 Inch - 650 +/- 5mm -
46 Inch - - -
43 Inch - 550 +/- 5mm -
PAGE 08-26
DP-0X BEAM FORM ADJUSTMENT
(NO ADJUSTMENT)ZERO FIELD SPACER
PICTURE TUBE SIDE
4-POLE BEAM SHAPECORRECTION MAGNET
2-POLE BEAMALIGNMENT MAGNET
ADJUSTMENTTABS
a
b
Figure 1 Figure 2
BEAM SHAPE (FORM) Preparation for adjustment IMPORTANT: Screen format should be “PROGRESSIVE“. 1) Pre Heat, Cut-Off, Pre-optical
focus, DCU Phase Data, H. Pos Course, Raster Tilt, Beam Alignment, Raster Position, Vertical and Horizontal Size adjustment should be com-pleted.
2) Brightness: 90%, Contrast: Max.
3) Input a NTSC DOT signal.
Adjustments procedure: 1) Green CRT beam shape adjust-
ment. 2) Short-circuit 2P sub-mini con-
nectors on Red and Blue CRT PWB to project only the Green beam.
3) Turn the green static focus VR fully clockwise.
4) Make the dot at the screen cen-ter a true circle, using the 4-Pole magnet shown in (Figure 2 be-low.)
5) Also adjust the Red and Blue CRT beam shapes according to the steps (1) to (3).
6) After the adjustment is com-pleted, return R, G and B static VRs to the Best Focus point.
PAGE 08-27
DP-0X LENS FOCUS ADJUSTMENT
Preparation for adjustment 1) Receive the Cross-hatch
pattern signal. 2) The electrical focus adjust-
ment should have been completed.
3) Deflection Yoke tilt should have been adjusted.
4) Brightness = 50% 5) Contrast = 60% to 70% Adjustment procedure 6) Short the 2 pin sub-
miniature connector on the CRT P.W.B. TS, to pro-duce only the color being adjusted and adjust one at a time. (The adjustment order of R, G and B is just an example.)
7) (See Figure 1) Loosen the fixing screw on the lens assembly so that the lens cylinder can be turned. (Be careful not to loosen the screw too much, as this may cause movement of the lens cylinder when tightening.)
8) Rotate the cylinder back and forth to obtain the best focus point, while observ-ing the Cross-Hatch. (Observe the center of the screen).
• Hint: Located just below
the screen are the two wooden panels. Remove the panels to allow access to the focus rings on the Lenses.
9) After completing optical focus, tighten the fixing screws for each lens.
10)When adjusting the Green Optical focus, be very careful. Green is the most dominant of the color guns and any error will be eas-ily seen.
11)Repeat Electrical Focus if necessary.
Figure 1
FIXING SCREW
LENS ASSEMBLY R, G, B.
Lens
Cyli
nder
PAGE 08-28
DP-0X STATIC FOCUS ADJUSTMENT
ADJUSTMENT PREPARATION: A) Pre Heat Run should be finished. FOCUS ADJUSTMENT: 1) Short the 2pin sub-
miniature connector on the CRT PWB (TS), to remove any color not being adjusted and adjust one color at a time. (The adjustment order of R, G and B is just an example.)
2) Adjust the Focus VR for Red until maximum Focus is achieved.
3) Repeat for Blue and Green.
4) To Return to Service Menu, press the CURSOR RIGHT [u] key on re-mote.
Projection Front View
R G B
R G B
Screen VR
Focus VR
FOCUS PACK
RED CRT GREEN CRT BLUE CRT
Screen VRs
Focus VRs
PAGE 08-29
DP-0X BLUE DE-FOCUS ADJUSTMENT
Adjustment Preparation: 1) Video Control: Brightness
90%, Contrast Max. 2) SCREEN FORMAT
should be PROGRES-SIVE mode.
Adjustment Procedure 1) Receive any NTSC cross-
hatch signal. 2) Turn the B FOCUS VR
fully clockwise. 3) Adjust BLUE defocus ac-
cording to the following specifications.
1mm on each side equal-ing 2mm total. See figure Below.
Projection Front View
R G B
R G B
Screen VR
Focus VR
FOCUS PACK
RED CRT GREEN CRT BLUE CRT
Screen VRs
Focus VRs
Blue Defocus “Sticking Out”
Center of Blue crosshatch line
PAGE 08-30
White balance adjustment 1) Screen adjustment 2) High brightness white
balance 3) Low brightness white
balance Adjustment VRs: Screen adjustment VRs on Focus Block Drive adjustment VRs on CRT P.W.B. Red Drive = R829R Green Drive = R879G Preparation for adjustment 1) Start adjustment 20 min-
utes or more after the power is turned on.
2) Turn the brightness and black level OSD to mini-mum by remote control.
3) Receive a tuner signal, (any channel, B/W would be best).
4) Set the drive adjustment VRs (Red R829R and Green R879G) to their me-chanical centers.
Adjustment procedure 1) Go to I2C ADJ. Mode.
(With power ON, press DTV/SAT and Cursor Down buttons at the same time. Service Menu is dis-played.)
2) Choose SERVICE item Number [2] of I2C ADJ. Mode. (Select ON by Cur-sor Right and the Vertical will collapses).
3) Gradually turn the screen adjustment VRs (red, green, blue) clockwise and set them where the red, green and blue lines are equal and just barely visi-ble.
4) Return Service item on I2C ADJ to Off by Cursor Right. Number [2]. Adjust the Sub Brightness Number [1] SUBBRT us-ing I2C Bus alignment procedure so only the slightest white portions of the raster can be seen.
5) Input a gray scale signal into any Video input and select that input using the INPUT button on the re-mote or front control panel.
6) Turn the Brightness and Contrast OSD all the way up.
7) Make the whites as white
as possible using the drive adjustment VRs (Red R829 and Green R879).
8) Set the Brightness and Contrast to minimum. (10800 Kelvin)
9) Adjust the low brightness areas to black and white, using screen adjustment VRs (red, green, blue).
10) Check the high brightness whites again. If not OK, repeat steps 6 through 9.
11) Press the MENU key on remote to Exit Service Menu.
DP-0X WHITE BALANCE ADJUSTMENT
Projection Front View
R G B
R G B
Screen VR
Focus VR
FOCUS PACK
RED CRT GREEN CRT BLUE CRT
Screen VRs
Focus VRs
Note: When Vertical is collapsed, make adjustments quickly, the image can burn the CRTs.
PAGE 08-31
ALTERNATE METHOD: ADJUSTMENT PREPA-RATION: (Coarse Adjustment) 1) Start adjustment 20 min-
utes or more after the power is turned on.
2) Receive a tuner signal. 3) Set the contrast and color
controls to minimum. 4) Set the brightness to mini-
mum position on the dis-play.
5) The room light should be very low.
ADJUSTMENT PROCE-DURE 1) Go to I2C ADJ. Mode.
(With power ON, press TV/SAT and Cursor Down buttons at the same time. Service Menu is dis-played.)
2) Adjust Sub Brightness Number [1] SUBBRT, so that only the brightest points of the picture can be seen on screen, using I2C Bus alignment procedure.
3) (Also see White Balance Tracking).
4) Press the MENU key to exit Service Menu
USING A GENERATOR: 1) Use the input signal
shown below, (GRAY SCALE)
2) Adjust Sub Brightness Number [1] SUBBRT, so that the points A1 and A2 sink to black and A3 is slightly visible, using I2C Bus alignment procedure.
3) Press the MENU key to exit Service Menu
DP-0X SUB BRIGHTNESS ADJUSTMENT
R G B
R G B
Screen VR
Focus VR
FOCUS PACK
Projection Front View
RED CRT GREEN CRT BLUE CRT
Screen VRs
Focus VRs
Note: When Vertical is collapsed, make adjustments quickly, the image can burn the CRTs.
W Y CY G MG R BL
A7 A6 A5 A4 A3 A2 A1
75%
B
D
Q I W 100% BLK
The background is set to black. Perform the adjustment without observing the boundary parts.
The background is set to lighter black.
PAGE 08-32
Adjustment Preparation: 1) Video Control: Brightness
90%, Contrast Max. Adjustment Procedure PROGRESSIVE MODE: 1) Receive any NTSC circle
pattern signal. 2) Screen Format is PRO-
GRESSIVE 3) Enter the I2C Bus align-
ment menu and select Item [12] HPOSI
4) Adjust the data so that the Left and Right hand side are equal as noted in the figure on the right.
5) Press the “MENU” button to exit from the Service Menu.
HD Mode Adjustment: 1) Receive any 2.14H
33.75kHZ signal. 2) Display Format is HD
mode.
3) Enter the I2C Bus align-ment menu and select Item [12] HPOSI
4) Adjust the data using the left and right cursor keys and balance the Left and Right hand side.
5) Press the “MENU” button to exit from the Service Menu.
DP-0X HORIZONTAL POSITIONS (FINE) ADJUSTMENT
PROGRESSIVE MODE: Balance left and right side display position.
HD MODE: Balance left and right side display position.
PAGE 08-33
BR
H. SIZE
V. SIZE Progressive ( ) HD [ ]
Centering Offset
Red and Blue Centering Offset is necessary to free up memory in the Digital Convergence Unit. It is important to offset the Red and Blue centering during Magnet Centering. Failure to do so, could produce a Memory Overrun error. Red Offset = 20mm and Blue Offset = 35mm for Progressive and HD Mode. Green is Geometrically centered.
DP-05F OVERLAY DIMENSIONS FOR THE 43 INCH (4 x 3 Aspect) JIG
HORIZONTAL SIZE Progressive Mode = 860 HD Mode = 860
VERTICAL SIZE Progressive Mode = 550 HD Mode = 550
(72) [72]
(46.7) [41.8]
(93.4) [83.6]
(1.1) [35.4]
(5) [5]
(874) [874]
(656) [656]
H312225 = Progressive Mode JIG Screen Kit H312226 = HD Mode JIG Screen Kit
Not for 43GX01B Use: H310222 Overlay Jig
PAGE 08-34
BR
H. SIZE
V. SIZE Progressive ( ) HD [ ]
Centering Offset
Red and Blue Centering Offset is necessary to free up memory in the Digital Convergence Unit. It is important to offset the Red and Blue centering during Magnet Centering. Failure to do so, could produce a Memory Overrun error. Red Offset = 15mm and Blue Offset = 25mm for Progressive and HD Mode. Green is Geometrically centered.
DP-05/06 OVERLAY DIMENSIONS FOR THE 53 INCH (4 x 3 Aspect) JIG
(88.8) [88.8]
(57.5) [43.5]
(115) [103]
(1.5) [43.5]
(6.2) [6.2]
(1078) [1078]
(808) [808]
HORIZONTAL SIZE Progressive Mode = 1050 HD Mode = 1050
VERTICAL SIZE Progressive Mode = 670 HD Mode = 670
H312223 = Progressive Mode JIG Screen Kit H312224 = HD Mode JIG Screen Kit
Not for Other 53 Inch Models Use:
H310359 Progressive H312184 HD Mode
Overlay Jigs
PAGE 08-35
BR
H. SIZE
V. SIZE Progressive ( ) HD [ ]
Centering Offset
Red and Blue Centering Offset is necessary to free up memory in the Digital Convergence Unit. It is important to offset the Red and Blue centering during Magnet Centering. Failure to do so, could produce a Memory Overrun error. Red Offset = 15mm and Blue Offset = 25mm for Progressive and HD Mode. Green is Geometrically centered.
DP-06 OVERLAY DIMENSIONS FOR THE 61 INCH (4 x 3 Aspect) JIG
(102.1) [102.1]
(66.2) [50]
(132.4) [118.6]
(1.6) [50]
(7.4) [7.4]
(1200) [1200]
(930) [930]
H310355 = Progressive Mode JIG Screen Kit H312181 = HD Mode JIG Screen Kit
HORIZONTAL SIZE Progressive Mode = 1200 HD Mode = 1200
VERTICAL SIZE Progressive Mode = 775 HD Mode = 775
PAGE 08-36
BR
H. SIZE
V. SIZE Progressive ( ) HD [ ]
Centering Offset
Red and Blue Centering Offset is necessary to free up memory in the Digital Convergence Unit. It is important to offset the Red and Blue centering during Magnet Centering. Failure to do so, could produce a Memory Overrun error. Red Offset = 15mm and Blue Offset = 25mm for Progressive and HD Mode. Green is Geometrically centered. Grid show is NOT in proper (16X9) aspect, however values are correct.
DP-07 OVERLAY DIMENSIONS FOR THE 53 INCH (16 x 9 Aspect) JIG
(96.6) [96.6]
(46.9) [42.1]
(94.0) [84.1]
(1.1) [35.6]
(7.0) [7.0]
(1173.2) [1173.2]
(660) [660]
16X9
Unknown = Full Mode JIG Screen Kit Unknown = Smooth/Widel Mode JIG Screen Kit
HORIZONTAL SIZE Progressive Mode = 1135 HD Mode = 1135
VERTICAL SIZE Progressive Mode = 550 HD Mode = 550
PAGE 08-37
BR
H. SIZE
V. SIZE Progressive ( ) HD [ ]
Centering Offset
Red and Blue Centering Offset is necessary to free up memory in the Digital Convergence Unit. It is important to offset the Red and Blue centering during Magnet Centering. Failure to do so, could produce a Memory Overrun error. Red Offset = 15mm and Blue Offset = 25mm for Progressive and HD Mode. Green is Geometrically centered. Grid show is NOT in proper (16X9) aspect, however values are correct.
DP-07 OVERLAY DIMENSIONS FOR THE 61 INCH (16 x 9 Aspect) JIG
(111.2) [111.2]
(54.2) [48.6]
(108.5) [97.1]
(1.3) [41.1]
(7.8) [7.8]
(1350) [1350]
(762) [762]
16X9
Unknown = Full Mode JIG Screen Kit Unknown = Smooth/Widel Mode JIG Screen Kit
HORIZONTAL SIZE Progressive Mode = 1305 HD Mode = 1305
VERTICAL SIZE Progressive Mode = 635 HD Mode = 635
PAGE 08-38
DP-0X DIGITAL CONVERGENCE ADJUSTMENT POINT (3X3 and 5X7) STOPPING POSITIONS
3 X 3 MODE (9 stopping positions) (NOTE: This mode can only be activated when the Digital RAM is cleared.) To clear the RAM: Press and Hold the SERVICE ONLY SWITCH (Service only switch is located on the deflection PWB), then press the POWER BUTTON. Set will have no convergence correction. Press RECALL 5 times on the CLU-572TSI to access the 3 X 3 Mode. NOTE: Old ROM data can be restored by pressing the SWAP button TWICE. The set will be restored to the last condition when data was stored.
1
23
4
5 6 7
8
9
MUST USE OVERLAY IN THIS MODE
Begin with Green in this mode
1
23
4
5 6 7
8
910
11
12 13
14
1520
21
22
16171819
23 24 25 26 27 28 29
30
31
32
333435
5 X 7 MODE (35 stopping positions) DIGITAL CONVERGENCE CURSOR STOPPING POINTS.
Press the 0 button on the remote 5 times. The raster will blink and the cursor will flash indicating 5 X 7 MODE.
This mode should only be needed when a complete Digital convergence adjustment is nece s sary.
Note: Grid will actually be slightly different than shown.
PAGE 08-39
DP-0X DIGITAL CONVERGENCE ADJUSTMENT POINT (13X9) STOPPING POSITIONS
1
23
4
5 6 7
8
9
101112
13
14
15
16 17 18 19 20
21
22
23
242526
27
28
29
30 31
32
33
34
3536
37
38
39
40 41
42
43
44
45
464748495051
52
53
54
55
56
57 58 59 60 61 62 63 64 65 66
78798081828384
93 94 95 96 97 98 99 100
71
72
73
92 101 102 103 104105
106
107
108
109
110
111
67
68
69
70
7475767785
86
87
88
89
90
91
112113114115116117
13 X 9 MODE (117 stopping positions) Press the INPUT button on the CLU-572TSI remote 5 times to activate the 117 stopping posit ions. The raster will blink and the cursor will flash indicating 13 X 9 MODE. NOTE: This is the normal mode when entering the digital convergence adjustment mode.
S o m e t i m e s d u r i n g a d j u s t m e n t , S - D i s t o r t i o n c a n o c c u r . T h i s i s w h e n t h e l i n e h a s a n o t i c e a b l e w a v y
a p p e a r a n c e a t a c e r t a i n l o c a t i o n . I f t h i s i s e n c o u n t e r e d , e n t e r t h e ( 5 X 7 ) m o d e a n d r e a d j u s t t h e l i n e . T h e n
p e r f o r m C a l c u l a t i o n . I t m a y b e n e c e s s a r y t o r e t u r n t o t h e ( 3 X 3 ) m o d e a s w e l l .
N o t e : S t o r e w i l l a l s o p e r f o r m C a l c u l a t i o n .
PAGE 08-40
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Digital Convergence Alignment
Center the Overlay Jig geometrically on the screen
Clear RAM data (DCU RAM)
Select the External Center Cross Signal by
pressing the EXIT button 5 times, then theRemote INPUT button .
No DCU Correction added
results in severepincushion distortion
Center Magnet Adjustments
Press and hold the SERVICE SWITCHButton, then press the POWER Button
simultaneously until the set is on.
When video appears, press SERVICESWITCH again.
Internal
Digital"Cross Hatch
Signal" is
projected
Service only
switch
is on thedeflection
PWB.
Receive any NTSC signal (Crosshair if possible)Set SCREEN FORMAT TO PROGRESSIVE mode
A l i g n t h e G , R , B
individual center crossesto their respective marks
on the Overlay using the
Yoke Center Magnets
Red =Left 15mm
Blue =
Right 25mm
Green =Center
Geometric Center of Screen
External Selected CenterCross with no DCU center
data
R G B
R G BFront View
Use the Centering
Magnets closest tothe Yoke
A
PAGE 08-41
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Press the Remote FRZ button(extra lines will appear at top
and bottom )
Static Centering Alignments(Moves Entire Raster)
A
Press the Remote Cursor buttons tomatch the selected Crosshatch
(red and blue) to the green.
Align Red and Blue static centers
Press the RemoteFRZ button
to exit Static Centering.(extra lines will disappear)
Green should already be centered
Internal CrossHatch Signal
selected
B
Extra Linesappear
indicatingRasterMode
AdjustColor
Left
Adjust Color Up
Adjust Color Down
AdjustColorRight
Remote
SELECT
Input Selects BLUE0 Selects RED
PAGE 08-42
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Press the Remote RECALLbutton 5 times to enter the
3X3 Adjustment Mode
Use the Remote 2, 4, 5, 6 numberbuttons to move the Adjustment
Point location (intersection ofblinking cursor) and the Cursor
Buttons to adjust the lines so thatthe green cross hatch align
with the Overlay (Jig)
Convergence 3x3 Point Adjustment Mode
(Green Coarse Alignment)
Press the RemoteMENU button toproject the green
tube only
Selects GREEN
Before Adjustment
After Adjustment
Moves location ofAdjustment Point
(Intersection ofblinking cursor)
Remote
4 5 6
2
Lines symmetricallyaligned at Adjustment
Points
Cursor blinksat intervals
of 3 toindicate the
3X3Adjustment
Mode
C
Green Only
3X3 Mode =
9 Adjustment Points
RECALL Button
is used forselecting the
3X3Adjustment
Mode (whenpressed 5
times).
(The 3X3 Modecan only be
entered whenthe DCU RAM
data is cleared)
B
Continue on next page
Remote
Adjusted by cursor keys
Press the Remote RECALL button to enter the Green
Adjustment Mode
SELECT
RECALL
Remote
PAGE 08-43
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Press the RemoteINFO button to
interpolate as often asnecessary
Press the Remote "INFO " buttonto Calculate points in between the
adjustment points
C
After interpolation, press the Remote 0 button to
select the Red Convergence Adjustment Mode
0
987
654
Remote
0 Selects RED
Press the Remote 2,4,5,6 buttons to movethe adjustment point, and the Cursor buttonsto converge the selected color onto green
Convergence 3x3 Mode (9 Point) Adjustment
(Red / Blue Coarse Alignment)
Green alwaysprojected
Selects
Blue
Crosshatch isyellow when the
red and greencrosshatches align
Crosshatch is cyan when the blueand green crosshatches align
Has the Blue3x3 Convergence
Mode beenaligned?
Yes
Press MenuButton D
No
White internal crosshatchshould be projected
Calculation averages the error between thepoints to prevent "S" Distortion
Before Calculation
Press the RemoteINPUT button toSelect the BlueConvergence
Adjustment Mode
INPUT C.S.
0
987
654
Remote
Cursor Blinks Blue
Cursorblinks RED
PAGE 08-44
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Press the Remote RECALL button
to project the green only
Convergence 7x5 Point Adjustment(Green Only Alignment)
D
Press the Remote 0 button five
times to enter the 7X5 mode0
987
654
Remote
Selects the 7X5
mode
Press the Remote INFO button to
interpolate points in between theadjustment points
35 convergence adjustment
points in 7X5 mode
E
Use the Remote Cursor and 2,4,5,6 buttons to
perform convergence point adjustment at every
other intersection of the crosshatch
AdjustColor
Left
Adjust Color Up
Adjust Color Down
AdjustColorRight
Remote
Selects GREEN
SELECT
RECALL
Remote
PAGE 08-45
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Press the Remote 0 button to projectthe Red/Green Crosshatch
0
987
654
Remote
Convergence 7x5 Point Adjustment(Red/Blue Alignment)
Press the Remote Cursor and 2,4,5,6buttons to perform convergencepoint adjustment at every otherintersection of the crosshatch
Press the Remote INPUT
button to select the BlueConvergence Adjustment
Mode
0
987
654
Remote
Performadjustment
at every
otherintersection
Has the Blue7X5 Convergence Mode
been aligned?
Yes
Press Menu Button
E
White InternalCrosshatch
should beprojected
Cursor Blinks Blue
Cursor blinks redat intervals of 2to indicate the
7x5 mode
Selects Blue foradjustment
F
Press the
Remote INFObutton to
interpolate asoften as
necessary
Input
PAGE 08-46
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Convergence 13X9 Point Adjustment(Green Only Alignment)
F
Press the Remote RECALLbutton to projectthe green only
Press the Remote INPUTbutton five times to
enter the 13X9 mode
INPUT
Remote
Selects the13X9 mode
Use the Remote Cursor and 2,4,5,6buttons to perform convergencepoint adjustment at every otherintersection of the crosshatch
117 convergenceadjustment points in
13X9 mode
GPress the Remote INFO button tointerpolate points in between the
adjustment points
AdjustColor
Left
Adjust Color Up
Adjust Color Down
AdjustColorRight
Remote
Selects GREEN
RECALL
Remote
SELECT
PAGE 08-47
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Press the Remote " 0 " button to enter RED AdjustmentMode and to project the Red/Green Crosshatch
0
987
654
RemoteConvergence 13X9 (117 Point)
Adjustment (Red/Blue Alignment)
Press the Remote Cursor and2 , 4 , 5 , 6 buttons to performconvergence point adjustment ate v e r y i n t e r s e c t i o n o f t h ecrosshatch
Press the Remote INPUTbutton to select the BlueConvergence Adjustment
Mode
INPUT
Remote
Performadjustment
at everyintersection
Has the Blue13X9 Convergence
Mode beenaligned?
Yes
Press the Menu Buttonto Display all colors
G
White InternalCrosshatchshould beprojected
Cursor Blinks Blue
Cursor blinks redindicating the13X9 mode
Selects Blue foradjustment
No
Press theRemote INFO
button tointerpolate as
often asnecessary
H
AdjustColor
Left
Adjust Color Up
Adjust Color Down
AdjustColorRight
Remote
SELECT
PAGE 08-48
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Store New Convergence Data in Rom
H
Press the Remote MOVE buttontwice to begin the ROM Write
mode = STORE
ROM WRITE?
This screen is projected at the firstpress of MOVE button
Screen goes blank for severalseconds at the second push of
the MOVE button
1 2
3
!!!! WARNING !!!!Initialization must be done after aWrite to Rom, (STORE) in orderfor MAGIC FOCUS to operate.If this is not done, when the
MAGIC FOCUS button is pressed,the Static Centering Mode
will be entered.Return to the Digital Conv.
Adjustment Mode and Initializethe Magic focus.
I
This screen appears with a series ofgreen dots indicating a successful
Write to Rom or Store.Note: If Red dots appear, retry the
process. If Red dots appear thesecond time, replace the Digital
Convergence module.
Press the Remote MOVE button toreturn to the Digital Convergence
Adjustment mode
PAGE 08-49
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES DP-85 DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Magic Focus Initialization
ROM WRITE?1
Again the screen projectsROM WRITE at the first
press of MOVE button
2
3
Press the Menu Button to return to Crosshatch. Finishedwith Digital Convergence Setup for PROGRESSIVE.
Press the Service Only Switch to Exit to Normal Mode
I
MAGIC FOCUS
Press the Remote PIP CH button tobegin the Initialization Mode
Screen projects different lightpatterns during theInitialization Mode
Press the Remote MOVE button once
Change the screen format to HD mode.Install the HD Overlay. Press the Service
Only switch to enter the DCAM.Return to (D) and align to the Overlay.
After completing PROGRESSIVE ANDHD mode adjustments, operation complete.
This screen appears with a series ofgreen dots indicating successful
sensor Data Initialization
PAGE 08-50
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Additional MINOR AdjustmentsAvailable to the Service Technician
AdjustColor
Left
Adjust Color Up
Adjust ColorDown
AdjustColorRight
Remote
Press and hold the Magic Focusbutton for 10 seconds until
STATIC appears on Screen.
Press and Hold Magic Focusbutton for 5 seconds until
CENTER appears on Screen
Release ButtonRelease Button
CENTERADJUSTMENT
Internal crosshatchshould appear.
Internal Crosshair orCenter Cross should appear.
Press "MAGIC FOCUS Button" to Exit to normal Mode
Static or Centeralignment
is off.
STATICADJUSTMENT
STATICCENTER
Center Cross will blink indicatingwhich Color can be adjusted.
Adjust using the cursor keys on the Remote.To select other color, press the Menu Button.
Center Cross will blink indicating whichColor can be adjusted. Adjust using the
cursor keys on the Remote.To select other color, press the Menu
Button.
Screen goes blackfor several seconds.
SELECT
PAGE 08-51
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Enter the Service Mode by pressing theService Only Switch on Deflection PWB.
Convergence TouchupOverlays NOT required!
Touch Upcomplete
Convergence Point AdjustmentIMPORTANT: Begin in PROGRESSIVE mode.
When adjustment is complete, STORE the NewDATA by pressing the MOVE button twice.
Press the Service Only Switchto Exit to PROGRESSIVE mode.
Press "0" five times to select the 7X5 ModePress "INPUT" five times to select the 13X9 Mode
Note: 3X3 mode can not be entered without clearing ROM data.
Press "2, 4, 5, 6" to move Adjustment PointPress cursor Up / Down / Left / Right to Adjust Convergence
After HDhas been completed
1 2
Set display modeto HD mode
After Storing, initialize the MAGIC FOCUSby pressing the MOVE button ONCEand then press the PIP CH button.
See "Complete Digital ConvergenceAlignment procedure" for more details.
Press the MENU button to Removecolors not being adjusted.
SECTION 9
KEY COMPONENT INFORMATION
DP-06 KEY COMPONENTS
DESCRIPTION IDENTIFICATION PART NUMBER
SIGNAL SUB PWB Comes with Signal PWB JT20471
RAINFOREST IC TA1298AN IX01 CP05662URED OUTPUT QX23 2325691RGREEN OUTPUT QX28 2325691RBLUE OUTPUT QX33 2325691RVM OUTPUT QX41 2320637MPOWER / DEFLECTION PWB JT20491
Bridge Rectifier RBV-406M (60V) DP01 2338313RAW 150 Vdc Protector EP91 AZ00109M220V (Screen Voltage) Protector EP92 AZ00107MRegulator Protector EP93 AZ00101MHeater and SW+8V Protector EP94 AZ00109MSW-8V Protector EP95 AZ00109M+28V Protector (Convergence) EP96 AZ00421MM28V Protector (Convergence) EP97 AZ00421M120V Protector (Deflection) EP98 AZ00106MHigh Voltage Driver IC (Regulator) M62501P IH02 CP07091+5V Regulator (for DCU) IK01 CP05571Convergence Mute IC IK02 CP01631R+5V Regulator (for SRAM DCU) IK03 CP05571Convergence Output (RH, RV & GV) IK04 CZ00431Convergence Output (GH, BH & BV) IK05 CZ00431Switching Regulator (Driver IC) IP01 CZ00865Heater Regulator IP02 CP05141120V Regulator IP03 2381349120V Regulator (Photo Coupler) IP04 2000465Vertical Output I601 CP06891Side Pin Cushion (Comparator) I651 2365452Horizontal Driver IC (TA1300AN) I701 CP06551Horizontal Output (High Voltage) QH01 CF02541Shut Down SCR QP01 2323782R120V B+ Excessive Current Sensor QP02 2321112MShort Detection Sensor Transistor QP03 2320637M Horizontal Vcc ON/OFF SW QP04 2327461Horizontal Output (Deflection) Q777 CF02511FDeflection Horizontal Output Driver Q751 2326216Deflection Power Supply Relay (On Sub Power PWB) S901 FJ00142Flyback Transformer (High Voltage) TH01 BW00634MAIN CHASSIS UE07341
SIGNAL PWB JT20471
MICROPROCESSOR (MN102H51KHPP) I001 CP07162UMEMORY EEPROM I002 CK32542RRESET IC I006 CP06941RFRONT AUDIO OUTPUT IC IC01 2004751POWER ON / OFF Relay Driver Q002 2320647M+3.3 Volt REGULATOR Micro. B+ Q029 2312171MAIN TUNER V6-A30FT U001 HC00311PinP TUNER V8-A68CT U002 HC004013D/YC COMB FILTER KC-301S U204 HP00705FLEX CONVERTER (HC5611) U205 CS00491
PAGE 09-01
DP-06 KEY COMPONENTS
TERMINAL PWB JT20481
A/V SELECT IC I401 CK30941U
2-Line COMB FILTER for PinP Only I402 CW00022SUB VIDEO A/V SELECTOR IC (TA1270BF) I403 CK07923USURROUND PWB JT20531SURROUND DAC IC IS01 CK31071R
FRONT AUDIO CONTROL IS03 CK33691RFRONT GRAPHIC EQUALIZATION IS05 CP06901UCENTER/SUBWOOFER AUDIO CONTROL IS08 CK33691RCENTER GRAPHIC EQUALIZER IS10 CP06901UREAR AUDIO CONTROL IS11 CK33691RCENTER AUDIO OUTPUT IC IS15 2004751REAR AUDIO OUTPUT IC IS16 2004751COAXIAL/OPTICAL IC IS17 CK32011RCOAXIAL/OPTICAL INVERTER IC IS18 CK34031RPERFECT VOLUME IS19 CP02601DIGITAL Convergence Unit (HC2151) UKDG CS00451
SUB POWER PWB Signal Power (Low Voltage) JT20501
BRIDGE RECTIFIER D901 2338313RAW 150V PROTECTOR E991 AZ00109MFRONT/REAR AUDIO +28V PROTECTOR E992 AZ00109MCENTER +28V PROTECTOR E993 AZ00109MSTBY+35V PROTECTOR E994 AZ00108M-14V PROTECTOR E995 AZ00108MMAIN FUSE F901 2722359SWITCHING REGULATOR I901 CZ00864REGULATOR FEEDBACK (Photo Coupler) I902 2000465SHUT DOWN (Photo Coupler) I903 2000465CLOCK (AC Photo Coupler) I904 2000465STANDBY +7V REGULATOR I905 CP03922FSTANDBY +11V REGULATOR I906 CP03923FSTAND BY 12V (A12V) REGULATOR I907 CP03922FON/OFF CONTROL Q903 2320591MSHUT DOWN SCR Q905 2323782RAUDIO RELAY DRIVER Q911 2320591MON/OFF RELAY (Deflection B+) S901 FJ00142AUDIO RELAY S902 FJ00142STANDBY +35 VOLT RELAY S903 FJ00142DIGITAL SURROUND PROCESSOR HC4051 US01 CS00481
CONTROL PANEL PWB
INFRARED RECEIVER HM01 CZ00941VELOCITY MODULATION PWB Comes with CRT PWBs JT20511
CRT PWB Comes with Velocity Modulation PWB JT20511
RED DRIVER Q805 2312372FGREEN DRIVER Q855 2312372FBLUE DRIVER Q8A5 2312372FRED CRT SOCKET E801 EY00941GREEN CRT SOCKET E851 EY00941BLUE CRT SOCKET E8A1 EY00941
PAGE 09-02
DP-06 KEY COMPONENTS
ADDITIONAL PARTS INFORMATION
REMOTE CONTROL CLU-752TSI HL01322
SCREEN ASSY. 53” KR01162 SCREEN ASSY. 61” KR01161BLUE CRT ASSY. 53” UE07893GREEN CRT ASSY 53” UE07892 RED CRT ASSY 53” UE07891 BLUE CRT ASSY. 61” UE07896GREEN CRT ASSY 61” UE07895RED CRT ASSY 61” UE07894MIRROR GLASS (61”) GLASS KS00163MIRROR GLASS (53”) GLASS KS02021FOCUS PACK TYPE MHF116 AZ0006 DEFLECTION YOKE BY01551SOLAR BATTERY (MF Sensors) FT00011CONVERGENCE JIG OVERLAY (Progressive) H310359 CONVERGENCE JIG OVERLAY (HD) H312184 SBB LENS Assy. BLUE 53” KQ00371KSBB LENS Assy. BLUE 61” KQ00431KSBB LENS Assy. GREEN 53” KQ00374KSBB LENS Assy. GREEN 61” KQ00434KSBB LENS Assy. RED 53” KQ00375KSBB LENS Assy. RED 61” KQ00435KULTRA SHIELD 61” KR01573ULTRA SHIELD 53” KR01291SPEAKER GRILLE 61SDX01B PH06772SPEAKER GRILLE ASSY 53SDX01B PH07412ANTENNA SWITCH HP00771ANTENNA SWITCH HP00771
PAGE 09-03
