Reg. No. :

M.E./M.Tech. DEGREE EXAMINATION, JANUARY 2011.

First Semester

VLSI Design

(Common to Applied Electronics)

252101 – DSP INTEGRATED CIRCUITS

(Regulation 2010)

Time : Three hours Maximum : 100 marks

Answer ALL questions.

PART A — (10 × 2 = 20 marks)

1. List few applications of ASIC’s?

2. Draw the two input NAND gate using MOS logic.

3. Calculate the % reduction in computation via FFT when N = 512. Assume radix - 2 DIT algorithm.

4. Write the discrete cosine transform pair.

5. If

↑

= },5.7,5.2,5.6,7,2,1,0{)(nx find )3( nx .

6. Define first order coefficient sensitivity of digital system.

7. What are the characteristics of ideal DSP architecture?

8. State the advantages of Bitserial system (DSP).

9. Name the FFT processor, IC No.

10. Compare Conventional number system with residue number system.

PART B — (5 × 16 = 80 marks)

11. (a) Describe with the help of block diagram DSP system, design from first principles.

Or

(b) Write short notes on

(i) CMOS circuit of two input XOR gate and its working principle and VLSI layout.

(ii) VLSI process technologies.

Question Paper Code : 20107

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12. (a) Explain the least mean square (LMS) method of finding optimal weight

vector for stationary random signals. (Assume Adaptive transversal

filter)

Or

(b) (i) Find the DFT of the following sequences.

(1) ,2,1,0,)75.0()( == nnxn

—————7

,9,8,0 == n —————15

(2) ,2,1,0),2()1()( =−+−= nnnnx δδ ————— 7.

(ii) State and explain the sampling process of analog signals.

13. (a) Describe a rational sampling rate converter with frequency conversion

factor L/M = 0.8

(i) Sketch a block diagram of sampling rate converter.

(ii) Find the difference equation for the sampling rate converter.

Or

(b) (i) Draw the three different structure for H(z)

)6.0()06.05.0()1()( 1121 ++++= −−−−zzzzzH

(ii) Explain a method of measurement of round off noise in digital

system.

14. (a) (i) Differentiate between multiprocessors with multicomputers.

(ii) Explain systolic and wave front arrays and its applications.

Or

(b) What is complex PE? Discuss the hardware implementation based on

complex PE? What are its merits and demerits of such system?

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15. (a) Design a complex multiplier using two different techniques and compare

their performance.

Or

(b) Write short notes on

(i) Residue number system.

(ii) Layout of VLSI circuit by taking an example.

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