12
Introduction to USRP E310 1 www.tenettech.com

E3XX_USRP.pdf

Embed Size (px)

DESCRIPTION

The USRP E310 integrates a rich set of features and peripherals necessary for mobile radio, wireless sensor networks, and remote sensing applications such as the integrated GPS for position awareness and time synchronization, and two host USB ports for extending storage, I/O and communication options with off-the-shelf USB devices. Using the same USRP Hardware Driver™ (UHD) architecture, common to all Ettus Research USRP devices, designers can programmatically control all USRP devices with a common UHD C++ API, or choose from a wide selection of third-party tools and software such as GNU Radio.

Citation preview

Page 1: E3XX_USRP.pdf

Introduction to USRP E310

1

www.tenettech.com

Page 2: E3XX_USRP.pdf

USRP E300: DEPLOYABLE SDR

Applications

• Deployed monitoring and generation

• Sensor network research

• Land mobile communication / safety radio

Features

• 2x2 TX/RX Channels, 70 MHz – 6 GHz

• Customizable Xilinx 7 Series FPGA

• Selectable RX/TX filter banks for improved RF

• Integrated battery for portable/ deployed operation

• 375 grams (with reduced weight options)

• 2-6W typical

Audience

• Mil/Aero/Gov

• Academic Research

www.tenettech.com

Page 3: E3XX_USRP.pdf

USRP E300 SYSTEM ARCHITECTURE

AD9361

RFIC

Ethern

et

GPS

Ant

TRX-A

RX2-A

TRX-B

RX2-B

Power

USB 2.0 Host

MicroSD Flash

JTAG

Debug

Power

Management

Filter bank ARM

ARM

1GB

DRAM 512MB

DRAM

TCXO

FP

GA

Local

Oscillator &

Sample

Clock

GPS

Receiver

RF B

RF A

Sync

www.tenettech.com

Page 4: E3XX_USRP.pdf

FORM FACTOR

• Size: 133 x 68.2 x 26.4 mm

• Weight: 375 grams (225 gram OEM version)

• Includes bottom mounting holes

• 2-6 Watts typical (18W Max)

USRP N210 & USRP E310 size comparison

www.tenettech.com

Page 5: E3XX_USRP.pdf

PERIPHERALS

Front Panel Back Panel

Top Row • TRX-A – RF A, Transmit/ Receive • RX2-A – Alternate RX path • TRX-B – RF B, Transmit/ Receive • RX2-A – Alternate RX path • Bottom Row • Power Button • Micro SD card port (SDXC capable) • GPS - antenna port • Sync - digital line to FPGA • Audio Jack – 2.5mm Mic/speaker

Left to Right • CONSOLE – serial over USB com

port • 2 x USB2 Host – for USB peripherals • 10/100/1000 – Ethernet interface • 5-15V DC – Power supply, 2-6W

typical

www.tenettech.com

Page 6: E3XX_USRP.pdf

RFIC & FILTER BANK

• Rx filters: reduce interference from out-of-band signals, while Tx filters: suppress spurious harmonics

• Selections chosen dynamically by the driver

* Filter bank pass bands with normalized gain, based on component characteristics. www.tenettech.com

Page 7: E3XX_USRP.pdf

FP

GA

ARM

ARM

ZYNQ HARDWARE & SOFTWARE ARCHITECTURE

FPGA Resources Xilinx7 FPGA

Programmable Logic Cells 85k

LUTs 53,200

Flip-Flops 160,400

Block Ram 560kB

DSP Slices 220

Peak DSP Performance 276 GMACs

ARM Processor Cortex A9

Processor cores 2

Clocking frequency 667 MHz

DMA Channels 8

External DRAM 1 GB

Em

be

dd

ed

Lin

ux

Custom Application

C / Other GNU Radio Python / GRC

UHD Driver

FP

GA

UHD FPGA Bitfile

RF

IC

www.tenettech.com

Page 8: E3XX_USRP.pdf

SHIPPING KIT CONTENTS

Qty Description

1 USRP E310 Hardware

1 4GB micro SD card

1 1 Gigabit Ethernet 3m cable

2 SMB-F to SMA-F adapter

1 6V power supply

1 USB console cable

www.tenettech.com

Page 9: E3XX_USRP.pdf

E310 – INTEGRATED GPS-DISCIPLINED CLOCK

• With GPS lock

• Improved frequency accuracy

• Global time & frequency sync

• GPS location information

GPS

uC

TCXO

Precision Time

Precision Frequency Ref

GPS Antenna Global Position

<< Available at Lunch

<< Future Capability

<< Future Capability

www.tenettech.com

Page 10: E3XX_USRP.pdf

PRODUCT COMPARISON: USRP PLATFORM

Low Cost B2xx

Embedded E3xx

General Purpose N2xx

High Performance X3xx

Frequency (Hz) 70 M – 6 G 70 M – 6 G DC-30M & 50M–6G DC-30M & 50M–6G

Bandwidth 56MHz (34 MHz 2x2) 56MHz (34 MHz 2x2) 20 MHz 120 MHz

Channels 2 Tx, 2 Rx 2 Tx, 2 Rx w/ filter banks

1 Tx, 1Rx 2 Tx, 2 Rx

DAC/ADC Res./Rate

DAC: 12b , 61.44MS/s ADC: 12b , 61.44MS/s

DAC: 12b , 61.44MS/s ADC: 12b , 61.44MS/s

DAC: 16b, 400 MS/s ADC: 14b,100 MS/s

DAC: 16b, 800 MS/s ADC: 14b, 200 MS/s

Noise Figure 5-7 dB

Processing Host PC Zynq 7020 (Xilinx 7 FPGA, Dual ARM CORTEX A9)

Host PC Kintex7 FPGA Host PC

MIMO Phase Coherent Phase Coherent Phase Coherent *Phase Coherent

Latency ms to Host uS to FPGA uS to Host

mS to Host uS to FPGA uS to Host

Bus USB3, USB2 AXI-DMA (FPGA to ARM) 1 GbE (ARM to Host)

1 GigE 1/10GbE Cabled PCIe x4

**Calibration None None None None

*Same Daughterboard in each slot **UHD provides correction software www.tenettech.com

Page 11: E3XX_USRP.pdf

SUMMARY

“The USRP E310 extends the embedded USRP product family, engineers can begin prototyping using a low-cost B200 or MIMO capable X300 platform and deploy on the USRP E310 for stand-alone applications with a common software experience.”

– Matt Ettus,

Founder and President of Ettus Research

The USRP E310 integrates a rich set of features and peripherals necessary for algorithm prototyping, mobile radio, wireless sensor networks, and remote sensing applications.

www.tenettech.com

Page 12: E3XX_USRP.pdf

Thank you!!! 12

www.tenettech.com