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Slide 1W. Rhett Davis NC State University ECE 546 Fall 2012

ECE 546 - VLSI Systems Design

Lecture 16: SRAM

Fall 2012W. Rhett Davis

NC State University

with significant material from Rabaey, Chandrakasan, and Nikoli

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Announcements

Re-grade Requests for Midterm due in 1 week

HW#7 Due Tuesday

Project Introduction Tuesday

Continue forming project groups

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Todays Lecture

SRAM

Multi-Port SRAM

CAM

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6-transistor CMOS SRAM Cell

WL

BL

VDD

M5M

6

M4

M1

M2

M3

BL

QQ

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CMOS SRAM Analysis (Read)

Assume bit-lines precharged high, Q=1, Q=0 What could go wrong?

WL

BL

VDD

M 5

M 6

M 4

M1 V

DDVDD VDD

BL

Q = 1Q = 0

Cbit Cbit

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Read Upset Problem

Modified equations

(12.2) and (12.3)(by Harun Demircioglu)

What are the operating

regions assumed by

these equations? Is this valid for our

technology?

WL

BL

VDD

M5M6

M4

M1 VDDVDD VDD

BL

Q= 1Q= 0

Cbit Cbit

55

11

LW

LWCR

22

2

01,

2

05,

VVVBVVk

VVVVBVVVk nnTDDMn

DSATnDSATnDDnnTDDMn

CRB

VVCRCRVVVCRVBVn

nTDDDSATnnTDDDSATnn

21211

2

0

22

0

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CMOS SRAM Analysis (Read)

For which side of this curve does the SRAM work properly?

0

0

0.2

0.4

0.6

0.8

1

1.2

0.5 1 1.2 1.5 2

Cell Ratio (CR)

2.5 3

Volta

geRise(V)

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Read Static Noise Margin (SNM)

A more robust definition is the maximum noise voltageneeded to flip the value during a read For simplicity on HW and Exams, we wont use this definition

At low supply voltages, Read SNM is too often negative,due to Vt variation between transistors

As a result, supply voltages have not scaled below 1V inadvanced technologies

Source:

Calhoun &

Chandrakasan,

JSSC 2007

V from slide 6

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CMOS SRAM Analysis (Write)

Assume cell contains 1, try to write 0 What needs to happen for a successful write?

BL = 1 BL = 0

Q = 0

Q = 1

M1

M4

M5

M6

VDD

VDD

WL

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Conditions for Successful Write

Modified equations(12.5) and (12.6)(by Harun Demircioglu)

What are the operating

regions assumed bythese equations?

Is this valid for ourtechnology?

BL= 1 BL= 0

Q= 0Q= 1

M1

M4

M5M6

VDD

VDD

WL

66

44

LW

LWPR

22

2

04,

2

06,

DSATp

DSATpDDQppTDDMp

Q

QQnnTDDMn

VVVVBVVk

VVVBVVk

n

DSATp

DSATppTDDp

n

p

DSATppnTDDDSATppnTDD

QB

VVVVBPRVBVVVBVV

V21

212

2

0

2

00

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CMOS SRAM Analysis (Write)

For which side of this curve does the SRAM work properly?

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6T-SRAM LayoutVDD

GND

QQ

WL

BLBL

M1 M3

M4M2

M5 M6

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Another Bit-Cell Layout

This bit-cell was createdby Xi Chen, Ting Zhu,and Harun Demircioglufor the Fall 2007 project

Best performance inclass

See their report on lastyears web-page group 35

see Project Results

Will this bit-cell still work,now that we havelithographic simulations?

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Summary

In an SRAM

Size NMOS larger than pass-gate to avoid read-upset

Size PMOS small for successful write

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Todays Lecture

SRAM

Multi-Port SRAM

CAM

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Extending the SRAM Cell

This bit-cell supports

a read or write to one

location in the array

How would we

change it if we

wanted to read orwrite to two

locations?

WL

BL BL

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2-Port SRAM Cell

This bit-cell supports

reads and/or writes to

two locations in thearray

How could we

optimize the cell if thesecond port were

read-only?

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Read/Write + Read SRAM Cell (1)

What is the

advantage

of this cell?

What is the

disadvantage

of this cell?

R/WWL

R/WBL RBL

RWL

R/WBL

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Read/Write + Read SRAM Cell (2)

What is the

advantage

of this cell?

What is the

disadvantage

of this cell?

R/WWL

R/WBL RBL

RWL

R/WBL

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Another Approach to Multi-Ports

Use two separate single-port arrays and re-direct logic to send requests to each

When is this advantageous?

RowD

ecoder

Bit line2L2 K

Word line

K

K1 1

L2 1

A0

M.2K

AK2 1

Sense amplifiers / Drivers

Column decoder

Input-Output(M bits)

Storage cell

RowD

ecoder

Bit line2L2 K

Word line

K

K1 1

L2 1

A0

M.2K

AK2 1

Sense amplifiers / Drivers

Column decoder

Input-Output(M bits)

Storage cell

Re-direct logic

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Todays Lecture

SRAM

Multi-Port SRAM

CAM

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Content-Addressable Memory (CAM)

Primary function is to look up the address of

stored data, rather than the data itself

Most often used in Internet Protocol Routers to

classify & forward packets

Similar to SRAM, but has 4 types of wires in the

array

Bit-line (BL) and Word-line (WL), used to write data

into the array

Search-Line (SL), used to drive the searched value

Match-line (ML), used to indicate a match

Ternary CAM (TCAM) also stores "don't care"

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High-Level CAM Architecture

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CAM Bit-Cells

Source: Pagiamtzis & Sheikholeslami, JSSC '06

NOTE: Bit-lines and access transistors removed

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