EE141 Combinational Circuits 1 Chapter 6 (I) Designing Combinational Logic Circuits Static CMOSStatic CMOS Pass Transistor LogicPass Transistor Logic V1.0

EE1411

Combinational Circuits

Chapter 6 (I)Chapter 6 (I)Designing Designing CombinationalCombinationalLogic CircuitsLogic Circuits

•Static CMOSStatic CMOS•Pass Transistor LogicPass Transistor Logic

V1.0 4/25/2003V1.1 5/2/2003V2.0 5/4/2003

EE1412


Revision ChronicleRevision Chronicle

5/2: Add some NAND8 figures (to compare NAND8 circuits) from old Weste textbook to this slide.

5/4: Add 4 Pass-Transistor Logic Slides from Weste

textbook Split Chapter 6 into two parts: Part I focuses on

Static and Pass Transistor Logic. Part II focuses on Dynamic Logic

EE1413


Combinational vs. Sequential LogicCombinational vs. Sequential Logic

Combinational Sequential

Output = f(In) Output = f(In, Previous In)

CombinationalLogicCircuit

OutInCombinational

LogicCircuit

OutIn

State

EE1414


Static CMOS CircuitsStatic CMOS Circuits•At every point in time (except during the switching transients) each gate output is connected to either via a low-resistive path (PUN, PDN)

•The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring the transient effects during switching periods).

•This is in contrast to the dynamic CMOS circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

VDD or Vss

EE1415


Static Complementary CMOSStatic Complementary CMOS

Pull-up Network (PUN) and Pull-down Network (PDN) are Dual Logic Networks

VDD

F(In1,In2,…InN)

In1In2

InN

In1In2

InN

PUN

PDN

PMOS only(good for transfer 1)

NMOS only (good for transfer 0)

……

EE1416


Threshold Drops in NMOS and PMOSThreshold Drops in NMOS and PMOS-- Check Candidates for PUN and PDN-- Check Candidates for PUN and PDN

VDD

VDD 0PDN

0 VDD

CL

CL

PUN

VDD

0 VDD - VTn

CL

VDD

VDD

VDD |VTp|

CL

S

D S

D

VGS

S

SD

D

VGS

G

G G

G

EE1417


Complementary CMOS Logic StyleComplementary CMOS Logic Style

EE1418


NMOS Transistors NMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection

Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high

X Y

A B

Y = X if A and B

X Y

A

B Y = X if A OR B

NMOS Transistors pass a “strong” 0 but a “weak” 1

EE1419


PMOS Transistors PMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection

X Y

A B

Y = X if A AND B = A + B

X Y

A

B Y = X if A OR B = AB

PMOS Transistors pass a “strong” 1 but a “weak” 0

PMOS switch closes when switch control input is low

EE14110


Example 1: NAND2 GateExample 1: NAND2 Gate

(Use DeMorgan’s Law)

EE14111


Example2: NOR2 GateExample2: NOR2 Gate

),3,2,1(),3,2,1(

Connnet to:PUN

GND Connect to:PDN

InInInFInInInG

VBABAF

BAG

DD

DDV

EE14112


Design of Complex CMOS GateDesign of Complex CMOS Gate

D

A

B C

D

A

B

C

DDV

)( CBADF

EE14113


Constructing a Complex GateConstructing a Complex Gate

C

(a) pull-down network

SN1 SN4

SN2

SN3D

FF

A

DB

C

D

F

A

B

C

(b) Deriving the pull-up networkhierarchically by identifyingsub-nets

D

A

A

B

C

VDD VDD

B

(c) complete gateSN1

SN1

SN2

SN2

EE14114


Static CMOS PropertiesStatic CMOS Properties Full rail-to-rail swing: High noise margins Logic levels not dependent upon the relative device sizes:

Ratioless Always a path to Vdd or GND in steady state: Low output

impedance Extremely high input resistance; nearly zero steady-state

input current (input to CMOS gate) No steady-state direct path between power and ground:

No static power dissipation Propagation delay function of output load capacitance and

resistance of transistors

EE14115


Switch Delay ModelSwitch Delay Model

A

Req

A

Rp

A

Rp

A

Rn CL

A

CL

B

Rn

A

Rp

B

Rp

A

Rn Cint

B

Rp

A

Rp

A

Rn

B

Rn CL

Cint

NAND2 INVNOR2

EE14116


Input Pattern Effects on DelayInput Pattern Effects on Delay Delay is dependent on the pattern of

input (Assume Rp = 2 Rn for same size of transistors)

Low-to-high transition: Both inputs go low

– Delay is 0.69 (Rp/2) CL One input goes low

– Delay is 0.69 (Rp) CL High-to-low transition:

Both inputs go high (required for NAND)

– Delay is 0.69 (2Rn)CL

CL

B

Rn

A

Rp

B

Rp

A

Rn Cint

EE14117


Transistor SizingTransistor Sizing

CL

A

Rn

A

Rp

B

Rp

B

Rn Cint

B

Rp

A

Rp

A

Rn

B

Rn CL

Cint

2

2

2 2

11

4

4

Assumes Rp = 2Rn at same W/L

NAND is preferred than NOR implementation!!

EE14118


Delay Dependence on Input PatternsDelay Dependence on Input Patterns

-0.5

0

0.5

1

1.5

2

2.5

3

0 100 200 300 400

A=B=10

A=1, B=10

A=10, B=1

time [ps]

Vo

ltage

[V]

Input Data

Pattern

Delay

(psec)

A=B=01 69

A=1, B=01 62

A= 01, B=1 50

A=B=10 35

A=1, B=10 76

A= 10, B=1 57

NMOS = 0.5m/0.25 mPMOS = 0.75m/0.25 mCL = 100 fF

A=1, B=10 (for both Cint and CL)

A=1, B=01 (Consider Body effect)

NAND2 is trueOUT connects to GND

EE14119


Transistor Sizing a Complex Transistor Sizing a Complex CMOS GateCMOS Gate

OUT = D + A • (B + C)

D

A

B C

D

A

B

C

1

2

2 2

4

4

8

8

2/NR

case) criticalfor oneonly (wide,2/NR

EE14120


Fan-In ConsiderationsFan-In Considerations

4-input NAND Gate

EE14121


Fan-In ConsiderationsFan-In Considerations

DCBA

D

C

B

A CL

C3

C2

C1

Distributed RC model (Elmore delay)

tpHL = 0.69(R1C1+(R1+R2)C2

+ (R1+R2+R3)C3

+ (R1+R2+R3+R4)CL

=0.69 Reqn(C1+2C2+3C3+4CL)

Propagation (H L) delay deteriorates rapidly as a function of fan-in no. : Quadratically in the worst case.

R4

R3

R2

R1

EE14122


ttpp as a Function of Fan-In as a Function of Fan-In

tpLH

t p (

pse

c)

fan-in

0

250

500

750

1000

1250

2 4 6 8 10 12 14 16

tpHL

Quadratic (H->L)

tp

(L H)Linear Increase in Intrinsic Capacitance,Assume Only one PMOS is On for criticalcase

EE14123


(tpHL, tpLH) as a Function of Fan-Out(tpHL, tpLH) as a Function of Fan-Out

Gates with a fan-in greater than or equal to 4 becomes excessively slow and should be avoided!

EE14124


ttpp as a Function of Fan-In and Fan-Out as a Function of Fan-In and Fan-Out

Fan-in: quadratic due to increasing

resistance and capacitance

Fan-out: each additional fan-out gate

adds two gate capacitances to CL To the

preceding stage)

EE14125


Fast Complex Gates: Design Technique 1Fast Complex Gates: Design Technique 1

Transistor sizing Increase Intrinsic parasitic cap and create CL of the

preceding stage

Progressive sizing

InN CL

C3

C2

C1In1

In2

In3

M1

M2

M3

MNDistributed RC line:

•M1 > M2 > M3 > … > MN (the FET closest to the output is the smallest)

•Not simple in Layout!

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EE14127



Input reordering: Put late arrival signal near the output node.

C2

C1In1

In2

In3

M1

M2

M3 CL

C2

C1In3

In2

In1

M1

M2

M3 CL

critical path critical path

charged1

01charged

charged1

Delay determined by time to discharge CL, C1 and C2

Delay determined by time to discharge CL

1

1

01 charged

discharged

discharged

EE14128



Logic Restructuring

In general, C > B > A in speed

(A)

(B)(C)

F =NAND8 Gate

EE14129


Design Technique 3: Logic RestructuringDesign Technique 3: Logic Restructuring

(from Neil Weste, 2nd Ed, 93)

Tradeoff between Area and Speed (and Power?)

EE14130



Isolating fan-in from fan-out using buffer insertion

CLCL

EE14131


Fast Complex Gates: Layout Technique Fast Complex Gates: Layout Technique

(A) (B)

(A): 4 internal cap 2 output diff cap(B): 4 internal cap 4 output diff cap

(A) Is better than (B)

EE14132


Optimizing Performance in Combinational Optimizing Performance in Combinational NetworksNetworks

N

iiii fgpDelay

1

For given N: Ci+1/Ci = Ci/Ci-1

To find N: Ci+1/Ci ~ 4

How to generalize this to any combinational logic path? E.g., How do we size the ALU datapath to achieve maximum speed?

CL

InOut

1 2 N

(in units of inv)

EE14133


Logical EffortLogical Effort

Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates

Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current

Logical effort increases with the gate complexity

EE14134


Logical EffortLogical EffortLogical effort is the ratio of input capacitance of a gate to the inputcapacitance of an inverter with the same output current

g = 1 g = 4/3 g = 5/3

B

A

A B

F

VDDVDD

A B

A

B

F

VDD

A

A

F

1

2 2 2

2

2

1 1

4

4

Inverter 2-input NAND 2-input NOR

EE14135



From Sutherland, Sproull

EE14136


Estimated Intrinsic Delay FactorEstimated Intrinsic Delay Factor

EE14137



fgpt

C

CCRktDelay

p

in

Lunitunitp

0

1

p – intrinsic delay : gate parameter g – logical effort : gate parameter f – effective fanout

Normalize everything to an inverter:ginv =1, pinv = 1

Divide everything by inv

(everything is measured in unit delays inv)Assume = 1.

EE14138


Delay in a Logic GatesDelay in a Logic Gates

Gate delay:

d = h + p

Effort delay Intrinsic delay

Effort delay:

h = g f

Logical Effort

Effective fanout = Cout/Cin

•Logical effort is a function of topology, independent of sizing•Effective fanout (electrical effort) is a function of load/gate size

EE14139


Logical Effort of GatesLogical Effort of Gates

IntrinsicDelay

EffortDelay

1 2 3 4 5

Fanoutf

1

2

3

4

5

Inverter:

g = 1; p = 12-in

put NAND:g

= 4

/3;p

= 2

No

rmal

ized

Del

ay

EE14140


Logical Effort of GatesLogical Effort of Gates

Fan-out (f)

Nor

mal

ized

del

ay (

d)

t

1 2 3 4 5 6 7

pINVt pNAND

F(Fan-in)

g = 1p = 1d = f+1

g = 4/3p = 2d = (4/3)f+2

EE14141


Add Branching EffortAdd Branching Effort

Branching effort:

pathon

pathoffpathon

C

CCb

EE14142


Multistage NetworksMultistage Networks

•Stage effort: hi = gifi

•Path electrical effort: F = Cout/Cin

•Path logical effort: G = g1g2…gN

•Branching effort: B = b1b2…bN

•Path effort: H = GFB

•Path delay D = di = pi + hi

N

iiii fgpDelay

1

EE14143


Optimum Effort per StageOptimum Effort per Stage

HhN

When each stage bears the same effort:

N Hh

PHNpfgD Niii )(ˆ /1

Minimum path delay

Effective fanout of each stage: ii ghf

Stage efforts: g1f1 = g2f2 = … = gNfN

EE14144


Optimal Number of StagesOptimal Number of Stages

For a given load, and given input capacitance of the first gateFind optimal number of stages and optimal sizing

invN NpNHD /1

0ln /1/1/1

invNNN pHHH

N

D

NHhˆ/1Substitute ‘best stage effort’

EE14145


Example: Optimize PathExample: Optimize Path

1a

b c

5

g = 1f = a

g = 5/3f = b/a

g = 5/3f = c/b

g = 1f = 5/c

Effective fanout, F = 5G = 25/9H = GF=125/9 = 13.9h = 1.93 (optimal stage effort) = a = 1.93b = ha/g2 = 2.23c = hb/g3 = 5g4/f = 2.59

4 H

EE14146


Example – 8-input ANDExample – 8-input AND

EE14147


Method of Logical EffortMethod of Logical Effort

Compute the path effort: F = GBH Find the best number of stages N ~ log4F Compute the stage effort f = F1/N

Sketch the path with this number of stages Work either from either end, find sizes:

Cin = Cout*g/f

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

EE14148


SummarySummary

Sutherland,SproullHarris

EE14149


Pass-TransistorPass-TransistorLogicLogic

EE14150


Pass-Transistor LogicPass-Transistor LogicIn

puts

Switch

Network

OutOut

A

B

B

B

• N transistors

• No static consumption

EE14151


Pass Transistor Logic BasicsPass Transistor Logic Basics

ImpedanceHigh :

,,,1,0 Signals Pass

Signals Control

Z

ZXXV

P

iii

i

)()()( 2211 nn

iii

VPVPVP

VPF

Logic Function:

B

B

A

F = AB

0

Example: AND GateExample: AND Gate

A, B: A is Input signal, B is the Control Signal

EE14152


Example: Design of XNOR2Example: Design of XNOR2

(b) Pass-network Karnaugh map

A as the control signals B as the passed signals

(a) Truth table

)()( BABAF

(c) Logic function

EE14153


Example: Implementation of XNOR2Example: Implementation of XNOR2

(a) Transmission Gate (b)NMOS (c)Cross-couple

EE14154


Example2: Construct Boolean FunctionsExample2: Construct Boolean Functions

•Implement:

•Truth Table:

EE14155


NMOS-Only LogicNMOS-Only Logic

VDD

In

Outx

0.5m/0.25m0.5m/0.25m

1.5m/0.25m

0 0.5 1 1.5 20.0

1.0

2.0

3.0

Time [ns]

Vo

ltage

[V]

xOut

In

Suffer from •Vt degradation•Body effect (Vsb has value)

EE14156


NMOS-only SwitchNMOS-only Switch

A = 2.5 V

B

C = 2.5 V

CL

A = 2.5 V

C = 2.5 V

BM2

M1

Mn

Threshold voltage loss causesstatic power consumption

VB does not pull up to 2.5V, but 2.5V - VTN

NMOS has higher threshold than PMOS (body effect)

EE14157


NMOS Only Logic: NMOS Only Logic: Level Restoring TransistorLevel Restoring Transistor

M2

M1

Mn

Mr

OutA

B

VDDVDDLevel Restorer

X

•Advantage: Full Swing•Restorer adds capacitance, takes away pull down current at X•Ratio problem among (Mr and Mn)

EE14158


Restorer SizingRestorer Sizing

0 100 200 300 400 5000.0

1.0

2.0

W/Lr =1.0/0.25 W/Lr =1.25/0.25

W/Lr =1.50/0.25

W/Lr =1.75/0.25

Vol

tage

[V]

Time [ps]

3.0

•Upper limit on restorer size•Pass-transistor pull-down can have several transistors in stack

EE14159


Solution 2: Single Transistor Pass Gate with Solution 2: Single Transistor Pass Gate with VVTT=0=0

Out

VDD

VDD

2.5V

VDD

0V 2.5V

0V

WATCH OUT FOR LEAKAGE CURRENTS

EE14160


Complementary/Differential Pass Transistor Complementary/Differential Pass Transistor Logic (CPL/DPL)Logic (CPL/DPL)

A

B

A

B

B B B B

A

B

A

B

F=AB

F=AB

F=A+B

F=A+B

B B

A

A

A

A

F=AÝ

F=AÝ

OR/NOR EXOR/NEXORAND/NAND

F

F

Pass-Transistor

Network

Pass-TransistorNetwork

AABB

AABB

Inverse

(a)

(b)

EE14161


Solution 3: Use of Transmission GateSolution 3: Use of Transmission Gate

A B

C

C

A B

C

C

B

CL

C = 0 V

A = 2.5 V

C = 2.5 V

EE14162


Resistance of Transmission GateResistance of Transmission Gate

Vout

0 V

2.5 V

2.5 VRn

Rp

0.0 1.0 2.00

10

20

30

Vout, V

Res

ista

nce

, oh

ms

Rn

Rp

Rn || Rp

EE14163


Application1: Inverting 2-to-1 MultiplexerApplication1: Inverting 2-to-1 Multiplexer

AM2

M1

B

S

S

S F

VDD

)( BSASF GND

VDD

A BS S

S S

F

EE14164


Application2: 6-T(ransistor) XOR GateApplication2: 6-T(ransistor) XOR Gate

B A F

0 0 0

0 1 1

1 0 1

1 1 0

A

A

A

A

Truth Table

A

B

F

B

A

B

BM1

M2

M3/M4

B=0: Pass A Signal

B=1: Inverting A Signal

EE14165


Application3: Transmission Gate Full AdderApplication3: Transmission Gate Full Adder

A

B

P

Ci

VDDA

A A

VDD

Ci

A

P

AB

VDD

VDD

Ci

Ci

Co

S

Ci

P

P

P

P

P

Sum Generation

Carry Generation

Setup

Similar delays for Sum and Carry

EE14166


Delay in Transmission Gate NetworksDelay in Transmission Gate Networks

V1 Vi-1

C

2.5 2.5

0 0

Vi Vi+1

CC

2.5

0

Vn-1 Vn

CC

2.5

0

In

V1 Vi Vi+1

C

Vn-1 Vn

CC

In

ReqReq Req Req

CC

(a)

(b)

C

Req Req

C C

Req

C C

Req Req

C C

Req

C

In

m

(c)

EE14167


Delay OptimizationDelay Optimization

Documents

EE141 Combinational Circuits 1 Chapter 6 (I) Designing Combinational Logic Circuits Static CMOSStatic CMOS Pass Transistor LogicPass Transistor Logic V1.0