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CHAPTER 6

STUCK-OPEN FAULT ANALYSIS IN CMOS TRANSISTOR

BASED COMBINATIONAL CIRCUITS

6.1 INTRODUCTION

The imperfect manufacturing process of integrated circuits presents

new challenges for identifying defects that creeps into some of the fabricated

chips. These defects can take a wide variety of forms, from localized spot

defects, typically extra or missing material caused by particles to defects

affecting much larger areas, such as reduced capacitance caused by

inadequate implantation.

Defects are unpredictable in both location and effect, and the

processes that cause them include a wide range of variables. In order to

simplify the identification of defective circuits, this infinite defect space is

approximated by a finite set of faults. Faults, often considered localized

within a circuit (e.g. When a particular gate is broken), can also be thought of

as the transformations that change the Boolean function implemented by a

circuit. Thus the choice of fault model depends on test generation, prediction

of manufacturing quality, defect diagnosis, and characterization for defect

tolerance.

Interconnect ‘breaks’, which are prevalent in copper technology,

and ‘opens’ are major sources of the defects. During conventional chip testing

it has been observed that most of the test escapes correspond to ‘open’

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defects. Additional tests are needed to detect their presence, which may be

modelled by transition faults, delay faults, or stuck-open faults. When open

defect occurs, the output may float to intermediate value and the logic test

might not catch this defect. But the stuck-open fault model covers the

physical defects not covered by stuck-at fault models.

This chapter presents an easily testable CMOS implementation of a

combinational circuit based on ESOP expressions for detecting single stuck-

open faults. A stuck-open fault in a combinational circuit may induce a

sequential behaviour in the circuit. Testing of a stuck-open fault requires a

two-pattern test, consisting of an initialization and a test vector. Owing to the

presence of arbitrary delays in the circuits, a two-pattern test may be

invalidated. A two-pattern test, which cannot be invalidated, is called robust,

and a circuit in which every irredundant stuck-open fault has a robust test

pair, is called robustly testable.

For detection of stuck-open faults in ESOP circuits, the design is

slightly modified by using a few additional control inputs and one extra

observable output. The modified circuit becomes robustly testable and admits

a universal test sequence of length (2n +10) for an ESOP circuit (Rahaman

et al 2004b), where n is the number of input variables. The test sequence can

be stored in a ROM on chip for built-in self-testing. Thus, the control inputs

may be treated as internal lines without having increased the number of

external I/O pins.

6.2 CMOS GENERAL CONCEPTS

CMOS stands for complementary metal-oxide-semiconductor. It is

a major class of integrated circuits. CMOS chips include microprocessor,

microcontroller, static RAM, and other digital logic circuits. The central

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characteristic of the technology is that it only uses significant power when its

transistors are switching between on and off states. Consequently, CMOS

devices use little power and do not produce as much heat as other forms of

logic. CMOS also allows a high density of logic functions on a chip.

The word "complementary" refers to the fact that the design uses

pairs of transistors for logic functions, only one of which is switched on at

any time. It means that CMOS uses both n-type (nMOS) and p-type (pMOS)

transistors. Older designs had used only n-type transistors, and are referred to

as NMOS logic.

“Metal-Oxide-Semiconductor” refers to the construction method of

the component Field-Effect Transistors (MOSFETs). It is a reference to the

nature of the fabrication process originally used to build CMOS chips. That

process created field effect transistors having a metal gate electrode placed on

top of an oxide insulator, which in turn is on top of a semiconductor. Instead

of metal, today the gate electrodes are almost always made from a different

material, polysilicon, but the name CMOS nevertheless continues to be used

for the modern descendants of the original process.

All CMOS gates are arranged in two parts: the pull-up network,

built from p-type transistors and connect to source; and the pull-down

network, built from n-type transistors and connected to ground (also called

drain) as shown in Figure 6.1. The two parts are logical complements of each

other, so that if the pull-up network is active, then the pull-down network is

inactive, and vice-versa. In this way there can never be a direct path between

source and ground in steady state.

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Figure 6.1 General Structure of CMOS Gate

The biggest advantage of CMOS over NMOS is that CMOS has a

rapid change from both hi-to-low and from low-to-hi. NMOS transitions only

slowly from low-to-hi (because it uses a resistor in place of a pull-up network,

and since overall circuit speed must take into account the worst case, NMOS

circuits must be much slower. The physical structure of CMOS is shown in

Figure 6.2.

Figure 6.2 CMOS Physical Structure

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6.3 MOSFET SWITCHES

Schematically MOSFET transistors are typically identified using

three possible schematic symbols. These symbols are shown in Figure 6.3 for

both n-channel (nMOS) and p-channel (pMOS) devices. It shows the source

(S), the drain (D) and the gate (G) terminals for each switch. The substrate

terminal is not indicated since it is normally shorted to either the source or the

drain terminal.

Figure 6.3 Schematic Symbols for MOSFET Transistor as a Switch

The structures for an n-channel enhancement type transistor

consists of moderately doped p-type silicon substrate into which two heavily

doped n+ regions, the source and the drain, are diffused. Between these two

regions there is a narrow region of p-type substrate called the channel, which

is covered by a thin insulating layer of Silicon dioxide (SiO2), called Gate

oxide. Over this oxide layer is a polycrystalline silicon electrode, referred to

as the gate.

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The nMOS switch shown in Figure 6.4 is closed or ON if drain and

source are connected. This occurs when a logical ‘1’ is applied to its gate

terminal. The switch is open or OFF if the drain and source are disconnected.

A ‘0’ on the gate ensures this condition. The pMOS switch action is the

logical complement of an nMOS switch as shown in Figure 6.5.

Figure 6.4 nMOS Switch

Figure 6.5 pMOS Switch

6.3.1 Working of n-MOSFET

6.3.1.1 Switch in OFF condition

Figure 6.6 shows the CMOS switch in the ‘OFF’ condition. There

is 0V on the gate junction and there is no conducting layer under the gate to

allow current to flow between the drain and source junctions. With no

potential on the gate, there is no depletion region for current to flow between

the drain and source terminals and so the switch is off.

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Figure 6.6 n-MOSFET Switch in OFF Condition

6.3.1.2 Switch in ON condition

Figure 6.7 shows the CMOS switch in the ‘ON’ condition, as there

is +5V on the gate junction. The positive gate potential attracts electrons from

the substrate causing a region of electrons formed under the gate insulation

region. Current can now flow through this induced n-channel ‘inversion

region’ between the drain and source terminals.

The positive voltage applied on the gate with respect to the

substrate enchances the number of electrons in the channel and hence

increases the conductivity. The operation of pMOS is analogous to the nMOS

transistor, with the exception that majority carriers are holes and voltages are

negative with respect to the substrate. It is possible to make n-devices

conduct when the gate voltage is equal to the source voltage.

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Figure 6.7 n-MOSFET Switch in ON Condition

6.4 CMOS SWITCHING CIRCUITS

Given below is the sequence of steps to be followed to implement a

CMOS switching function F= f(a,b,c, …).

Step 1: Reduce Using De-Morgan to eliminate the inverted

operation

Step 2: Form pMOS network by complementing the inputs

Fp = f (a’, b’, c’, …)

Step 3: Form nMOS network by complementing the output

Fn = f ‘(a,b,c, …)= F’

Step 4: Construct Fn and Fp using AND/OR series/parallel

MOSFET structures

For example, the implementation of a NAND gate is shown below.

Step 1: F= (ab)’ (6.1)

Step 2: Fp= (a’.b’) = (a+b) (6.2)

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Step 3: Fn= ((ab)’)’ = (ab) (6.3)

Step 4: Construction as shown in Figure 6.8.

Figure 6.8 CMOS NAND Gate Implementation

The equivalent physical layout of CMOS gate is shown in Figure 6.9.

Figure 6.9 Stick Diagram for CMOS NAND Gate

6.5 WORKING OF CMOS INVERTER

6.5.1 Analysis with Vin set to 5V (Vcc = 5V)

The CMOS transistor implementation for a logic inverter is shown

in Figure 6.10. The gate voltage Vgs across the N-type CMOS transistor (TR2)

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is 5V, well above the threshold value of VT+Vsat (approximately 1V) and

therefore TR2 will be switched ON. The Vgs across the P-type CMOS

transistor (TR1), the difference between Vcc and Vin, will be 0 volt. This

device requires a voltage difference of atleast (Vcc - VT+Vsat) at its gate

before it switches on and so this device is OFF. Thus with TR1 OFF and TR2

ON, Vout will be connected to 0V via TR2.

Figure 6.10 CMOS Inverter

6.5.2 Analysis with Vin set to 0V (Vcc = 5V)

The Vgs across the N-type CMOS device is 0V, below VT+Vsat and

therefore TR2 will be switched OFF. The Vgs across the P-type CMOS

transistor will now be approximately -5V (Vin – Vcc). This device requires a

voltage difference of atleast (Vcc - VT+Vsat) at its gate before it switches on.

Since in this case it will be nearly 5V and so this device will be switched ON.

Thus with TR1 ON and TR2 OFF. Vout will be connected to 5V (Vcc) via TR1.

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6.6 FAULTS IN ICs

Fabrication of an ASIC is a complicated process requiring hundreds

of processing steps. Problems may introduce a defect that in turn may

introduce a fault. Any problem during fabrication may prevent a transistor

from working and may break or join interconnections. Defects may also arise

after chip fabrication is complete while testing the wafer, cutting the die from

the wafer, or mounting the die in a package. Wafer probing, wafer saw, die

attach, wire bonding, and the intermediate handling steps each have their own

defect and failure mechanisms.

Many different materials are involved in the packaging process that

have different mechanical, electrical, and thermal properties, and these

differences can cause defects due to corrosion, stress, adhesion failure,

cracking, and peeling. Yield loss also occurs from human error using the

wrong mask, incorrectly setting the implant dose as well as from physical

sources: contaminated chemicals, dirty etch sinks, or a troublesome process

step. It is possible to repeat or rework some of the reversible steps. However,

reliance on rework indicates a poorly controlled process. At the chip level,

defects generally fall under one of the following categories:

Opens

These include opens in the interconnects which connect transistors

within the same gate or between gates. Opens may occur along input lines,

output lines, or feedback lines. Opens can also result from missing drains and

sources.

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Shorts

These include shorts between two or more interconnect lines.

Shorts include input to input shorts; input to output shorts, output to output

shorts, and shorts to power supply lines.

Cross talk

With the advent of deep submicron technology and future sub -

100nm technology, crosstalk is playing a significant role in testing. Improper

wire spacing can cause crosstalk, which can result in degraded delay

performance or even logic errors. Crosstalk has generally been regarded more

of a design-induced problem as opposed to a manufacturing defect, but the

fact is that it can result from either source.

Pattern Sensitivity

Some defects are pattern sensitive in that their presence depends on

the actual input patterns that are applied. These types of defects may result

from erroneous charge sharing and redistribution and occur in very dense

structures such as DRAMs.

6.6.1 Defects in PLDs

Some defects are unique to PLDs such as missing/extra links in the

AND/OR plane of PLAs. These defects result in missing/extra logic terms in

the logic functions implemented by the PLA. Some defects affect the

magnitude of device parameters but may or may not affect the logic operation

of the device. Examples of these defects include gate-oxide shorts, and

improper diffusion area doping.

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Gate-Oxide Shorts

These include cracks in the gate oxide layer which separates the

gate from the substrate. The result is additional leakage into the substrate

which may or may not cause logic failure depending on the severity of the

oxide short.

Improper Doping

This can affect the performance of the device such as the delay

performance due to improper capacitance values and threshold voltages that

affect switching speed.

The stick-diagram of NAND gate in Figure 6.11 shows the physical

faults occurring in CMOS circuits.

Figure 6.11 Faults in CMOS Layout

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6.7 FAULT MODELS

Fault modeling can be performed at different levels of the design

hierarchy including transistor level, logic level, and behavioral level.

However, the most commonly used fault models today are logic (gate) level

models because of their simplicity. Yet the recent efforts have been directed

towards modeling at higher levels such as the behavioral level.

6.7.1 Logic level

At the logic level, fault models include the stuck-at fault where a

gate-level node is permanently fixed at a logic value, and the bridging fault

where two wires are shorted together.

6.7.1.1 Stuck-at fault

This model includes single Stuck-at faults (assumes only one

Stuck-at fault exists for each test) and multiple Stuck-at faults (assumes

multiple faults can occur simultaneously). The single Stuck-at fault model is

the most widely used fault model because of its simplicity in terms of

employing it in test tools. The Stuck-at fault is used at both the chip and PCB

levels.

Figure 6.12 shows examples of Stuck-at faults. Since the output of

the inverter is Stuck-at-1, no matter what is applied to the input, the output

will be at logic 1. If any of the AND gate inputs is Stuck-at-0, no matter what

is applied to the inputs, the output is always zero. The Stuck-at fault model,

although popular, is not a realistic model for many kinds of circuit defects.

However, test vectors which are developed to detect Stuck-at faults also

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detect a variety of other faults if the coverage of Stuck-at faults is sufficiently

high.

Figure 6.12 Stuck-at Fault

6.7.1.2 Bridging fault

In wired fault model, shorted wires perform logical AND/OR and

in dominant model stronger driving gate dominates the short as shown in

Figure 6.13.

Figure 6.13 Bridging Fault Models

6.7.2 Transistor level

Fault modeling at the transistor level is in general more accurate in

representing defects as opposed to logic level fault models. However,

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transistor level fault modeling is computationally very expensive and thus not

widely used. Transistor fault models can represent opens and shorts at inner

nodes which are not represented at the logic gate level.

Transistor level fault models include Stuck-on faults where a

transistor is permanently conducting (switched on), and Stuck-open faults

where a transistor is permanently switched off. A Stuck-on fault on a P-type

transistor may result if the transistor gate node is shorted to ground. A Stuck-

open fault may result if there is an open defect along the gate of an N-type

transistor as shown in Figure 6.14.

Transistor level faults are more difficult to detect because they can

cause a combinational gate to exhibit sequential behavior. Transistor can be

Stuck-on (stuck-short) and result in excessive quiescent drain current IDDQ.

IDDQ was successfully used to detect bridge defects and gate oxide shorts.

It can be Stuck-off (stuck-open) and result in “memory” node (logic gate

latch). Gate level fault is accurate for NMOS but not for CMOS. If a gate

input is stuck-at then is equivalent to the effect of 2 transistors stuck-at in

CMOS.

Figure 6.14 Transistor Fault

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6.7.3 Behavioral level

With the increased use of behavioral level design tools such as

VHDL, researchers are looking at fault models that can be applied at the

behavioral level. For example, a behavioral level fault may affect the number

of states and/or state to state transitions in a finite state machine.

6.7.4 Degradation fault

A degradation fault may be a parametric fault or delay fault (timing

fault). A parametric fault might lead to an incorrect switching threshold in a

TTL/CMOS level converter at an input. A delay fault might lead to a critical

path being slower than specification. Delay faults are much harder to test in

production.

6.8 STUCK OPEN FAULTS IN CMOS ESOP CIRCUITS

6.8.1 Two Pattern Test

A permanent disconnection between source and drain of a transistor

is modeled by a stuck-open fault. Under this fault, i.e. in the presence of a

non-conducting transistor, the output of the circuit under certain input may

float and show the previous logic value. Thus in faulty condition, a

combinational circuit may behave as a sequential machine. Detection of this

fault requires a two-pattern test consisting of an initialization vector XI and a

test vector XT.

A test vector XT for a stuck-open fault in a CMOS combinational

circuit realizing a non-constant function F is a vector, on application of which

the output becomes floating in the presence of the fault. An initialization

vector XI for a stuck-open fault is an input, such that f(XI) is the complement

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of f(XT), in the fault-free condition. Owing to the presence of unequal delays

in the circuit, some transient vector may appear at the inputs of the circuit

when XT is applied following XI. This may invalidate initialization and thus

fail to detect the fault.

6.8.2 Stuck-Open Example

In this section, it is shown that the order or sequence in which the

test inputs are applied to a circuit can result in different operation and hence is

important for intended execution of the circuit function. For example,

considering a CMOS NOR gate with one of its transistors stuck-open as

shown in Figure 6.15, the results of tests applied in the incorrect and correct

orders are discussed in Table 6.1 and Table 6.2.

Figure 6.15 Example of Stuck-Open Fault

Table 6.1 NOR Operation for Test Inputs in Wrong Sequence

A B Ideal Actual Operation

1 0 0 0 A pulls Y low

0 1 0 0 B cannot pull Y low; Y floats

0 0 1 1 A and B pull Y high

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Table 6.2 NOR Operation for Test Inputs in Correct Sequence

A B Ideal Actual Operation

0 0 1 1 A and B pull Y high

0 1 0 1 B cannot pull Y low; Y floats

1 0 0 0 A pulls Y low

From the observations, it is obvious that test sequences should be

generated such as to identify the open transistor.

6.8.3 Testing of NAND and XOR

A CMOS realization of a NAND gate is shown in Figure 6.16. If

the faulty transistor (stuck open) is fed by the literal xj, then the stuck-open

fault in a p-transistor of a NAND gate can be robustly detected by the

following two-pattern test:

{x1, x2,…xj…xk} = { 1, 1... 1 …1 } and {1, 1... 0... 1 }

Similarly, for a n-transistor, the two-pattern test is given by

{ x1, x2, … xj… xk }= { 1, 1... 0... 1) and {1, 1... 1... 1 }.

Figure 6.16 A CMOS NAND Gate With n Inputs

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Figure 6.17 Two-Input CMOS XOR Gate

Any single stuck-open fault in the XOR gate of Figure 6.17 can be

robustly detected by any one of the following two-pattern tests:

{ x1, x2 }= { 0, 0 } and { 0, 1 }

{ x1, x2 }= { 0, 1 } and { 0, 0 }

However, the inputs can also be { 1, 1 }, instead of { 0, 0 }, since

either combination produces the same output. Similarly, the vector { 0, 1 }

may also be replaced by { 1, 0 }.

Considering the first set, applying {0,0} produces a 0 output, while

applying {0, 1} changes the output to 1. Similarly, for the second set, the

output changes from 1 to 0.

6.9 TESTING SCHEME FOR ESOP NETWORK

6.9.1 Network Structure

The testable realization network for detection of stuck-open faults

(Figure 6.18) in CMOS combinational circuit employing ESOP form consists

of four parts (Rahaman et al 2004c):

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Literal part

NAND part

XOR part (linear part)

Check part

The literal part consists of XOR gates with a control line and is

used to produce the positive (uncomplemented) or negative (complemented)

literals. In the proposed scheme the AND part is replaced by a NAND array and the check part consists of an XOR cascade with an extra observable

output O and is used to test the literal part. The linear part has XOR cascade.

Three control lines are needed; c1 in the literal part, c2 in the XOR part and check part and c3 in NAND part.

Figure 6.18 Stuck-Open Testable ESOP Circuit The scheme is based on the following steps:

Step 1: Each AND term in the ESOP expression is replaced by

NAND for ease of synthesis.

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Step 2: The literals that appear even number of times in the

ESOP expression are used to feed a new NAND gate

with a control input c3. To realize the original function by

setting c3=0; we complement the expression as obtained

in step-1.

Step 3: If the constant function 1 appears in the expression, we

eliminate it by changing an XOR operation with an Ex-

NOR operation.

Step 4: Following the expression obtained in step 3, we

synthesize the circuit.

(The basic NAND and XOR gates in CMOS are realized using the

structures of Figures 6.16 and 6.17 respectively).

Figure 6.19 depicts the above steps in flowchart form.

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Figure 6.19 Flowchart for Stuck-open Fault Network Structure

Replacement of every AND gate of given function by a NAND gate

Circuit synthesis

End

Start

Any variable occurring even no. of times ?

Variable connected to addl. NAND gate

with control input c3

Yes

Constant 1 in given function ?

XOR replaced with XNOR

Yes

No

Yes

No

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6.9.1.1 Examples

f ( x1, x2 )= x1 x2 x1' x2' (6.4)

Step1: In terms of NAND operation, the expression can be

written as f = ( x1x2 ) ' ( x1'.x2 ' ) ' (6.5)

Step2: Since the literals x1 and x2 appear even no. of times, it is

rewritten as f' = ( x1x2 ) ' ( x1'.x2 ' ) '( c3 x1 x2 )’ (6.6)

Step 3: There is no constant function.

Step 4: The circuit is synthesised using NAND and XOR gates

structure shown in Figures 6.16 and 6.17. The circuit

realized is as shown in Figure 6.20.

Figure 6.20 Stuck-Open Example for f( x1, x2)= x1x2 x1' x2'

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Similarly for three variable and six variable functions testable

circuits are realized as shown in Figures 6.21 and 6.22 respectively.

Figure 6.21 Stuck-Open Fault Testable Circuit for f(x1, x2, x3)= x1' x2 x3

x1 x2' x3

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Figure 6.22 Stuck Open Fault Testable Circuit for f(x1,…x6)= x2' x3 x4'

x1' x2' x6 x3 x4 x5

6.9.2 Universal Test Set for ESOP Realization

6.9.2.1 Linear part test set

For c1=0, the ESOP circuit is same as a PPRM circuit. If each XOR

gate in the linear part is realized with a CMOS circuit of Figure 6.16, the

linear part of the ESOP network is robustly testable by the following universal

test sequence T1 of length 6 (Table 6.3). Each XOR gate in this part receives

three two pattern vector pairs: {00 or 11, 01}, {00 or 11,10}, {01 or 10, 00}

(Rahaman et al 2004c).

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Table 6.3 Linear Part Test Set

c1 c2 c3 x1 x2 … xj … xn

0 0 0 0 0 … 0 … 0

0 1 0 0 0 … 0 … 0

T16 x (n+3): 0 0 0 0 0 … 0 … 0

0 1 1 1 1 … 1 … 1

0 0 1 1 1 … 1 … 1

0 1 1 1 1 … 1 … 1

6.9.2.2 NAND part test set

Any single stuck-open fault in NAND gates of an ESOP network is

robustly testable by the universal test sequence T2 of length (2n+3)

(Table 6.4). Since c1= 0 all literals will be positive.

The following two sequence patterns with respect to xj in T2, viz.

{ c1, c2, c3, x1, x2…xj…xn } = { 0, d, 1, 1, 1...0…1} and { 0, d, 1, 1, 1…1…1}

produce (x1, x2…xj…xn) = { 1, 1…0…1} and { 1, 1…1...1 }. Hence they

detect the stuck-open fault in the n-transistor fed by the literal xj

.

Similarly the following two consecutive patterns in T2, namely (c1, c2,

c3, x1, x2…xj…xn ) = { 0, d, 1, 1, 1...1…1 } and { 0, d, 1, 1, 1…0…1 }

produce (x1, x2…xj…xn) = {1, 1…1…1} and {1, 1…0...1} respectively.

Hence they can detect the stuck-open fault in the p-transistor fed by

the literal xj. The circuit response is observed at the functional output F and

auxiliary output O.

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Table 6.4 NAND Part Test Set

c1 c2 c3 x1 x2 … xj … xn

0 d 1 1 1 … 1 … 1

0 d 0 1 1 … 1 … 1

0 d 1 1 1 … 1 … 1

0 d 1 0 1 … 1 … 1

0 d 1 1 1 … 1 … 1

0 d 1 1 0 … 1 … 1

T2(2n+3) x (n+3): . .

. .

. .

0 d 1 1 1 … 0 … 1

0 d 1 1 1 … 1 … 1

0 d 1 1 1 … 1 … 0

0 d 1 1 1 … 1 … 1

6.9.2.3 Literal part test set

The literal part of an ESOP network is testable by the test sequence

TL = ( T2 T3 ), where T3 is as shown in Table 6.5.

Table 6.5 Literal Part Test Set

c1 c2 c3 x1 x2 … xj … xn

T32 x (n+3)= 0 d 0 0 0 … 0 … 0

1 d 0 0 0 … 0 … 0

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Application of test patterns in T2 produces ( 10, 00 ) and ( 00, 10 )

to the inputs of all XOR gates in the literal part. Similarly, when T3 is

applied, all XOR gates receive ( 00, 01 ). By observing the response at the

output O, the fault can be detected.

6.9.2.4 Check part test set

The check part is robustly testable by T1. The first three vectors of

T1 produce ( 00, 01, 00 ) to the inputs of each XOR gate. Similarly, the last

three vectors of T1 produce ( 11, 10, 11 ). By observing the response at O, we

detect any single stuck-open fault in this part.

6.9.2.5 Complete test set

Any stuck-open fault in the ESOP network designed as in Figure

6.19 is robustly testable by the following universal test sequence T of length

(2n+10) (Table 6.6):

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Table 6.6 Complete Test Set of (2n+10) Test Vectors

c1 c2 c3 x1 x2 … xj … xn

0 1 1 1 1 … 1 … 1

0 0 1 1 1 … 1 … 1

0 1 1 1 1 … 1 … 1

0 1 0 1 1 … 1 … 1

0 1 1 1 1 … 1 … 1

0 1 1 0 1 … 1 … 1

0 1 1 1 1 … 1 … 1

0 1 1 1 0 … 1 … 1

. .

T(2n+10) x (n+3): . .

. .

0 1 1 1 1 … 0 … 1

0 1 1 1 1 … 1 … 1

0 1 1 1 1 … 1 … 0

0 1 1 1 1 … 1 … 1

0 0 0 0 0 … 0 … 0

1 0 0 0 0 … 0 … 0

0 0 0 0 0 … 0 … 0

0 1 0 0 0 … 0 … 0

0 0 0 0 0 … 0 … 0

The depth of the linear cascade will be at most (p+1) where p is the

number of product terms in the ESOP expression. The test sequence T can be

stored in a ROM of size (2n +10)*(n+ 3) bits. The test sequence is universal

and robust.

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6.10 SIMULATION

The simulation has been carried out in MultiSim environment for

the the random ESOP functions f= (x1x2 x1' x2') and the results have been

discussed.

6.10.1 Multisim

Multisim 2001 is a complete system design tool that offers a large

component database, schematic entry, full analog/digital SPICE simulation,

VHDL/Verilog HDL design entry/simulation, FPGA/CPLD synthesis, RF

capabilities, Postprocessing features and seamless transfer to PCB layout

packages such as Ultiboard, also from Electronics Workbench. It offers a

single, easy-to-use graphical interface for most of the design needs. Multisim

provides all the advanced functionality you need to take designs from

specification to production. Further, since the program tightly integrates

schematic capture, simulation, printed circuit board (PCB) layout and

programmable logic, the design can be made with confidence, free from the

integration issues often found when exchanging data between applications

from different vendors. It supports every step of the overall circuit design

process.

6.11 RESULTS

Using Multisim, the testable ESOP circuits for stuck-open faults

were simulated for a two-variable function f= (x1 x2 x1' x2'). A single stuck-

open fault in the gate terminals of each transistor of the various XOR gates is

considered to be present in the circuit at a time. The test vectors were applied

sequentially and the outputs F and O were observed.

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The simulation circuits for the NAND and XOR gate structures

used for the example functions are shown in Figures 6.23 and 6.24

respectively.

Figure 6.23 Simulation of NAND Gate Structure

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Figure 6.24 Simulation of XOR Gate Structure

6.11.1 Fault-free case

Figure 6.25 is the simulation for the fault-free condition, of the two

variable function f= (x1x2 x1' x2'), with the test vector applied as

{ c1, c2, c3, x1, x2 }= { 0, 1, 1, 0, 1 } (6.7)

The input signals are shown as battery supplies.

The outputs of all the logic gates are shown for reference and

verification of the respective logic functions. Circles with lines around

represent logic 1 value, whereas logic 0 is indicated as circles without lines

around. Both the responses F and O obtained for this test vector can be seen to

be 0.

124

Figure 6.25 Simulation of Fault Free Testable Circuit for the Function

f(x1,x2)= (x1 x2 x1' x2')

The complete test vectors and the corresponding simulation outputs

F and O are for this function are shown in Table 6.7

Decimalizing the binary outputs F and O, considering the responses

for the first input vector as the corresponding MSBs, results in the fault-free

or reference decimal output set as ( 10933, 11938 ).

125

Table 6.7 Test Inputs and Simulation Outputs for f(x1,x2)= (x1 x2

x1' x2')

Inputs Outputs

Vector c1 c2 c3 x1 x2 F O

1 0 1 1 1 1 1 1

2 0 0 1 1 1 0 0

3 0 1 1 1 1 1 1

4 0 1 0 1 1 0 1

5 0 1 1 1 1 1 1

6 0 1 1 0 1 0 0

7 0 1 1 1 1 1 1

8 0 1 1 1 0 0 0

9 0 1 1 1 1 1 1

10 0 0 0 0 0 1 0

11 1 0 0 0 0 0 0

12 0 0 0 0 0 1 0

13 0 1 0 0 0 0 1

14 0 0 0 0 0 1 0

Similarly, Figure 6.26 shows the simulation diagram for the three

variable function f(x1,x2,x3)= ( x1' x2 x3 x1 x2' x3) with the input vector

{ c1, c2, c3, x1, x2 }= { 0, 1, 1, 0, 1 } (6.8)

while Figure 6.27 is for the six variable function f(x1,…x6)=( x2' x3 x4'x1' )

(x2' x6 x3 x4 x5 ) with the test vector

{ c1, c2, c3, x1, x2 }= {0, 1, 1, 1, 1}. (6.9)

126

Figure 6.26 Simulation of Fault-Free Testable Circuit for the Three

Variable Function f(x1,x2,x3)= (x1' x2 x3 x1 x2' x3)

127

Figure 6.27 Simulation for Fault-Free Testable Circuit for the Six

Variable Function f(x1,…x6) = (x2' x3 x4' x1'x2'x6 x3 x4 x5)

6.11.2 Stuck-open fault

Figure 6.28 represents the simulation result with the gate terminal

of transistor T1 (Figure 6.24) of XOR gate1 opened. The input vector is the

same as mentioned in the previous section. Both the responses F and O can

be observed to be 1.

128

Figure 6.28 Simulation with Transistor T1 of XOR Gate1 (XOR1)

Stuck-open for f(x1,x2) = (x1x2 x1' x2') Tables 6.8 to 6.14 show the decimal equivalents of the simulation

outputs for the function of(x1,x2)=(x1x2x1' x2') for the simulated opening of

gate terminals of each of the transistors T1 to T6 of each of the XOR gates XOR 1 to XOR 7. Table 6.8 Decimal Equivalents of the Observed Simulation Outputs

for Simulated Open-gate Terminals of XOR Gate XOR 1 for f= (x1x2 x1' x2')

Transistor F O

T1 11189 12213

T2 11189 12213

T3 10941 11946

T4 5141 4162

T5 21 5

T6 10933 11957

129

Table 6.9 Decimal Equivalents of the Observed Simulation Outputs

for Simulated Open-Gate Terminals of XOR Gate XOR 2

for f = (x1x2 x1' x2')

Transistor F O

T1 10933 12021

T2 10933 12021

T3 10941 11938

T4 5141 258

T5 21 11936

T6 10933 11936

Table 6.10 Decimal Equivalents of the Observed Simulation Outputs

for Simulated Open-gate Terminals of XOR Gate XOR 3 for

f= (x1x2 x1' x2')

Transistor F O

T1 10933 11938

T2 10933 11938

T3 21 11944

T4 10912 11944

T5 21 11944

T6 11261 11944

130

Table 6.11 Decimal Equivalents of the Observed Simulation Outputs

for Simulated Open-gate Terminals of XOR Gate XOR 4 for

f= (x1x2 x1' x2')

Transistor F O

T1 16053 11944

T2 16053 11944

T3 21 11938

T4 11261 11944

T5 21 11944

T6 10912 11944

Table 6.12 Decimal Equivalents of the Observed Simulation Outputs

for Simulated Open-gate Terminals of XOR Gate XOR 5 for

f= (x1x2 x1' x2')

Transistor F O

T1 16055 11944

T2 16055 11944

T3 21 11944

T4 10912 11944

T5 0 11944

T6 10941 11944

131

Table 6.13 Decimal Equivalents of the Observed Simulation Outputs

for Simulated Open-gate Terminals of XOR gate XOR 6 for

f= ( x1x2 x1' x2')

Transistor F O

T1 10933 11959

T2 10933 11959

T3 10933 11936

T4 10933 16042

T5 10933 0

T6 10933 2

Table 6.14 Decimal Equivalents of the Observed Simulation Outputs

for Simulated Open-gate Terminals of XOR Gate XOR 7

for f= (x1x2 x1' x2')

Transistor F O

T1 10933 12023

T2 10933 12023

T3 10933 2

T4 10933 11936

T5 10933 2

T6 10933 12279

132

6.11.3 Identifiabilty and distinguishability calculations

Total open faults in the gate terminals = 6 x 7 = 42 (6.10)

(No. of XOR gates * No. of transistors in each XOR gate)

6.11.3.1 Identifiability

No. of unidentifiable open-gate terminal faults

= No. of faults producing the output set same as that of fault-free

circuit

= No. of faults producing the output set {10933, 11938}=2 (6.11)

(due to open gates of transistors T1 and T2 of XOR 3)

Hence, Identifiability factor = 100 (1 - 2/42) = 95.24 % (6.12)

6.11.3.2 Distiguishability

The output sets occurring more than once, but different from the

fault-free set is shown in Table 6.15, from which the individual as well as

overall distiguishability factors can be determined.

133

Table 6.15 Output Sets for Distinguishability Calculations

D -- Distiguishability

Set No. { F, O } Repetitions Open-Gate-Terminal

location % D

1 ( 11189, 12213 ) 2 T1 & T2 of xor1 95.24 2 (10933, 12021 ) 2 T1 & T2 of xor2 95.24

3 ( 10933, 11936 ) 3 T6 of xor2, T3 of xor6, T4 of xor7

92.86

4 ( 21, 11944 ) 4 T3 & T5 of xor3, T5 of xor4, T3 of xor5

90.48

5 ( 10912, 11944 ) 3 T4 of xor3, T6 of xor4, T4 of xor5

92.86

6 ( 11261, 11944 ) 2 T6 of xor3, T4 of xor4 95.24 7 ( 16053, 11944 ) 2 T1 & T2 of xor4 95.24 8 ( 16055, 11944 ) 2 T1 & T2 of xor5 95.24 9 ( 10933, 11959 ) 2 T1 & T2 of xor6 95.24 10 ( 10933, 11936 ) 2 T3 of xor6, T4 of xor7 95.24

11 ( 10933, 2 ) 3 T6 of xor6, T3 & T5 of xor7

92.86

12 ( 10933, 12023 ) 2 T1 & T2 of xor7 95.24 Total 29

Total No.of sets with repetitions (excluding the unidentifiable case):12

(6.13)

Total No.of repetitions : 29 (6.14)

Overall Distiguishability factor = 100 (1 – 29/42) = 30.95 % (6.15)

(Minimum for individual sets: 90.48 % Maximum: 95.24 %)

6.11.4 Remarks

The identifiability is of the order of 95 % and hence the

number of unidentifiable faults is quite low (only 2 for the

example function).

134

The overall distinguishability is quite low, of the order of only 30 %, showing that the total number of repeated output sets, on the whole, is large (29 out of 42 possible faults).

Though the overall distinguishability is low, the individual distinguishability indices are much higher (between 90% and 95% for the function considered).

The location of the fault can be easily inferred from the output set values.

The high values of identifiability and individual distinguishability factors indicate that the number of fault locations is very limited and hence suitable rectification can be made quickly.

The identifiabilty and distinguishability factors have been calculated for stuck-open gate-terminals only; hence the values are likely to be different if the drain and source terminal faults are also considered.

6.12 CONCLUSION

CMOS transistor based logic circuits find extensive application in VLSI and FPGA. In addition to the stuck-at faults at the inputs or outputs of various logic gates implemented for a function, the CMOS circuits can also have other different types of faults. This chapter discusses the analysis and diagnosis for stuck-opened gate terminals of the various CMOS transistors implementing the testable realized circuit. The process of testing and fault identification are explained with reference to a specific two variable function containing three terms. It is shown that even this simple circuit has a lot of fault possibilities. Only a single gate terminal is assumed to be stuck-open at a time. Similar studies on the effect of stuck-open faults at the drain and source terminals also should be made for complete analysis for a given function.