Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

Importance of Layer-to-Layer Alignment

marginal contact

Design Rules are needed:

• Interface between designer & process

engineer

• Guidelines for designing masks

Example of Design Rule:

If the minimum feature size

is 2l, then the safety margin

for overlay error is l.

Example: metal line to contact hole

no contact!

safety margin to allow for misalignment

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

IC RESISTOR MASK LAYOUTS – REGISTRATION OF EACH MASK

Registration of mask patterns is critical show separate layouts to

avoid ambiguity

Oxide mask (dark field)

Al mask (clear field)

Contact mask (dark field)

A A

B

B

0

1

2

“registration” shows overlay of patterns

scale in m

for B-B “cut”

Registration of one mask to the next (also called “alignment” and

“overlay”) is a crucial aspect of lithography

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

Same Layout but with misregistration (misalignment)

perfect registration

A A

B

B

0

1

2

scale in m

for B-B “cut”

A A

B

B

0

1

2

scale in m

for B-B “cut”

Contact mask misaligned by 2m

Lets look again at cross-section A-A to understand the consequence of

this misalignment. Note contact mask 2m

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

Layout with no misregistration (misalignment)

perfect registration

A A

B

B

0

1

2

AA

STEP 7

Al

p-type layer

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

Layout with misregistration (misalignment)

A A

B

B

0

1

2

scale in m for

B-B “cut”

Contact mask misaligned by 2m

Thus we need safety margins in layout which take into account

the possible tolerances in fabrication. Each process has a set of

“design rules” which specify the safety margins.

This resistor has

an open circuit !!

AA

STEP 7

Al

p-type layer

Al

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

6

Layout Design Rules

(1) Absolute-Value Design Rules

* Use absolute distances

(2) l -based Design Rules

6

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

7

EE143 Layout Design Rules

1. Basic length unit = l = 2m

1.2 Overlay accuracy = l

1.1 Lithography and etching limit =2l

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

8

2.1 Metal-Si Contact Hole

l2

ll

Min. contact hole = 2 l x 2 l

l2

Min contact hole to diffusion

layer distance = l

n+

p-sub

SiO2

n+

p-sub

SiO2

Al

(same rule for Metal-poly)

l

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

9

2.2. Metal Lines

Min. metal-metal

spacing = 3l

l3

l2

Line

2

Line

1

[Rationale] metal runs

on rough

topography

3 l spacing to ensure no shorting between the 2 lines.

Min width = 2l

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

10

Min overlap of contact hole = l

l

l

Si

Etching

problemCVD SiO2

deposition.

problem in

narrow gap

l

SiO2

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

11

Metal line-width is larger when running

over a contact hole

l

l2

l

l4

l2

2l

l

l

Configuration 1

Configuration 2

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

12

2.3 Poly-Si Lines

Min width = 2l

Min poly-poly spacing = 2 l

Min underlap of

metal/poly contact = l

l2

l2

Line 2

ll

ll 44

poly

metal

Line 1

[Rationale: Unlike metal lines,

poly-Si runs on smoother topography]

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

13

ll poly

metal

Example: Metal Contact to Poly

Note:

Both metal and poly linewidths

will enlarge to accommodate

contact hole overlay error l

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

14

2.4. MOS Thin-Oxide Region

Min spacing = 3 l

Thick Oxide Region (FOX)

Thin Oxide Region

(active device area)l2

l2

l2

l3

Min Width = 2 l

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

15

Min underlap of thin-oxide contact = l

l

l

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

16

3. Poly-Si Gate

n+ n+

n+

Min gate-overlap of

field oxide = l2

[Comment]

l2

Avoid n+ channel formation during S/D Implant

idealWith overlay error

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

17

Min thin-oxide contact to gate spacing = 2 l

2 l2 l

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

18

Al

Poly

SiO2

Si

~400OCAl

Poly

SiO2

Si

Al

spike

Al

Poly gate

Comment:

Al to poly contact

should not be directly on top

of gate oxide area

Si

Gate oxide

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

19

SiO2 (CVD)

FOX

l2

Al contact on thick

oxide area ok

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

20

Min Gate Width = 2 l

Min Gate Length = 2 l

Usually: W/L are

specified by circuit

requirement.

Min. poly to thin oxide spacing = l

l

Professor N Cheung, U.C. Berkeley

Lecture 20EE143 F2010

21

Design a minimum-size poly-gate MOS transistor

with W/L = 4m/4m (2 l x 2l )

Example

Minimum size contact = 2lx2l

Minimum thin-oxide-region underlap of contact = l

Minimum source/drain contact to gate spacing = 2l

Minimum L = 2l Minimum W = 2l

Minimum gate overlap of field-oxide region = 2l

Minimum metal overlap of contact = l

Minimum thin-oxide-region to thin-oxide-region spacing = 3l

* Layout area /transistor = 15lx7l = 105 l2

metal

poly

Active region

Contact hole

Half-way

distance to

next MOSFET

( = 1. 5 l )