VG < Vthreshold VGee143/fa10/lectures/Lec_23.pdf“Yau Model” for short-channel effect. Professor N Cheung, U.C. Berkeley EE143 F2010 Lecture 23 28 •Implantation at low energy

Professor N Cheung, U.C. Berkeley

Lecture 23EE143 F2010

1

Negligible electron concentration

underneath Gate region;

Source-Drain is electrically open

High electron concentration

underneath Gate region;

Source-Drain is electrically connected

VG < Vthreshold VG > Vthreshold

Metal -Oxide-Semiconductor Transistor [ n-channel]



2

MOSFET I-V Analysis

n+ n+

VS VG

W

VB=0

VD

ID

L

Qn

N-MOSFET

•In general, inversion charge Qn ( [VG-VT]) decreases from Source toward

Drain because channel potential VC increases.

VT increases



3

Let VT defined to be threshold voltage at Source

2

VVVC

)average(VVC)average(Q

2

VV~)average(V

DSTGOX

TGOXn

DSTT [ This is an approximation ]

ID = Wt (-q n vdrift)

= W Qn vdrift

Inversion layer thickness Inversion layer concentration

Approximate Analysis

Note: ID is constant for all positions

along channel



4

L

VEvWith DSn

ndrift

DSDS

TGOXD V2

VVVC

L

WI

VDS

ID

Linear with VDS

Quadratic with VDS



5

VD saturation

n+ n+

VS=0

VD

Qn=0 at the drain

Lateral E-field

Electrons moves

saturation velocity

VDsat is defined to be the value of VD

with Qn=0 at drain.

From Qn = Cox (VG -VT -VD), we get VDsat =VG-VT



6



7

VD

ID



8

DSDS

TGOXn

D VV

VVCL

WI

2

MOSFET I-V Characteristics Summary

For VD < VDsat

2

2TGOX

nDsatD VVC

L

WII

For VD > VDsat

Note: VDsat = VG - VT



9

Ex

SiO2

inversion

layer

Mobility of inversion charge carriers

*Carrier will experience

additional scattering at the

Si/SiO2 interface

*Channel mobility is lower

than bulk mobility

* (effective) is extracted from MOSFET I-V characteristics

* Typically ~0.5 of (bulk)



ID vs. VDS Characteristics

The MOSFET ID-VDS curve consists of two regions:

1) Resistive or “Triode” Region: 0 < VDS < VGS VT

2) Saturation Region:

VDS > VGS VT

oxnn

TGSn

DSAT

Ck

VVL

WkI

where

2

2

oxnn

DSDS

TGSnD

Ck

VV

VVL

WkI

where

2

process transconductance parameter

“CUTOFF” region: VG < VT



If L is small, the effect of DL to reduce the inversion-

layer “resistor” length is significant

ID increases noticeably with DL (i.e. with VDS)

Channel-Length Modulation

ID

VD

S

ID = ID(1 + lVDS)

l is the slope

ID is the intercept



N-Channel MOSFET Summary

VDS and VGS normally positive values

• VGS< Vt : cut off mode, IDS=0 for any VDS

• VGS> Vt : transistor is turned on

1) VDS< VGS-Vt: Triode Region

2) VDS> VGS - Vt: Saturation Region

Boundary between Triode and Saturation Regions

GS t DSv V v

2

DSDStGSD vv)Vv(22

KP

L

Wi

2

tGSD )Vv(22

KP

L

Wi



P-Channel MOSFET Summary

vDS and vGS normally negative values

• vGS > Vt :cut off mode, IDS=0 for any VDS

• vGS < Vt :transistor is turned on

1) vDS > VGS-Vt: Triode Region

2) vDS < vGS-Vt: Saturation Region

Boundary

GS t DSv V v

2

DSDStGSD vv)Vv(22

KP

L

Wi

2

tGSD )Vv(22

KP

L

Wi



P-Channel MOSFET ID vs. VDS

• As compared to an n-channel MOSFET, the signs of all the

voltages and the currents are reversed:



MOSFET VT Measurement

• VT can be determined by plotting ID vs. VGS,

using a low value of VDS :

DSDSTGSD VV)VV(2KI ID (A)

VGS

(V)VT

0



16

Approximation assumes

VSi does not change much

OX

OXC

nV

DD

SiOXFBG VVVV

Picks up all

the changes

in VG

Justification:

If surface electron density

changes by n Ei

Ef

kTen

nln

D

D but the change of VSi changes

only by kT/q [ ln ( n)] – small!

Why xdmax ~ constant beyond onset of strong inversion ?

Higher than VT



17

VSi n-surface

0 2.10E+04

0.1 9.84E+05

0.2 4.61E+07

0.3 2.16E+09

0.4 1.01E+11

0.5 4.73E+12

0.6 2.21E+14

0.7 1.04E+16

0.8 4.85E+17

0.9 2.27E+19

n-surface

p-Si

Na=1016/cm3

Ef

Ei

0.35eV

n-bulk = 2.1 104/cm3

qVSi

Onset of strong inversion

(at VT)

n-surface = n-bulk e qVSi/kT



18

Parameter Extraction from MOSFET I-V

(A) VT VD

ID

D

S

.

0

221

2

'

'

modesaturationinisMOSFET

offpinchatisDrain

VV

VqNC

VV

drainatV

VVVFor

TG

Dpas

OX

pDFB

T

TGD



19

2TDDsatD VV

L

WkII

VDVT

DI

L

kWslope

VG

nCOX



20

Alternative way to extract VT

•Measure ID versus VG for a fixed small VDS (say <100mV)

The intercept of ID versus VG plot on VG-axis is VT.

DSTGOXn

DSDS

TGOXn

D

VVVCL

W

V2

VVVC

L

WI

VT

VG

ID



21

VD

ID

VB(varies)

VD

VB =0 VB1 VB2

VT0 VT1VT2

DI

OX

as

pSBp

SBTSBT

C

qN

V

VwithVVwithV

2

22

00

(B) Body Coefficient



22

ID

VD

VG2

VG1

(C)

VD

DTGOXn

D

D

DD

TGOXnD

VsmallforVVL

WC

V

I

VV

VVCL

WI

2

ID

VG slope

L

WCOXn



23

(D) Transconductance gm

(a) For VDS<VDsat

(b) For VDS > VDsat

DVfixedG

Dm

V

Ig

DSOXn

G

D

DSDS

TGOXn

D

VL

WC

V

I

VV

VVCL

WI

2

TGOXn

G

D

TGOXn

DsatD

VVCL

W

V

I

VVCL

WII

2

2

ID

VDS

VG1+DVG

VG1

VDsat

[gm varies with VDS]

[gmsat varies with VG]



24

ID

VD

VDsat

real

ideal

n+ n+

Qn

1

2

)(01.01.0~

12

volttoTypically

VVVk

I DSTGDsat

l

l

(E) Channel Modulation Parameter l



25

Short Channel Effect on VT

VT

ideal

analysis

L

depletion

charge

controlled

by gate.

n+ n+

VG

pdepletion layer

L



26

n+ n+

VS=0 VD=0

Wo

x

WoXj+Wo

Xj

Xj

Xj

L’

L

12

12

2

2'

22

j

oj

jooj

X

WXL

XWWXL

xLLNote: Wo is xdmax

Same

electric

potential

because of

heavily

doped n+



27

fX

W

L

X

Q

Q

WWLL

Nq

j

oj

ideal

actual

oa

12

11

2

1

Area of gate charge distribution

“Yau Model” for short-channel effect.



28

•Implantation at low energy

•Small Dt.

•Minimize channeling and

transient enhance diffusion

To make f 1

Xj

Wo •Increase Na

L large

S/D S/D

L small

S/DS/D



29

VT

L

Large VDS

VDS ~ 0

Effect of VDS on VT Lowering

Large VDS Larger S/D depletion charge at the drain side

Smaller depletion region charge contributed by gate

VT starts to decrease at larger L

n+ n+

VG

depletion layer

Depletion charge

contributed

by gate



30

parasitic

charge

which has to

be created

by gate bias

VT is larger than ideal analysis.

Fox Fox

W

Ideal Depletion charge

W

Narrow Width Effect (related to W)



31

VT

W

VT

L

Narrow Width Effect

Narrow Channel Effect



32

Small Geometry Effects Summary

W

L

Actual gate

control charge

Ideal

gate control

charge



SUMMARY of MOS Module

33

• Accumulation, Depletion, and Inversion Modes

• Flat Band Voltage, Threshold Voltage

• Charge Distributions and E-field Distributions

• Voltage drop across Silicon and across oxide

• Channel Bias and Substrate Bias

• Oxide Charge Effects

• Threshold Voltage Tailoring by Implantation

• NMOS and PMOS

• Small Signal Capacitance versus VG

• MOSFET I-V Characteristics

• VDsat and IDsat

• MOSFET Parameters Extraction

• Short Channel and Narrow Channel Effects (qualitative)

Documents

VG < Vthreshold VGee143/fa10/lectures/Lec_23.pdf“Yau Model” for short-channel effect. Professor N Cheung, U.C. Berkeley EE143 F2010 Lecture 23 28 •Implantation at low energy