EEE515J1 Combinational Logic: Truth tables to equations

4 October, 2005 www.eej.ulst.ac.uk/~ian Slide 1 of 15

EEE515J1Combinational Logic:

Truth tables to equations

Ian McCrum Room 5D03B

Tel: 90 366364 voice mail on 6th ring

Email: [email protected]

Web site: http://www.eej.ulst.ac.uk


Two example circuits


To analyse the bottom circuit

• Create a table with columns for the 8 possible input patterns.

• There are 3 inputs so there are 2^3=8 unique input patterns

• Add columns and labels for intermediate signals as well as the output


ABC AC B/C /ABC Y

000

001

010 1 1

011 1 1 1

100

101

110 1 1

111 1 1

To come up with a circuit from a truth table, concentrate on each output at a’1’ that is needed

We need to detect four particular input patterns, {010,011,110,111}

This could be done by using a three input AND gate to detect each ‘1’ and then ORing each of the “on-term” detectors.


ABC AC B/C /ABC Y

000

001

010 1 1

011 1 1 1

100

101

110 1 1

111 1 1

“On-term” detectors also called “Product Term detectors

e.g. to detect the product term {110} (sometimes called m6) we use an invertor on C, so the AND gate will go high when the input is AB/C

I.E go high when the input is /AB/C

This type of circuit is called AND-OR

And directly generates the SUM of PRODUCTS (SOP) form

Y=/ABC + /ABC + AB/C + ABC


ABC AC B/C /ABC Y

000

001

010 1 1

011 1 1 1

100

101

110 1 1

111 1 1

i.e. Generate a ‘1’ when inputs are 010 or 011. Also generate a ‘1’ when the inputs are 110 or 111. but for an input pattern of 010 or 011 you only need to detect 01 on the A and B inputs. (/AB)

Likewise detect 11 on the A or B inputs, C can be either a ‘0’ or a ‘1’ – it doesn’t matter. Hence use the term AB.

Now Y=/AB+AB ; again A can be ‘0’ or ‘1’ so the answer is just B Note again in the truth table, the bold terms are when we want to o/p to be a ‘1’.

A B C

AND OR


ABC AC B/C /ABC Y

000

001

010 1 1

011 1 1 1

100

101

110 1 1

111 1 1

With practice you can spot these minimisations by inspection.

They are examples of the “logic adjacency theorem” – if two product terms are absolutely identical except they differ in having one variable in a normal form in one term and in the complementary form in the other term then you can remove that term. Taking the first pair of ones…

/A B /C + /A B C = /A B


What you should know

• How to write down a SOP equation from a truthtable

• Save ink if possible and be quick (try and apply the adjacency theorem by inspection) Don’t worry if you don’t/can’t

• If you really need to minimise – use a computer! See the package McBoole or let Quartus do it for you.


Points so far

• A product term or minterm or “on-term” generates a ‘1’ output in a truth table

• A canonical product term contains every variable• The “Sum of Product form or AND-OR circuit is a

useful way of generating an o/p• Two product terms can be combined – and a

variable is removed, by using the adjacency theorem

• We can cost circuits – according to a “Cost model”


Cost models

• What costs?• Silicon area• Gate count• Power consumption• Speed• Number of soldered joints• Number of packages• Number of unusual packages• Stores inventory• Etc…!!!


“McCrum’s Cost Model”

• The simplest I could come up with and still allows you to show you have thought about costing.

• One penny per gate input, with free invertors!

• Later on we will add 6p per D-type flop-flop and 9p for any other flip-flop type.


Example

3p

2p+2p+3p+3p = 10p

A canonical solution will cost 3p+3p+3p+3p + 4p = 16p

Since the truth table had 4 on-terms in it – 4 product term detectors each of which was a 3 i/p AND gate.


Tutorials (verify by quartus!)

0000 0 0 0 1

0001 0 0 1 0

0010 0 0 1 1

0011 0 1 0 0

0100 0 1 0 1

0101 0 1 1 0

0110 0 1 1 1

0111 1 0 0 0

1000 1 0 0 1

1001 1 0 1 0

1010 1 0 1 1

1011 1 1 0 0

1100 1 1 1 0

1101 X X X X

1110 1 1 1 1

1111 0 0 0 0

ABCD P Q R SThis is taken from the file super13.doc. It is 4 separate circuits – one for P, one for Q, one for R and one for the S output. There are 4 inputs A,B,C and D. Generate the schematics and simulate to prove the truthtable/schematic is correct. [Tut L2_1, L2_2, L2_3 and L2_4]

We could also specify this problem by numbering the input patterns, m0 to m15

Thus P = f(ABCD) = ∑(m7-m12, m14)

Some software will allow the use of don’t care terms, using a ‘d’ or ‘x’ term. See the file McBoole.txt in the files section of the website for an example.

0111 1

100X 1

101X 1

11X0 1

1101 d


More costings [Tutorials]

0000 0 0 0 1

0001 0 0 1 0

0010 0 0 1 1

0011 0 1 0 0

0100 0 1 0 1

0101 0 1 1 0

0110 0 1 1 1

0111 1 0 0 0

1000 1 0 0 1

1001 1 0 1 0

1010 1 0 1 1

1011 1 1 0 0

1100 1 1 1 0

1101 X X X X

1110 1 1 1 1

1111 0 0 0 0

ABCD P Q R S

Each product term will require a 4 input AND gate, ignoring m13 we need 15 such gates or 60p

P needs a 7 i/p OR

Q needs a 7 i/p OR

R needs a 8 i/p OR

S needs a 7 i/p OR

Total cost = 89p

(cost of P is 35p)

0111 1

100X 1

101X 1

11X0 1

1101 D

This solution costs

4p+3p+3p+3p for AND gates and 4p for the output gate for P

(cost of P is 13p)

TUT L2_5; what is a more minimal cost of Q,R and S?


• A product term or minterm or “on-term” generates a ‘1’ output in a truth table

• A canonical product term contains every variable• The “Sum of Product form or AND-OR circuit is a

useful way of generating an o/p• Two product terms can be combined – and a

variable is removed, by using the adjacency theorem• We can cost circuits – according to a “Cost model”• Be able to move from truth tables to AND-OR

equations and circuits• Be able to do a little minimisation be inspection• Be able to “cost” a circuit• You now have 5 tutorials to try! [Tut L2_1 to L2_5]

Conclusion

Documents

EEE515J1 Combinational Logic: Truth tables to equations