ELEC 301 SPRING 2009 VOLKAN KURSUN ELEC 301 Design Metrics Volkan Kursun

ELEC 301 SPRING 2009 VOLKAN KURSUN

ELEC 301ELEC 301

Design MetricsDesign Metrics

Volkan Kursun


AnnouncementsAnnouncements Project is announced

Form a group of two students by March 19 2009 (next Thursday)

Give the names of your group members to the lab technician Alex by March 19 2009

You cannot modify the group members after March 19


AnnouncementsAnnouncements HW1 solution is on the web

HW2: on the web

Midterm exam Venue: Lecture Theater A Date: 31 Mar 2009 (Tue) Time: 18:50 - 21:00 Closed book exam No copy sheets Bring a calculator


Representation of Digital SignalsRepresentation of Digital Signals Digital systems perform operations on logical

(Boolean) variables A logical variable can have two discrete values

– X: 0, 1

A logical variable is a mathematical abstraction Physical implementation requires the

representation of logical variables with electrical quantities Voltage


Representation of Digital SignalsRepresentation of Digital Signals Node voltage

Not discrete Has a continuous range of values

Turn the electrical voltage into a discrete variable by associating a nominal voltage level with each logic state 1: VOH 0: VOL VOH and VOL represent the nominal high and low

logic levels, respectively


Reliability―Reliability―Noise in Digital Integrated CircuitsNoise in Digital Integrated Circuits

i(t)

Inductive coupling Capacitive coupling Power and ground noise

v(t) VDD

Noise: unwanted variation of voltage and current at a circuit node


Mapping Between Analog and Digital SignalsMapping Between Analog and Digital Signals

“0”

V OL

V ILV IHV OH

Und

efin

ed

Reg

ion

“1”

Digital circuits can tolerate certain amount of deviations from the nominal voltages

Logic levels are represented by a range of acceptable voltages, rather than only by a nominal voltage

The voltage ranges of logic levels are separated by a region of uncertainty


DC OperationDC OperationVoltage Transfer CharacteristicsVoltage Transfer Characteristics

Electrical function of a gate is determined by the voltage transfer characteristics DC transfer characteristics

Plot the output voltage as a function of the input voltage Vout = f (Vin) Determine the acceptable ranges of input and output

voltages


DC OperationDC OperationVoltage Transfer CharacteristicVoltage Transfer Characteristic

Vin

Vout

VOH

V OL

VM

VOH

V OL

f

Vout = Vin

Switching Threshold Voltage

Nominal Voltage Levels

VOH = f(VOL)VOL = f(VOH)VM = f(VM)


VIL

VIH

Vin

Slope = -1

Slope = -1

VOL

VOH

Vout

“ 0” VOL

VIL

VIH

VOH

UndefinedRegion

“ 1”

The regions of acceptable high and low voltages are delimited by VIH and VIL

Vin = Vout

Gate switching threshold voltage

Mapping Between Analog and Digital SignalsMapping Between Analog and Digital Signals


Noise MarginsNoise Margins For a gate to be robust, the acceptable voltage

ranges of the “0” and “1” logic levels must be as large as possible

Concept of noise margins A measure of the tolerance of a gate to noise

Noise margin low (NML) Quantizes the range of voltages considered valid 0

Noise margin high (NMH) Quantizes the range of voltages considered valid 1


Definition of Noise MarginsDefinition of Noise Margins

Noise margin high

Noise margin low

VIH

VIL

UndefinedRegion

"1"

"0"

VOH

VOL

NM H

NM L

Gate Output Gate Input

Steady-state signals must avoid the undefined region for a proper operation

Lowest voltage that is considered logic high: “1”

Highest voltage that is considered logic low: “0”


Noise BudgetNoise Budget

Noise sources: supply noise, cross talk, and interference

Differentiate between static and dynamic noise sources

Static noise budget allocates gross noise margins to expected sources of noise

Static noise margins result in very conservative designs


Regenerative PropertyRegenerative Property

v2

v1

f(v)

finv(v)

v3

out

v

A voltage v0 that deviates from the nominal voltages is applied to the first inverter

The signal gradually converges to one of the nominal values after a number of inverter stages


Signal Regeneration (Restoration)Signal Regeneration (Restoration)

A chain of inverters

v0 v1 v2 v3 v4 v5 v6

2

V (

Volt

)

4

v0

v1v2

t (nsec)0

2 1

1

3

5

6 8 10 Simulated response

Ex: Chain input signal Vo is degraded due to noise → reduced voltage swing

The deviation in voltage levels disappears as the signals propagate through a chain of inverters


Fan-in and Fan-outFan-in and Fan-out

N

Fan-out N Fan-in M

M

Fan-out: number of loading gates connected to the output of a gate

Fan-in: number of inputs


Fan-in and Fan-outFan-in and Fan-out

N

Fan-out N

Increasing the fan-out can affect the output logic level

To minimize the effect of fan-out on logic levels Input resistance of load gates

must be as large as possible– Low output current to the fan-out

gates

Output resistance of the driver gate must be as small as possible

– Reduce the effect of output currents on the output voltage level


The Ideal Gate Voltage Transfer The Ideal Gate Voltage Transfer CharacteristicsCharacteristics

Ri = Ro = 0Fanout = NMH = NML = VDD/2 g =

V in

V out


An Old-time Inverter: NMOSAn Old-time Inverter: NMOS

NM H

Vin (V)

NM L

VM

0.0

1.0

2.0

3.0

4.0

5.0

1.0 2.0 3.0 4.0 5.0

VDD = 5V, VGND = 0V

VOH = 3.5V, VOL = 0.45V, VIH = 2.35V, VIL = 0.66V, VM = 1.64V, NML = 0.21V, NMH = 1.15V

Issues:• Asymmetrical VTC• Narrow noise margins

• Low NML• VOH < VDD

• VOL > 0

• Low output voltage swing (VOH - VOL) < VDD


Delay DefinitionsDelay Definitions How quickly does a circuit respond to a change

of the inputs? Delay experienced by a signal while

propagating through a circuit Propagation delay is a function of

Technology– GaAs vs. silicon CMOS

Circuit topology Slopes of the input signals Load and driver impedances


Delay DefinitionsDelay Definitions

Vout

tf

tpHL tpLH

tr

t

Vin

t

90%

10%

50%

50%

High-to-low and low-to-high propagation delays

tp = (tPHL + tPLH) / 2

Rise time: tr

Fall time: tf


Ring OscillatorRing Oscillator

v0 v1 v5

v1 v2v0 v3 v4 v5

T = 2 tp N

For oscillation: 2Ntp >> tr+tf

Otherwise the propagating signals overlap and dampen the oscillation

1

0 0 0

1 11 1 1

0 0 0


A First-Order RC NetworkA First-Order RC Network

vout

vin C

R

tp = ln (2) = 0.69 RC

Simplest model to represent the delay of an inverter


Power: energy dissipated or stored per unit of time

Influences several design decisions Power supply Power distribution network

– Nominal supply voltage VDD and tolerable variation– Supply current demand

Battery lifetime Heat dissipation

– Packaging– Cooling system

Power DissipationPower Dissipation


Limits the number of devices than can be integrated on an IC

Limits how fast a circuit can operate Faster circuits tend to consume more power

Limits the number of operations that can be performed between battery changes



Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)

Peak power: ppeak = Vsupplyipeak = max [p(t)] Critical in power supply and distribution network design

Average power:

Critical to determine the cooling and battery requirements


Tt

t

Tt

t supplysupply

ave dttiT

Vdttp

TP )(

1


Power – Components Power – Components Dynamic power: Occurs during transients when

a circuit is switching Due to charging of capacitors + temporary current paths between the supply rails Proportional to the switching frequency

– The higher the number of switching events the greater the dynamic power consumption

Static power: Occurs statically, all the time, regardless of a switching activity Caused by the static conduction paths between the

supply rails and the leakage currents


Power – Speed Relationship Power – Speed Relationship Propagation delay is determined by the speed

at which a given amount of energy can be transferred to/from the parasitic capacitors of a circuit (C = Q / V)

The faster the energy transfer, the higher the circuit speed is

– Faster energy transfer means higher power consumption

Reminder:– Power: energy dissipated or stored per unit of time


A First-Order RC NetworkA First-Order RC NetworkVdd

Vout

isupply

CL

E0->1 = CLVdd2

PMOS

NETWORK

NMOS

A1

AN

NETWORK

E0 1 P t dt

0

T Vdd isupply t dt

0

T Vdd CLdVout

0

Vdd

CL Vdd 2= = = =

Ecap Pcap t dt

0

T Vouticap t dt

0

T CLVoutdVout

0

Vdd 1

2---C

LVdd

2= = = =

vout

vin CL

R


Energy and Energy-Delay ProductEnergy and Energy-Delay Product

Power-Delay Product (PDP) = Pav tp

PDP: Energy (E) consumed by a gate per switching event

Energy-Delay Product (EDP) = power x delay2

quality metric of a gate = E tp

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ELEC 301 SPRING 2009 VOLKAN KURSUN ELEC 301 Design Metrics Volkan Kursun