ELX304-Topic5-Lesson 4_pr2.pdf

Electronic Systems Design (ELX304) Lesson 4 – CMOS Analogue design

University of Sunderland Page 1

LESSON 4

CMOS ANALOGUE DESIGN

INTRODUCTION This lesson discusses those analogue applications suitable for implementation using VLSI and the methodologies used for their construction.

YOUR AIMS At the end of this lesson, you should be able to

• appraise critically the performance/operation of conversion devices between the analogue and digital domains

• analyse alternative structures used in analogue VLSI Circuits.

STUDY ADVICE This particular lesson is designed to be selfcontained. However, the following references will provide additional support material.

SUPPORT MATERIAL Allen, P.E., Holberg, D.R. (2002) CMOS Analog Circuit Design. Oxford University Press.

Geiger, R. L., Allen, P. E. & Strader, N.R. (1990) VLSI, Design techniques for Analog and digital circuits. McGraw Hill. (Chapter 8)

Ismail, M., Fiez, T. (1994) Analogue VLSI: Signal and Information Processing. McGraw Hill. (Chapter 9)





4.1 ANALOGUE VLSI DESIGN To date we have mainly considered the construction of MOS transistors for the implementation of digital logic. In this lesson we will be investigating the use of these technologies for Analogue applications. However, in previous modules analogue circuit design has involved the use of

i) Passive Technology: Circuits constructed from Resistors, Capacitors and Inductors alone, for example filters.

ii) Active Technology: Circuits built using electronic amplifiers, for example operational amplifiers.

In VLSI terms passive technology is not considered as circuits built entirely from resistors and capacitors are wasteful of available silicon area, compared with transistors, and inductor construction is problematic.

However, amplifier construction can be achieved using Bipolar Junction Technology or CMOS technology and so the basic building blocks for more complex applications are available to the designer for construction within VLSI. The operational amplifier is a particularly useful device as it is a high gain differential amplifier which ideally has the characteristics of high input impedance, low output impedance, high bandwidth and low offset.

The above schematic shows that in practice, this is achieved using a basic differential amplifier in conjunction with further circuitry specifically designed to improve its overall characteristics.

Although this lesson will not address operational amplifier design the following table, in conjunction with the recommended reading, identifies circuit designs for anyone wishing to investigate further.

Differential Amplifier Stage

High Gain Amplification

Stage

Output Buffer

Differential Input

Compensation Circuitry

Bias Circuitry

Output



Current Sink Current Mirror Load Differential Amplifier Source Coupled Pair Inverter High Gain Stage Current Sink Load Current Source Bias Circuit Current Mirror Source Follower

Operational Amplifier

Output Buffer Current Sink Load

4.1.1 APPLICATION TECHNOLOGIES The VLSI design technology described in previous lessons has allowed the design of digital Application Specific Integrated Circuits (ASIC's) in house using suitable CAD software. Unfortunately several problems exist using the above technology as it is specifically developed for digital computation and storage. The main problem being low integration levels (large silicon usage) required for analogue IC implementation since it uses hybrid technology in its construction.

More recently, with the advent of doublepolysilicon CMOS (BiMOS) technology, some of these problems have been overcome. In particular, the construction of high value capacitors in a much smaller area than is possible with metalsilicon capacitors is possible by using two polysilicon layers as conducting plates. In addition Bipolar Transistor's, the basic building block of linear analogue IC's, may also be constructed on the same chip providing increased speed, improved noise performance and more precise characteristics than is available using CMOS technology alone.

As analogue signals exist in continuous time with continuous amplitudes then the previous circuits will be expected to work in the active, linear, region where power consumption is relatively high. However, an alternative solution is to use logic switching at high frequencies, with some form of averaging, so that the digital system appears continuous. The following table illustrates suitable technologies for signal processing applications:

MOS Digital Logic MOS Analogue Bipolar Digital Logic Bipolar Analogue BiCMOS Optical GalliumArsenide Frequency (Hz) 1 10 100 1K 10K 100K 1M 10M 100M 1G 10G

Seismic Audio Telecommunications Microwave 100G



4.2 SIGNAL PROCESSING In signal processing there is a major need to be able to communicate between the Analogue and Digital domains in order to fully utilise the benefits afforded by both technologies. In particular:

i) Data Acquisition Systems The collection of continuous signals (audio and video signals, measurements via transducers, etc...) and their subsequent analysis/storage within digital devices (computers, controllers, disks, memories, etc...). For example:

Multiplexer Analogue Signals

Sample

Hold &

Analogue to

Digital Converter

n bit

Signal Digital

ii) Digital Control Systems In order to complete the feedback control loop we require the ability to manipulate a process input, via actuators, using a signal generated by a computer control algorithm. That is:

Analogue Analogue to

Digital

Converter

n bit

Signal Digital Filter

Signal Amplifier

Optional Devices

The following sections will investigate commonly used circuits for constructing the elements identified above.



4.2.1 DIGITAL TO ANALOGUE CONVERTERS (DAC'S)

The digital to analogue converter, DAC, is required to provide an analogue output which is proportional to an nbit digital code input. That is to produce a unique voltage level for each of the possible 2 n digital codes that can occur when using an nbit converter. Although there are numerous methods of achieving this they all share the following basic structure:

n bit Signal Digital

Scaling Network

D.Vref Output Amplifier

Vout

Binary Latches

b1 b2 b3 bn

Vref Voltage Reference

where b1 is the Most Significant Bit (MSB) and bn the Least Significant Bit (LSB) which, when switched, lead to changes in analogue voltage equivalent to:

MSB: V

b range

2 1 ≅

and where Vrange = Voutmax – Voutmin

LSB: V

b n range

n 2 ≅

and therefore the DAC output will approach that of an ideal analogue output as n→ ∞ .

Note that the range is actually covered by 2 n –1 bit changes in level then the maximum output voltage obtainable from a DAC is generally

( )

− = − n range

n n

range V 2 V

2 1 1 1

2

and therefore falls short by one LSB. This is compensated for in practice by some gain/offset trimming outside of the chip.



4.2.1.1 SWITCHED RESISTOR NETWORKS (CURRENT SCALING NETWORKS)

(a) Binary Weighted Vref

b1

b2

b3

b4

b5

b6

b7

b8

R

2R

4R

8R

16R

2 R 7

6 2 R

5 2 R _

+

Rf

Vo

I

I 1

I2

I3

I4

I5

I6

I7

I8

Here digital bits which are logic high switch the reference voltage Vref onto the summing amplifier, via an appropriately weighted resistance, to provide the required amount of current. Bits which are logic low ground the appropriate input and produce no current. Thus the i'th bit produces an associated output voltage of

i i f

ref b R

R V .

2 . 1

− −

Thus, by setting the required Rf /R ratio and Vref to provide the required output range then (here with Rf = R/2):

+ + + + + − = n n

ref o b b b b b

V V 2

.... 16 8 4 2 4 3 2 1

The major problem with the VLSI construction of the above network is the spread in the required values of the resistance's especially as the number of bits n increases. This causes a doubling of the maximum resistor size for each bit increase in the digital word and therefore, a doubling of the required silicon area. In addition, there are problems regarding the exact value of the resistors (especially the MSB resistor R) if the DAC is to remain 'linear' and expensive trimming may need to be done to ensure accuracy.



One practical solution to alleviate this problem is to use cascaded structures, that is a parallel/serial hybrid arrangement, where overall conversion speed is sacrificed for accuracy/linearity:

Another alternative is to use matched FET transistors to provide the appropriate current pulldown. Where a single FET is used to establish the LSB current and 2 n1 FET’s in parallel to provide the MSB current.

(b) R2R Ladder One resistive solution to alleviate these problems is the R2R Ladder DAC:

i/2

i/4

i/8

i/16

i/32

i/64

i/128

i/256

2R Vref

R

b1

b2

b3

b4

b5

b6

b7

b8

_

+

Rf

Vo

I

I 1

I2

I3

I4

I 5

I6

I7

I8

R

R

R

R

R

R

R

2R

2R

2R

2R

2R

2R

2R

i

Here, a current divider network is used to generate the desired op amp input currents of the required magnitude for each bit. However, only two values of resistor are required and therefore their manufacture is easier, even though there are almost twice as many resistors required. Since the right hand end of the 2R resistors will be connected to ground irrespective of the bit switch position, either directly (bi = 0) or via the opamps virtual earth (bi=1), then:

R V

= i ref

and, as above

+ + + + + − = n

n f ref o

b b b b b R R

V V 2

.... 16 8 4 2

. . 4 3 2 1

1:16 Resistor Divider Network

Bits 14 Generates 'bit'

switched currents of I/2, I/4, I/8 and I/16

I From Inverting OpAmp

Bits 58

(Structure as Bits 14)



One of the problems with the R2R ladder network is that there are up to 2 n1 floating nodes in the arrangement. That is nodes that have a relatively large resistance to ground which are then susceptible to parasitic capacitance. The need to charge/discharge these 'capacitors' reduces the operating speed of the converter.

In order to develop Bipolar versions of the ladder converter then BJT's with appropriate Emitter area's (since Emitter area is proportional to emitter current) must be used to sink the bit controlled currents. That is:

Vref

_

+

Rf

Vo

I

'Base'

Vee

Bit Controlled Switching Network

BJT Switches with Binary Weighted Emitter Area's

'Emitter' R2R Ladder Network

To overcome the need for BJT's with varying 'size' of emitter then the R2R network must be placed between the opamp and the bit switching network. All the BJT emitters can then be connected to Vee with resistors of the same value, and thereby pass the same current.

4.2.1.2 SWITCHED VOLTAGE NETWORKS Here, every possible output voltage level is generated via a reference voltage and a series resistance network. The appropriate level being switched through to the amplifier via a bit controlled switching network. The resulting converter has a regular structure and is therefore ideal for MOS technology. However, the required area of the converter increases rapidly as the number of bits increase. In addition, speed is reduced as parasitic capacitance's arise at the ‘floating’ nodes.

Both of which can be improved by replacing the switching network to 2 n bit level switches fed via an n to 2 n decoder for large bit converters.



4.2.1.3 SWITCHED CAPACITOR NETWORKS (CHARGE SCALING NETWORKS)

Commencing with initially uncharged capacitor's a twophase clock is used to share the total charge which is applied to a capacitor array. For example consider the following arrangement:

During φ1 of the clock all the DAC's capacitors are discharged. Whilst during φ2 the capacitors associated with the relevant bits are:

i) bi = 0 left uncharged (connected to ground ) ii) bi = 1 charged (connected to Vref)

The output voltage, V0, reflects the sum of capacitors that are charged, Cc, with respect to the total capacitance in the network, 2C. That is, for any digital code then the following network exists:

Vref Vo

Cc

2CCc

and therefore Vo Vref

Cc Cc C Cc

Cc C

= = + − ( ) 2 2

The accuracy of the above device is limited by the accuracy of the ratio between the capacitors and the area required is a function of the number of bits. MOS accuracy is around 0.1%, so that 10 bit resolution is possible. However the area required would require a ratio of 1024:1 between the MSB and the LSB, which is clearly undesirable. To overcome this then other scaling approaches are required such as the cascaded approaches shown previously (for current scaling).

φ2

1 φ b2 .

b2 .

φ2

C/2

φ2

1 φ b1 .

b1 .

φ2

C

Vref

+ _ V0

φ2

1 φ bn .

bn .

φ2

C/2 n1 C/2 n1

1 φ



4.2.1.4 CHARGE REDISTRIBUTION DAC Here, the operation of the converter is sequential. That is information is passed down a network using switches to isolate, for an nbit converter then n clock pulses are required before conversion can take place ad is therefore slower in operation than the previous parallel structures.

clk

Vref Vo Vc1 Vc2 C1 C2

bit.clk

bit.clk Reset

Before conversion commences Vc2, and therefore Vo (Vo = Vc2), is set to zero via the Reset signal. Then capacitor C1 is charged to Vref if bit = 1 or discharged if bit = 0. On the clock pulse going high, clk, then the charge is shared between C1 and C2 such that Vc1 = Vc2. The process repeating for the required number of clock pulses.

Note: The converter commences with the LSB decision, which is then repeatedly halved at each clock, until finally the MSB decision is applied.

WORKED EXAMPLE 1 Show the conversion of the signal 0101 (MSB to LSB) using a charge distribution DAC with C1 = C2.



SOLUTION

CLK

0.0

0.25

0.5

0.75

1.0

time

0.0

0.25

0.5

0.75

1.0

time

Vc1/Vref

Vc2/Vref

b4 (1) b3 (0) b2 (1) b1 (0)

Although the converter structure is very simple the control circuitry required to operate the device is not. In addition its accuracy is somewhat limited by parasitic capacitance and clock feed through errors.

4.2.1.5 ALGORITHMIC DAC'S Algorithmic devices consist of unit delays and weighted summers which rely upon the LSB decision to ripple through to the output a stage at a time. For analysis purposes the unit of time delay (clock) is represented in the ztransformation form, where:

One clock Delay

n clock Delays

≡

− ≡

−

−

z z n

1

In addition these devices are bipolar in nature and hence a logic high and low are represented by a 1 and –1 respectively. Consider the structure of a 4bit converter:

Σ Z 1 Σ Z 1 Σ Z 1 Σ Z 1

Vref +Vref

b4 b3 b2 b1

0 Vo C B A 1/2 1/2 1/2

LSB MSB

which can be represented by the equation

1 1 here w . 2

..... . 2 4

. 2 3

. 2 2

. 1 ) ( 1 4

3 3

2 2 1 + ≤ ≤ −

+ + + + + = − −

− − − − i

n n b Vref z bn z b z b z b z b z Vo



Note:

The output of the converter will range between ± − −

2 1 2 1

n

n Vref . for

all possible digital inputs.

The main advantage of the algorithmic converter is that it does not rely upon capacitor/resistor ratio's for its accuracy. However, the amplifiers required to provide the gain of a half do and therefore so does the overall network. The converter is also slow in operation due to its sequential operation.

Note: Note that for an nbit conversion n clocks are required. However clock control is not necessary as the converter will ripple through to the correct conversion value provided sufficient time is left to allow for the propagation delay of the LSB through the circuit.

WORKED EXAMPLE 2 Show the conversion of the digital word 1101 (MSB to LSB) using a bipolar algorithmic DAC.

SOLUTION Following the signals rippling down the network at the applied clocks then

A B C

Position in

Network Vo

1 2 3 4 Clock No.

Vref

Vref Vref

Vref Vref Vref Vref Vref/2 Vref/2 Vref/2 Vref/2 3Vref/4 3Vref/4 3Vref/2 5Vref/4 11Vref/8

Check via

Vref Vref z Vo 8 11

2 1

2 1

2 1

1 ) ( 3 2 =

+ −

+ + =



4.2.2 ANALOGUE TO DIGITAL CONVERTER’S (ADC'S)

An analogue to digital converter, ADC, is used to convert an analogue input signal into an equivalent nbit digital word. In general the all zero's digital word is used to represent the minimum analogue value in the range and the all one's case the maximum. However, due to constructional problems offset, gain and nonlinearity errors may exist in practice.

As was the case for DAC’s, both serial and parallel forms of ADC exist although the majority employ feedback and have the following basic structure:

+ _

Control Logic

DAC

nbit

word Digital

Analogue Input

equivalent

Error

DAC

Vin

Vd Analogue

It is simply the form of the control logic used during the conversion that distinguishes one converter from another.

4.2.2.1 COUNTER ADC The most simple form of where the control logic is simply a clock operated counter which, after a start conversion signal which resets the counter, continues a digital count until the analogue equivalent of the digital word, Vd, bcomes greater than the analogue input, Vin. Where upon the count ceases and the digital word is held for output.

100%

75%

50%

25%

0%

Vd

Time (clock Pulses)

Vin

1 LSB

1 clock



Note that the conversion time is proportional to the size of Vin and that the rate of change of the count for an nbit ADC covering the range Vspan (operating at a clock frequency fc) is:

Vspan fc Volts n 2 . / sec

A simple extension to the Counter ADC is the Tracker ADC where an Up/Down counter is used depending upon whether Vin is bigger than Vd or not respectively. Thus the analogue input is continuously tracked at a maximum rate which is dependant upon the minimum loop operating time (hence the maximum clock frequency), the analogue range and the number of bits as above.

4.2.2.2 SUCCESSIVE APPROXIMATION ADC (SAC) In order to speed conversion times up then the SAC decides upon the correct value for the MSB to the LSB in sequence.

100%

75%

50%

25%

0%

Vd

Time (clock Pulses)

Vin

In order to achieve this, the control logic required becomes more complex than for previous approaches. Generally, a shift register is used to identify each bit (from MSB to LSB) in turn and the decision is then based upon the sign of the error between Vd and Vin. The conversion may be terminated by sending the shift register to the all zero's case whereupon no further changes in output can occur.



+ _ Vin

error

DAC

1 1 1

K J clr K J clr K J clr

clk

start '0'

MSB LSB

& & &

start clk

nbit shift register

Thus, although the maximum clock frequency may be slower due to the longer loop times required to perform the control logic correctly, then approximately n clock pulses are required for an n bit converter irrespective of the range and the value of the input, thus SAC conversion time is n/fc.

WORKED EXAMPLE 3 Show the 4bit SAC conversion (using the above structure) of an analogue input of 70% of its range.

SOLUTION

OUTPUT Operation Shift Register FlipFlop DAC Error

Output Outputs inputs Status

Start 1 0 0 0 0 0 0 0 1 0 0 0 1 (Vd = 50%) clk 1 0 1 0 0 1 0 0 0 1 1 0 0 0 (Vd = 75%) clk 2 0 0 1 0 1 0 0 0 1 0 1 0 1 (Vd = 62.5%) clk 3 0 0 0 1 1 0 1 0 1 0 1 1 1 (Vd = 68.75%) clk 4+ 0 0 0 0 1 0 1 1 1 0 1 1 etc...



4.2.2.3 SERIAL ADC'S (SLOPE CONVERTERS) The basis of the majority of serial converters is the integrator and the most commonly employed device are Slope Converters.

(a) Single Slope ADC’s Single slope devices operate by counting the time (on a clocked counter) taken for an integrated reference voltage to become equal to the analogue input. That is, the higher the value of the input voltage, the longer the integration of the reference voltage takes to reach this value, the higher the digital count reached. Hence to ramp to maximum Vin, thus the integration rate is:

− = =

c

n span in

ref

f

V t V V

RC 1 2 1

max δ δ

However, this means that their accuracy is critically dependant upon matching the RC values of the integrator to the correct ratio to the clock frequency. The nature of the devices operation means that conversion time can take anywhere up to 2 n clocks (not including reset).

(b) Dual Slope ADC’s A common structure for the implementation of a dual slope device is shown below:

Vref

Interface =1

'0'

& &

clk

Counter

up

Q Q MSB

+

_ Vin '0'

'1'

R

0v

+

_

C

Register clk

The major benefit of the dual slope approach is that both the charging and discharging times are dependant upon the integrator gain RC and therefore its accuracy is no longer critical. Consider the following waveforms:



Thus considering the integrator output signal during the conversion then, at its maximum value (Vin * ) then

=

−

c

out ref

c

n

in f ADC V

RC f V

RC 1 1 2 1

which simplifies to

( ) 1 2 −

= n

ref

in out V

V ADC

Hence its output is not dependant upon the integrator’s slope or the clock frequency and is therefore very accurate. However, it does take approximately 2(2 n ) clocks to convert.

Integrator

Comparator

Nand 2

Counter

Q

0

Vin/RC +Vref/RC

+15

15 1

0

Interface & ExOr

Nand 1 1

0

1

0

clk clk counter disabled

+ve edge for storage in register

111..11

000..00

1

0

clocked on counter reset

Conversion time

count stored

Vin *



4.2.2.4 ALGORITHMIC ADC

This particular structure shows a Bipolar device which can convert in the range –Vref to +Vref. The actual sign of Vref which is applied to the summer being dependant upon the sign of the previous comparators output:

Previous bit decision high, sum –Vref Previous bit decision low, sum +Vref

Its accuracy is dependant upon the accuracy of the multipliers (x2) and the characteristics of the summers/comparators.

WORKED EXAMPLE 4 Consider the a 4bit converter with a Vref of 10V converting an analogue input of +4V.

SOLUTION MSB: 4V > 0V therefore MSB = +1 Voltage fed to next stage is 2 * 4V – Vref = –2V Bit 2: –2V < 0V " Bit 2 = –1 Voltage fed to next stage is 2 * –2V + Vref = 6V Bit 3: 6V > 0V " Bit 3 = +1 Voltage fed to next stage is 2 * 6V – Vref = 2V LSB: 2V > 0V " Bit 4 = +1 End of Conversion, Result 1011.

To check the result, use the formulae:

( ) ( ) Volts b b b b Vref Vd 375 . 4 = 4375 . 0 10 = 16 1

8 1

4 1

2 1 10 2 . 2 . 2 . 2 . = 4

4 3

3 2

2 1

1

+ + − = + + + − − − −

The above form of converter is a serial pipeline device which has the disadvantage that it will take n clocks to perform a single conversion (although a conversion is produced at each clock).

MSB

Vin

+ _

2 Z 1

+ _

2 Z 1

+ _

LSB

+Vref

Vref

+1 1 +1 1

Σ Σ



The converter can be operated iteratively, to save silicon area, using the form:

+ _ Digital

Output

Vref

Vb x2 Sample and hold

Vref

Gnd (0V) 1 +

Vin

Va

Note: The above converter is unipolar in operation of span Vref. To directly construct the previous bipolar device then you must compare with respect to 0V and switch +/– Vref.

WORKED EXAMPLE 5 Show how the iterative form of a unipolar algorithmic ADC provides an 8bit conversion of 7V (Vref=10V).

SOLUTION For 8bit conversion then 8 clock pulses are required, where the initial switch position only is at Vin, and

Clock No. 1 2 3 4 5 6 7 8 Va/Vref 0.7 0.4 0.8 0.6 0.2 0.4 0.8 0.6 Vb/Vref 1.4 0.8 1.6 1.2 0.4 0.8 1.6 1.2 Output 1 0 1 1 0 0 1 1

Check:

Vd Volts = = 0.69922 10 1 2

0 4

1 8

1 16

0 32

0 64

1128

1256

+ + + + + + +



4.2.2.5 PARALLEL ADC

Vin Vref

R

R

R

R

R

R

R

R

+ _

+ _

+ _

+ _

+ _

+ _

+ _

Digital Encoding Network

Digital Output

7/8Vref

6/8Vref

5/8Vref

4/8Vref

3/8Vref

2/8Vref

1/8Vref

Shift Register

Parallel operation ensures that this particular ADC is the quickest in terms of conversion. The conversion time being limited only to that of the transmission times of the slowest comparator, Encoding network and shift register. However, accuracy problems do exist due to the large number of identical resistors (of value R) and comparator's required in addition to the large silicon area which is required. Since a doubling in area is required for each single bit increase in the converter alternative parallel/series combinations are used to trade off the silicon area against speed of conversation, e.g

Vin +_ 2 n Vin* Parallel

ADC Converter

n/2 bit

DAC Parallel ADC

Converter

n/2 bit

Shift Register

n bit Digital Output



4.2.3 SAMPLEHOLD NETWORKS The purpose of the samplehold is to maintain the sampled (pulse) signal for a finite time (T – sampling time) to allow any further operations, such as AD conversion, to take place correctly. In its simplest form it consists of a switched capacitor:

Vin Vout

C

Vin

C

+ _

+ _

Control Gate

Vout

The major problem with capacitor storage devices being the conflict of requirements in terms of its charging/discharging times. That is a small value of C is required for quick acquisition (charging from the last input value to the present) of data, but a large value of C is required for long term storage of this value. In the arrangement above the capacitor will charge, when the FET is on, at a rate determined by the output resistance of the amplifier, Ro, and the 'on' resistance of the FET, RDS. If these are small then the rate of charge of the capacitor will be limited by the maximum current, I, which the amplifier can deliver:

dVc dt

I C

=

To improve the acquisition time then some form of current amplifier is used to increase I. The following device utilises an external complementary emitter follower.

Vin + _

Control Gate

C

+ _

Vout

V

+V

It should be noted that the inclusion of this extra 'integrator' in the control loop can cause some stability problems. Capacitors with polycarbonate, polyethylene or polystyrene dielectrics are



recommended as their decay rate is slower and they have less absorption (causing the capacitor to remember its last voltage level after a sudden change).

4.3 SWITCHED CAPACITOR FILTER’S Signal processing also requires the use of active circuits in order to amplify, integrate and filter signals. Previous modules illustrated the requirement to use operational amplifiers with suitable resistor/capacitor arrangements connected about them to achieve this. However, previous lessons have also shown that accuracy and physical size limitations exist whenever these passive components are constructed in silicon. One commonly employed solution to these problems is to replace the resistor's with a switched capacitor (SC) structure. The subsequent arrangement of FET switches and capacitor(s) may be used to restrict current flow with the additional benefit of decreased power consumption.

Consider the two arrangements below:

In order to determine the effective resistance, Reff, of the SC network, note that for network a):

R V V = I out in −

1

In network b) charge is switched across the network during each clock phase providing that the clock frequency, fc, is much sufficiently large that the changes in voltage across the network are small. This is a limiting factor although a high clock frequency is required if operation is to appear continuous anyway. The analysis of such circuits requires the calculation of the average current I1 that flows into the SC network for each clock phase. Thus

( ) ( ) ( ) T T T

T t dq dt

dt t dq

T dt t i

T I

0

1

0

1

0 1 1

1 1

= = = ∫ ∫

I1 R

Vin C Vin

T1 T2

Vout Vout

φ1 φ2

a) Standard Resistor b) Switched Capacitor 'Resistor'

I1



Therefore, for the above circuit, then (assuming that the voltages are approximately constant over the clock period, T:

φ1 (0 to T/2): ( ) [ ] ( ) Vout Vin C = t dq T/2 0 − 1

φ2 (T/2 to T): ( ) [ ] 0 1 = t dq T T/2

Thus ( ) ( ) Vout Vin C f T Vout Vin C = I C 1 − =

− .

and therefore fc . C

= C T R eff

1 =

Let us consider the use of the above SC network to construct a passive RC filter:

From previous lessons, and the above analysis, then:

RC Filter Time Constant (τ )

Accuracy CMOS Implementation

Passive R.C C

C R R δ δ

+ % 20 5 → SC

R C C f C . C

C

R

R

f f

C C

C C δ δ δ

− − % 1 . 0 ≅

And hence the relative accuracy of the capacitors makes the SC variant more accurate, particularly as the clock frequency variation, δfc, is generally very small.

R

Vin Vin Vout Vout

a) Passive RC Filter b) Switched Capacitor RC Filter

CR C

T1

φ1

T2

φ2

C



WORKED EXAMPLE 6 Using the above RC network what would be the capacitor ratio required to construct a passive RC filter of Bandwidth 1KHz and clock frequency 200KHz

SOLUTION Noting that a first order filters 3dB bandwidth is 1/τ then

005 . 0 200 1

10 200 10 1 /

3

3 3 = =

× ×

= = C

dB R

f W B

C C

4.3.1 ALTERNATIVE SC NETWORKS The SC network outlined above is a parallel realisation. Other forms of network commonly used are

4.3.1.1 SERIES SC NETWORK

φ2 φ1

C

Vi Vo

4.3.1.2 SERIESPARALLEL SC NETWORK

C1 C2

Vi Vo

φ1 φ2

Req = 1

C.fc

Req = 1

(C1+C2).fc



4.3.1.3 BILINEAR SC NETWORK

Vi Vo

φ1 φ2

C

φ1 φ2

4.3.1.4 STRAY INSENSITIVE SC NETWORK

Vi

φ2 φ1

Vo C1

φ2 φ1 C A C B

One of the most commonly used networks practically. Here capacitor C1 is charged (from Vi) during φ1 of the clock. and the charge is then passed on to the operational amplifiers inverting input during φ2 of the clock for integration. When the capacitor is not being charged/discharged it is disconnected.

However during φ1 of the clock, CA charges its ‘stray capacitance’ to Vi while CB is discharged. The other φ2 operated FET being effectively grounded via the φ1 operated FET and the virtual earth of the opamp and therefore remains uncharged. During φ2 the charged CA is discharged and the uncharged CB is paralled with the virtual earth of the opamp and therefore remains uncharged. Therefore the stray capacitances CA and CB do not contribute charge to C1 or C2 and hence do not affect the accuracy of the circuits operation.

Req = 1

4C.fc

Req = 1

C.fc



4.3.2 SWITCH CAPACITOR ‘ACTIVE’ FILTER CIRCUITS

SC networks, combined with an operational amplifier, can be used to implement active filter circuits. For example consider the integrator shown below:

Vi

C2

Vo _

+ C1

φ2 φ1

Analysis of the above integrator, replacing the SC network by Reff, shows that

Vo s Vi s sR C s

fc C C eff

( ) ( )

. = = − − 1

2 1 1

2

4.3.2.1 ‘RESISTIVE’ FEEDBACK CIRCUITS The above procedure can be used to establish various filter circuits simply by applying the required feedback around the operational amplifier. For example consider the construction of a noninverting First Order Low Pass Filter (LPF):

Vo

φ2 φ1

Vi

_

+

φ2 φ1

φ2 φ1

C2

Cr C

C1



However, the arrangement shown above is impractical as the feedback path is always disconnected, since φ1 and φ2 are never ‘on’ simultaneously. Therefore a practical realisation of the above is:

Vo

φ2 φ1

Vi

_

+

φ2 φ1

C2

Cr C

φ1

C1

Which is a First order Noninverting amplifier of steady state gain, Avo, where

Avo ff ff ff

C C C

= = Re Re Re 1 2

1

1 2 2

+ +

The steady state gain is independent of the clock frequency because both the SC networks in the feedback path operate at the same frequency.

And whose time constant, τ, is

τ = = = C q C Cr fc

T C Cr r .Re

. .

Using the above SC networks, any type of filter may be constructed using the design techniques proposed by Butterworth, Chebyshev, etc.



4.3.2.2 FREQUENCY RESPONSE The ability of the switched capacitor networks to approximate their continuous time counterparts is best shown by analyzing their respective frequency responses. Let us once again consider the passive first order low pass filter (LPF) and its parallel switched capacitor equivalent:

Using Laplace transforms, the transfer function of the continuous circuit can be shown to be

( ) 1 /

1 1

1 1

1

0 + =

+ =

+ =

ω τ s s sRC s H

which, by replacing s by jω provides the frequency response whose magnitude and phase are described via

( ) ( ) 1 /

1 2

0 + =

ω ω ω j H and

( )

− = ∠ −

0

1 tan ω ω ω j H

However, analysis of the switched capacitor equivalent requires the use of discrete time theory using difference equations and z transforms. Consider the switched capacitor circuit at the end of the (n–1)th clock period, then

Prior to φ1:

During φ1:

R

Vin Vin Vout Vout CR C

φ1 φ2

C

Vi (n1) CR Vo(n1) C Vo(n1)

Vi (n1) CR Vo(n1) C Vi(n1)



Start of φ2:

Therefore the next output voltage, Vo(n), of the above circuit can be found after the charge in the above circuit has been shared, that is

( ) ( ) ) 1 ( ) ( ) ( ) 1 ( − − = − − = n V n V C n V n V C I o o o i R

) 1 ( ) 1 ( ) ( −

+

+ −

+

= n V C C

C n V C C

C n V o R

i R

R o

To find the ztransfer function we simply replace V(n–m) by V(z).z m and equate terms, hence

) ( 1 ) ( 1 1 z V z C C

C z C C

C z V i R

R

R o

− −

+

=

+

−

therefore (α = C/CR)

( ) ( ) ( )

+ −

+ =

+ −

+ =

+

−

+

= = + −

−

−

−

α α α α α α 1 / 1

1 1

1 / 1 1 1

1 ) ( ) (

1 1

1

1

1

z z z

z C C

C

z C C

C

z V z V z H

R

R

R

i

o

whose frequency response can be found by replacing z +1 by e jωt where from eulers theory

e jωt ≅ cos(ωt)+jsin(ωt) hence

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t j t t j t e H t j

ω α α ω α α α ω ω α ω

sin 1 cos 1 1

1 / sin cos 1

1 1

+ + − + =

+ − +

+ =

whose magnitude and phase are described via

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t t t t

e H t j

ω α α ω α α ω α α ω α

ω

cos 1 1 2 1 1

sin 1 cos 1 2 cos 1

1 2 2 2 2 2 − + +

= + + − + − +

=

and

( ) ( ) ( ) ( ) ( )

( ) ( ) ( )

+ −

− =

− +

+ − = ∠ − −

α α ω ω

α ω α ω α ω

1 / cos sin tan

cos 1 sin 1 tan 1 1

t t

t t e H t j

Vi (n1) CR Vo(n1) C Vi(n1)

Vo(n) CR C

Vi(n1) + _ Vo(n1)

+ _



The following diagram shows the comparison between the desired frequency response of the normalized (ωo=1) continuous time LPF and its switch capacitor alternative for various ωc/ωo ratios, noting the design equations:

o

c ω ω

β = therefore o c

T βω

π ω

π 2 2 = =

and

R eff C

T R = therefore T T

CR C C

o

eff

R ω α 1

= = =

hence

demonstrating clearly the effect of clock frequency, ωc, on the overall response of the filter. The faster the clock the smaller the charge transferred, the closer the switched capacitor becomes to its continuous counterpart.

10 1 10 0

10 1

10 2

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

ω/ωc

Magnitude

Normalised (ω1 = 1) 1 st order LPF

ωc/ωo = 10

ωc/ωo = 100



WORKED EXAMPLE 7 Show that the discrete time transfer function is the same when a first order LPF is constructed using series and parallel SC networks.

SOLUTION Consider the series 1 st order LPF Network:

φ2 φ1

CR Vi Vo C

Then, from the end of the (n–1)th clock period:

During φ1:

Start of φ2:

Therefore the next output voltage, Vo(n), of the above circuit can be found after the charge in the above circuit has been shared, that is

Which is the same as in the parallel SC case above, hence

) 1 ( ) 1 ( ) ( −

+

+ −

+

= n V C C

C n V C C

C n V o R

i R

R o

Because the difference equations and effective resistance for both SC networks are the same, T/CR, then so must their transfer functions and frequency response characteristics.

Vi (n1)

Vi (n1) CR

Vo(n1) C

discharged

CR

Vo(n1) C 0

Vo(n)

CR C Vi(n1)

Vo(n1) + _



SUMMARY This lesson has introduced the use of VLSI design for analogue circuit applications. The majority of analogue applications fall into the general area of signal processing and therefore the material covered has demonstrated the use of digital technology to construct circuits capable of conditioning analogue signals and/or converting between the analogue/digital domains.

In terms of circuit construction, the basic building block of analogue circuits is the operational amplifier which itself can be manufactured from bipolar or CMOS technology. In this lesson, only a basic introduction to the design of high gain amplifier circuits and the compensation subcircuits required to achieve ‘ideal’ characteristics. Interested parties are encouraged to read Allen & Holberg (see the lessons references) which cover the topic in much greater detail.

Finally, the use of switched capacitor networks to minimize silicon area and improve accuracy has been investigated. Basically, switched storage structures have been used to control current flow, via charge transfer, in order to achieve the desired behaviour, provided that the switching frequency is considerably higher (>10) than the bandwidth required of the circuit in question.





SELFASSESSMENT QUESTIONS

QUESTION 1 Show that the output voltage of a switched capacitor Network DAC of section 4.2.1.3 is given by

Vref C Cc Vo

2

=

and sketch the characteristics of a 3bit converter.

QUESTION 2 What modifications are required to convert the bipolar algorithmic DAC of section 4.2.1.5 in order to achieve unipolar operation of 0Vref volts?

QUESTION 3 The following circuit shows a single slope ADC converter (ignoring reset and based around the dual slope device of section 4.2.2.3). Sketch its conversion operation and evaluate an expression for its output.

QUESTION 4 How would you construct a unipolar version (span Vref) of the algorithmic ADC of section 4.2.2.4? Demonstrate your solution by showing 8bit conversion of 6V assuming the reference voltage is 10V.

QUESTION 5 Evaluate the effective resistance of the Bilinear SC network of section 4.3.1.3.

&

clk

Counter up

ADCout

+ _

Vin

R

0v

+ _

C

Vref





ANSWERS TO SELFASSESSMENT QUESTIONS

ANSWER 1 From section 4.2.1.3 the network effectively looks like a capacitive potential divider with C1 = CC and C2 = 2C – CC. Thus as the impedance of a capacitor is 1/jωC then

+

+

+

+

+ 2 1

1

2 1

2 1

2

2 1

2

2 1

2

2 1

2 0

1

1 1

1

1 1

1

C C C =

C C C C

C =

C C

C =

jωω jωω

jωω = Z Z

Z = V V

ref

Therefore

− + C C

= C C C

C =

V V C

C C

C

ref 2 2 0

For a nbit converter then:

00...00: CC = 0, and V0 = 0 00…01: CC = C/2 n1 , and V0 = Vref/2 n1

.

. 11…11: CC = 2C – C/2 n1 , and V0 = (1 – 1/2 n )Vref

Hence for a 3bit converter the following characteristics will arise:

000 001 010 011 100 101 110 111

8Bit Digital Code

Vref

7Vref/8

3Vref/4

5Vref/8

Vref/2

3Vref/8

Vref/4

Vref/8

0

V0

Ideal



ANSWER 2 The only way to change the output range of an algorithmic DAC is to switch from different reference levels. For a unipolar output of 0 to Vref volts then, as the output is approximately twice the common input (at the limits of converter operation):

i) For 0V out when all bits are low they must connect to 0V ii) For Vref out when all bits are high they must connect to Vref/2 volts, hence:

Which can be represented by the equation

1 0 here w 2

. 2

..... . 2 4 .

2 3 .

2 2 . 1 ) ( 1

4 3

3 2

2 1

1 + ≤ ≤

+ + + + + = − −

− − − − i

ref n n b

V z bn z b z b z b z b z Vo

Note that the output of the converter will actually range between

0 and ref n V

−

2 1

1

That is it will fall one LSB short of Vref. This would be acceptable for large bit DAC’s but if precision is required then Vref/2 must be trimmed to

2 1 2 2 ref n

n V

−

1/2 Σ Z 1 Σ Z 1

Σ Z 1 Σ

Z 1

0

Vref/2

b4 b3 b2 b1

0 V0 1/2

LSB MSB

1/2



ANSWER 3 From the circuit provided then the following signals will arise during conversion:

Inspection of the integrator output shows

=

=

c

out

in ref

f ADC V

V RC t

V 1 δ δ

which simplifies to

( ) c ref

in out f RC

V V

ADC

=

Hence its output is dependant upon the integrator’s slope and the clock frequency.

Integrator

Comparator

And

Counter

0

+Vref/RC

1

0 1

0

clk counter disabled

111..11

000..00 Conversion time

count stored

Vin



ANSWER 4 Note the first comparison, and all there after, requires a MSB value to be set if the input is greater than half the unipolar range, that is Vref/2. This compares with the unipolar structure of the iterative form, shown in section 4.2.2.4, as here the comparator is before the 2multiplier.

Hence

MSB: 6V > 5V therefore MSB = 1 Voltage fed to next stage is 2 * 6V – 10 = 2V Bit 2: 2V < 5V " Bit 2 = 0 Voltage fed to next stage is 2 * 2V + 0 = 4V Bit 3: 4V < 5V " Bit 3 = 0 Voltage fed to next stage is 2 * 4V + 0 = 8V Bit 4: 8V > 5V " Bit 4 = 1 Voltage fed to next stage is 2 * 8V – 10 = 6V Bit 5: 6V > 5V " Bit 5 = 1 Voltage fed to next stage is 2 * 6V – 10 = 2V Bit 6: 2V < 5V " Bit 6 = 0 Voltage fed to next stage is 2 * 2V + 0 = 4V Bit 7: 4V < 5V " Bit 7 = 0 Voltage fed to next stage is 2 * 4V + 0 = 8V LSB: 8V > 5V " LSB = 1 End of Conversion, Result 10011001.

To check the result, use the formulae:

( ) 8 8

7 7

6 6

5 5

4 4

3 3

2 2

1 1 2 . 2 . 2 . 2 . 2 . 2 . 2 . 2 . = − − − − − − − − + + + + + + + b b b b b b b b Vref Vd

therefore

( ) Volts Vd 977 . 5 = 5977 . 0 10 = 256 1

128 0

64 0

32 1

16 1

8 0

4 0

2 1

10 =

+ + + + + + +

MSB

Vin

+ _

2 Z 1

+ _

2 Z 1

+ _

LSB

0

Vref

+1 1 +1 1

Σ Σ

Vref/2 Vref/2 Vref/2



ANSWER 5 Therefore, for the above circuit, then (assuming that the voltages are approximately constant over the clock period, T:

End of φ1 (T/2): ( ) [ ] ( ) out in T/2 0 V V C = t dq − 1

End of φ2 (T): ( ) [ ] ( ) in out T T/2 V V C = t dq − 1

Thus the charge change from phase to phase is

( ) [ ] ( ) ( ) ( ) ( ) out in in out out in V V C V V C V V C = t dq 2

1 − = − − − 2 1

φ φ

Since a period covers two such changes then

( ) ( ) out in C out in

1 V V C f T V V C

= I − = −

. 4 4

and therefore

fc . C =

C T R eff 4

1 4

=



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