ENG241 Digital Design Week #10 Sequencing and Control

ENG241 Digital Design

Week #10 Sequencing and Control

Fall 2014 ENG241/Digital Design 2

Week #10 Topics

The Control Unit Algorithmic State Machines ASM Elements Hardwired Control

I. One Flip-Flop Per StateII. Sequence Register and Decoder

VHDL Representation


Resources

Chapter #8, Mano Sections 8.1 The Control Unit 8.2 Algorithmic State Machines 8.3 ASM Examples 8.4 Hardwired Control


Parts of CPUs

Datapath The registers and logic to perform

operations on them Control unit

Generates signals to control datapath

Control Data Path


The Control Unit

The binary information stored in a digital computer can be classified as either data or control information.

1. Data is manipulated in a data-path To perform arithmetic, logic, shifting, and other

data-processing tasks. These operations are implemented with ALUs,

registers, multiplexers, and busses.2. The control unit

Provides signals that activate the various micro-operations in the data-path to perform the specified data processing tasks.

The control unit also determines the sequence in which the various actions are performed (i.e. when they are to be performed)


Control Unit Types

Two distinct classes: Programmable Non-programmable.

A programmable control unit has: An external ROM or RAM array for storing instructions and

control information A program counter (PC) or other sequencing register with

contents that points to the next instruction to be executed Decision logic for determining the sequence of operations

and logic to interpret the instructions A non-programmable control unit (hardwired Control)

does not fetch instructions from a memory but just determines the operations to be performed and the sequence of those operations based only on inputs and status bits.

In ENGG2410 we are mainly concerned with the design of a non-programmablenon-programmable control unit.


Algorithmic State Machines

The function of a state machine (or sequential circuit) can be represented by a state table or a state diagram.

What is wrong with state diagrams? Solution? A flowchart is a way of showing actions and control

flow in an algorithm. An Algorithmic State Machine (ASM) is simply a

flowchart-like way to specify state diagrams for sequential logic and, optionally, actions performed in a datapath.

While flowcharts typically do not specify “time”, an ASM explicitly specifies a sequence of actions and their timing relationships.


ASM Primitives

1. State Box (a rectangle)

2. Scalar Decision Box (a diamond)

3. Vector Decision Box (a hexagon)

4. Conditional Output Box (oval).

The State Box is a rectangle, marked with the symbolic state name, containing register transfers and output signals activated when the control unit is in the state.

The Scalar Decision Box is a diamond that describes the effects of a specific input condition on the control. It has one input path and two exit paths, one for TRUE (1) and one for FALSE (0).

The Vector Decision Box is a hexagon that describes the effects of a specific n-bit (n > 2) vector of input conditions on the control. It has one input path and up to 2n exit paths, each corresponding to a binary vector value.

The Conditional Output Box is an oval with entry from a decision block and outputs activated for the decision conditions being satisfied.


A rectangle with: The symbolic

name for the state marked outside the upper left top

Containing register transfer operations and outputs activated within or while leaving the state

An optional state code, if assigned, outside the upper right top

(Symbolic Name)IDLE

(Register transfers or outputs)

R ← 0RUN

(Optional state code)

0000

State Box


A diamond with: One input path

(entry point). One input condition,

placed in the center of the box, that is tested.

A TRUE exit path taken if the condition is true (logic 1).

A FALSE exit path taken if the condition is false (logic 0).

(Input)START

(True Condition)(False Condition)

0 1

Scalar Decision Box


Vector Decision Box

A hexagon with: One Input Path (entry

point). A vector of input

conditions, placed in thecenter of the box, that istested.

Up to 2n output paths. The path taken has a binary vector value that matches the vector input condition

(Vector of InputConditions)

(Binary Vector Values)

00

01


10

Z, Q0


Conditional Output Box An oval with:

One input path from a decision box or decision boxes.

One output path Register transfers or outputs

that occur only if the conditional path to the box is taken.

Transfers and outputs in a state box are Moore type - dependent only on state

Transfers and outputs in a conditional output box are Mealy type - dependent on both state and inputs

(Register transfers or outputs)

R ← 0RUN

From Decision Box(es)


By connecting boxes together, we begin to see the power of expression.

What are the:I. States?II. Inputs?III. Outputs?IV. Conditional Outputs?V. Transfers?VI. Conditional Transfers?

Connecting Boxes Together

IDLE

R← 0

START0 1

PC ← 0

AVAIL

INIT


ASM Blocks

One state box alongwith all decision andconditional outputboxes connectedto it is called an ASMBlock.

The ASM Blockincludes all items on thepath from the currentstate to the same or otherstates.

IDLE

AVAIL

START

R← R + 1 R ← 0

Q00 1

MUL0 MUL1

ASM BLOCK

Entry

Exit

Exit Exit


From State Diagram to ASM

A B C

S = 0

S = 1

Z = 0

Z = 1


From State Diagram to ASM

A 00

S0 1

B

C

01

10

Z0 1

A B C

S = 0

S = 1

Z = 0

Z = 1


Find the ASM chart corresponding to the following description

1. There are two states A, B2. If in state A and input X is `0’ then the next state is A3. If in state A and input X is `1’ then the next state is B4. If in state B and input Y is `1’ then the next state is B5. If in state B and input Y is `0’ then the next state is A6. Output Z is equal to `1’ while the circuit is in state B

Solution:1. Total States 22. Two Inputs X, Y3. One Output Z

Example (1)


ASM for Example (1)

0

A

B

X

Z = 1

Y1

1

0


Designing the Control Unit:I. One Flip-flop per State

A flip-flop is assigned to each of the states and at any time, only one of the flip flops contains a 1, with all the rest containing 0.

II. Sequence Register and Decoder Uses a sequence register for the control states and a decoder to provide an output signal corresponding to each of the states.

Hardwired Control


As the name implies the method uses one flip-flop per state and a simple set of transformation rules to implement the circuit.

The design starts with the ASM chart, Then all you do is replace:

1. A State Box with a D flip-flop,2. A Scalar Decision Box with a demultiplexer

with 2 outputs,3. A Vector Decision Box with a (partial)

demultiplexer 4. Any Junction with an OR gate, and5. Any Conditional Output with an AND gate (for

a Mealy Machine!!)

I. One Flip-Flop per State


State Box Transformation Rules

Each state box transforms to a D Flip-Flop Entry point is connected to D FF input. Exit point is connected to the D FF `Q’ output.

STATE

Entry

Exit

D Q

Entry

Exit

STATE


Scalar Decision Box Transformation Rules

Each Decision box transforms to a Demultiplexer Entry points are "Enable" inputs. The Condition is the "Select" input. Decoded Outputs are the Exit points.

X0 1

Entry

Exit 0 Exit 1

XEntry

Exit 0 Exit 1


Vector Decision Box Transformation Rules

Each vector decision box transforms to a Demultiplexer Entry point is Enable inputs. The Conditions are the Select inputs. Demultiplexer Outputs are the Exit points.

(Vector of InputConditions)


00

01


10

X1, X0

X1

Entry Exit 0Exit 1

X0

DEMUX

EN

A1A0

D0

D2

D1

D3

Exit2

Exit 3


Junction Transformation Rules

Entry 1

Exit

Entry 2 Entry 1

Exit

Entry 2

Where two or more entry points join, connect the entry variables to an OR gate

The Exit is the output of the OR gate


Conditional Output Box Rules

X 1

Entry

Exit 1

OUTPUT

X

Entry

Exit 1

OUTPUT

Entry point is Enable input. The Condition is the "Select" input. Demultiplexer Outputs are the Exit points. The Control OUTPUT is the same signal as the exit value.


A 00

S0 1

B

C

01

10

Z0 1

Implement using 1 Flip Flop Per State

Note: One FF is assigned to each of the states, and at any time, only one of the FFs contains a 1, with all the rest containing 0.

When a 1 is in the FF assigned to a particular state, the sequential circuit is in that same state.

The single 1 propagates from one FF to another under the control of decision logic


One Flip Flop Per State

D

C

OR

DeMux

D

D

C

C

S

OR

DeMuxZ

A 00

S0 1

B

C

01

10

Z0 1


This method uses a decoder and a set of flip flops (or a register) to implement the circuit.I. The design starts with the ASM chart, II. According to the number of states 2n, we

will use n flip flops (log2 # state)

III. Construct State Table (directly from ASM)IV. Use an n-to-2n decoder has 2n outputs

Sequence Register and Decoder


A 00

S0 1

B

C

01

10

Z0 1

Implement Sequence Register/Decoder

How many Flip Flops?

Decoder Size?



D

D

C

C

M0

M1

0

1

2

3

Decoder

A

B

C

X

Sequence Register


State Table: Construction

Present State

Name M1 M0

A 0 0

0 0

B 0 1

C 1 0

1 0

X 1 1

Inputs

S Z

0 x

1 x

x x

x 0

x 1

x x

Next State

M1 M0

0 0

0 1

1 0

1 0

0 0

x x

Decoder Outputs

A B C1 0 0

1 0 0

0 1 0

0 0 1

0 0 1

x x x


Sequence Register and Decoder

Present State Inputs Next State Decoder Outputs

Name M1 M0 S Z M1 M0 A B C

A 0 0 0 x 0 0 1 0 0

0 0 1 x 0 1 1 0 0

B 0 1 x x 1 0 0 1 0

C 1 0 x 0 1 0 0 0 1

1 0 x 1 0 0 0 0 1

X 1 1 x x x x x x x



DM0 = A.S

DM1 = B + C.Z’

34


D

D

C

C

A0

A1

0

1

2

3

Decoder

S

DM1 = B + C.Z’

Z’

A

B

CDM0 = A.S


At first glance, it may seem that the one FF per state method would increase the cost of the system, since more flip-flops are used.

But the method offers some cost advantages that may not be apparent:

One advantage is the simplicity with which the logic can be designed – merely by inspection of the ASM chart or state diagram.

No state or excitation tables are needed if D flip-flops are employed.

This offers a savings in design effort, an increase in logic simplicity.

One FF per State vs. Sequence Register and Decoder


VHDL Code

Process that willdepend on clock

event to reset systemto Idle State and

implement state_registerbased on CLK

Process that will act as asequencer that will dictatethe state you are in given

the input

Process that will controlyour data path

(If you have a data path!)

Similar to Sequencer

P1

P3

P2


Implement Using VHDL

X

Y

Z

IDLE 00

G0 1

LOAD 01

10

S0 1

ADD

What are the Inputs?

Remember that this

is a state machine

and we have to

start somewhere at

power up!


VHDL Code-- VHDL Code entity declaration

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity sequential_machine is

port (CLK, RESET, G, S : in std_logic;

X,Y, Z : out std_logic);

end sequential_machine;


VHDL Code: Architecture

-- VHDL Code Architecturearchitecture behavior of sequential_machine is type state_type is (IDLE, LOAD, ADD); signal state, next_state : state_type;begin

end behavior;

State_register: process (CLK) .....Next_state_func: process (G,S,state) ......Datapath_func: process (CLK) ......


VHDL Code: State-Register Process

-- VHDL Code State Register Process

State_Register: process (CLK, RESET)

begin

if (RESET = ‘1’) then

state <= IDLE; elsif (CLK'event and (CLK = '1')) then state <= next_state; end if;end process;


VHDL Code: Next-State Process-- VHDL Code for next_state_func

next_state_func: process (G,S,state)

begin case state is when IDLE => if G = ‘1’ then next_state <= LOAD; else next_state <= IDLE; end if; when LOAD => next_state <= ADD; when ADD => if S = ‘1’ then next_state <= IDLE; else next_state <= ADD; end if; end caseend process;

X

Y

Z

IDLE 00

G0 1

LOAD 01

10

S0 1

ADD


VHDL Code: datapath Process-- VHDL Code for datapath_func

Output_func: process (state)

begin

case state is when IDLE => X <= 1; when LOAD => Y <= 1; when ADD => Z < =1 end case end process;

X

Y

Z

IDLE 00

G0 1

LOAD 01

10

S0 1

ADD

Fall 2014 43

Multiplier Example: ASM ChartMultiplier Example: ASM Chart

0 1G

IDLE

MUL0

0 1Z

MUL1

0 1

0C ← 0, A ←P ← n – 1

A ← A + B,C ← Cout

P ← P – 1C ← 0, C || A || Q ← sr C || A || Q,

Q0

Complicated!!


Multiplier Example: Control Unit

In implementing a complex control unit, designers usually have to deal with (separate) two distinct aspects The generation of the control signalscontrol signals SequencingSequencing of the operations (what will happen next)

We can separate the two aspects by dividing the original ASM specification into two parts: A table that defines the control signals table that defines the control signals in terms of states

and inputs A simplified ASM chart simplified ASM chart that represents only transitions

from state to state

Fall 2014 45

Multiplier Example: ASM Chart

0 1G

IDLE

MUL0

0 1Z

MUL1

0 1

0C ← 0, A ←P ← n – 1


P ← P – 1C ← 0, C || A || Q ← sr C || A || Q,

Q0

Fall 2014 46

Example - Sequencing Part of ASM

0 1

IDLE

MUL0

0 1

01

MUL1 10

00

G

Z

47

Multiplier Example: Flip-flop per State Design Logic Diagram

D

C

IDLE

D

C

MUL0

D

C

MUL1

Initialize

Clear _C

Load

Shift_dec

Clock

Z

Q0

4

1

G

2

5

45

1

1 5

DEMUXD0

D1A0

EN

2

DEMUXD0

D1A0

EN

START

0 1

IDLE

MUL0

0 1

01

MUL1 10

00

G

Z


Sequencer and Decoder Design

IDLEMUL0MUL1

Initialize

Clear_C

Shift_dec

M0

Load

M1

G

Z

Q0

DECODERA0

A1

0

321

D

C

D

C

START


m Microoperations from Ta Binary Co oSummary

Control units are an essential part of any CPU. Control units can either be programmable or

non-programmable. Non-programmable CU:

One FF per state Sequence Register and Decoder.

Obtaining the ASM is the key to designing any control unit.

Use the process statement to implement any sequential circuit, state diagrams and algorithmic state machines.



Find an ASM chart for a traffic light controller that works as follows:

I. A timing signal T is the input to the controllerII. T defines the yellow light as well as the

changes of RED and GREEN lightsIII. While T = 0, the green light is on for one

signal, the red light is on for other signalIV. While T = 1, the yellow light is on for the signal

that was previously green and the signal that was previously red remains red

V. When T becomes 0, the signal that was previously yellow becomes RED and the signal that was previously RED becomes GREEN

VI. This pattern continues

Example (Traffic Light Controller)


While T = 0, the green light is on for one signal, the red light is on for other signal

While T = 1, the yellow light is on for the signal that was previously green and the signal that was previously red remains red

When T becomes 0, the signal that was previously yellow becomes RED and the signal that was previously RED becomes GREEN

This pattern continues

Example (Traffic Light Controller)


ASM for Traffic Light Controller

0 1

GREENRED

YELLOWRED

REDGREEN

REDYELLOW

T T T T0 0 01 11

Implement using One Flip Flop Per State

Implement using Sequence Register and Decoder


m Microoperations from Ta Binary Co oII Micro-Programmed Control

A control unit with its binary control values stored as words in memory is called a micro-programmed control.

Each word in the control memory contains a microinstruction that specifies one or more micro-operations for the system.

A sequence of microinstructions constitutes a micro-program.

A micro-program is often fixed at the time of the system design and so is usually stored in ROM.

A micro-program can also be written in RAM but has to be loaded initially at system startup.


m Microoperations from Ta Binary Co oA Micro-Programmed Control Unit Organization

1. Control Address Register (CAR) specifies the address of the microinstruction.

2. The control data register (CDR) may hold the instruction currently being executed.

3. The next address generator produces the next address.


Multiplier Example

Example: (101 x 011) Base 2

Note that the partial productsummation for n digits, base 2 numbers requires adding up to n digits (with carries) in a column.

Note also n x m digit multiplygenerates up to an m + n

digit result (same as decimal).

1 0 1

x 0 1 1

1 0 1

1 0 1

0 0 0

0 0 1 1 1 1

Partial products are: 101 x 0, 101 x 1, and 101 x 1


Example (1 0 1) x (0 1 1) Again Reorganizing example to follow hardware

algorithm:

1 0 1

x 0 1 1

0 0 0 0

+ 1 0 1

0 1 0 1

0 0 1 0 1

+ 1 0 1

0 1 1 1 1

0 0 1 1 1 1

0 0 0 1 1 1 1

Clear C || A

Multipler0 = 1 => Add B

Addition

Shift Right (Zero-fill C)

Multipler1 = 1 => Add B

Addition

Shift Right

Multipler2 = 0 => No Add,

Shift Right


Hardware ? (Data Path + Control)

1. A Parallel Adder2. Switches to enter Multiplier/Multiplicand3. Shift Register Q (Multiplier)4. Register B (Multiplicand)5. Counter (to know when to stop)6. Zero detection circuit (input to control)7. Shift Register A (scratch pad)8. Flip Flop to store Carry of Adder9. Detect when Q0 is zero or one (input to control)10. A Go signal to start (input to control)11. Control Output? Load, Load_B, Clear_C, Initialize_A, Shift


Multiplier Example: Block Diagram

Cout

n

n

n21

Counter P

Zero detect

Controlunit

G (Go)

log2n

Qo

Z

Parallel adder

Multiplicand

Register B

Shift register A0 C Shift register Q

Multiplier

Product

OUT

IN

Control signals

n

n n

4


Multiplexer Example: Operation

1. The multiplicand (top operand) is loaded into register B (X)2. The multiplier (bottom operand) is loaded into register Q (X)3. Register C|| A is initialized to 0 when G becomes 1.4. The partial products are formed in register C||A||Q.5. Each multiplier bit, beginning with the LSB, is processed (if bit

is 1, use adder to add B to partial product; if bit is 0, do nothing)

6. C||A||Q is shifted right using the shift register Partial product bits fill vacant locations in Q as multiplier

is shifted out If overflow during addition, the outgoing carry is

recovered from C during the right shift7. Steps 5 and 6 are repeated until Counter P = 0 as detected by

Zero detect.• Counter P is initialized in step 4 to n – 1, n = number of

bits in multiplier


Multiplier Example: ASM Chart (continued)

Three states are employed using a Mealy output model:

IDLE - state in which: input G is used as the condition for

starting the multiplication, and C, A, and P are initialized

MUL0 - state in which conditional addition is performed based on the value of Q0.

MUL1 - state in which: right shift is performed to capture the

partial product and position the next bit of the multiplier in Q0

the terminal count of 0 for down counter P is used to sense completion or continuation of the multiply.



0 1G

IDLE

MUL0

0 1Z

MUL1

0 1

0C ← 0, A ←P ← n – 1


P ← P – 1C ← 0, C || A || Q ← sr C || A || Q,

Q0


Multiplier Example: Control Unit

In implementing a complex control unit, designers usually have to deal (separate) two distinct aspects The generation of the control signalsSequencing of the operations (what will happen next)

We can separate the two aspects by dividing the original ASM specification into two parts:A table that defines the control signals in terms of

states and inputsA simplified ASM chart that represents only transitions

from state to state


Multiplier Example: Control Signal Table

Block DiagramModule

Register A :

Register B:

Flip-Flop C

Register Q

Counter P:



Block DiagramModule Microope ration

Register A : A ← 0A ← A + BC || A || Q sr C || A || Q

Register B: B ← IN

Flip-Flop C: C ← 0 C ← Cout

Register Q : Q ← INC || A || Q ← sr C || A || Q

Counter P: P ← n – 1P ← P – 1

←




ControlSign al Name

Register A : A ← 0 InitializeA ← A + BC || A || Q sr C || A || Q Shift_dec

Register B: B ← IN Load_B

Flip-Flop C: C ← 0 Clear_CC ← Cout Load

Register Q : Q ← IN Load_QC || A || Q ← sr C || A || Q Shift_dec

Counter P: P ← n – 1 InitializeP ← P – 1 Shift_dec

←Load

Fall 2014 67


0 1G

IDLE

MUL0

0 1Z

MUL1

0 1

0C ← 0, A ←P ← n – 1


P ← P – 1C ← 0, C || A || Q ← sr C || A || Q,

Q0

ENG241/Digital Design




ControlSign al Name

ControlExpression

Register A : A ← 0 Initialize GA ← A + B Load MUL0 · Q0

C || A || Q sr C || A || Q Shift_dec MUL1

Register B: B ← IN Load_B LOADB

Flip-Flop C: C ← 0 Clear_C IDLE · G + MUL1C ← Cout Load —

Register Q : Q ← IN Load_Q LOADQC || A || Q ← sr C || A || Q Shift_dec —

Counter P: P ← n – 1 Initialize —P ← P – 1 Shift_dec —

IDLE ·

←


Signals are defined on a register basis LOADQ and LOADB are external signals controlled

from the system using the multiplier and will not be considered a part of this design

Note that many of the control signals are “reused” for different registers.

These control signals are the “outputs” of the control unit

With the outputs represented by the table, they can be removed from the ASM giving an ASM that represents only the sequencing (next state) behavior

Multiplier Example: Control Table (continued)

Fall 2014 70

Example - Sequencing Part of ASM

0 1

IDLE

MUL0

0 1

01

MUL1 10

00

G

ZENG241/Digital Design


Multiplier Example: Flip-flop per State Design Logic Diagram

D

C

IDLE

D

C

MUL0

D

C

MUL1

Initialize

Clear _C

Load

Shift_dec

Clock

Z

Q0

4

1

G

2

5

45

1

1 5

DEMUXD0

D1A0

EN

2

DEMUXD0

D1A0

EN

START


Example: Cont .. Sequencer and Decoder Design

First, define: States: IDLE, MUL0, MUL1 Input Signals: G, Z, Q0 (Q0 affects outputs, not next state) Output Signals: Initialize, LOAD, Shift_Dec, Clear_C State Transition Diagram Output Function.

Second, find State Assignments (two bits required) We will use two state bits to encode

the three state IDLE, MUL0, and MUL1.

State M1 M0

IDLE 0 0

MUL0 0 1

MUL1 1 0

Unused 1 1


Assuming that state variables M1 and M0 are decoded into states, the next state part of the state table is:

Current State Input G Z

Next State M1 M0

IDLE 0 0 0 0 IDLE 0 1 0 0 IDLE 1 0 0 1 IDLE 1 1 0 1 MUL0 0 0 1 0 MUL0 0 1 1 0 MUL0 1 0 1 0 MUL0 1 1 1 0

Current State M1 M0

Input G Z

Next State M1 M0

MUL1 0 0 0 1 MUL1 0 1 0 0 MUL1 1 0 0 1 MUL1 1 1 0 0 Unused 0 0 d d Unused 0 1 d d Unused 1 0 d d Unused 1 1 d d






Finding the equations for M1 and M0 is easier due to the decoded states: M1 = MUL0 M0 = IDLE · G + MUL1 · Z’

Note that since there are five variables, a K-map is harder to use, so we have directly written reduced equations.

The output equations using the decoded states: Initialize = IDLE · G Load = MUL0 · Q0 Clear_C = IDLE · G + MUL1 Shift_dec = MUL1


Sequencer and Decoder Design

IDLEMUL0MUL1

Initialize

Clear_C

Shift_dec

M0

Load

M1

G

Z

Q0

DECODERA0

A1

0

321

D

C

D

C

START


VHDL for Binary Multiplier - 1-- Binary Multiplier with n = 4library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity binary_multiplier is port(CLK, RESET, G, LOADB, LOADQ: in std_logic; MULT_IN: in std_logic_vector(3 downto 0); MULT_OUT: out std_logic_vector(7 downto 0));end binary_multiplier;


VHDL for Binary Multiplier - 1-- Binary Multiplier with n = 4architecture sequential of binary_multiplier is type state_type is (IDLE, MUL0, MUL1); signal state, next_state: state_type; signal P: std_logic_vector(1 downto 0); signal A,B,Q: std_logic_vector(3 downto 0); signal C,Z: std_logic;begin Z <= P(1) NOR P(0); MULT_OUT <= A &Q

state_register: process (CLK, RESET) …….. next_state_func: process (G, Z, state) …….. datapath_func: process (CLK) ……..

end sequential;


-- state registerstate_register: process (CLK, RESET)begin if (RESET = '1') then state <= IDLE; elsif (CLK'event and (CLK = '1')) then state <= next_state; end if;end process;

VHDL for Binary Multiplier - 2


-- next state functionnext_state_function: process (state, G, Z)begin case state is when IDLE => if (G = '1') then next_state <= MUL0; else next_state <= IDLE; end if; when MUL0 => next_state <= MUL1; when MUL1 => if (Z = '1') then next_state <= IDLE; else next_state <= MUL0; end if; end case;end process;



-- datapath function

Datapath_func: process (CLK)variable CA: std_logic_vector (4 downto 0); begin if (CLK'event and (CLK = '1')) then if (LOADB = '1') then B <= MULT_IN; elsif (LOADQ = '1') then Q <= MULT_IN; end if;

case state is when IDLE => if G = '1‘ then C <= ‘0’; A <= "0000"; P <= “11”; end if;



-- cont ….datapath function case state is ……. when MUL0 => if Q(0) = ‘1’ then CA := (‘0’ & A) + (‘0’ & B); else CA <= C & A; end if; C <= CA(4); A < CA (3 downto 0); when MUL1 => C =< ‘0’ A <= C & A(3 downto 1); Q <= A(0) & Q(3 downto 1); P = P – “01”; end case; end if;end process


Documents

ENG241 Digital Design Week #10 Sequencing and Control