Evolutionary Migration from LPDDR3 to LPDDR4

Copyright © 2013 SK hynix

CES 2014

Minho Kim

ContentsContents

� Mobile Application Trend

� Introduction of LPDDR4

� New Features of LPDDR4

Mobile Application Trend

Smart Mobile Devices as Heart of LifeSmart Mobile Devices as Heart of Life

Unlike PC devices, mobile device performance has been rapidly improving

Sin

gle

Th

read

ed

Flo

ati

ng

-Po

int

Perf

orm

an

ce

DM

IPS

10 4

Enormous Improvementon Performance of SOCwith higher clock speed

and multi-core processor

4

8

16

32

Multi-Core

Driven

System Performance Trend ( PC vs. Smartphone )System Performance Trend ( PC vs. Smartphone )S

ing

le T

hre

ad

ed

Flo

ati

ng

DM

IPS

10 3

2000 2005 2010

Year2000 2005 2010

Year

4

1

2

[Source : Specfp®]

Clock

Speed

Driven

Driven

1/4

1/2

Mobile EvolutionMobile Evolution

LPDDR LPDDR2 LPDDR3 LPDDR4

Feature phone(Media phone)

Smartphone Smartphone

Mobile ConvergenceSmart Mobile Devices

• Smartphone• Tablet PC

The mobile evolution is expanding to more powerful deviceswith endless innovation of low power consumption and high performance.

(Media phone)

Tablet

Tablet PC

ULT

Automotive Application

Consumer Application

• Tablet PC• Computing• Wearable devices

What’re Key Values from Mobile DRAM …… What’re Key Values from Mobile DRAM ……

Better Media Experience

�Higher and Clearer Resolution

�Panorama Photograph

�Multi-screen Display

2160p UHD 20GB/s

Required DRAM Bandwidth

1080p FHD8.8GB/s @ 60fps

4.4GB/s @ 30fps

1.9GB/s @ 30fps720p HD

Next Generation Mobile DRAMNext Generation Mobile DRAM

LPDDR LPDDR2 LPDDR3 LPDDR4

• 1.8V

• ~400Mbps / pin

• ~1.6GBps (x32)

• 1.2V

• ~1066Mbps / pin

• ~4.3GB/s (x32)

• ~8.5GBps (x64)

• 1.2V

• ~1866Mbps / pin• ~7.5GB/s (x32)

• ~15GBps (x64)

• 1.1V

• ~ 3200Mbps + / pin (ODT)• ~12.8GB/s (x32) • ~25.6GBps (x64)

20062006 20102010 20132013 20152015

Mobile DRAM Evolutionary Path

• ~8.5GBps (x64) • ~15GBps (x64) • ~25.6GBps (x64)

Wide IO Wide IO2

• 1.2V

• 266Mbps/pin

• 17GB/s (x512)

• 1.1V• 800Mbps + / pin

• 25.6GBps (x256)• 51.2GBps (x512)

??

Future Mobile PositioningFuture Mobile Positioning

WIO2

LPDDR3

LPDDR4

Po

wer

Effic

ien

cy

WIO2

Extremely High B/W

& Low Power

WIO2

Extremely High B/W

& Low Power

LPDDR4LPDDR4

LPDDR3

Wide IO2

LPDDR4

LPDDR3

Cost

LPDDR3LPDDR4

Density Scalability

at Affordable price

LPDDR4

Density Scalability

at Affordable price

Mobile System’s Density RequirementMobile System’s Density Requirement

3GB and 4GB Mobile system is just around the corner.

2GB LPDDR2

4GBLPDDR3/4

2GB LPDDR3

3GB LPDDR3Flagship

SmartphoneMemoryDensity

2014

512MB LPDDR1

1GB LPDDR2

256MB LPDDR1

2009 2010 2011 2012 2013

Density

Mono Die 2Gb LPDDRx 4Gb LPDDRx 6/8Gb LPDDRx

Key Factors for Next Mobile SolutionKey Factors for Next Mobile Solution

Requiring over Cost is the

3 key factors are driving next mobile solutions

Requiring over

20GB/s BW

Power budget is critically necessary

Cost is the

first driver

Introduction of LPDDR4

Advantages of LPDDR4Advantages of LPDDR4

Power Efficiency Low Frequency Mode

1.2V ���� 1.1V

Lower Power Supply

LPDDR4LPDDR3

(mw/GBps)

LPDDR435 % Better Power Efficiency

Low Frequency Mode(1600Mbps w/o term.)

High Frequency Mode

(3200Mbps w/ term.)

Power Saving inLow Frequency Mode

Mobile DRAM Features ComparisonMobile DRAM Features Comparison

LPDDR2-S4B LPDDR3 LPDDR4

Data Rate (per pin) 333~1066 Mbps 800~2133 Mbps400~3200 Mbps (~4266Mbps)

Density 64 ~ 8Gb 4Gb ~ 32Gb 8Gb ~ 32Gb

Interface HSUL_12HSUL_12

w/ optional ODTLVSTL

Command/Address Bus

DDR DDRSDR

(Multi cycle command)

Data Bus DDR DDR DDR

VoltageVoltage(VDD1/2/CA/Q)

1.8V/1.2V/1.2V/1.2V 1.8V/1.2V/1.2V/1.2V 1.8V/1.1V/1.1V

I/O organization x16 / x32 x16 / x32 2 ch. x16 (total x32 per die)

Number of Banks 4/8 8 8 / ch. (total 16 banks per die)

Pre-fetch 4 8 16

Burst Length 4/8/16 8 16 / 32 / On the fly

CA ODT - - Supported

DQ ODT - Supported (Optional) Supported

On die ECC - -for future DRAM process

(vendor specific / transparent spec)

Package Types MCP/PoP MCP/PoP MCP/PoP

New Features of LPDDR4

New 2 Channel Dual Edge Pad ArchitectureNew 2 Channel Dual Edge Pad Architecture

DQ

DQByte3

DQ_AByte1

DQ_BByte1

Reduced routing distance allows lower core power and high speed operation

LPDDR2/3 LPDDR4

CA

DQByte2

DQByte0

DQByte1

CA_A

DQ_AByte0

CA_B

DQ_BByte0

Long Data Path Short Data Pathfor each side

New Command Definitions for Lower Pin CountNew Command Definitions for Lower Pin Count

LPDDR2/3 LPDDR4

To minimize pin count increase, CA pins are reduced from 10 to 6.

CA0 CA1 CA2 CA3 CA4 CA5

LPDDR4’s reduced CA pin

Reference: JC42.6 committee item no. 1814.21

LPDDR4’s reduced CA pin

count and changed CA

protocol (SDR) requires

new command definitions.

Low Frequency

LPDDR4 for All Frequency RangeLPDDR4 for All Frequency Range

High Frequency

LPDDR4 provides an easy option to switch over

between different operating frequencies

Zzz...

FSP

* Frequency Set Point

3D Games

Video Recording

New Training OptionsNew Training Options

To enable high speed operation, various training are needed. C

AD

Q

CA

DQ DQ Read Training

DQ Write Training

DQS Interval OscillatorCA

DQ

CA

DQ

Command Bus Training

VREF (DQ) Training

ZQ Calibration

DQS Interval Oscillator

New Signaling SchemeNew Signaling Scheme

VDDQ(1.1V)

VDDQ(1.1V)

With VSSQ TerminationWithout VSSQ Termination

Low Voltage Swing

Low Voltage swing with VSSQ termination allows better signaling

0V

(1.1V)

0.4V

0V

(1.1V)

0.4V

Low Voltage Swing

Clear DATA EYE

New Package / SOC ArchitectureNew Package / SOC Architecture

2ch. architecture will require new ball matrix for package

LPDDR2/3 LPDDR4

1ch.CA

DQ

_3

DQ

_1

DQ

_0

CA

_A

CA

_B

DQ

_A

1

DQ

_B

1

2ch.

DQ

_2

CA_B

DQ_B3DQ_B1DQ_B0DQ_B2

CA

_A

DQ

_A

3D

Q_A

1D

Q_A

0D

Q_A

2

Ball Area

DQ

_A

0

DQ

_B

0

CA_ADQ_A0 DQ_A1 CA_CDQ_C0 DQ_C1

CA_BDQ_B0 DQ_B1 CA_DDQ_D0 DQ_D1

Spec. Ready for Future DRAM TechnologySpec. Ready for Future DRAM Technology

PPR(Post Package Repair)

On die ECC(Error Correction Code)

DATA

Even CustomersCan Repair Failed Cellvia SW setting (MRS)

Error Bit by DRAMPhysical Limitation

Normal

Cell

Redundancy

Cell

…

Failed

Cell

ElectricRepair

(Fuse Cut)

Error Correction Code

Bit Correction

Corrected DATA

Thank you. -감사합니다감사합니다감사합니다감사합니다....