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Exploring the Design Space for Resistive Nonvolatile Memory Crossbar Arrayswith Mixed Ionic-Electronic-Conduction (MIEC)–based Access Devices
P. Narayanan, G. W. Burr, R. S. Shenoy, S. Stephens, K. Virwani, A. Padilla, B. Kurdi, and K. Gopalakrishnan‡
IBM Research – Almaden, 650 Harry Road, San Jose, CA 95120 (‡IBM T. J. Watson Research Center, Yorktown Heights, NY 10598)Tel: (408) 927–2920, Fax: (408) 927–2100, E-mail: [email protected]
AbstractUsing circuit-level SPICE simulations, we explore the design
constraints on crossbar arrays composed of a nonvolatile memory(NVM) (+1R) and a highly nonlinear Access Device (AD) enabledby Cu-containing Mixed Ionic-Electronic Conduction (MIEC) ma-terials [1-5]. Such ADs must maintain ultra-low leakage througha large number of unselected and partially selected 1AD+1R cells,while delivering high currents to the few cells selected for eitherread or write. We show that power consumption during write, notread margin, is the most stringent constraint for large 1AD+1Rcrossbar arrays, with NVM switching voltage VNV M and selectorvoltage margin Vm being much more critical than write current. Weshow that scaled MIEC devices (Vm ∼ 1.54V [4]) can support 1Mbarrays for VNV M up to 1.2V. Stacking two MIEC devices enablesVNV M ∼ 2.4V . A 20% improvement in Vm can either enable a 4×increase in array size or counteract a 5× increase in interconnectline resistance.Keywords: Access device, MIEC, crossbar array, NVM selectors
IntroductionMIEC-based ADs [1–5] exhibit ideal characteristics for 3D-
stacking of large crossbar arrays of any resistive NVM in the BEOL,including bipolar diode-like characteristics (Fig.1), large ON/OFFratios, high voltage margin Vm (for which leakage stays below 10nA), ultra-low leakage (< 10 pA), and high ON current densities.Even with such attractive characteristics, however, the design of alarge crossbar array of 1AD+1R devices (Fig. 2) — within whichwrites and reads must be reliable yet leakage through non-selecteddevices low — requires careful choice of selected & unselectedwordline (VW & VR) and bitline (VB & VC) voltages. We quantifythe design-space enabled by scaled MIEC-based ADs (Vm ∼ 1.54V[4]) in terms of achievable array size, excess required power duringwrite, and read margin.
Simulation frameworkWe assume an NVM device that transitions between an ohmic
Low Resistance State (LRS) and a High Resistance State (HRS)exhibiting Poole-Frenkel (PF) conduction (Fig.3). The equivalentcircuit for the MIEC AD (Fig. 3, inset) is carefully fit to exper-imental data (Fig. 1). Before each SPICE simulation, the innervoltages VC , VR (Fig.4(b)) are chosen for an aggregate unselectedleakage of 10uA (e.g., for a 1Mb array, 10pA/device). As outervoltages VB , VW are swept apart, the voltage across the worst-caseselected 1AD+1R device(s) (Fig. 4(a)) increases. After the simu-lation completes, the NVM switching event (Fig. 5) identifies theexternal voltages (VB , VW ) required for a successful write. DefaultNVM, MIEC AD, and array parameters are shown in Table.1. Totalrequired power is examined just before and just after switching forboth the LRS-to-HRS and HRS-to-LRS transitions.
Design space for NVM writeIn our approach, only voltage choices which trigger a success-
ful write are even considered. A design point becomes unfavor-able when the total applied power becomes much larger than thebase 1AD+1R write power. For instance, even a 10% increase inVHRS causes applied power to increase by two orders of magnitude(Fig.6). This extra applied voltage at the far-edge selected device(Fig. 4(a)) exponentially increases leakage in nearby half-selecteddevices (Fig.4(b)). The resulting larger voltage drops in the wiringthen exacerbate voltage stress at near-edge half-selected devices.While this positive feedback effect is roughly the same for theworst-case (all LRS) and for random stored data patterns, it can be
suppressed by the high resistance of the HRS state (Fig. 6, inset).Like VHRS , there is a VLRS threshold, beyond which write powergrows dramatically. However, the array design is quite robust toincreases in switching currents IHRS , ILRS (Fig.6).
Fig.7 shows that small increases in VHRS dramatically reduceachievable array size. When the design works (blue region at left),almost all the externally applied power reaches the selected device,opening up opportunities for parallel writes; when the design fails,almost all external power is dissipated in half-selected 1AD+1Rdevices. Figs. 8 and 9 show that, similar to NVM voltage VHRS ,maintaining a sufficiently large AD voltage margin Vm is critical tosuccessful array design. Degradations in AD slope S lead to excesspower (Fig.8), yet can be offset by Vm improvements (Fig.9).
For a given NVM, improvements in either the slope S or thevoltage margin Vm of the MIEC-based AD can enable significantincreases in the achievable array size (Fig. 10), or can be used toaccommodate the increases in line resistances expected at scaledtechnology nodes (Fig. 11). Fig. 12 shows the achievable arraysize for both the scaled MIEC AD (Vm ∼ 1.54V) and a stackedcombination of two MIEC ADs. The larger voltage margin far out-weighs the degradation in AD slope and series resistance, allowinga stacked MIEC diode to support 1Mb arrays for NVM switchingvoltages as large as 2.4V. Note that large SPICE simulations areenabled by modeling all unselected 1AD+1R device pairs with asingle aggregate device (Fig.13).
Design space for NVM readRead margin is the change in voltage across a peripheral load
resistor RLOAD (Fig.13) when the selected device moves betweenthe HRS and LRS states. The applied read voltage is determinedbased on avoiding a disturb (Fig.13(A)) on the near-edge cell, thetwo reads are performed with a true V/2 scheme and data patternsshown in Fig.13(B,C)) (other schemes/patterns showed similar per-formance, not shown). The load resistance is chosen to increaseread margin (Fig. 14, inset) without excessive RC timing issues.While read margin degrades with lower read voltage/disturb con-dition (Fig.14), and higher interconnect resistance (Fig.15, inset),NVM resistance contrast has the most significant impact (Fig.15).Read margin does depend upon AD parameters (Fig.16), but writepower considerations are clearly far more stringent (Figs.8,9).
ConclusionsWe have explored the design of 1AD+1R crossbar arrays us-
ing highly nonlinear Access Devices (AD) based on Mixed Ionic-Electronic Conduction (MIEC) [1-5]. Circuit-level SPICE simu-lations were used to show that achievable array size and excessrequired power during write depends strongly on careful match-ing between the turn-on voltage Vm of the AD and the switchingvoltage VNV M of the NVM. This implies that research in this fieldshould be directed towards NVMs with lower VNV M (and ADswith higher Vm), as opposed to decreases in raw NVM switchingcurrent. Scaled MIEC devices (Vm ∼ 1.54V [4]) are shown tosupport VNV M up to 1.2V (for 1Mb arrays), and two stacked MIECdevices enable VNV M ∼ 2.4V .
References[1] K. Gopalakrishnan et. al., VLSI Tech. Symp., 19.4 (2010).[2] R. S. Shenoy et. al., VLSI Tech. Symp., 5B.1 (2011).[3] G. W. Burr et. al., VLSI Tech. Symp., T5.4 (2012).[4] K. Virwani et. al., IEDM Tech. Digest, 2.7 (2012).[5] G. W. Burr et. al., VLSI Tech. Symp., T6.4 (2013).[6] ITRS 2011 Interconnect tables (www.itrs.net).
10uA
100uA
pulsed IV[u
A]
1uA
100nA
10uA pulsed IV(300ns)
rren
t 100nA
10nA
1nA Vm~1.53VSlope
Cur
1nA
100pA
10pA DC IV
Vm 1.53VS~ 85mV/dec
Slope
-1.5 -1.0 -0.5 0 0.5 1.0 1.5
10pA
1pA
Voltage [V]
DC IV
Voltage [V]Fig. 1 Scaled MIEC access de-vices exhibit voltage margins Vm
(at 10nA) of∼1.54V, ON-OFF con-trast in excess of 107 and ultra-lowleakage at low bias [1-5], suitablefor large arrays with many unse-lected devices.
Selected CellPartially (WL) Selected Cells
VW
es)
Selected CellPartially (WL) Selected Cells
s (W
ordl
ine
VR
cted
Cel
ls
elec
t Ro
ws
VR
(BL)
Sel
ec
(N-1
) U
nse
VR
Part
ially
VB(M-1) Unselect Columns (Bitlines)
(
VC VC VC
Fig. 2 Crossbar array with selected, par-tially (WL) selected, partially (BL) se-lected, and unselected 1AD+1R cells.
Rseries I(selected NVM)
(VLRS , ILRS)
INFV(selected NVM)
(VHRS , IHRS) RHRS
V(selected NVM)Vh(VHRS , IHRS)
RHRS-PF
(VLRS , ILRS)
Fig. 3 Generic NVM model for SPICE, withswitching between an ohmic LRS and an HRSexhibiting Poole-Frenkel conduction. Insetshows equivalent circuit for SPICE modelingof the bipolar, highly non-linear MIEC AD.
Voltage drop across ADI
Total Voltage to Switch NVMa)
across AD
Log
… + Voltage drop across NVM
+ drop across wiring
VCVR VWVBb)
Log
I
VCVR VWVBb)
Fig. 4 Total applied voltage at switch-ing is a) NVM voltage VNV M + ADvoltage + wiring IR-drop, identified byb) sweeping select-lines VW and VB
at fixed unselect bias (and leakage).
Current100uANVM “SET” snapback
1uALRSHRS
Half selectedSelecteddevice
10nAHalf-selecteddevices
device
100pA
V lt
Un-selecteddevices
1pA0.5 1.0 1.5 2.0 2.5 3.0 3.5
Voltage [V]
Fig. 5 Cell currents vs. total applied voltagefor the HRS-to-LRS (“SET”) operation on a64×64 array, exhibiting NVM transition.
SET Switching VHRS , IHRS 1.2V, 3µARESET Switching VLRS , ILRS 0.8V, 30µAHolding V during SET Vh 0.5VRead Disturb Voltage VDIS 0.25×VHRSResistance States RLRS , RHRS 26.67kΩ, 400kΩPF HRS @ 0.1V RHRS−PF 10MΩ
Voltage Margin Vm 1.54VTurn-on Slope S 85mV/decSeries Resistance Rs 2850ΩNoise Floor INF 3pA
Array Size N ×M 1Mb (1024×1024)Interconnect R/cell[6] Rint 2.215ΩTable. 1 Default simulation parameters.
10VHRS (1.2V)
Wat
ts] HRS ( )
VLRS (0.8V)
mill
i-W
1ILRS (30uA)
wer
[m
I
Pow IHRS (3uA)
0.1
% Change in Individual Parameters -50% -30% +10%-10% +30% +50%
Fig. 6 Switch-ing voltages(VHRS , VLRS )are much morecritical to lowpower 1AD+1Rcrossbar designthan switch-ing currents(IHRS , ILRS ).Inset: impact ofdata patterns.
≥10mW2.25MbArray size
≥10mW
1.89Mb
2.25Mb
1.57Mb
5mW
1Mb
1.26Mb
% Change in VHRS6 b
784Kb
1Mb
HRSfrom nominalVHRS=1.2V
1mW
50% 30% 10%10% 30% 50%256Kb400Kb576Kb
-50% -30% +10%-10% +30% +50%56 b
Fig. 7 Write power vs. VHRS and array size: smallchanges in VHRS dramatically reduce achievable ar-ray size.
10
Wat
ts] 10
Vm (1.54V)
mill
i-W
1S (85mV/dec)
wer
[m 1
Pow Rs (2850Ω)
0.1
% Change in Individual Parameters -50% -30% +10%-10% +30% +50%
Fig. 8 Voltage margin Vm (at 10nA) is the mostcritical AD parameter in 1AD+1R crossbar Design.
+50% ≥10mW% Change in S from nominal S = 85mV/dec+30%
+40%
+50% ≥10mW
S 85mV/dec
+10%
+20%
+30%
+10%
10%
0 5mW
30%
-20%
-10%
% Change in Vmfrom nominal Vm = 1.54V
50%
-40%
-30%
1mWm-50%
-50% -30% +10%-10% +30% +50%
Fig. 9 Write power as a function of voltage margin Vm
and AD slope S.
V10
+10% Vm
Vm (1.54V)
Wat
ts]
S60mV/dec
mill
i-W
1
wer
[m 1
+20% VmPow
+20% Vm
2 6 b b b 2 2 b 3 b b
0.1
256Kb 1Mb 1.57Mb 2.25Mb 3.14Mb 4MbArray Size
Fig. 10 Any improvement in AD parameterspermits significantly larger size arrays.
10 +10% VmV (1 54V)
Wat
ts] Vm (1.54V)
[mill
i-W
1
wer
1S60mV/dec
Po
0 1 +20% Vm0.1
1X 2X 4X3X 5X 6X
+20% Vm
1X (2.215 Ω/cell)
2X 4X3X 5X 6XChange in Line Resistance
Fig. 11 Alternatively, improved AD parameterscan be used to accommodate the higher line resis-tances of scaled technology nodes.
4Mb
16Mb
Size
1Mb
4Mb
rray
S
MIECStackedMIEC
256Kb
um A
r MIEC(Vm 1.54V, S 85mV/dec)
MIEC(Vm 3.08V, S 170mV/dec)
16Kb
64Kb
axim
u
Full SPICE modelApproximate,
4Kb0.72 0.96 1.20 1.44 1.68 1.92 2.16 2.40
Ma Approximate,
iterative model
NVM Switching Voltage [V]
Fig. 12 Maximum achievable array size vs. VNV M . For twostacked MIEC ADs, Vm improvement outweighs degradationin turn-on slope and series resistance. A simple model, iteratingout from the selected device, is close to SPICE in accuracy.Selected CellPartially (WL) Selected Cells Selected CellPartially (WL) Selected Cells
s
VW = VA/2
ecte
d Ce
lls
HRSHRS
A. Worst-case Read Disturb
y (B
L) S
ele
VR
HRS HRS
Part
ially
VR
HRSLRS
B. Read HRS
LRSLRS
C. Read LRS
V V /2
RLOADVC VREAD
LRS LRS HRS HRS
VB = -VA/2
Fig. 13 One aggregate 1AD+1R canmodel the combined leakage of all uns-elected crosspoints; read operation addsRLOAD at array periphery. Insets showassumed patterns of stored data.
VDIS (0.3V)250
200mV]
150gin
[m
RHRS (400kΩ)RLRS (26.67kΩ)100M
arg
RLRS (26.67kΩ)
50
100
ead
M
0
50
Re
Individual Parameters % Change in
0-50% -30% +10%-10% +30% +50%
Fig. 14 Sensitivity of read margin toVDIS , RHRS and RLRS . Inset: Readmargin is maximized when RLOAD ap-proaches RHRS−PF . Default value ofRLOAD =
√RLRSRHRS ∼ 103kΩ.
mV] 160
180
rgin
[m
140
adM
ar
100
120
Rea
60
80
40
60
15X 12X 6X9X 3X 1.5XResistance Contrast
Fig. 15 Read margin deteriorates sig-nificantly with loss of resistance contrast(LRS resistance approaches ohmic HRS),and (inset) decreases linearly as intercon-nect resistance increases.
180
S160[m
V] S (85mV/dec)
140argi
n Vm (1.54V)
120ad M
a
100
120
Rea
80
100
Individual Parameters % Change in
80-50% -30% +10%-10% +30% +50%
Fig. 16 The impact ofVm andS changeson read margin is significantly less criti-cal than their write power impact (Fig.8).