Faster Close Webinar

8/10/2019 Faster Close Webinar

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©Synopsys2009 1 IC Compiler 2009 Webinar Series

IC Compiler 2009 Webinar Series

Faster Design Closure with

Congestion Minimization

Design Compiler Graphical & IC Compiler

JC Lin, R&D VP

Janet Olson, R&D Group Dir June 9th, 2009




Welcome!IC Compiler 2009 Webinar Series

ICCompiler

CongestionMinimization

Signoff-Driven

Closure

In-DesignRail

Analysis

In-DesignPhysical

Verification

• Previous topics:

– Signoff-driven closure

– In-design physical verification

• Upcoming topic:

– In-design rail analysis on 6/25

• Today’s topic:

– Congestion minimization

Recordings and presentations available at

www.synopsys.com




Welcome!Presenters Introduct ion

Dr. JC Lin

R&D VP, Placement and CTS in IC Compiler

Janet Olson

R&D Group Dir, Design Compiler Graphical




• Routing congestion and its sources – Congestion causes schedule delays

• Design Compiler Graphical and IC Compiler – Best solution for congestion minimization

• Traditional congestion minimization flow – Iterations required between synthesis and place & route

• Congestion minimization with Design Compiler Graphical

– Faster convergence with higher schedule predictability

• Summary

Agenda







• Congestion minimization with Design Compiler Graphical


• Summary

Agenda




Routing Congestion: A Problem

Almost Every IC Designer Faces

• Congestion occurs

when the number of

wires going through a

routing region exceedsits capacity

– To meet timing

– To avoid blockages

– Due to area constraints

Congestion Map

To resolve congestion, Place & Route tools need to make

intelligent tradeoff between timing QoR and routability


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Sources of Routing Congestion

• Floorplan

– i.e. macro-placement

• RTL structures

– i.e. MUX trees

• High utilization – i.e. limited room

Floorplan-related

RTL-related



Congestion Can Be A Major

Contributor To Schedule Delays

Customer A

3 months delay

RTL modifications

90 nm

500K instances

Consumer Electronics

Customer B

3 months delay

RTL modifications

65 nm

400K instances

3G Wireless





Galaxy Platform EvolutionFrom Dataflow to Smart ‘Look Ahead’ Technology

2002

Dataflow

S i g n o f f

Place & Route

Physical

Synthesis

Design

Planning

Synthesis

2004

Correlation

S i g n o f f Design

Planning

Synthesis

Place & Route

2007

‘Look Ahead’

Place & Route

Synthesis

S i g n o f f



Design Compiler + IC Compiler Leading Choice for Design Implementat ion

Leading Choice For Synthesis

• Best-in-class QoR

• Correlation w/ layout minimizes congestion

• Automated & complete power synthesis• Faster TAT with in-built test

Leading Choice For Physical Design

• Best-in-class QoR• 45nm/32nm production proven

• Optimized for power and DFM

• Excellent signoff correlation

IC

Compiler

Design

Compiler

S i g n o f f



Design Compiler + IC CompilerTopog raphical Technology fo r Predictabi l i ty

Timing & Area Power Test

IC

Compiler

Design

Compiler

S i g n o f f




Design Compiler Graphical + IC Compiler Best Solut ion fo r Congest ion Minim ization

Accurate prediction of congestion

Early physical visualization

Congestion optimization in synthesis

MCMM synthesis

Shared technology with IC Compiler

Design Compiler Graphical

IC Compiler






• Traditional congestion minimization flow – Expensive iterations required

• Design Compiler Graphical congestion minimization


• Summary

Agenda




Traditional Flow For Handling Congestion

Synthesis • Focused on timing, power,area & test





Synthesis

Gate level Netlist

Place and Route

• P&R tries to resolve

congestion

• Timing driven congestion-removal

• Auto-area-recovery for

high density hot spots

• Congestion analysis for

floorplan adjustment and

placement controls

Congestion

minimization

techniques

High congestion

discovered





Synthesis

Gate level Netlist

Place and Route

Congestion

minimization

techniques

High congestion

discovered Sometimes P&R succeeds to

resolve congestion





Synthesis

Gate level Netlist

Place and Route

Congestion

minimization

techniques

High congestion

discovered Sometimes P&R does not

succeed




Convergence Issues with Traditional Flow1. Congestion is Detected to o Late in the Design Cycle

• Design is optimizedwithout considering theeffect of congestion – RTL optimizations are

optimistic

• Congestion removal inP&R leads to tradeoffbetween timing QoR

and routability – Increased wirelength

degrades timing QoR

Synthesis

• WNS: -0.46ns

Place & Route

• WNS: -0.81ns• Area increase post

placement: 15%




Convergence Issues with Traditional Flow2. Congestion Removal in P&R May Require FP Changes

• Congestion removal

in P&R may need

floorplan adjustments

late in the flow – Schedule gets

impacted

– Possible increase in

die size – Timing degradation

because of long paths

Congestion with

increased channel size

Congestion withoriginal channel size




Convergence Issues with Traditional Flow3. Some Congest ion Canno t Be Resolved in P&R

• RTL structures can beintrinsically congested – i.e. large MUX trees,

ROM

– Not trivial to identify inP&R

• Intelligent synthesisalgorithms needed tofree logic fromintrinsic congestion

ROM




Conclusion

• Reducing congestion in

P&R can be expensive

• At times, congestion

cannot be resolved in P&R

Synthesis

Place &

Route

A solution that considers the effect of

congestion in RTL synthesis is needed




Ideal RTL Synthesis Solution

Tight correlation between synthesis and P&RShared technology

Better starting point for layoutFaster convergence

Concurrent congestion optimizationTogether with timing, area, power and test

Early visibility into routing congestion

Assessing and fixing congestion in synthesis









• Summary

Agenda




• Introduction

• Key capabilities

• Design Compiler Graphical + IC Compiler

best practices






Design Compiler GraphicalExtend ing Topographical Techno logy to Rout ing Congest ion

DC Graphical

IC Compiler

• Breakthrough synthesiscapabilities

– Congestion prediction

– Congestion optimization

– Physical visualization – MCMM Synthesis

• Shares technology with ICC






Design Compiler GraphicalUtil izing ICC Technolog y to Address Rout ing Congest ion

Virtual placement is

congestion driven

using global route

RTL &

Constraints

Congestion

optimization in

synthesis allows for

larger changes N e t M o

d e l

A c c u r

a c y

O p t i m i z

a t i o n


Netlist

Timing, power, area, test and

congestion optimized

Highly correlated to ICC




• Introduction

• Key capabilities

– Congestion prediction – Physical visualization

– Congestion optimizations

• Design Compiler Graphical + IC Compilerbest practices






Design Compiler GraphicalCongest ion Predict ion – Est imat ion

• Global Route-based

congestion estimation

• Design partitioned into

virtual array of GlobalRoute Cells (GRCs)

• Shared Synopsys Global

Route technologyVirtual Grid

Virtual Route

Violation = # of wires ‒ max # allowed wiresi




• Text based reporting with report_congestion

– Similar format as IC Compiler

• Provides quick assessment of congestion status

Design Compiler GraphicalCongest ion Predic t ion - Repor t ing

Design : Test

Version: B-2008.09-SP3

Date : Fri Feb 13 11:38:50 2008

****************************************

Both Dirs: Overflow = 4651 Max = 5 (10 GRCs) GRCs = 3401 (0.59%)

H routing: Overflow = 2386 Max = 3 (50 GRCs) GRCs = 1788 (0.31%)

V routing: Overflow = 2265 Max = 3 (18 GRCs) GRCs = 1961 (0.34%)

Overflow = ∑ {Violation(i) x #GRCs with violation(i)}i




Design Compiler GraphicalPhys ical Visualizat ion

Debug timing issues due tolayout

Layout view Congestion map

Congestion due

to Floorplan

Congestion

due to RTL

Detect and debug sources ofcongestion

Long path due

to macro location

Early Detection and Debug of Layout Issues




Design Compiler GraphicalPhysical Visual izat ion - Congest ion Analysis

Congestion Map in Layout Viewer

7

6

5

4

3

2

10

-20

0

0






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6

5

4

3

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-20

0

0






7

6

5

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-20

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Design Compiler GraphicalCongest ion Opt imizat ions

ROM Example

Creates a Better Starting Point for Place and Route

Timing/Area Congestion-Aware

case (a)

12'h000: z = 16'h991e;

12'h001: z = 16'hbf94;

12'h002: z = 16'hc0bf;

12'h003: z = 16'h991e;

12'h004: z = 16'hbf84;

12'h005: z = 16'hc0cf;::::::::::::::::::::::12'hffe: z = 16'ha1af;

12'hfff: z = 16'h0c0c;

endcase

4Kx16 ROM • Optimizes highly connected

logic structures

• Creates self-contained sub-

structures to minimize wire

crossing

• Performs congestion-driven

virtual layout optimizations

DC G hi l + IC C il S d U




DC Graphical + IC Compiler Speed Up

Design ClosureDC Graphical IC Compiler

Congestion

Prediction

Congestion

Optimization

Correlated

Correlated

C G




• High compression levels canimpact congestion

– High number of global connections

for de/compressor logic

– Many scan chains routes required

• Adaptive scan compression

congestion optimizations

– Routing friendly sharing of

compressor/de-compressor logic

– Scan chain partitioning to reducecongestion

Design Compiler GraphicalCongest ion Opt im izations fo r Adapt ive Scan Compression

Scan de-compressor logic

D i C il G hi l




Design Compiler GraphicalCongestion Opt im izat ion for 50X Adaptive Scan

No Congestion

Optimization

Congestion

Optimization

Pre DFT Post DFT Post ICC

Pre DFT Post DFT Post ICC

D i C il G hi l




Design Compiler GraphicalCongest ion Opt imizat ions Complement ICC

Source of

congestion

Identify/Fix phase Type of optimization

RTL structure Identify in DC Graphical

Fix in DC Graphical

Logic based: netlist

structuring, mapping,

decompositionFloorplan Identify in DC Graphical

or ICC

Fix in ICC

Floorplan based: MinChip,

manual floorplan updates

High celldensity Identify in DC Graphicalor ICC

Fix in ICC

Placement based: cellspreading





• Introduction

• Key Capabilities

• Design Compiler Graphical + IC Compiler

best practices





D i C il G hi l IC C il




Design Compiler Graphical + IC CompilerConsistency Checker to Ensure Convergence

• Correlation issues often due toinconsistent settings

• Automated checking compares settings

and highlights differences for:

– Library setup

– Variable/command settings

– Timing constraints

– Physical constraints

• Available as SolvNet article 026366https://solvnet.synopsys.com/retrieve/026366.html

DC Ultra

IC Compiler

DC

Settings

ICC

SettingsIC

Compiler

IC CompilerDC

ConsistencyCheckerNetlist

https://solvnet.synopsys.com/retrieve/026366.html

https://solvnet.synopsys.com/retrieve/026366.html









• Summary

Agenda

D i C il G hi l




Design Compiler GraphicalDelivers Faster Turn around Time & Predictable Schedu le

Tight correlation between synthesis and P&RShared technology

Better starting point for layoutFaster convergence

Concurrent congestion optimizationTogether with timing, area, power and test

Early visibility into routing congestion

Assessing and fixing congestion in synthesis

D i C il G hi l + IC C il




Design Compiler Graphical + IC Compiler Best Solut ion fo r Congest ion Minim ization

• Congestion can be a major

contributor to schedule

delays

• Traditional congestionminimization flow may have

convergence issues

• Design Compiler Graphical

addresses congestion duringsynthesis providing a better

starting point for IC Compiler

for faster closure


IC Compiler



Predictable Success

Documents

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