Floorplan Evaluation with Timing-Driven Global

Wireplanning, Pin Assignment and Buffer / Wire Sizing

Christoph Albrecht Synopsys, Inc., Mountain View formerly Research Institute for Discrete Mathematics, Bonn, Germany

Andrew B. Kahng, Ion Măndoiu UC San Diego, La JollaAlexander Zelikovsky Georgia State University, Atlanta

ASPDAC 2002, Bangalore

Outline

•Previous Work

•Buffer Block-/ Site-Methodologies

•Floorplan Evaluation Problem

•Key Ingredient: Gadgets

•Multicommodity Flow Approximation

Algorithm / Randomized Rounding

•Experimental Results

Previous Work•Floorplan

Chen et al. – BBL [VLSI’83], Dai et al. [TCAD’87],Cong [TCAD’91]

•Buffer Block MethodologyCong et al. [ICCAD’99], Tang&Wong [ISPD’00]

•Buffer Site MethodolgyAlpert et al. [DAC’01]

•Multicommodity Flow Approximation AlgorithmGarg and Konemann [FOCS’98]Fleischer [SIDMA’00]

•Application to Global RoutingAlbrecht [ISPD’00 + TCAD’01]

•Application to Buffer Block MethodologyDragan et al. [ICCAD’00 + ASPDAC’01 + WADS’01]

Buffer-Block MethodologyCong et al. [ICCAD’99], Tang&Wong [ISPD’00],

Dragan et al. [ICCAD’00 + ASPDAC’01]:

• Buffers inserted in blocks located within available free space• Simplifies design by isolating buffer insertion from circuit block

implementations

Buffer-Site MethodologyAlpert et al. [DAC’01]

• Block designers leave “holes” in circuit blocks to be used for buffer insertion

• Alleviates congestion problems of buffer blocks

Buffer-Site MethodologyAlpert et al. [DAC’01]

• Block designers leave “holes” in circuit blocks to be used for buffer insertion

• Alleviates congestion problems of buffer blocks

Buffer-Site MethodologyAlpert et al. [DAC’01]

• Block designers leave “holes” in circuit blocks to be used for buffer insertion

• Alleviates congestion problems of buffer blocks

Floorplan Evaluation Problem

• Tile graph G to model congestion:

wire capacity w(u,v): number of free routing channels

between tile u and v.

buffer capacity b(v): possible number of buffers in tile v.

• Netlist (source and sink pins given as sets of tiles)

• Maximum wireload of buffers / sources U

Given:

Floorplan Evaluation Problem

• Tile graph G to model congestion:

wire capacity w(u,v): number of free routing channels

between tile u and v.

buffer capacity b(v): possible number of buffers in tile v.

• Netlist (source and sink pins given as sets of tiles)

• Maximum wireload of buffers / sources U

Given:

Find:Pin assignment and feasible buffered routing for nets,

subject to buffer and wire congestion constraints and

minimizing the total routing area,

(#buffers) + (total wirelength),

where , 0 are given scaling constants

Key Ingredient: Gadgets

Tile graph G

Key Ingredient: Gadgets

Key Ingredient: Gadgets

Cap = b(u)

Cap = w(u,v)

Cap = b(v)

Key Ingredient: Gadgets

Lemma: 1-to-1 correspondence between feasible buffered paths for net N in G and s – t paths in H.i ii

Cap = b(u)

Cap = w(u,v)

Cap = b(v)

Integer Program

px

x

GEvuvuwxEp

GVvvbxEp

xEpEp

p

p p

p pvu

p pv

p pvu vuv v

path feasible {0,1},

net ,1

)(),( ),,(ν

)( ),(μ| s.t.

min

0,

0

),( ,

|

||

| | | |

Integer Program

px

x

GEvuvuwxEp

GVvvbxEp

xEpEp

p

p p

p pvu

p pv

p pvu vuv v

path feasible {0,1},

net ,1

)(),( ),,(ν

)( ),(μ| s.t.

min

0,

0

),( ,

|

||

| | | |

x p 0Linear Relaxation

Dual Linear Program

GEvu

vuwvb y

l

v v

i i

)(),(

),(ν

)(μ s.t.

max

00

z

u,v

u,v

D u 1

GVv )( y v

z u,v 00

l i

Ep

Ep

vu vu

v v

, ,

| |

| |

y vu

u

ppath

Solution

Linear Relaxation =Multicommodity flow with set constraints

Garg and Konemann [FOCS’98]Fleischer [SIDMA’00]

Randomized RoundingRaghavan & Thomson [COMB’87]

xp=0, yv=/0b(v), ze=/0w(e), u=/D, pi=While v b(v)yv + e w(e)ze + Du < 1 For i = 1,…, #nets do

If pi = or weight(pi) > (1+) li

Find path pi with min weight li among si-ti paths End If

xpi = xpi

+ 1

For every vV(G) and eE(G):

yv = yv( 1 + |piEv| / 0b(v) )

ze = ze( 1 + |piEe| / 0w(e) )

u = u( 1 + ( v|piEv| + e|piEe|) / D ) End For End ForEnd WhileOutput x scaled by the number of ‘While’ iterations

Approximation Algorithm

Extensions

•Sink delay upper bounds (Elmore-Delay)

•Buffer-wire sizing and layer assignment

•Multi-pin nets

Testcase Algo Wirelen. %LB Gap #Buffers %LB Gap W_congest B_congest CPU

ami49 RABID 7592 11.87 1339 21.51 0.93 0.36 167324 nets

a9c3 RABID 30723 5.64 4225 11.95 0.60 0.44 5021526 nets

playout RABID 27601 6.38 3840 15.04 0.45 0.64 8131663 nets

xc5 RABID 27060 8.35 4410 23.25 0.84 0.81 6942149 nets

Experimental Results

Testcase Algo Wirelen. %LB Gap #Buffers %LB Gap W_congest B_congest CPU

ami49 RABID 7592 11.87 1339 21.51 0.93 0.36 167324 nets MCF 6792 0.07 1135 2.99 1.00 0.47 314

a9c3 RABID 30723 5.64 4225 11.95 0.60 0.44 5021526 nets MCF 29082 0.00 3801 0.72 0.63 0.31 1082

playout RABID 27601 6.38 3840 15.04 0.45 0.64 8131663 nets MCF 25946 0.00 3428 2.70 0.51 0.32 1393

xc5 RABID 27060 8.35 4410 23.25 0.84 0.81 6942149 nets MCF 25155 0.73 3841 7.35 0.96 0.60 1641

Experimental Results

Testcase Algo Wirelen. %LB Gap #Buffers %LB Gap W_congest B_congest CPU

ami49 RABID 7592 11.87 1339 21.51 0.93 0.36 167324 nets MCF 6792 0.07 1135 2.99 1.00 0.47 314

MCF+PA 6041 0.01 991 4.87 1.00 0.50 304

a9c3 RABID 30723 5.64 4225 11.95 0.60 0.44 5021526 nets MCF 29082 0.00 3801 0.72 0.63 0.31 1082

MCF+PA 26057 0.00 3376 0.75 0.58 0.30 1079

playout RABID 27601 6.38 3840 15.04 0.45 0.64 8131663 nets MCF 25946 0.00 3428 2.70 0.51 0.32 1393

MCF+PA 23138 0.00 3004 4.12 0.40 0.32 1386

xc5 RABID 27060 8.35 4410 23.25 0.84 0.81 6942149 nets MCF 25155 0.73 3841 7.35 0.96 0.60 1641

MCF+PA 22265 0.05 3340 4.87 0.98 0.50 1644

Experimental Results

Conclusions

• First coherent approach to floorplan definition, timing and congestion-driven buffered global route planning, wire/buffer sizing, layer assignment and pin assignment.

• Provably good results by multicommodity flow approximation algorithms and randomized rounding.