FPGA IMPLEMENTATION OF AUTOMATED ENCRYPTION STANDARD ALGORITHM

1. INTRODUCTION:

Advanced Encryption Standard (AES), adopted by US government is widely used encryption algorithm because of its ease of implementation and high performance. To provide high security to hacking, FPGA based implementation of AES is done for high speed data. To increase the complexity of hacking further a new key expansion scheme is proposed along with high throughput pipelining structure for hardware implementation of AES design. The proposed AES design is implemented in MATLAB demonstrating its application to image encryption. AES algorithm is then to be implemented using HDL language and is functionality to be verified on FPGA.

2. PROJECT FLOW:

3. AES STRUCTURE:

4. SIMULATION RESULTS:

4.1 MATLAB IMPLEMENTATION OF AES ALGORITHM

Input:

Data to be encrypted such as text, image, file etc. of any size. Data is treated as matrix and is encrypted block by block.

User defined Key of any length can be used to encrypt the data matrix.

Internally Generated:

A Predefined Key is used to encrypt the User defined Key.

Substitution Box & Inverse Substitution Box for Sub Bytes algorithm.

Polymat & Inverse Polymat matrices for Mix Column algorithm

Example Simulation

5. VERILOG IMPLEMENTATION OF AES:

ALGORITHM:

Image is resized [256*256] and converted to text (input.txt) using Matlab. input.txt file is stored in memory[0:65535](2D image converted to 1D) in Verilog Every 128bit data block processed and data encrypted using AES encrypt algorithm(sub bytes,

shift rows, mix columns, add round key operation for 10 rounds) Encrypt.txt is given as input to decrypt algorithm and then decrypted out.txt is obtained. out.txt is again converted back to image using Matlab

5.1. SIMULATION RESULTS:

Input:

Image to be encrypted of any size (Encryption) and Encrypted image (Decryption).

User defined Key of any length can be used to encrypt the data matrix.

Internally Generated:

A Predefined Key is used to encrypt the User defined Key.

Substitution Box & Inverse Substitution Box for Sub Bytes algorithm.

Output:

Encrypted image for encryption and Decrypted Image for decryption.

5.2 AES ENCRYPTION:

5.3 AES DECRYPTION:

5.4 IMAGE ENCRYPTION:

Parameter Matlab VerilogNPCR(Number of Pixel Change rate) 64% 46.68%UACI(Unified Average Changing Intensity) 39% 25%

5.5 REPORT SUMMARY:

AES 128 bit Encryption and Decryption

Device: EP2C3672C6

Family: Cyclone II

Number of clock cycles required to generate 128 bits=4

Parameter Encryption DecryptionArea: Total Registers 5120 5120Power(mw) 155.37 155.32Clock Frequency(MHZ) 413.74 420.17Period(ns) 2.417 2.380Throughput(GBPS) 13.23 13.44

6. REFERENCES:

1. Qiang Liu, Zhenyu Xu, Ye Yuan, “High throughput and secure advanced encryption standard on field programmable gate array with fine pipelining and enhanced key expansion” ,Computers & Digital Techniques, IET, Year: 2015, Volume: 9, Issue: 3,Pages: 175 - 184, IET Journals & Magazines.

2. Dhede, O.S.; Shah, S.K, "A review: Hardware Implementation of AES using minimal resources on FPGA”, Pervasive Computing (ICPC), 2015 International Conference on Year: 2015, Pages: 1 - 3, IEEE Conference Publications

3. Xinmiao Zhang, Keshab K. Parhi, “High-Speed VLSI Architectures for the AES Algorithm”, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 9, SEPTEMBER 2004