From Physics to Power, Performance, and Parasitics

The GTS-Team

Global TCAD Solutions GmbH,Boserndorferstraße 1/12,

1010 Vienna, Austria

O. Baumgartner et al. (GTS) GTS 1 / 25

Scales, methods, hierarchies

Abstraction level Transistors Description Quantity

System level 1.000.000.000 Behavioral Message

Register transfer level (HDL) 1.000.000

Gate level 1.000.000 Signal state 0/1

Transistor level (SPICE) 10.000 ODE I

Classical TCAD 100 PDE (DD) J(x , y , z)

Nano TCAD 1 PIDE (SBTE) Jn(x , y , z ,E )

Quantum transport ≤ 1 NEGF

Atomistic < 1 DFT

O. Baumgartner et al. (GTS) GTS 2 / 25

Introducing TCAD in design

Fab/foundry Designer/customer

Process

Characterization

TCAD models Design rules Compact models

Standard cells

PDK

TCAD models

incomplete information

• Potential benefit: More spot-on designs; fewer, shorter iterations

• Problem for TCAD in design: Where to start from?

• No calibrated device models (mobility)

• No detailed process information

O. Baumgartner et al. (GTS) GTS 3 / 25

Introducing TCAD in design

Fab/foundry Designer/customer

Process

Characterization

TCAD models Design rules Compact models

Standard cells

PDK

TCAD models

incomplete information

• Potential benefit: More spot-on designs; fewer, shorter iterations

• Problem for TCAD in design: Where to start from?

• No calibrated device models (mobility)

• No detailed process information

O. Baumgartner et al. (GTS) GTS 3 / 25

Our solutions

Single-device TCAD Large-scale TCADNano-scale TCAD

• Path finding

• Process to device to cell to circuit variability

• Design-technology co-optimization (DTCO)

O. Baumgartner et al. (GTS) GTS 4 / 25

Modules

• Layout-based structrue generation• Rapid prototyping• Process-flow awareness

• Device simulation• Steady-state, transient, AC• Reliability• What about calibration?

• Parasitics extraction• R/C-network topology extraction

• Self-heating• Quasi-transient simulation• Thermal network extraction

O. Baumgartner et al. (GTS) GTS 5 / 25

Layout-based structure generation

M2

M1

M0

FEOL

BP

3D Cell LayoutTechnologyLayout Technology

O. Baumgartner et al. (GTS) GTS 6 / 25

Process emulators

• Voxel-based topographical processemulators

• Coventor SEMulator3D• Synopsys Process Explorer

• Valuable tools for process explorationand integration

• Lacking features of a full-fledgedprocess simulator

• Require detailed knowledge aboutprocess

• Combination with device simulationposes difficulties

• Voxel-based topography containsstep-like surfaces

• Layer thicknesses?

• Requires repair procedure

• May contain artifacts

• High number of surface points

; Large mesh size,excessive device simulation times

O. Baumgartner et al. (GTS) GTS 7 / 25

Process emulators

• Combination with device simulationposes difficulties

• Voxel-based topography containsstep-like surfaces

• Layer thicknesses?

• Requires repair procedure

• May contain artifacts

• High number of surface points

; Large mesh size,excessive device simulation times

O. Baumgartner et al. (GTS) GTS 7 / 25

Process emulators

• Combination with device simulationposes difficulties

• Voxel-based topography containsstep-like surfaces

• Layer thicknesses?

• Requires repair procedure

• May contain artifacts

• High number of surface points

; Large mesh size,excessive device simulation times

O. Baumgartner et al. (GTS) GTS 7 / 25

What is Layout-Based Structure Generation?

• Built on a Constructive Solid Geometry (CSG) kernel

• Human-readable/writeable script (Tech file) directs CGS kernelbased on layout (GDSII file)

• No process details required

• Process-flow aware

• Integrated meshing, high-quality mesh output, no repairs

• 2 × less mesh points than process emulation

• 5 × faster device simulation

• 100 % successful convergence

O. Baumgartner et al. (GTS) GTS 8 / 25

Layout-based structure generation – FEOL

• “TechX” based on IMEC iN14

• Fin tapering

• Rounded corners

• Conformal dielectric layers

• Realistic epi-shapes

• Process-flow awareness:• Self-aligned processes• Doping distribution

O. Baumgartner et al. (GTS) GTS 9 / 25

Layout-based structure generation – BEOL

• “TechX” based on IMEC iN14

• Realistic interconnect geometries

• Conformal TiN-barriers

• Cu-fill

O. Baumgartner et al. (GTS) GTS 10 / 25

Variability: line-edge roughness (LER)

Technologydescription

GDSII layout

3D cell

Doping

Analytic Imported Implant,diffusion,activation

Variability

LER Maskmisalignment

Lithographyeffects

Analyticrounding

Importedfrom GDSII Imported

devicegeometry

Importedstress

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Adding LER to gate lines

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Doping with LER – closeup

correlated

doping follows roughness

O. Baumgartner et al. (GTS) GTS 13 / 25

Doping with LER – closeup

correlated

doping follows roughness

O. Baumgartner et al. (GTS) GTS 13 / 25

Doping with LER – closeup

correlated

doping follows roughness

O. Baumgartner et al. (GTS) GTS 13 / 25

Adding LER to fin patterning mask (SADP)

O. Baumgartner et al. (GTS) GTS 14 / 25

Variability: mask misalignment

Technologydescription

GDSII layout

3D cell

Doping

Analytic Imported Implant,diffusion,activation

Variability

LER Maskmisalignment

Lithographyeffects

Analyticrounding

Importedfrom GDSII Imported

devicegeometry

Importedstress

O. Baumgartner et al. (GTS) GTS 15 / 25

Mask misalignment

R increaseC increase

O. Baumgartner et al. (GTS) GTS 16 / 25

Device simulation – steady-state characteristics

NSFET @ |VDS| = 0.6 V

HP

PM

OS

NM

OS

LP

PM

OS

NWFET @ |VDS| = 0.7 V

parasitic channel

VS

S

VD

D

NMOS

PMOS

PMOS

NMOS

CFET @ |VDS| = 0.7 V

O. Baumgartner et al. (GTS) GTS 17 / 25

Transient device simulation – power vs. performance

FinFETNSNWCFET

VDD=0.8 V

VDD=0.5 V

O. Baumgartner et al. (GTS) GTS 18 / 25

Calibration & prediction

Hardware Data

Performance Pre-dictions withProcess and De-sign Variations

FF N14

NW N10

FF N14, FFN10, FF N7

NW N7, NWN5, NW N3

NS N5, NSN3, NS N2

NMOS

SimulationMeasurement

PMOS

SimulationMeasurement

O. Baumgartner et al. (GTS) GTS 19 / 25

Automated parasitics extraction

O. Baumgartner et al. (GTS) GTS 20 / 25

BEOL resistances & capacitances

O. Baumgartner et al. (GTS) GTS 21 / 25

FEOL resistances

O. Baumgartner et al. (GTS) GTS 22 / 25

Multi-scale self-heating

O. Baumgartner et al. (GTS) GTS 23 / 25

Modules – summary

• Layout-based structrue generation• Rapid prototyping• Process-flow awareness

• Device simulation• Steady-state, transient, AC• Reliability• What about calibration?

• Parasitics extraction• R/C-network topology extraction

• Self-heating• Quasi-transient simulation• Thermal network extraction

O. Baumgartner et al. (GTS) GTS 24 / 25

Our solutions

Single-device TCAD Large-scale TCADNano-scale TCAD

• Path finding

• Process to device to cell to circuit variability

• Design-technology co-optimization (DTCO)

O. Baumgartner et al. (GTS) GTS 25 / 25