Future Memory Technologies in Nano Era
Kinam Kim, Hongsik Jeong* Semiconductor R&D Center Samsung Electronics Co. Ltd. Contents Introduction
Opportunities and Reality of New Types of Memories Technology Scaling and Technology Barriers of New Memories 1)FRAM 2)MRAM 3)PRAM 4.Summary History of Memory Device
1947 : The invention of Transistor - William B. Shockley, John Bardeen and Walter H. Brattain at The Bell Laboratories - Nobel Prize, 1956 1951 : The invention ofBJT 1955 : The invention of FET 1958-9: First Integrated Circuit - Jack Kilby at Texas Instruments ( 2000, Nobel Prize ) Robert Noyce at Fairchild Camera 1966 : Invention of DRAM Paper Clip, Ge 1970 : Intel, 1Kb DRAM D/R = 8 m World First Transistor : Point Contact Memory Density : X 1,000,000 Feature Size : X 1/100 2004 : Samsung, 1Gb DRAM D/R = 0.08 m Memory Scaling Trend Growing technical complexity, fabrication cost, physical limit What are showstoppers? ? 2000 2005 2010 2015 2020 20 40 60 80 100 1 10 Design Rule [nm] Density [Gb] FLASH DRAM 25nm 10nm 55nm 100nm 1Gb 8Gb 64Gb 512Gb 256Gb 32Gb 4Gb 512Mb 3rd Node 1st Node 2nd Node -5nm / year 1.41 / year Year Scaling Limit of DRAM Cell transistor scaling
Gate contact Electric field distribution ( V/cm ) Maximum electric field Channel length decrease Channel doping increase Electric field increase Junction leakage currentincrease Retention time decrease Cell Transistor Technology
3D Cell Structure reducing E-Field Planar Transistor RCAT ( Recessed Cell TR.) FINFETTr. Scaling Limit of NAND Flash
Cell-to-cell coupling CTUN CONO CFGX CFGY CFGXY CFGCG V1 V2 V3 V4 V6 V5 VFG VCG Control gate ONO Floating gate Tunnel oxide Silicon substrate STI Narrower word-line space Cell-to-cell capacitance increase Wide distribution of Vth Over-program / under-erase Scaling Limit of NAND Flash
Cell-to-cell coupling estimation Steep increase of coupling below 40 nm Improvement : - Low-k dielectric - Floating gate height scale down. Cell transistor scaling Cell to cell interference
Scaling Limit of Memories Lifetimes of conventional memories are far shorter than that of CMOS Need new memories with longer lifetime, less technical barriers and betterfunctional properties Memory & Device Fundamental limiting factor Limit of technology node DRAM Cell transistor scaling 50 nm NAND Flash Cell to cell interference 20 nm NOR Flash Si-SiO2 barrier height SRAM CMOS 10 nm Electron wave length Contents Introduction
Opportunities and Reality of New Types of Memories Technology Scaling and Technology Barriers of New Memories 1)FRAM 2)MRAM 3)PRAM 4.Summary Characteristics of Emerging New Memories
New Paradigm of IT World requires Ideal Memory - New Materials and New Function Devices New Function Non-volatility :> 10 years Fast random access :tRead = 10ns tWrite = 5ns ~ 100ns Virtually unlimited usage :> 10^12 cycles New Material FRAM: Ferroelectric Material PZT, SBT, BLT MRAM: Ferromagnetic Material NiFe, CoFe, PRAM: Chalcogenide GeSbTe, Opportunities of New Memories
Memory management in systems complicated multiple memory simplified single memory Reduce power consumption mobile system High Speed Data Storage Merge code and data storage memory Simplify data changing process Block write (flash) bit-by-bit write enhance system performance Virtually unlimited endurance No need for complicated software New applications Instant on PC, Simplified Data Process / No Buffer Memory
New Memory Applications Mobile Devices Simplified Data Process / No Buffer Memory Flash + RAM Solution New Memory Solution The Reduction of Data Storage Time (7sec 7ms)
New Memory Applications High Speed Data Storage The Reduction of Data Storage Time (7sec 7ms) The Comparison of 2Mb PixelPicture Storage Time - VGA, 640x480, 420KB Block Erase Program:7000ms NOR Flash NAND Flash New Memory 1x 245ms 35x 7ms 1,000x The possibility of Motion Picture or Continuous Taking Photos Emerging Memory Devices
MRAM ( Magnetic RAM ) FRAM ( Ferroelectric RAM ) PRAM ( Phase-Change RAM ) CellSw. Speed High Speed (~10ns) High Speed(~10ns) Moderate Speed (>100ns ) Density Low Density Very Low Density High Density Potential Tunnel Ox. Control ( 1015 105 >1013 Read time 10 ns 2 ns 25 s 70 ns Write time 300 s 10 s 5 ns 200 ns Commercially available memories
DRAM SRAM NAND Flash NOR FRAM Memory capacity 1Gb 64 Mb 2 Gb 128 Mb 256 Kb Tech. node 90 nm 100 nm 120nm 350 nm Cell Area Factor (F2) 8 90 5.3 11 80 New types of memories are only at the early stage of verification or creating niche market, despite its great potentials FRAM passed the criteria of commercial product but its density is still very low Contents Introduction
Opportunities and Reality of New Types of Memories Technology Scaling and Technology Barriers of New Memories 1)FRAM 2)MRAM 3)PRAM 4.Summary Technology Scaling of FRAM
Cell area scaling WL BL F-Cap. 1.Larger capacitor area for given footprint 2.Larger remnantpolarization 3.Thinner ferroelectric film Nonvolatile loose constraint on array transistor Cell Area Scaling of FRAM
3-mask etch Separate via & plate 700nm cap stack 1-mask etch Common via & plate 300nm cap stack 3D capacitor Etchless capacitor Technology Barriers of FRAM
Ferroelectric film thickness scale down Degradation of electrical and physical properties Lower thickness limit few nm ? Need new growth technique! Technology Barriers of FRAM
Reliability requirement -Endurance > 1014 cycles -Retention time > 10 85C 50nm thick MOCVD PZTon Ir Deposition Temp. : 530o C Fatigue stress : 125oC Bake Contents Introduction
Opportunities and Reality of New Types of Memories Technology Scaling and Technology Barriers of New Memories 1)FRAM 2)MRAM 3)PRAM 4.Summary MRAM Operations Magnetic tunneling resistance variation
depending onrelative magnetization directions of electrode Rap Rp Al2O3 NiFe CoFe Rp Rap Requirements for proper operations
2. Immunity to writing disturbance Resistance uniformity R Distribution Hard axis field (Oe) Easy axis field Write Window Reference 1.0 Sensing noise PDF 0.5 0 1 0.0 8 10 R ( k W ) 12 14 16 Only MTJs at the crosspoint of bit-line and digit-line should be switched - Small ditribution of switching field - Asteroid curve close to L-shape Large MR ratio Small distribution of resistance Technology Barriers of MRAM
Small sensing signal TMR ratio = Rap Rp Rp Maximum TMR ratio ?60% so far. Resistance variation Exponential dependence on Al2O3 thickness Technology Barriers of MRAM
Writing Disturbance Operating condition Possible fail with Disturbance Need to decrease switching field distribution - Roughness - MTJ shape - MTJ aspect ratio - Free layer magnetization - Free layer thickness Technology Barriers of MRAM
Scaling trend ofwritingcurrent Smaller MTJ size Higher switching field Higher writing current - Power consumption increase - Chip size increase - Reliability issues Improved by flux concentrating layer DL BL 0.45 m 0.2 m -100 -50 50 100 -200 200 Bit line field (Oe) Digit line field (Oe) 1.2x0.6 m 2 0.8x0.4 0.4x0.2 NiFe Prospects for MRAM Nearly ideal memory
-Non-volatile, fast read and write, unlimited endurance Many technical barriers Scaling issues large cell size - SOC chip application is more suitable than stand-alone memory application Contents Introduction
Opportunities and Reality of New Types of Memories Technology Scaling and Technology Barriers of New Memories 1)FRAM 2)MRAM 3)PRAM 4.Summary PRAM Operations Reversible phase change of chalcogenide (Ge2Sb2Te5)
Phase change by heating current control Amorphizing RESET Pulse (~few ns) Crystallizing SET Pulse ~50ns Tm Tx Time Temp BEC Crystalline Top Electrode Bottom Electrode Low resistance SET state : 0 High resistance RESET state : 1 BEC Top Electrode Bottom Electrode Amorphous Cell area scaling PRAM density vs writing current
(NMOS Cell Tr) Need enough cell transistor width to flow required writing current Cell area is mainly determined by cell transistor width Technology Barriers of PRAM
Large writing current - Require large cell transistor Cell area increase - Reliability degradation - Current scales down with contact and GST size ! 0.66x1.28 0.72x0.72 0.66x0.66 0.62x0.62 0.56x0.56 0.48x0.48 0.40x0.40 1.5 2.0 2.5 3.0 3.5 Reset Current ( mA ) GST Size PRAM Writing Current Reduction
Edge contact cell M0 BEC BE GST TEC M1 Contact area is controlled by BE thickness & width more small and uniform contact area Reset current reduction by more than 80% Prospects for PRAM Writing current reduction new structure, new material Intrinsic advantage for size scaling -High density Feasibility -Stand-alone memory with moderate speed (Possibility of NOR flash replacement) Contents Introduction
Opportunities and Reality of New Types of Memories Technology Scaling and Technology Barriers of New Memories 1)FRAM 2)MRAM 3)PRAM 4.Summary Summary Assessment of memory products
- We needto consider functional and cost aspects at the same time - Functional aspect : random access, speed, non-volatility, endurance, - Cost aspect : technical complexity, technical barrier, technology scaling Prospects for Conventional memories - Non-ideal functional aspects - Excellent cost aspects - Will be dominant players down to 30~50nm technology node Summary Prospects for New types of memory
- Manufacturing and cost aspects are not properly evaluated yet 1) FRAM : No serious limitations in theory except ferroelectric film thickness 2) MRAM : Excellent device characteristics, Scaling difficulty Suitable for SOC chip application 3) PRAM : Less technical barriers compared to FRAM and MRAM Intrinsic advantage for size scaling - Future of emerging memory depend on how far we can keep its key attributes ( ferroelectric cap in FRAM, MTJ in MRAM, reset current in PRAM)