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1/60 Digital Integrated Circuits2nd

Sequential Circuits

Digital Integrated

CircuitsA Design Perspective

Designing Sequential

Logic Circuits

Jan M. Rabaey

Anantha ChandrakasanBorivoje Nikolic

November 2002

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Sequential Circuits

Sequential Logic

2 storage mechanisms

positive feedback

charge-based

COMBINATIONALLOGIC

Registers

Outputs

Next state

CLK

Q D

Current State

Inputs

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Sequential Circuits

Naming Conventions

In our text:

a latch is level sensitive

a register is edge-triggered

There are many different namingconventions

For instance, many books call edge-

triggered elements flip-flops This leads to confusion however

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Sequential Circuits

Latch versus Register

Latchstores data when

clock is low

D

Clk

Q D

Clk

Q

Register

stores data when

clock rises

Clk Clk

D D

Q Q

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Digital Integrated Circuits2ndSequential Circuits

Latches

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Latch-Based Design

N latch is transparent

when f= 0P latch is transparent

when f= 1

N

LatchLogic

Logic

P

Latch

f

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Characterizing Timing

Clk

D Q

tC2 Q

Clk

D Q

tC2 Q

tD2 Q

Register Latch

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Maximum Clock Frequency

FF

s

LOGIC

tp,comb

f

Also:tcdreg+ tcdlogic> thold

tcd: contamination delay =minimum delay

tclk-Q+ tp,comb + tsetup= T

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Positive Feedback: Bi-StabilityVo1

V

i25Vo1

Vi25Vo1

Vi1

A

C

B

Vo2

Vi1=Vo2

Vo1 Vi2

Vi2=Vo1

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Meta-Stability

Gain should be larger than 1 in the transition region

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Writing into a Static Latch

CLK

CLK

CLK

D

Q D

CLK

CLK

D

Converting into a MUXForcing the state(can implement as NMOS-only)

Use the clock as a decoupling signal,that distinguishes between the transparent and opaque states

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Mux-Based Latches

Negative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

CLK

1

0D

Q 0

CLK

1D

Q

InClkQClkQ InClkQClkQ

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Mux-Based Latch

CLK

CLK

CLK

D

Q

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Mux-Based Latch

CLK

CLK

CLK

CLK

QM

QM

NMOS only Non-overlapping clocks

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Master-Slave (Edge-Triggered)

Register

Two opposite latches trigger on edgeAlso called master-slave latch pair

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Master-Slave Register

QM

Q

D

CLK

T2I2

T1I1

I3 T4I5

T3I4

I6

Multiplexer-based latch pair

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Setup Time

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Reduced Clock Load

Master-Slave Register

DQT1 I1

CLK

CLK

T2

CLK

CLKI2

I3

I4

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Avoiding Clock Overlap

CLK

CLK

A

B

(a) Schematic diagram

(b) Overlapping clock pairs

X

D

Q

CLK

CLK

CLK

CLK

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Overpowering the Feedback Loop

Cross-Coupled Pairs

Forbidden State

S

S

R

Q

Q

Q

QRS Q

Q00 Q101 0

010 1

011 0RQ

NOR-based set-reset

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Cross-Coupled NAND

S

Q

Q

M1

M2

M3

M4

Q

M5S

M6CLK

M7 R

M8 CL

VDD

Q

Cross-coupled NANDsAdded clock

This is not used in datapaths any more,but is a basic building memory cell

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Sizing Issues

Output voltage dependenceon transistor width

Transient response

4.03.53.0

W/L5 and 6

(a)

2.52.00.0

0.5

1.0

1.5

2.0

Q(Volts)

time (ns)

(b)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

1

2

W = 1 m

3

Volts

Q S

W = 0.9 m

W = 0.8 m

W = 0.7 m

W = 0.6 m

W = 0.5 m

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Making a Dynamic Latch Pseudo-Static

D

CLK

CLK

D

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More Precise Setup Time

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Clk-Q Delay

TSetup-1

TClk-Q

Time

Setup/Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

Timet=0

ClockDataT

Setup-1

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Clk-Q Delay

TSetup-1

TClk-Q

Time

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

Timet=0

ClockDataT

Setup-1



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Clk-Q Delay

TSetup-1

TClk-Q

Time

Timet=0

ClockDataT

Setup-1



D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

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Clk-Q Delay

TSetup-1

TClk-Q

Time

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

Timet=0

ClockDataT

Setup-1



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Timet=0

ClockDataT

Setup-1

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1



Clk-Q Delay

TSetup-1

TClk-Q

Time

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Hold-1 case

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

Timet=0

DataClockT

Hold-1

0

Clk-Q Delay

THold-1

TClk-Q

Time

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Clk-Q Delay

THold-1

TClk-Q

Time

Timet=0

DataClockT

Hold-1


Hold-1 case

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

0

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Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

Timet=0

DataClockT

Hold-1


Hold-1 case

0

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Digital Integrated Circuits2nd Sequential Circuits

Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

Timet=0

Clock

THold-1

Data


Hold-1 case

0

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Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

Timet=0

Clock

THold-1

Data


Hold-1 case

0

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Other Latches/Registers: C2MOS

M1

D Q

M3CLK

M4

M2

CLK

VDD

CL1

X

CL2

Master Stage

M5

M7CLK

CLK M8

M6

VDD

Slave Stage

Keepers can be added to make circuit pseudo-static

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Insensitive to Clock-Overlap

M1

D Q

M4

M2

0 0

VDD

X

M5

M8

M6

VDD

(a) (0-0) overlap

M3

M1

D Q

M2

1

VDD

X

M71

M5

M6

VDD

(b) (1-1) overlap

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Pipelining

REG

REG

REG

logCLK

CLK

CLK

Out

REG

REG

REG

log

a

CLK

CLK

CLK

REG

CLK

REG

CLK

Out

b

Reference Pipelined

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Other Latches/Registers: TSPC

CLKn

VDD

CLK

VDD

In

Out

CLK

VDD

CLK

VDD

Out

Negative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

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Including Logic in TSPC

CLKn CLK

VDDVDD

Q

PUN

PDN

CLK

VDD

Q

CLK

VDD

In1

In1 In2

In2

AND latchExample: logic inside the latch

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Pulse Triggered Latches

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Pulse-Triggered Latches

An Alternative Approach

Master-Slave

Latches

D

Clk

Q D

Clk

Q

Clk

DataD

Clk

Q

Clk

Data

Pulse-Triggered

Latch

L1 L2 L

Ways to design an edge-triggered sequential cell:

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Pulsed Latches

CLKGD

VDD

M3

M2

M1

CLKG

VDD

M6

Q

M5

M4

CLK

CLKG

VDD

X

MP

MN

(a) register (b) glitch generation

CLK

CLKG

(c) glitch clock

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Pulsed Latches

Hybrid Latch Flip-flop (HLFF), AMD K-6 and K-7 :

P1

M3

M2D

CLK

M1

P3

M6

Qx

M5

M4

P2

CLKD

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Hybrid Latch-FF Timing

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N Bi t bl S ti l Ci it

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Non-Bistable Sequential Circuits

Schmitt Trigger

In Ou t

Vin

Vout VOH

VOL

VM VM+

VTC with hysteresis

Restores signal slopes

N i S i i S h itt

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Noise Suppression using Schmitt

Trigger

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CMOS Schmitt Trigger

Moves switching thresholdof the first inverter

Vin

M2

M1

VDD

X Vout

M4

M3

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Schmitt Trigger Simulated VTC

2.5

VX(V) VM2

VM1

Vin(V)

Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of thePMOS deviceM4. The width isk* 0.5 m.m

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

2.5

Vx(V)

k= 2k= 3

k= 4

k= 1

Vin(V)

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

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CMOS Schmitt Trigger (2)

VDD

VDD

Outn

M1

M5

M2

X

M3

M4

M6

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Multivibrator Circuits

Bistable Multivibrator

Monostable Multivibrator

Astable Multivibrator

flip-flop, Schmitt Trigger

one-shot

oscillator

S

R

T

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Transition-Triggered Monostable

DELAY

td

In

O u t

td

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Monostable Trigger (RC-based)

VDD

I n

OutA B

C

R

I n

B

Ou tt

VM

t2t1

(a) Trigger circuit.

(b) Waveforms.

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Astable Multivibrators (Oscillators)

0 1 2 N-1

Ring Oscillator

simulated response of 5-stage oscillator

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Relaxation Oscillator

Out2

CR

Out1

Int

I1 I2

T= 2 (log3) RC

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Voltage Controller Oscillator (VCO)

In

VDD

M3

M1

M2

M4

M5

VDD

M6

Vcontr Current starved inverter

Iref Iref

Schmitt Trigger

restores signal slopes

0.5 1.5 2.5V

c o n t r (V)

0.0

2

4

6

tpHL

(nsec)

propagation delay as a functionof control voltage

Differential Delay Element and VCO

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Differential Delay Element and VCO

in2

two stage VCO

v1

v2

v3

v4

Vctrl

Vo2 Vo1

in1

delay cell

simulated waveforms of 2-stage VCO

0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

2 0.51.5

V1 V2 V3 V4

time (ns)

2.5 3.5

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