GS66504B-EVBDB GaN E-HEMT Daughter Board and … · i8271 Iso. Gate Driver Q1 Si827 1Iso. Q2 Gate Driver Iso. DC/DC or ... RS1/CS1 and RS2/CS2 are place holders to allow user to experiement

GS66504B-EVBDB 650V GaN E-HEMT Evaluation Board

User’s Guide _____________________________________________________________________________________________________________________

GS66504B-EVBDB UG rev. 161120 © 2016 GaN Systems Inc. www.gansystems.com 1

Please refer to the Evaluation Board/Kit Important Notice on page 29

GS66504B-EVBDB GaN E-HEMT Daughter Board and GS665MB-EVB Evaluation Platform

User’s Guide

Visit www.gansystems.com for the latest version of this user’s guide.

DANGER! This evaluation kit is designed for engineering evaluation in a controlled

lab environment and should be handled by qualified personnel ONLY.

High voltage will be exposed on the board during the test and even brief

contact during operation may result in severe injury or death.

Never leave the board operating unattended. After it is de-energized,

always wait until all capacitors are discharged before touching the board.

CAUTION:

This product contains parts that are susceptible to damage by electrostatic

discharge (ESD). Always follow ESD prevention procedures when

handling the product.

http://www.gansystems.com/


User’s Guide _____________________________________________________________________________________________________________________



Overview

The GS665XXX-EVBDB daughter board style evaluation kit consists of two GaN Systems 650V GaN

Enhancement-mode HEMTs (E-HEMTs) and all necessary circuits including half bridge gate drivers,

isolated power supplies and optional heatsink to form a functional half bridge power stage. It allows

users to easily evaluate the GaN E-HEMT performance in any half bridge-based topology, either with the

universal mother board (P/N: GS665MB-EVB) or users’ own system design.

Features:

Serves as a reference design and evaluation tool as well as deployment-ready solution for easy in-

system evaluation.

Vertical mount style with height of 35mm, which fits in majority of 1U design and allows

evaluation of GaN E-HEMT in traditional through-hole type power supply board.

Current shunt position for switching characterization testing

Universal form factor and footprint for all products

The daughter board and universal mother board ordering part numbers are below:

Table 1 Ordering part numbers

Part Number GaN E-HEMT P/N: Description

GS66502B-EVBDB GS66502B GaN E-HEMT 650V/7.5A, 200mΩ

GS66504B-EVBDB GS66504B GaN E-HEMT 650V/15A, 100mΩ

GS66508B-EVBDB GS66508B GaN E-HEMT 650V/30A, 50mΩ

GS66508T-EVBDB GS66508T GaN E-HEMT top side cooled 650V/30A, 50mΩ

GS66516T-EVBDB GS66516T GaN E-HEMT top side cooled 650V/60A, 25mΩ

GS665MB-EVB Universal 650V Mother Board

Control and Power I/Os:

The daughter board GS665XXX-EVBDB circuit diagram is shown in Figure 1. The control logic inputs on

2x3 pin header J1 are listed below:

Table 2 Control pins

Pin Descriptipon

ENA Enable input. It is internally pulled up to VCC, a low logic disables all the PWM gate

drive outputs.

VCC +5V auxillary power supply input for logic circuit and gate driver. On the daughter

board there are 2 isolated 5V to 9V DC/DC power supplies for top and bottom switches.

VDRV Optional 9V gate drive power input. This pin allows users to supply separate gate drive

power supply. By default VDRV is connected to VCC on the daughter board via a 0 ohm

jumper FB1. If bootstrap mode is used for high side gate drive, connect VDRV to 9V

PWMH High side PWM logic input for top switch Q1. It is compatible wth 3.3V and 5V

PWML Low side PWM logic input for bottom switch Q2. It is compatible wth 3.3V and 5V

0V Logic inputs and gate drive power supply ground return.


User’s Guide _____________________________________________________________________________________________________________________



The 3 power pins are:

VDC+: Input DC Bus voltage

VSW: Switching node output

VDC-: Input DC bus voltage ground return. Note that control ground 0V is isolated from VDC-.

Figure 1 GS665XXX-EVBDB Evaluation Board Block Diagram

GS66504B-EVBDB half bridge daughter board

Figure 2 GS66504B-EVBDB top side

Si8271 Iso.

Gate DriverQ1

Q2Si8271 Iso.

Gate Driver

Iso. DC/DC

or Bootstrap

Iso. DC/DC

VDC+

VSW

VDC-

VCC

ENABLE

JP1

C4-10

PWMH

PWML


User’s Guide _____________________________________________________________________________________________________________________



Figure 3 GS66504B-EVBDB bottom side

A. 2x GaN Systems 650V E-HEMT GS66504B, 15A/100mΩ

B. Decoupling capacitors C4-C11

C. Isolated gate driver Silab Si8271GB-IS

D. Optional current shunt position JP1.

E. Test points for bottom Q2 VGS.

F. Recommended probing positions for Q2 VDS.

G. Optional RC Snubber (RS1/CS1, RS2/CS2), not populated

H. 5V-9V isolated DC/DC gate drive power supply

GaN E-HEMTs:

This daughter board includes two GaN Systems E-HEMT GS66504B (650V/15A, 100mΩ) in a

GaNPx™ B type package. The large S pad serves as source connection and thermal pad.

Figure 4 Package outline of GS66504B


User’s Guide _____________________________________________________________________________________________________________________



Gate drive power supply:

Bipolar gate drive bias with +6V and -3V for turning off is chosen for this design for more robust

gate drive and better noise immunity.

5V-9V isolated DC/DC converters are used for gate drive. 9V is then splited into +6V and -3V bias

by using 6V Zener diode

By default gate drive supply input VDRV is tied to VCC +5V via 0Ω jumper (FB1). Remove FB1 if

separate gate drive input voltage is to be used.

Gate driver circuit:

Silab Si8271GB-IS (6V gate drive) or Si8271AB-IS (6/-3 gate bias) isolated gate driver can be used

for this design. This driver is compatible with 6V gate drive with 4V UVLO and has CMTI dv/dt

rating up to 200V/ns. It has separated source and sink drive outputs which eliminates the need

for additional diode.

GaN E-HEMT switching speed and slew rate can be directly controlled by the gate resistor. By

default the turn-on Rgate (R6/R12) is 15Ω and turn-off gate resistor (R7/R14) is 2Ω. User can

adjust the values of gate resistors to fine tune the turn-on and off speed.

FB1/FB2 are 0603 footprints for optional ferrite beads for damping gate ringing/oscillation. By

default they are populated with 0Ω jumpers. If gate oscillation is observed, it is recommended to

replace them with ferrite bead with Z=10-20Ω@100MHz.

Figure 5 Gate driver circuit

RC Snubber:

RS1/CS1 and RS2/CS2 are place holders to allow user to experiement with RC snubber circuit (not

installed). At high frequency operation the power dissipation for RS1/RS2 needs to be closely watched

and CS1/CS2 should be sized correctly. It is recommended to start with 33-47pF and 10-20Ω.

PS2

PES1-S5-S9-M

GND1

VIN2

+VO5

0V4

NC

8

0V

VDRV

C144.7uFC0805 C16

4.7uFC0805

R93.3K

LED2

LED-0603

VDDL_+9V

U4

SI8271GB-IS

VI1

VDDI2

GNDI3

EN4

GNDA5

VO-6

VO+7

VDD8PWML

JP1

CON-JMP-CSHUNT

VDDL_+6V

GNDL

C154.7uFC0805

DZ2

6.2VSOD323-ACA

C

R161K

C214.7uFC0805

VEEL

VEEL

GNDL

C22

1uF

GNDL

FB1

0R

VDRV VCC_+5V

R103.3K

R11

10R

PWML_IN

PGND

Q2S

Q2

GS66504B

1

2

3

ENABLE

R133.3K

Q2GFB3

0R

R12

15R

R14

2R

Q2_GOUTQ2_VO+

GNDL

Q2_VO-

C17

1uF

RS233RR1206

CS2100p 1kVC1206

VDDL_+6V

DNP

C181uF

DNP

0V

VCC_+5V


User’s Guide _____________________________________________________________________________________________________________________



Current shunt JP1:

The board provides an optional cuwwwrrent shunt position JP1 between the source of Q2 and

power ground return. This allows drain current measurement for switching characterization test

such as Eon/Eoff measurement.

The JP1 footprint is compatible with T&M Research SDN series coaxial current shunt

(recommended P/N: SDN-414-10, 2GHz B/W, 0.1Ω)

If current shunt is not used JP1 must be shorted. JP1 affects the power loop inductance and its

inductance should be kept as low as possible. Use a copper foil or jumper with low inductance.

CAUTION:

Check the JP1 before the first time use. To complete the circuit JP1 needs to

be either shorted or a current shunt must be inserted before powering up.

Figure 6 Current shunt position JP1

Measurement with current shunt:

1. When measuring VSW with current shunt, ensure all channel probe grounds and current shunt

BNC output case are all referenced to the source end of Q2 before the current shunt. The

recommended setup of probes is shown as below.

2. The output of coaxial current shunt can be connected to oscilloscope via 50Ω termination

impedance to reduce the ringing.

3. The measured current is inverted and can be scaled by using: Id=Vid/Rsense.

Current

Shunt

Q2 Source VDC-


User’s Guide _____________________________________________________________________________________________________________________



Figure 7 Recommended probe connection with current shunt

Thermal design:

1. GS66504B has a thermal pad at the bottom side for heat dissipation. The heat is transferred to the

bottom side of PCB using thermal vias and copper plane.

2. A heatsink (35x35mm size) can be attached to the bottom side of board for optimum cooling.

Thermal Interface Material (TIM) is needed to provide electrical insulation and conformance to

the PCB surface. The daughter board evaluation kit supplies with a sample 35x35mm fin heatsink

(not installed), although other heatsinks can also be used to fit users’ system design.

3. A thermal tape type TIM (Berguist® Bond-Ply 100) is chosen for its easy assembly. The supplied

heatsink has the thermal tape pre-applied so simply peel off the protective film and attach the

heatsink to the back of board as marked in Figure 3.

4. Forced air cooling is recommended for power testing.

Figure 8 The daughter board with heatsink attached

CAUTION:

There is no on-board over-temperature protection. Device temperature must

be closely monitored during the test. Never operate the board with device

temperature exceeding TJ_MAX (150°C)

VGL

VSL

VSW

BNC case

To oscilloscope

probe input (use

50Ω termination)

BNC tip

VDS

VGS

ID


User’s Guide _____________________________________________________________________________________________________________________



Using GS665XXX-EVBDB with universal mother board GS665MB-EVB

Figure 9 650V universal mother board GS665MB-EVB

GaN Systems provides a universal 650V mother board (ordering part number: GS665MB-EVB, sold

separately) that can be used as the basic evaluation platform for all the daughter boards.

The universal 650V mother board evaluation kit includes following items:

1. Mother board GS665MB-EVB

2. 12VDC Fan

12V input:

The board can be powered by 9-12V on J1. On-board voltage regulator creates to 5V for daughter board

and control logic circuits. J3 is used for external 12VDC fan.

PWM control circuit:

12V INPUT

(+)5V Power Supply

CIN

VSW

PWM control & dead

time circuit

Daughter Board

Probing point for VSW

For Ext.

12VDC Fan

Airflow direction

Optional CoutVDC- VOUT

VDC-

VDC+


User’s Guide _____________________________________________________________________________________________________________________



Figure 10 PWM control input and dead time circuit

Figure 11 On board dead time generatrion circuit

The top and bottom switches PWM inputs can be individually controlled by two jumpers J4 and J6. Users

can choose between a pair of complementary on-board internal PWM signals (non-inverted and inverted,

controlled by J7 input) with dead time or external high/low side drive signals from J5 (users’ own control

board).

An on-board dead time generation circuit is included on the mother board. Dead time is controlled by

two RC delay circuits, R6/C12 and R5/C11. The default dead time is set to about 100ns. Additionally two

potentiometers locations are provided (TR1/TR2, not included) to allow fine adjustment of the dead time

if needed.

0V

D1 PMEG2005EB

SOD523

R6

1K00

TR12K C11100pF

0V

R5

1K00

C10

1uF

C9

0.1uF

+5V

J7112538

1

2345

R4100RR1206

R2100RR1206

U2A

74VHC132

31

2

14

7

0V

R1

49R9

0V

D2 PMEG2005EB

SOD523

TR22K

C12100pF

0V

U2B

74VHC132

4

56

U2C

74VHC132

9

108

U2D

74VHC132

12

1311

TP7

TP8

DNP

DNP

PWM OUTPUT

INVERTED PWM OUTPUT

R3

49R9

DNPDNP

R7

49R9


User’s Guide _____________________________________________________________________________________________________________________



WARNING!

ALWAYS double check the jumper setting and PWM gate drive signals

before applying power. Incorrect PWM inputs or jumper settings may cause

device failures

Test points:

Test points are designed in groups/pairs to facilitate probing:

Test points Name Description

TP1/TP2 +5V/0V 5V bias power

TP7/TP8 PWMIN/0V PWM input signal from J7

TP4/TP3/TP13 PWMH/PWML/0V High/low side gate signals to daughter board

TP9/TP10 VDC+/VDC- DC bus voltage

TP11/TP12 VOUT/VDC- Output voltage

TP6/TP5 VSW/VDC- Switching node output voltage (for HV oscilloscope

probe)

Power connections:

CON1-CON7 mounting pads are designed to be compatible with following mounting terminals:

#10-32 Screw mount,

Banana Jack PCB mount (Keystone P/N: 575-4), or

PC Mount Screw Terminal (Keystone P/N: 8191)

Output passives (L and C14)

An external power inductor (not included) can be connected between VSW (CON1) and VOUT (CON4/5)

or VDC+ (CON2/3) for double pulse test. Users can choose their inductor size to meet the test

requirement. Generally it is recommended to use power inductor with low inter-winding capacitance to

obtain best switching performance. For the double pulse testing we use 2x 60uH/40Amp inductor (CWS,

P/N: HF467-600M-40AV) in series. C14 is designed to accommodate a film capacitor as output filter.

Double pulse test mode


User’s Guide _____________________________________________________________________________________________________________________



CON1

Q1

CON2

Q2

VDC-

CON4

CON3

LOUT

400V DC

+

VDC+

CON7CON6

VSW

CON5

+5V

0V

PWM

INPUT

(J7)

VDS

IL

ISW

VGL

+6V

0VVDS

VGL

IL

t0 t1 t2 t3TON1

Figure 12 Double pulse test setup

Double pulse test allows easy evaluation of device switching performance at high voltage/current

without the need of actually running at high power. It can also be used for switching loss (Eon/Eoff)

measurement and other switching characterization parameter test.

The circuit configuration and operating principle can be found in Figure 12:

1. The output inductor is connected to the VDC+.

2. At t0 when Q2 is switched on, the inductor current starts to ramp up until t1. The period of first

pulse Ton1 defines the switching current ISW = (VDS*TON1) / L.

3. t1-t2 is the free wheeling period when the inductor current IL forces Q1 to conduct in reverse.

4. t1 (turn-off) and t2 (turn-on) are of interest for this test as they are the hard switching trasients for

the half bridge circuit when Q2 is under high switching stress.

5. The second pulse t2-t3 is kept short to limit the peak inductor current at t3.

The double pulse signal can be generated using programmable signal generaotor or microcontroller/DSP

board. As this test involves high switching stress and high current, it is recommended to set the double

pulse test gate signal as single trigger mode or use long repetition period (for example >50-100ms) to void

excess stress to the switches. Q1 can be kept off during the test or driven synchronously (J4 set to OFF or

INT_INV) and Q2 is set to INT (or EXT position if PWM signal is from J5).

WARNING!

Limit the maximum switching test current to 15A and ensure maximum drain

voltage including ringing is below 650V for pulse testing. Exceeding this limit

may cause damage to the devices.

Buck/Standard half bridge mode


User’s Guide _____________________________________________________________________________________________________________________



CON1

Q1

CON2

Q2

VDC-

CON4

CON3

LOUT

400V DC

+

VDC+

CON7

CON6

VSW

CON5

COUT RLoad

This is standard half bridge configuration that can be used in

following circuits :

Synchronous Buck DC/DC

Single phase half bridge inverter

ZVS half bridge LLC

Phase leg for full bridge DC/DC or

Phase leg for a 3-phase motor drive

Jumper setting:

J4 (Q1): INT

J6 (Q2): INT_INV

Boost mode

CON1

Q1

CON2

Q2

VDC-

CON4

CON3

LIN

VDC+

CON7CON6

VSW

CON5

INPUT

VIN

When the output becomes the input and the load is

attached between VDC+ and VDC-, the board is

converted into a boost mode circuit and can be used for:

Synchronous Boost DC/DC

Totem pole bridgeless PFC

Jumper setting:

J4 (Q1): INT_INV

J6 (Q2): INT


User’s Guide _____________________________________________________________________________________________________________________



Using GS665XXX-EVBDB in system:

The daughter board allows users to easily evaluate the GaN performance in their own systems. Refer to

the footprint drawing of GS665XXX-EVBDB as shown below:

Figure 13 Recommended footprint drawing of daughter board GS665XXX-EVBDB

1 3 5

2 4 6

78 9

1. All units are in mm.

2. Pin 1-6: Dia. 1mm

3. Pin 7-9: 1.91mm (75mil) mounting hole for Mill-max Receptacle P/N: 0312-0-15-15-34-27-10-0.


User’s Guide _____________________________________________________________________________________________________________________



Quick Start procedure – Double pulse test

Follow the instructions below to quickly get started with your evaluation of GaN E-HEMT. Equipment

and components you will need:

Four-channel oscilloscope with 500MHz bandwidth or higher

high bandwidth (500MHz or higher) passive probe

high bandwidth (500MHz) high voltage probe (>600V)

AC/DC current probe for inductor current measurement

12V DC power supply

Signal generator capable of creating testing pulses

High voltage power supply (0-400VDC) with current limit.

External power inductor (recommend toroid inductor 50-200uH)

1. Check the JP1 on daughter board GS665XXX-EVBDB. Use a copper foil and solder to short JP1.

2. Install GS665XXX-EVBDB on the mother board. Press all the way down until you feel a click. Connect

probe between VGL and VSL for gate voltage measurement.

3. Set up the mother board:

a. Connect 12VDC bias supply to J1.

b. Connect PWM input gate signal (0-5V) to J7. If it is generated from a signal generator ensure

the output mode is high-Z mode.

c. Set J4 to OFF position and J7 to INT.

d. Set High voltage (HV) DC supply voltage to 0V and ensure the output is OFF. Connect HV

supply to CON2 and CON6.

e. Use HV probe between TP6 and TP5 for Vds measurement.

f. Connect external inductor between CON1 and CON3. Use current probe to measure inductor

current IL.

4. Set up and check PWM gate signal:

a. Turn-on 12VDC power.

b. Check the 2 LEDs on the daughter board. They should be turned on indicating the isolated

9V is present.

c. Set up signal generator to create the waveforms as shown in Figure 12. Use equation ISW =

(VDS*TON1) / L to calculate the pulse width of the first pulse and ensure the Isw_max is ≤15A at

400VDC.

d. Set the operation mode to either single trigger or Burst mode with repetition period of 100ms.

e. Turn on the PWM output and check on the oscilloscope to make sure the VGL waveform is

present and matches the PWM input.

5. Power-on:

a. Turn on the output of the HV supply. Start with low voltage and slowly ramp the voltage up

until it reaches 400VDC. During the ramping period closely observe the the voltage and

current waveforms on the oscilloscope.

6. Power-off:

a. After the test is complete, slowly ramp down the HV supply voltage to 0V and turn off the

output. Then turn off the 12V bias supply and signal generator output.


User’s Guide _____________________________________________________________________________________________________________________



Figure 14 Double pulse test setup example (GS66504B-EVBDB)


User’s Guide _____________________________________________________________________________________________________________________



Test results – GS66504B-EVBDB

Half bridge double pulse test (VDS=400V, IMAX = 15A, L=120uH, RG(ON)=15Ω, RG(OFF)=2Ω, VGS=+6/-3V):

Figure 15 400V/15A double pulse test waveform

Figure 15 shows the hard switching on waveforms at 400V/15A. A Vds dip can be seen due to the rising

drain current (di/dt in the power loop ΔV=Lpxdi/dt, where Lp is the total power loop inductance). After

the drain current reaches the inductor current, the Vds starts to fall. The Vgs undershoot spike is caused

by the miller feedback via Cgd under negative dv/dt.

Due to the low gate charge and small RG(OFF) , GaN E-HEMT gate has limited control on the turn-off

dv/dt. Instead the Vds rise time is determined by how fast the turn-off current charges switching node

capacitance (Coss).

The low Coss of GaN E-HEMT and low parasitic inductance of GaNPX™ package together with

optimized PCB alyout, enables a fast and clean turn-off Vds waveform with only 50V the turn-off Vds

overshoot at dv/dt > 100V/ns. The measured rise time is 3.9ns at 400V and 15A hard turn-off。


User’s Guide _____________________________________________________________________________________________________________________



a) hard switching turn-on 400V/15A (tf=5.9ns) b) hard switching turn-off 400V/15A

Figure 16 Double puls test switching transient waveforms

Switching Loss energy (Eon/Eoff) measurement

A T&M search coaxial current shunt (SDN-414-10, 0.1Ω) is installed for switching loss measurement as

shown below.

Figure 17 Eon/Eoff measurement probe connection with current shunt


User’s Guide _____________________________________________________________________________________________________________________



Figure 18 Eon/Eoff measurement and test bench setup

The switching energy can be calculated from the measured switching waveform Psw = Vds*Id. The

integral of the Psw during switching period is the measured switching loss. The channel deskewing is

critical for measurement accurary. It is recommended to manually deskew Id against Vds as shown in

Figure 19. The drain current spike is caused by charging the high side switch Coss (Qoss loss).

Figure 19 Turn-on switching loss measurement (Eon=41uJ, 400V/15A)


User’s Guide _____________________________________________________________________________________________________________________



Figure 20 Turn-off switching loss measurement (Eoff=5.5uJ, 400V/15A)

The switching loss measurements with drain current from 0 to 15A can be found in Figure 21. The turn-

on loss dominates the overall hard switching loss. Eon at 0A is the Qoss loss caused by charging Coss at

high side switch.

The turn-off loss remain almost constant from 0A up to 10A about 3.6uJ. the measured Eoff matches well

with the Eoss @400V, which indicates that turn-off energy is dominated by Eoss, the energy required to

charge Coss from 0V to bus voltage. This energy is not part of loss at turn-off, but actually part of turn-on

loss at next hard switching turn-on period. This means that with the fast turn-off speed the GaN E-HEMT

can achieve near zero turn-off switching loss.


User’s Guide _____________________________________________________________________________________________________________________



Figure 21 GS66504B Switching Loss Measurement (VDS = 400V, TJ=25°C)


User’s Guide _____________________________________________________________________________________________________________________



Synchronous Buck Test (L=120uH, VIN=400V, VOUT=200V, D=50%, FSW=100 kHz, POUT =750W)

The board is converted to a synchronous buck DC/DC converter and demonstrates efficiency 98.5% at

750W. With forced air cooling, the peak device temperature TJ_MAX was measured at 60°C at 750W output.

Figure 22 Synchronous Buck Efficiency and thermal measurement

Figure 23 Thermal image (Pout=750W)


User’s Guide _____________________________________________________________________________________________________________________



Appendix A - GS66504B-EVBDB

Circuit schematics

TP

1

TP

TH

-1M

MP

S2 PE

S1-S

5-S

9-M

GN

D1

VIN

2+V

O5

0V

4

NC8

Q1G

TP

2

TP

TH

-1M

M

0V

VD

RV

TP

4

TP

TH

-1M

M

C14

4.7

uF

C0805

Q2G

U2

SI8

271G

B-I

S

VI

1

VD

DI

2

GN

DI

3

EN

4G

ND

A5

VO

-6

VO

+7

VD

D8

TP

6

TP

TH

-1M

M

GN

DH

C16

4.7

uF

C0805

R9

3.3

K

LE

D2

LE

D-0

603

GN

DL

VD

DL_+9V

U4

SI8

271G

B-I

S

VI

1

VD

DI

2

GN

DI

3

EN

4G

ND

A5

VO

-6

VO

+7

VD

D8

D1

600V

1A

DO

-214A

C

TP

3

TP

TH

-1M

M

PH

R1

0R

R0805

DZ

1

6.2

VS

OD

323-A

C

AC

R15

1K

TP

5

TP

TH

-1M

M

Q2S

DNP

DNP

TP

7

TP

SM

D-1

mm

-cir

PW

MH

PW

ML

C19

4.7

uF

C0805

C3

4.7

uF

C0805

PR

OB

E T

ES

T P

OIN

T

INP

UT

CO

NN

EC

TO

RS

VD

DH

_+6V

TP

8

TP

SM

D-1

mm

-cir

TP

9

TP

SM

D-1

mm

-cir

VD

DL_+6V

TP

10

TP

SM

D-1

mm

-cir

J2 1 2 3 4 5 6

GN

DL

VE

EH

VC

C_+5V

VD

RV

0V

C4

C5

GN

DH

C6

C7

VIN

+

EN

AB

LE

PW

MH

_IN

PG

ND

PW

ML_IN

GN

DH

C20

1uF

GN

DH

JP

1

CO

N-J

MP

-CS

HU

NT

PH

R8

3.3

K

Q1G

VD

DL_+6V

C15

4.7

uF

C0805

GN

DL

DZ

2

6.2

VS

OD

323-A

C

AC

R16

1K

C21

4.7

uF

C0805

VE

EL

EN

AB

LE

VE

EL

GN

DL

C22

1uF

GN

DL

CO

N1

CO

N-E

DG

E-M

NT-3

260

CO

N2

CO

N-E

DG

E-M

NT-3

260

CO

N3

CO

N-E

DG

E-M

NT-3

260

VC

C_+5V

R2

3.3

KE

NA

BLE

PW

MH

_IN

FB

2

0R

PW

ML_IN

PS

1 PE

S1-S

5-S

9-M

GN

D1

VIN

2+V

O5

0V

4

NC8

VD

RV

0V

0V

R6

15R

R7

2R

Q1_G

OU

T

VD

RV

C1

4.7

uF

C0805

VD

DH

_+6V

GN

DH

FB

1

0R

VD

RV

VC

C_+5V

VS

W

VD

C+

VD

C-

PW

MH

_IN

R5

10R

Q1_V

O+

Q1_V

O-

GN

DH

R4

3.3

K

R10

3.3

K

C2

4.7

uF

C0805

R11

10R

PW

ML_IN

C9

C10

C12

1uF

C11

0.1

uF

1kV

C1812

PG

ND

VIN

-

Q2S

C8

VD

DH

_+6V

C13

1uF

VC

C_+5V

0V

Q1

GS

66504B

1

2

3

Q2

GS

66504B

1

2

3

R3

3.3

K

LE

D1

LE

D-0

603

VD

DH

_+9V

EN

AB

LE

R13

3.3

K

RS

133R

R1206

CS

1100p 1

kV

C1206

Q2G

FB

3

0R

R12

15R

DNP

DNP

R14

2R

Q2_G

OU

TQ

2_V

O+

GN

DL

Q2_V

O-

C17

1uF

RS

233R

R1206

CS

2100p 1

kV

C1206

VD

DL_+6V

C18

1uF

DNP

DNP

0V

VC

C_+5V

VE

EH

J1

12

34

56


User’s Guide _____________________________________________________________________________________________________________________



Assembly Drawing (Top)

Assembly Drawing (Bottom)


User’s Guide _____________________________________________________________________________________________________________________



PCB layout

Top Layer

Mid Layer 1

Mid Layer 2

Bottom Layer


User’s Guide _____________________________________________________________________________________________________________________



Bill of Materials

GS

66

50

2B

/04

B H

AL

F B

RID

GE

DA

UG

HT

ER

CA

RD

2

01

6-1

0-0

3

BO

AR

D N

AM

E:

GS

66

50

2B

/04

B-E

VB

DB

Re

vis

ion

A2

Assem

bly

Vari

an

ts

QtR

efe

ren

ce

Descri

pti

on

Valu

eP

ackag

e f

oo

tpri

nt

Man

ufa

ctu

rer

Part

nu

mb

er

Alt

Man

ufa

ctu

rer

Alt

part

nu

mb

er

GS

66502B

-

EV

BD

B

GS

66504B

-

EV

BD

BA

ssem

bly

No

te

1P

CB

PC

B b

are

4-layer

2oz C

u.

Shenzhen S

print

PC

B●

●

13

CO

N1,C

ON

2,C

ON

3C

ON

N P

C P

IN E

DG

E M

NT

C

ON

-ED

GE

-MN

T-3

260

con-e

dge-m

nt-

mill

max-

3260

Mill

-Max

3620-2

-32-1

5-0

0-0

0-0

8-0

●●

Mating r

ecepta

cle

:0312-0

-

15-1

5-3

4-2

7-1

0-0

on

moth

er

board

22

CS

1,

CS

2C

AP

, C

ER

, 100p,

1kV

, 1206

DO

NO

T IN

ST

ALL

38

C1,C

2,C

3,C

14,C

15,

C16,C

19,C

21

CA

P,

CE

R,

4.7

UF

, 25V

, +

/-

10%

, X

7R

, 0805

4.7

uF

C0805

TA

IYO

YU

DE

NT

MK

212A

B7475K

G-T

generic 2

5V

X7R

0805

●●

48

C4,C

5,C

6,C

7,C

8,C

9,

C10,C

11

CA

P,

CE

R,

0.1

UF

,1K

V,

+/-

10%

, X

7R

, 1812

0.1

uF

1kV

C1812

KE

ME

TC

1812C

104K

DR

AC

7800

●●

56

C12,C

13,C

17,C

18,C

20,C

22

CA

P,

CE

R,

1U

F,

25V

, +

/-

10%

, X

7R

, 0603

1uF

C0603

TA

IYO

YU

DE

NT

MK

107B

7105K

A-T

generic 2

5V

X7R

0603

●●

62

DZ

1,D

Z2

DIO

DE

ZE

NE

R 6

.2V

200M

W

SO

D323

6.2

V z

ener

SO

D323-A

CO

N S

EM

IM

M3Z

6V

2S

T1G

●●

71

D1

DIO

DE

ULT

RA

FA

ST

600V

1A

SM

A600V

1A

DO

-214A

CF

AIR

CH

ILD

ES

1J

DO

NO

T IN

ST

ALL

83

FB

1,F

B2,F

B3

RE

S,

0R

JU

MP

ER

, 1%

,

0603

30R

3A

R0603

generic

generic

●●

Use 0

OH

M J

UM

PE

R

91

JP

1C

UR

RE

NT

SH

UN

T J

UM

PE

RC

ON

-JM

P-C

SH

UN

TJP

-CS

HU

NT

DO

NO

T IN

ST

ALL

10

1J1

CO

NN

3P

IN D

UA

L R

OW

,

0.1

" P

ITC

H,

R/A

CO

N-H

DR

-2X

3con-2

X3-P

100-R

AS

AM

TE

CT

SW

-103-0

8-G

-D-R

AH

AR

WIN

IN

C.

M20-9

950345

●●

11

1J2

CO

N-6

PO

Scon-1

x6-p

100

FO

R F

CT

TE

ST

PO

INT

S,

DO

NO

T IN

ST

ALL

12

2LE

D1,L

ED

2LE

D,

GR

EE

N,

SM

D 0

603

LE

D-S

MD

-0603

LE

D-0

603

LIT

EO

NLT

ST

-C191K

GK

T●

●

13

2P

S1,P

S2

ISO

. D

C/D

C 5

-9V

, 1W

PE

S1-S

5-S

9-M

PS

-SM

D-P

ES

1-M

CU

IP

ES

1-S

5-S

9-M

MO

UR

NS

UN

F0509X

T-1

WR

2●

●

ALT

. P

AR

T M

OU

RN

SU

N

F0509X

T-1

WR

2

14

2Q

1,Q

2G

aN

E-H

EM

T 6

50V

GS

66502B

GA

NS

YS

-GS

66504B

GaN

Sy

ste

ms

GS

66502B

●

15

2Q

1,Q

2G

aN

E-H

EM

T 6

50V

GS

66504B

GA

NS

YS

-GS

66504B

GaN

Sy

ste

ms

GS

66504B

●

16

2R

S1.

RS

2R

ES

, 33R

, 1%

, 1206

10R

DO

NO

T IN

ST

ALL

17

1R

1R

ES

, 0R

, 1%

, 0805

0R

R0805

generic

generic

DO

NO

T IN

ST

ALL

18

7

R2,R

3,R

4,R

8,R

9,R

1

0,R

13

RE

S,

3.3

K,

1%

,1/1

0W

, 0603

3K

3R

0603

generic

generic

●●

19

2R

6,R

12

RE

S,

15R

, 1%

,1/1

0W

, 0603

15R

R0603

generic

generic

●●

20

2R

5,R

11

RE

S,

10R

, 1%

,1/1

0W

, 0603

10R

R0603

generic

generic

●●

21

2R

7,R

14

RE

S,

2R

, 1%

,1/1

0W

, 0603

2R

R0603

generic

generic

●●

22

2R

15,R

16

RE

S,

1K

, 1%

,1/1

0W

, 0603

1K

0R

0603

generic

generic

●●

23

6

TP

1,T

P2,T

P3,T

P4,T

P5,T

P6

Pro

be t

est

poin

tC

ON

-TP

-1P

OS

TP

TH

-1M

MD

O N

OT

IN

ST

ALL

24

4T

P7,T

P8,T

P9,T

P10

Pro

be t

est

poin

tC

ON

-TP

-1P

OS

TP

SM

D-1

mm

-cir

DO

NO

T IN

ST

ALL

25

2U

2,U

4IC

IS

O G

AT

E D

RIV

ER

2.5

KV

HIG

H C

MT

IS

I8271G

B-I

SS

OIC

-8S

ILIC

ON

LA

BS

SI8

271G

B-I

SS

I8271A

B-I

S●

●

26

1heats

ink,

35x3

5m

mx2

5.4

mm

, bla

ck a

nodiz

ed

SH

EN

ZH

EN

MIN

GZ

HI

PY

16-0

20-2

CO

OL IN

NO

VA

TIO

N3-1

41410U

BLA

N●

●

27

1E

lectr

ically

insula

ted T

herm

al pad

Berg

quis

tB

P100-0

.005-0

0-1

112

●●

Off

th

e b

oard

co

mp

on

en

ts:


User’s Guide _____________________________________________________________________________________________________________________



Appendix B - GS665MB-EVB

Circuit schematics

C1

4

10

uF

70

0V

FO

OTP

RIN

T F

OR

GS

665XX-E

VB

DB

M1

M2

M3

M4

PC

B S

TA

ND

OF

F 4

.75M

M M

NT H

OLE

KE

YS

TO

NE

8839-8

834

J1

1 2 VA

UX

_R

TN

U1 M

C7

80

5

IN1

OU

T3

GND4

C4

10u

C0

80

5

+5

VV

AU

X

0V

0V

CO

N2 1

CO

N61

EN

AB

LE

CO

N3 1

J5

12

34

5 76 8

0V

PW

M_

EXT

_H

PW

M_

INT

R6

1K

00

D1

PM

EG

20

05

EB

SO

D5

23

PW

M_

INT

_IN

V

TR

12K

C1

1100pF

0V

PW

M_

EXT

_L

PW

M_

INT

PW

M_

INT

_IN

V

VD

C-

R5

1K

00

C1

0

1uFC

9

0.1

uF

+5

V

J7

112538

1

2345

C1

3

10

uF

70

0V

R4

100R

R1

20

6

R2

100R

R1

20

6

U2

A

74

VH

C1

32

31 2

14 7

0V

R1

49

R9

0V

D2

PM

EG

20

05

EB

SO

D5

23

VD

C+

TR

22K

C1

2100pF

0V

U2

B

74

VH

C1

32

4 56

U2

C

74

VH

C1

32

9

10

8

U2

D

74

VH

C1

32

12

13

11

VD

C-

CO

N5 1

CO

N71

TP

3

TP

4

TP

1

TP

2

TP

7

+5

V

TP

8

0V

0V

VA

UX 1

2V

IN

EXTE

RN

AL P

WM

IN

PU

TTO

DS

P/M

CU

CO

NTR

OL B

OA

RD

PW

M IN

PU

T S

ELE

CTIO

N

ON

BO

AR

D D

EA

D T

IME

GE

NE

RA

TIO

N C

IRC

UIT

US

E T

R1 A

ND

TR

2 T

O A

DJU

ST D

EA

D T

IME

PO

S 2

/3:

IN

TE

RN

AL P

WM

SIG

NA

L

VO

UT

C1

22

0u

F 2

5V

CA

PA

L-P

AN

A-F

C2

1u

F 2

5V

VD

C_P

VD

C_N

VO

UT

+5V

VC

C

CO

N11

J31

1

22

TO

12V

FA

N

CO

N4 1

PO

S 1

: E

XT.

PW

M S

IGN

AL

DN

P

DN

P

DN

P

VS

W

TP

6

TP

9

TP

-KE

YS

TO

NE

-50

10

+5

V

PW

MH

_IN

TP

10

TP

-KE

YS

TO

NE

-50

10

TP

11

TP

-KE

YS

TO

NE

-50

10

TP

12

TP

-KE

YS

TO

NE

-50

10

TP

13

0V

+1

2V

PW

NL

_IN

PW

M

OU

TP

UT

INV

ER

TE

D

PW

M O

UTP

UT

VS

W

NO

TE

S -

UN

LE

SS

OTH

ER

WIS

E S

PE

CIF

IED

1.

ALL S

MD

RE

SIS

TO

RS

AN

D C

AP

AC

ITO

RS

AR

E 0

603 S

IZE

0V

0V

J2

12

34

56

J4

PO

S 4

: O

FF

C5

C6

T1

CM

C-0

8

14

23

J6

VD

RV

R3

49

R9

DN

PD

NP

+1

2V

R7

49

R9

C3

10u

C0

80

5

C7

C8

0.1

uF

1kV

C1

81

2V

DC

+

2.

DO

NO

T IN

STA

LL T

R1,T

R2,R

2,R

3 A

ND

C14

J8

1

J9

1

J1

01

TP

5


User’s Guide _____________________________________________________________________________________________________________________



Assembly drawing

Assembly Top

Assembly Bottom


User’s Guide _____________________________________________________________________________________________________________________



Bill of Materials

GA

N S

YS

TE

MS

65

0V

GA

N U

NIV

ER

SA

L M

OT

HE

R B

OA

TR

D

BO

AR

D P

/N:

GS

66

5E

VB

MB

Re

vis

ion

B1

La

st

Up

da

te6

/30

/20

16

Qu

an

tity

Re

fere

nc

eD

es

cri

pti

on

Va

lue

Ma

nu

fac

ture

rP

art

nu

mb

er

As

se

mb

ly N

ote

1P

CB

PC

B b

are

2-la

yer

2o

z C

u.

17

CO

N1

,CO

N2

,CO

N3

,CO

N4

,C

ON

5,C

ON

6,C

ON

7 T

ER

MIN

AL

SC

RE

W V

ER

TIC

AL

PC

MN

TC

ON

-10

-32

-SC

RW

MN

TK

EY

ST

ON

E8

19

1D

O N

OT

INS

TA

LL

21

C1

CA

P A

LU

M 2

20

UF

20

% 2

5V

SM

D

22

0uF

25

VP

ana

so

nic

EE

E-F

K1

E2

21

P

31

C2

,C1

0G

EN

ER

IC 1

UF

/25

V, 1

0%

X7

R S

MD

06

03

1uF

TA

IYO

YU

DE

NT

MK

10

7B

71

05

KA

-T

42

C3

,C4

GE

NE

RIC

10

UF

/25

V, 1

0%

SM

D 0

80

51

0uF

TA

IYO

YU

DE

NT

MK

21

2B

BJ1

06

KG

-T

54

C5

,C6

,C7

,C8

GE

NE

RIC

0.1

uF

/10

00

V, S

MD

18

12

0.1

uF

1kV

KE

ME

TC

18

12

C1

04

KD

RA

C7

80

0

61

C9

GE

NE

RIC

0.1

UF

/25

V, 1

0%

X7

R S

MD

06

03

0.1

uF

TA

IYO

YU

DE

NT

MJ1

07

BB

71

04

KA

HT

72

C1

1,C

12

GE

NE

RIC

10

0P

F/2

5V

5%

NP

0 S

MD

06

03

10

0p

FK

EM

ET

C0

60

3C

10

1J3

GA

CT

U

81

C1

3,C

14

CA

P F

ILM

10

UF

/60

0V

DC

5%

, 2

7.5

MM

LE

AD

SP

AC

ING

10

uF

70

0V

KE

ME

TC

4A

EH

BU

51

00

A1

1J

DO

NO

T IN

ST

AL

L C

14

92

D1

,D2

DIO

DE

SC

HO

TT

KY

20

V 5

00

MA

SO

D5

23

P

ME

G2

00

5E

BN

XP

PM

EG

20

05

EB

,11

5

10

1J1

TE

RM

BL

OC

K H

DR

2P

OS

R/A

5.0

8M

MC

ON

-TE

RM

-BL

K-2

PO

S-R

AT

E C

ON

NE

CT

IVIT

Y7

96

63

8-2

11

1J1

-PL

UG

TE

RM

BL

OC

K B

LU

G 2

PO

S 5

.08

MM

TE

CO

NN

EC

TIV

ITY

79

66

34

-2

12

1J2

CO

NN

RC

PT

6P

OS

.1

00

DB

L S

TR

PC

BC

ON

-RC

PT

-2X

3-B

OT

HA

RW

INM

20

-78

50

34

2M

OU

NT

FR

OM

BO

TT

OM

SID

E

13

1J3

CO

N-2

PO

S

CO

NN

EC

TO

R F

OR

12

V F

AN

, D

O N

OT

INS

TA

LL

14

2J4

,J6

CO

NN

HE

AD

ER

8P

OS

DU

AL

VE

RT

PC

B

CO

N-J

MP

-4P

OS

HA

RW

INM

20

-99

80

44

5

15

1J5

CO

NN

8

-PO

S, D

UA

L R

OW

2.5

4M

MC

ON

-HD

R-4

X2

AM

PH

EN

OL

75

86

9-1

32

LF

16

1J7

CO

NN

BN

C J

AC

K S

TR

50

OH

M P

CB

11

25

38

AM

PH

EN

OL

11

25

38

17

3J8

,J9

,J1

0C

ON

N R

EC

EP

T P

IN .0

32

-.0

46

" .0

75

"C

ON

-RC

PT

-ED

GE

MN

TM

ILL

MA

X0

31

2-0

-15

-15

-34

-27

-10

-0

MA

TIN

G S

OC

KE

T F

OR

MIL

LM

AX

ED

GE

MN

T P

IN

18

3R

1,R

3,R

7g

ene

ric 1

% s

md

06

03

49

R9

VIS

HA

Y D

AL

EC

RC

W0

60

34

9R

9F

KE

A

19

2R

2,R

4g

ene

ric 1

% s

md

12

06

10

0R

DO

NO

T IN

ST

AL

L

20

2R

5,R

6g

ene

ric 1

% s

nd

06

03

1K

00

VIS

HA

Y D

AL

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User’s Guide _____________________________________________________________________________________________________________________



Evaluation Board/kit Important Notice

GaN Systems Inc. (GaN Systems) provides the enclosed product(s) under the following AS IS conditions:

This evaluation board/kit being sold or provided by GaN Systems is intended for use for ENGINEERING

DEVELOPMENT, DEMONSTRATION, and OR EVALUATION PURPOSES ONLY and is not considered by GaN

Systems to be a finished end-product fit for general consumer use. As such, the goods being sold or provided are

not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective

considerations, including but not limited to product safety and environmental measures typically found in end

products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does not fall

within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances

(RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives,

or other related regulations.

If this evaluation board/kit does not meet the specifications indicated in the User’s Guide, the board/kit may be

returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE

EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES,

EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS

FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL

BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user

indemnifies GaN Systems from all claims arising from the handling or use of the goods. Due to the open construction

of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic

discharge.

No License is granted under any patent right or other intellectual property right of GaN Systems whatsoever. GaN

Systems assumes no liability for applications assistance, customer product design, software performance, or

infringement of patents or any other intellectual property rights of any kind.

GaN Systems currently services a variety of customers for products around the world, and therefore this

transaction is not exclusive.

Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to

handling the product. Persons handling the product(s) must have electronics training and observe good

engineering practice standards.

This notice contains important safety information about temperatures and voltages. For further safety concerns,

please contact a GaN Systems’ application engineer.


User’s Guide _____________________________________________________________________________________________________________________



In Canada:

GaN Systems Inc. 1145 Innovation Drive Suite 101 Ottawa, Ontario, Canada K2K 3G8 T +1 613-686-1996

In Europe:

GaN Systems Ltd., German Branch Terminalstrasse Mitte 18, 85356 München, Germany T +49 (0) 8165 9822 7260

In the United States:

GaN Systems Corp. 2723 South State Street, Suite 150, Ann Arbor, MI. USA 48104 T +1 248-609-7643

www.gansystems.com Important Notice – Unless expressly approved in writing by an authorized representative of GaN Systems, GaN Systems components are not designed, authorized or warranted for use in lifesaving, life sustaining, military, aircraft, or space applications, nor in products or systems where failure or malfunction may result in personal injury, death, or property or environmental damage. The information given in this document shall not in any event be regarded as a guarantee of performance. GaN Systems hereby disclaims any or all warranties and liabilities of any kind, including but not limited to warranties of non-infringement of intellectual property rights. All other brand and product names are trademarks or registered trademarks of their respective owners. Information provided herein is intended as a guide only and is subject to change without notice. The information contained herein or any use of such information does not grant, explicitly, or implicitly, to any party any patent rights, licenses, or any other intellectual property rights. General Sales and Terms Conditions apply. © 2009-2015 GaN Systems Inc. All rights reserved.

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