Hexagonal Boron Nitride - Ubiquitous Layered dielectric for Two-Dimensional Electronics
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State University of New York at Albany College of Nanoscale Science and Engineering Hexagonal Boron Nitride: Ubiquitous Layered Dielectric for Two-Dimensional Electronics Nikhil Jain A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE Doctor of Philosophy ALBANY, NEW YORK April 2015
Hexagonal Boron Nitride - Ubiquitous Layered dielectric for Two-Dimensional Electronics
1. State University of New York at Albany College of Nanoscale
Science and Engineering Hexagonal Boron Nitride: Ubiquitous Layered
Dielectric for Two-Dimensional Electronics Nikhil Jain A THESIS
SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE
Doctor of Philosophy ALBANY, NEW YORK April 2015
2. i ABSTRACT Hexagonal Boron Nitride: Ubiquitous Layered
Dielectric for Two- Dimensional Electronics Hexagonal boron nitride
(h-BN), a layer-structured dielectric with very similar crystalline
lattice to that of graphene, has been studied as a ubiquitous
dielectric for two-dimensional electronics. While 2D materials may
lead to future platform for electronics, traditional thin-film
dielectrics (e.g., various oxides) make highly invasive interface
with graphene. Multiple key roles of h-BN in graphene electronics
are explored in this thesis. 2D graphene/h-BN heterostructures are
designed and implemented in diverse configurations in which h-BN is
evaluated as a supporting substrate, a gate dielectric, a
passivation layer, or an interposing barrier in 3D graphene
superlattice. First, CVD-grown graphene on h-BN substrate shows
improved conductivity and resilience to thermally induced
breakdown, as compared with graphene on SiO2, potentially useful
for high-speed graphene devices and on-chip interconnects. h-BN is
also explored as a gate dielectric for graphene field-effect
transistor with 2D heterostructure design. The dielectric strength
and tunneling behavior of h-BN are investigated, confirming its
robust nature. Next, h-BN is studied as a passivation layer for
graphene electronics. In addition to significant improvement in
current density and breakdown threshold, fully encapsulated
graphene exhibits minimal environmental sensitivity, a key benefit
to 2D materials which have only surfaces. Lastly, reduction in
interlayer carrier scattering is observed in a double-layered
graphene setup with ultrathin h-BN multilayer as an interposing
layer. The DFT simulation and Raman spectral analysis indicate
reduction in interlayer scattering. The decoupling of the two
graphene monolayers is further confirmed by electrical
characterization, as compared with other
3. ii referencing mono- and multilayer configurations. The
heterostructure serves as the building element in 3D graphene, a
versatile platform for future electronics.
4. iii ACKNOWLEDGEMENTS Firstly, I would like to express my
sincere gratitude towards my advisor, Dr. Bin Yu. In the five years
that I have worked with Dr. Yu, I have always been amazed with how
his approach to research is so simple and yet so effective. He
would always say, Work smart, not hard and always try to dig deeper
than what is apparent. These two statements of his became guiding
principles for me over the years. He was always inspiring in his
mentorship and allowed me to think creatively. He made me learn the
skill of identifying the exact problem to figure out the
appropriate solution. I am also grateful to the NSF and SRC for
their financial support. I would like to thank Dr. Bhaskar
Nagabhirava and Dr. Tianhua Yu for their guidance and support
during my initial days at CNSE. It was the skills I learned from
them that allowed me to become independent in my research. Dr.
Tanesh Bansal, during his time in our group, helped me realize that
a committed approach to any problem has the potential to bring
about an answer. I want to acknowledge the procedures I learned
from Eui Sang Song that helped me immensely in my research. I want
to specially thank Dr. Mariyappan Shanmugam for the insightful
lunch time discussions which always helped me decide my next step.
I have enjoyed working with Dr. Fan Yang and Christopher Durcan
during my time at CNSE. But the one person from our group who
deserves the biggest acknowledgement is Robin Jacobs-Gedrim. Robin
and I joined the program together and have been partners-in-crime
throughout these five years. Countless hours that we spent together
talking science, life, philosophy, sports and pretty much
everything under the sun allowed this experience to be very humane
and enjoyable. There are many other people at CNSE who have helped,
supported and guided me. The entire CNSE student and faculty
community has always been very supportive and friendly. I take away
many happy memories from being part of this institution.
5. iv Throughout these last five years, I was involved as a
volunteer faculty with the Art of Living Foundation, organizing and
teaching many self-development programs with my volunteer group
under the guidance of its founder, Sri Sri Ravi Shankar. The wisdom
and knowledge that I keep learning from him has been hugely
responsible for my mental well-being and happiness. Through the Art
of Living Foundation, I have had a family-like atmosphere
throughout my time in Albany, for which I am deeply grateful. Over
the last five years, I have also had the pleasure of being deeply
associated with the Interfaith Center at UAlbany where Donna
Crisafulli has been a dear friend throughout. I would also like to
extend my sincere thanks to Dr. Robert Jones, my research advisor
during my Masters degree at the University of Cincinnati. I found
myself having a headstart in the Ph.D. program, largely due to the
expert training I had received from Dr. Jones. Many other friends I
made in Cincinnati are a big part of my life and I cant thank them
enough for bringing such wonderful perspectives to my life. It
would be safe to say that I would not have dreamed of getting
through this degree without the encouragement and support of my
family. My parents, and my sister Sonali have made me the person I
am today. My brother-in-law, Sameer has always been a guiding
force. Lastly, my friend Charu deserves a special mention for being
a bedrock in my life through these five years.
6. v CONTENTS Abstract.... i Acknowledgements. iii Contents...
v List of Figures and tables ix Chapter 1 Introduction 1 1.1
Introduction to 2-D materials 1 1.2 Classification of 2-D materials
5 1.2.1 Layer thickness/electronic structure based approach 5 1.2.2
Material extraction technique based approach 6 1.2.3 Conduction
properties based approach 8 1.3 Extraordinary properties in 2-D
materials 8 1.3.1 Novel phenomena in graphene 9 1.3.2 Hexagonal
boron nitride and its properties 10 1.3.3 Other 2-D materials 11
1.4 2-D materials based heterostructures 12 1.4.1 Limitations of
2-D heterostructures 14 1.5 Motivation for current work 15
Bibliography 17 Chapter 2 h-BN: Substrate for Graphene. 40 2.1
Introduction 40 2.2 Experimental methods 41 2.2.1 Synthesis of CVD
graphene 41 2.2.2 Graphene transfer 42
8. vii 4.2.1 Two-dimensional layer transfer method 75 4.2.2
Device fabrication 76 4.3 Results and Discussion 78 4.3.1
Environmental desensitization 78 4.3.2 Mobility preservation 80
4.3.3 Reliability enhancement 81 4.4 Conclusions 83 Bibliography 85
Chapter 5 h-BN: Intercalation Layer in Graphene Multilayer System.
88 5.1 Introduction 88 5.2 Experimental methods 90 5.2.1
Fabrication process 90 5.3 Sample characterization and analysis 92
5.3.1 Material characterization 92 5.3.2 Density function theory
analysis 94 5.3.3 Raman spectrum analysis 95 5.4 Electrical
measurements 101 5.4.1 Performance enhancement 101 5.4.2
Reliability improvement 105 5.4.2.1 Breakdown current and power
density 105 5.4.2.2 Lifetime reliability analysis 107 5.5
Conclusions 109
9. viii Bibliography 111 Chapter 6 Conclusions and future
directions... 114 6.1 Project summary 114 6.2 Future directions 115
List of Publications 117
10. ix LIST OF FIGURES AND TABLES Figure 1.1: A brief history
of graphene-based materials. Figure 1.2: An overview of
graphene-based nanomaterials. Graphene can be wrapped into OD
fullerenes (leftmost), rolled up into 1-D nanotubes (middle) or
stacked into 3-D graphite (far right). Figure 1.3: Band structure
of mono-, bi- and tri- layer graphene. Figure 1.4: A typical FET
structure using 2-D materials. Figure 2.1: CVD furnace set-up used
for graphene growth. Figure 2.2: Graphene transfer process (from
as-grown on Cu to target substrate). Figure 2.3: Fabrication
process for creating graphene FET/interconnect device on h-BN
Figure 2.4: SEM image of the fabricated sample - patterned graphene
on h-BN. Figure 2.5: Measured Raman spectrum of monolayer graphene
on h-BN. Figure 2.6: Measured graphene resistivity as a function of
back-gate voltage for three material systems: CVD graphene on h-BN,
CVD graphene of SiO2, and exfoliated graphene on SiO2. Significant
improvement is seen in graphene on h-BN. Figure 2.7: Extracted
carrier mobility as a function of carrier concentration for the
three types of graphene devices.
11. x Figure 2.8: Breakdown characteristics of the three
fabricated samples with different material configurations. Measured
I-V curve showing the critical point of permanent breakdown in
graphene (where the current drops abruptly). Figure 2.9: Power
density at breakdown for the three samples. Figure 2.10: Impact of
electrical annealing on graphene electrical conduction. Graphene
sheet resistance at zero substrate bias, RSH@VG=0V as a function of
annealing DC voltage for all three samples. Figure 2.11: Impact of
electrical annealing on graphene electrical conduction. Effect of
annealing voltage on sheet resistance, RSH, of CVD graphene on
h-BN. Figure 3.1: Schematic shows key steps in the fabrication of
the buried TiN gates Figure 3.2: The schematic shows the isometric
and the side-view of the buried-gate graphene transistor. Figure
3.3 Scanning Electron Microscope micrograph of the fabricated
device with the dashed lines showing the locations of the graphene
channel (white dashed line) and h-BN (black dashed line),
respectively. Figure 3.4: Raman spectrum showing the signature
peaks for the h-BN multilayer and the graphene monolayer. Figure
3.5: AFM data showing a line scan profiling along the vector marked
in the image (seen in the inset). The actual h-BN multilayer
thickness is the sum of step height from graphene to the left-over
h-BN nanosheet (after O2 plasma etching) and the step height from
the left-over h-BN nanosheet to substrate.
12. xi Figure 3.6: Thermal annealing in graphene. Improvement
in drain current vs. drain voltage after thermal anneal (pre-anneal
data shown in the inset.) Figure 3.7: Thermal annealing and
breakdown in graphene. (a) Improvement in drain current vs. drain
voltage after thermal anneal with pre-anneal data shown in the
inset. (b) Graphene permanent breakdown occurs, as 15V source-drain
voltage is applied. Graphene channel length is 750 nm. Figure 3.8:
Total device resistance vs. gate voltage showing improvement in the
graphene channel conductance, after the sample was electrically
stressed at varying voltages. Figure 3.9: The reduction in contact
resistance vs. stressing voltage. Figure 3.10: The schematic of the
metal/h-BN/metal structure used for studying the dielectric
properties of h-BN. Figure 3.11: Current density (JG) is plotted
against the applied gate electric field, showing the leakage
current density increases from 10 A/cm2 to 0.1 A/cm2 at the
critical dielectric strength of ~4 MV/cm for a gate area of 10-9
cm2 . It should be noted that leakage current stays in the nA level
until an electrical field of 15 MV/cm is reached. Figure 3.12:
Dependence of the transition voltage (Vtrans) on h-BN physical
thickness showing Critical Dielectric Strength of ~3.4 MV/cm.
Figure 3.13: Resistivity () of graphene vs. gate voltage, showing
the impact of electrical annealing.
13. xii Figure 3.14: Measured carrier mobility vs. vertical
effective electric field for three different channel/substrate
material systems, i.e., CVD-grown monolayer graphene (MLG) on h-BN,
exfoliated monolayer graphene (Ex-MLG) on SiO2 and CVD-grown
monolayer graphene on SiO2. It is noted that the carrier mobility
is ~20,000 cm2 /Vs at an effective field of 5 105 MV/cm. Figure
4.1: Schematic representation of the process flow for the assembly
of h-BN/monolayer graphene/h-BN heterostructure, including layer
transfer process for h-BN top passivating layer on the
pre-fabricated graphene/h-BN interconnect wire structure. Figure
4.2: Schematic cross-section view of the h-BN/graphene/h-BN
heterostructure used in this experiment. Figure 4.3: Optical
microscope image (with 50X magnification) showing the top-view of a
graphene interconnect wire with the bottom h-BN substrate layer
shown by red dashed line, graphene sheet by a black dotted line,
and the top h-BN passivation layer by a white dashed line. Figure
4.4: Measured R-VBG characteristics of the h-BN/graphene and
h-BN/graphene/h-BN heterostructure-based interconnect wires in both
ambient (air) and vacuum conditions. Figure 4.5: (a) Measured R-VBG
characteristics of the h-BN/graphene and h-BN/graphene/h-BN
heterostructure-based interconnect wires in both ambient (air) and
vacuum conditions. (b) Metal- to-graphene contact resistance in
different heterostructure and testing condition, as extracted from
the measured R-VBG characteristics shown in (a).
14. xiii Figure 4.6: Measured carrier mobility as a function of
the applied electric field for graphene interconnect wire samples
in both pre-encapsulation and post-encapsulation configurations.
Slight degradation is observed after the assembly of the top h-BN
passivation layer. Figure 4.7: Measured current density in graphene
device as a function of the applied voltage for three different
configurations, SiO2/graphene (green color), h-BN/graphene (red
color) and h- BN/graphene/h-BN (black color). Increased breakdown
voltage and maximal current density are observed for the
encapsulated graphene. Figure 4.8: Power-dissipation density at
breakdown for the encapsulated graphene in comparison with the
other two configurations, i.e. graphene/SiO2 and graphene/h-BN. The
PBD of encapsulated graphene exhibits ~90% increase from that of
graphene/h-BN and 10 times that of the graphene/SiO2 structure.
Figure 5.1: Schematic view of the fabrication process to make
dual-layer graphene heterostructure with a thin h-BN layer
sandwiched in-between. Figure 5.2: The atomic-lattice schematic of
the double-layered graphene structure separated by an intercalating
h-BN multilayer. Figure 5.3: The schematic tilted-view of the
graphene/h-BN/graphene heterostructure. Figure 5.4: The SEM image
showing the fabricated graphene/h-BN/graphene heterostructure with
two probing contacts (Ti/Au). Here the dash-dotted lines show the
edges of the plasma- etched graphene ribbon for eye-guiding
purpose. Figure 5.5: Schematic representation of the metal contact
to the DLG heterostructure.
15. xiv Figure 5.6: The density-functional-theory simulation
results of the E-k dispersion relationship in four different
configurations: (A) monolayer graphene, (B) AB Bernal- stacked
bilayer graphene, (C) double-layered graphene with an intercalating
h-BN monolayer, and (D) double-layered graphene with an h-BN
multilayer (22 nm thick). Figure 5.7: Raman spectra of the sample
before and after assembling the second graphene layer. Figure 5.8:
Intensity ratio of the G-peak and the 2D-peak as observed in the
Raman spectra measured on micromechanically exfoliated graphene and
transferred-and-stacked CVD-grown graphene samples. Figure 5.9: The
full-width-at-half maximum of the 2D peak in the Raman spectra of
graphene with different thickness. Figure 5.10: Lorentzian
curve-fitting of the 2D peak of an exfoliated graphene shows four
components (P1-P4). The numbers in the inset are the corresponding
peak values of wavenumber. Figure 5.11: Measured Raman spectra of
graphene/h-BN/graphene heterostructure in comparison with that of
CVD monolayer graphene (1L), exfoliated bilayer graphene (e-2L),
and stacked dual-layer graphene (s-2L). Figure 5.12: Measured
electrical current density in structures with four different
layered configurations, including monolayer graphene (1L),
exfoliated (AB-stacked) bilayer graphene (e- 2L), randomly-stacked
bilayer graphene (s-2L), and graphene/h-BN/graphene
heterostructure.
16. xv Figure 5.13: Conductivity as measured in different
configurations. Figure 5.14: Measured carrier mobility for all the
sample configurations as a function of temperature. Figure 5.15:
Breakdown current density for monolayer, bilayer, and dual-layer
graphene. Figure 5.16: Extracted power density at breakdown for all
the three tested samples. The width and length dimensions for each
of the tested samples are 500 nm and 4 m. Fig. 5.17: The impacts of
electrical stressing on graphene at elevated temperature (150C).
Resistance as a function of time under constant voltage stressing
at 10V. Figure 5.18: The impacts of electrical stressing on
graphene samples at elevated temperature (150C). Measured values of
time-to-failure for monolayer, bilayer, and dual-layer graphene
structures. Table 1. Summary of the characteristic parameters
measured from Raman spectra. Samples with different layer
configurations are characterized and analyzed, including CVD-grown
monolayer graphene (1L), exfoliated AB-stacked bilayer graphene
(e-2L), stacked dual-layer graphene (s- 2L), and
graphene/h-BN/graphene heterostructure. Table 2: Table showing that
both RG and RBN need to be high for the gap region to be in the
insulating (or OFF) state.
17. 1 Chapter 1 Introduction 1.1 Introduction to 2-D materials
2-D materials have become highly relevant in the recent times due
to their unique and unusual properties which make them ideal for
various useful applications (photovoltaics, semiconductors, etc.)
as well as a platform for studying physical phenomena that were
hitherto unexplored (Berrys phase of massless Dirac fermions,
anomalous Hall effect etc.) [1-11]. Till very recently, 2-D
materials had only been either studied theoretically as a starting
point to understand the properties of their 3-D counterparts or
grown epitaxially on solid surfaces (metals or carbides) [12, 13].
Peierls as well as Landau and Lifshitz had theorized that a purely
2-D lattice could not be thermodynamically stable at any
temperature unless it is coupled to a bulk crystal with a matching
lattice, a result highly accepted by the general community [14-16].
They argued that the thermal fluctuations in such low-dimensional
lattice systems will lead to atoms being displaced by a distance
comparable to the interatomic distances at any finite
temperature
18. 2 [17]. The theory was well supported by experimental
observations on thin films where any attempt to decrease the film
thickness below a few nanometers resulted in stability concerns as
the films segregated into islands [18, 19]. As a result, while the
physics of 2-D materials was considered rich, the lack of knowledge
to isolate them reliably in a lab was a major impediment to 2-D
materials based research. Gordon Walter Semenoff and David P.
DeVincenzo and Eugene J. Mele first outlined the massless Dirac
equation in graphene [8, 20]. By 1970s, detailed studies of
few-layer graphite were emerging along with reports showing
epitaxial growth of graphene and hexagonal boron nitride on
different substrates [21, 22]. Chemical and mechanical exfoliation
methods were employed in the 1990s to extract monolayer graphene
but nothing below 10 nm thickness could be obtained for macroscopic
samples [23]. Jang and Huang patented a technique to produce large
area graphene in 2002 [24] but the latest surge in 2-D material
research can be attributed to the discovery of a simple yet
effective method to measurably produce and isolate graphene from
3-D graphite crystals in the lab by means of micromechanical
exfoliation [10]. In 2004, Andre Geim and Konstantin Novoselov at
The University of Manchester presented a technique to isolate
monolayer graphene from bulk graphite using Scotch tape. The
technique itself finds its roots in the patent filed by Rutherford
and Dudman from EGC Enterprises Inc. in 2002 [25] but Geim and
Novoselov are regardless considered the pioneers in making 2-D
materials research a new frontier in physics as they proposed the
possibility to extend it to all 2-D materials [1]. Indeed graphene
became the first 2- D material to exist as a high quality crystal
without a matching underlying substrate lattice as well as in a
suspended configuration [26]. This was soon followed by similar
reports on several dichalcogenides, layered superconductors and
graphenes isomorphic twin, hexagonal boron nitride (h-BN) among
others [27-29]. Figure 1.1 explains a brief history of 2-D material
research
19. 3 until the point Geim and Novoselov isolated graphene in
their lab. It has now been established that since these 2-D flakes
are isolated from 3-D materials, they can be considered as quenched
in a metastable state. Additionally, a strong covalent bonding
prevents the thermal fluctuations (even at elevated temperature)
from generating dislocations or other crystal defects [16, 17].
Another approach attributes the stability of these 2-D sheets to
3-D warping or wrinkle formation which results in a gain elastic
energy while suppressing the thermal vibrations [30]. Figure 1.1: A
brief history of graphene-based materials From being a material
that was not supposed to exist to being the rising star, graphene
has shown great potential in future generation electronics owing to
its exceptional physical properties [11, 31]. The structure of
graphene shows a honeycomb lattice of sp2 -bonded carbon atoms in
layered two-dimensional form. 2-D material sheets can also be
thought of as basic building blocks for other derived
nanomaterials. For instance, graphene can be wrapped into
fullerenes, rolled into carbon nanotubes or stacked to form
graphite as shown in Figure 1.2.
20. 4 Figure 1.2: An overview of graphene-based nanomaterials.
Graphene can be wrapped into OD fullerenes (leftmost), rolled up
into 1-D nanotubes (middle) or stacked into 3-D graphite (far
right). Reproduced with permission from [11], copyright 2007,
Nature Publishing Group. As electronics makes a foray out of the
fab, 2-D materials have been increasingly touted to power the
future generation chips owing to their flexible, ultrathin and
robust nature allowing for wearable devices [32]. All classes of
materials, i.e., metals, semiconductors and insulators have been
identified among the family of 2-D materials and purely 2-D
materials based devices have started emerging [33]. Additionally,
several research groups have already demonstrated the reliability
of these devices under the effect of bending stress [34-36].
21. 5 1.2 Classification of 2-D materials 1.2.1 Layer
thickness/electronic structure based approach It is important to
define the limit where a thin crystal can no longer be called 2-D
for any practical purposes. While this classification could be
based on many different material properties, electronic structure
has been used to primarily define this distinction. For graphene,
the electronic structure is layer dependent for small layer numbers
( 108 A/cm2 ) [199], and immunity to electromigration [200] due to
its strong sp2 -bonded carbon lattice. In addition to being a
potential interconnect material, graphene has also been explored as
a contact electrode in FETs and solar cells. Further, graphene
based heterostructures have emerged
32. 16 as transistors. However, as discussed earlier, while
graphene in its pristine form can be very useful for many
applications, there is severe degradation in its properties when it
comes in contact with another material. h-BN is an isomorph of
graphene with a similar hexagonal layered structure. In both the
materials, weak Van der Walls bonds keep the layers sticking
together and there is only a small lattice constant mismatch
(1.7%). Hexagonal boron nitride is a chemically inert material, and
its layered crystalline structure allows for an atomically smooth
surface that is free of dangling bonds. Compatibility issues with
current dielectrics in the semiconductor industry is presenting
probably the biggest challenge to 2-D electronics. In addition to
being a substrate, a gate dielectric and a passivating layer, a
dielectric performs many other functions on a chip like screening
different conducting channels from each other to avoid
scattering/crosstalk losses among others. This project is aimed at
studying hexagonal boron nitride as a universal dielectric for 2-D
electronics. We study a variety of device prototypes using
graphene/h-BN heterostructures to establish the utility of h-BN as
an ideal nearest neighbor for graphene.
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56. 40 Chapter 2 h-BN: Substrate for Graphene 2.1 Introduction
Electrical properties of graphene are critically impacted by the
substrate material [1-7]. Degradation of conductivity in graphene
on SiO2 was reported, up to several orders of magnitude lower from
its intrinsic value. In addition, considerable loss is also
observed in carrier mobility [8]. From a reliability standpoint,
graphene undergoes breakdown even at low voltage stress when using
electrical annealing approach to improve graphene quality [9, 10].
We have studied h-BN as a new substrate material for graphene FETs
and interconnects. In this section, we investigate key performance
metrics of CVD graphene devices on h-BN such as electrical
resistivity, carrier mobility, and breakdown power density, as well
as the impact of electrical annealing on wire conduction and
reliability. In reference to IEEE copyrighted material which is
used with permission in this thesis, the IEEE does not endorse any
of University at Albanys products or services. 2012 IEEE.
Reproduced, with permission, from N. Jain, T. Bansal, C. Durcan
& B. Yu, Graphene-Based Interconnects on Hexagonal Boron
Nitride Substrate, IEEE Electron Device Letters, May 2012
57. 41 2.2 Experimental Methods 2.2.1 Synthesis of CVD graphene
Graphene monolayer was grown on the surface of Cu foils using
methane (CH4) as the precursor at an elevated temperature (1000 C)
in an LPCVD chamber [11] as shown in Figure 2.1. A 25 m thick
copper foil was cut into strips (1 cm 4 cm) and cleaned by dipping
in acetic acid (CH3COOH) for 15 minutes. This removes organic
impurities and native oxide from the surface. Afterwards, the Cu
strips were loaded into the growth chamber and annealed at 1000C in
an Ar (80sccm) + H2 (4.5 sccm) environment. Graphene is grown using
CH4 (20 sccm) as carbon precursor in an environment of Ar (180
sccm) +H2 (4.5 sccm) at 1000C for 30 minutes. At an elevated
temperature, Cu acts as a catalyst for the breakdown of methane
into carbon and hydrogen. While hydrogen is pumped out of the
chamber, carbon atoms arrange themselves on the surface of Cu.
Since Cu has the same lattice constant as graphene, the atoms
arrange themselves into domains of graphene. These domains keep
growing in size until they join to become a monolayer of graphene.
The solubility of carbon in copper is negligible and once the
surface is covered, copper isnt available to catalyze the reaction
anymore making this a surface- limited growth. As can be expected,
grain boundaries in graphene affect the carrier transport in
graphene adversely. Growth engineering involves controlling the
conditions (flow rates, growth time, temperature and pressure) to
facilitate the growth and surface treatment to increase the size of
graphene domains. More details on graphene growth can be found in
this paper by Ruoff et al [11].
58. 42 Figure 2.1: CVD furnace set-up used for graphene growth
2.2.2 Graphene transfer Figure 2.2: Graphene transfer process (from
as-grown on Cu to target substrate) The Cu-graphene stack as
obtained after the growth was then covered by a thick layer of PMMA
by spin-coating the polymer. This is followed by Cu etching by iron
chloride (FeCl3).
59. 43 The graphene on PMMA was cleaned repeatedly in DI water
and then transferred onto the target substrate. Heating the
substrate at 90 C for 3 minutes helped to remove absorbents and
enhance adhesion between graphene and h-BN. Polymer PMMA was
removed by acetone. The overall process is shown in Figure 2.2.
2.2.3 Sample fabrication Figure 2.3: Fabrication process for
creating graphene FET/interconnect device on h-BN Thin flakes of
h-BN were exfoliated on p-doped Si substrates with 70nm of thermal
oxide on top for good optical contrast while identifying the flakes
through the optical microscope (Olympus BX60M). This is followed by
graphene transfer as explained in Section 2.2. Subsequent to the
transfer, graphene is patterned using a PMMA/HSQ bilayer e-beam
resist
60. 44 stack. First a layer of 100 nm PMMA is coated on the
sample, followed by application of a 30 nm thick layer of HSQ. Here
electron-beam lithography was used to pattern the HSQ followed by
developing in CD-26 solution. The O2 plasma-based RIE is then used
to etch away uncovered PMMA and unwanted graphene. The remaining
PMMA acts as a sacrificial layer for lifting off residual of the
exposed HSQ. The probing contacts were patterned using e-beam
lithography, evaporation of metal (10 nm Ti/40 nm Au) at 10-6 Torr,
and liftoff. The fabrication process flow is shown in Figure 2.3.
The samples were annealed at 300 C in forming gas (Ar + H2)
overnight to minimize hysteretic behavior. The R-vs.-VG
measurements were taken using p-doped Si as the sweeping back gate.
The charge-neutrality peak (the Dirac Point) was observed very
close to VG = 0 V with a small negative shift, indicating slightly
n-type behavior. This could be attributed to the unintentional
doping in graphene due to surface absorbents (such as that from
ambient O2 or H2O molecules or residual PMMA) or charged impurities
in h-BN substrate. All the DC electrical characterization was
carried out at room temperature. 2.3 Results and Discussion 2.3.1
Material analysis Figure 2.4 is the top-view SEM image of one of
the fabricated samples. The length (L) and width (W) of the
graphene strip used in this study are found to be 3.38 m and 0.24
m, respectively. Figure 2.5 is the measured micro-Raman spectrum
showing the signature peaks of monolayer graphene on h-BN.
61. 45 Figure 2.4: SEM image of the fabricated sample -
patterned graphene on h-BN. Figure 2.5: Measured Raman spectrum of
monolayer graphene on h-BN. 2.3.2 Electrical analysis The RT - VG
characteristics of graphene is generated using Si substrate as
back-gate. Here RT is the total resistance composed of graphene
wire resistance (RW), contact resistance (2RC),
62. 46 and metal pad resistance (2RM),). While RM is
negligible, RC is extracted from a multiple- contact wire
configuration through a differentiation method, C = T2()1 T1()2 2(1
2) where RT1 and RT2 are the measured total resistances from wire
segments with length of L1 and L2, respectively. RW, a function of
the back-gate voltage (VG), is then obtained from RT - 2RC. The
graphene sheet resistance (RSH) is calculated from = . ( ) where W
and L are the width and length of the graphene wire, respectively.
The electrical resistivity of graphene is given by = . in which t
is the physical thickness of a monolayer of graphene
(approximately, 0.34 nm). The -vs.-VG plots of three
best-in-the-kind samples are shown in Figure 2.6: (i) CVD- grown
graphene on h-BN sheet, (ii) CVD-grown graphene on SiO2 substrate,
and (iii) exfoliated graphene on SiO2 substrate. Total eight
samples of each material structure were fabricated in three
separate experiment runs. All the samples were then annealed at a
DV voltage of 5 V to study the nearly-intrinsic conduction
characteristics. It can be seen that resistivity (at VG = 0V) drops
by approximately nineteen times in CVD graphene on h-BN as compared
with that on SiO2. Also, comparison with exfoliated graphene shows
a reduction in by approximately eight times. This significant
improvement is attributed to the fact that both h-BN and graphene
have isomorphic 2-D hexagonal crystal lattices free of dangling
bonds. The stack of two 2-D layered structures leads to absence of
interfacial states which largely contribute to the degradation of
carrier transport in graphene/SiO2 system.
63. 47 Figure 2.6: Measured graphene resistivity as a function
of back-gate voltage for three material systems: CVD graphene on
h-BN, CVD graphene of SiO2, and exfoliated graphene on SiO2.
Significant improvement is seen in graphene on h- BN. Due to
alleviation of scattering by charged interface states at
graphene/h-BN interface, ultra-high carrier mobility (eff), ~15,000
cm/Vs (at a carrier density of 11012 cm-2 ) is measured at room
temperature, as shown in Figure 2.7. At the carrier density of
11012 cm-2 , carrier mobility in CVD graphene on h-BN substrate is
improved by about 17 times and 3.5 times, as compared with CVD
graphene on SiO2 and exfoliated graphene on SiO2, respectively.
Higher mobility translates to reduced interconnect transmission
delay which is critical to the speed performance. The interface
quality between graphene and substrate material plays a key role in
impacting electronic transport performance. We attribute the
significant improvement of
64. 48 conduction in graphene on h-BN to atomically flat
interface that is free of dangling bonds and trap charges (due to
self-terminating crystalline planes in both materials). This avoids
rippling in graphene and reduces charge-scattering centers that
adversely influence the electrical performance of graphene
interconnects. Figure 2.7: Extracted carrier mobility as a function
of carrier concentration for the three types of graphene devices.
2.3.3 Reliability enhancement To explore the performance limit of
graphene interconnect as posted by material reliability, we
characterize the I-V behavior in the near-breakdown region. In
Figure 2.8 the current densities (J) as a function of voltage (V)
(across the graphene sample) is plotted for three samples. As shown
in Fig. 3(a), CVD graphene on h-BN shows the highest breakdown
current density (1.4 109 A/cm2 ), ~ 56% higher than that of CVD
graphene on SiO2.
65. 49 Figure 2.8: Breakdown characteristics of the three
fabricated samples with different material configurations. Measured
I-V curve showing the critical point of permanent breakdown in
graphene (where the current drops abruptly). The power density
dissipated at breakdown, PBD = JBD (VBD JBDRC), is increased by 7
times in CVD graphene on h-BN, as compared with that on SiO2
(Figure 2.9). Here JBD and VBD are the current density and voltage
at breakdown, respectively. The difference is explained by the
superb thermal conductivity in h-BN (~20 W/mK) which is ~20 times
higher than that in SiO2 (1.04 W/mK). Heat dissipation is more
efficient through h-BN than that through SiO2 under the 3-D heat
spreading model for thermal-induced breakdown in graphene [12]. It
is noticed that exfoliated graphene exhibits the highest VBD, which
could be attributed to better crystallinity in the sample (as
compared with CVD graphene which is typically polycrystalline and
contains more growth-induced defects). Nevertheless, the advantage
of using h-BN substrate is that it makes PBD of CVD graphene still
twice as much as that of exfoliated graphene on SiO2.
66. 50 Figure 2.9: Power density at breakdown for the three
samples. Lastly, we investigate the impact of electrical annealing
on graphene conducting behavior. Graphene sheet resistance
(measured at zero substrate bias, as in normal interconnect
operation) starts to drop when the DC voltage (applied across the
wire) reaches up to a certain value (~5 V in this case) as seen in
Figure 2.10 [10]. This is because sufficient Joule heating
generated by current would facilitate desorption of charged
impurities (which act as carrier scattering centers) at graphene
surface. It should be noted that the initial increase of RSH in
exfoliated graphene on SiO2 (from 0 V to 5 V) is due to shifting in
the Dirac point at low-voltage annealing.
67. 51 Figure 2.10: Impact of electrical annealing on graphene
electrical conduction. Graphene sheet resistance at zero substrate
bias, RSH@VG=0V as a function of annealing DC voltage for all three
samples. Figure 2.11 shows the RSH-vs.-VG characteristics as
influenced by annealing voltage. The value of RSH starts to
decrease as the voltage becomes higher than 5 V. Our preliminary
experiment using graphene on SiO2 showed the Dirac point in the RSH
- VG curve exhibit a large positive shift due to electrons
transferred from graphene to surface traps in SiO2 substrate
(making graphene more heavily p-type doped). Contrary to that
reported phenomenon, the Dirac Point does not show any positive
shift in graphene sample on h-BN, as shown in Figure 2.11. This
would be interpreted as one of the evidences of the absence of
surface traps on the h-BN substrate. The small amount of negative
shift of the Dirac Point at high-level annealing voltage is
attributed to desorption of charged absorbents on the graphene
surface, similar to the case in which SiO2 is used as the
substrate.
68. 52 Figure 2.11: Impact of electrical annealing on graphene
electrical conduction. Effect of annealing voltage on sheet
resistance, RSH, of CVD graphene on h-BN. 2.4 Conclusions In
summary, we conducted a comparative study of electrical conducting
characteristics among wire samples made of three different
structures. CVD-grown graphene on h-BN shows significantly
improvement in performance metrics including resistivity, carrier
mobility, and breakdown power density, as compared with CVD
graphene on SiO2. Its metrics are also better than that of
exfoliated graphene on SiO2 despite better crystallinity in the
latter. The boosted performance is attributed to the layered
structure of h-BN, a substrate that maximally preserves the
intrinsic electrical characteristics of graphene. Graphene on h-BN
substrate allows for realizing high-speed carbon-based on-chip
interconnects in the post-copper era.
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71. 55 Chapter 3 h-BN: Gate Dielectric 3.1 Introduction Given
the atomically-thin nature of graphene, the material behaviors are
strongly impacted by its dielectric environment. The study of
graphene/dielectric coupling effects has revealed that interfacial
traps, impurities, and surface phonons of the adjoining insulator
all contribute to degraded carrier transport in graphene [1].
Although suspended graphene has been shown to nearly preserve the
intrinsic material properties, it is not feasible in real device
configurations [2, 3]. Different device configurations, require
graphene to be in contact with a specific dielectric material. In a
FET structure, graphene needs to be in contact with a gate
dielectric. As h-BN is very similar to SiO2 in terms of dielectric
behavior, having a similar dielectric coefficient and bandgap, it
can potentially serve as a high-quality non-invasive dielectric for
graphene-based switches [4]. The graphene/h-BN stack could serve as
a key 2013 Elsevier. Reproduced in parts, with permission, from N.
Jain, T. Bansal, C. Durcan, Y. Xu & B. Yu, Monolayer
graphene/hexagonal boron nitride heterostructure, Carbon, April
2013.
72. 56 structural element in graphene-based electronics. But
study on the stability and robustness of the stacked
heterostructure has been lacked. In this chapter, locally buried
metal-gate configuration is used to report electrical stressing
induced effects in a graphene/h-BN heterostructure. The dielectric
strength and carrier-tunneling behavior in a thin h-BN multilayer
are also investigated using this graphene FET structure. 3.2
Experimental methods 3.2.1 Locally-buried metal-gate formation
Figure 3.1: Schematic shows key steps in the fabrication of the
buried TiN gates
73. 57 A locally-buried titanium nitride (TiN) gate electrode
was used in fabricating the graphene/h-BN heterostructure FET. The
key fabrication steps for the formation of the buried gates of TiN
are shown in Figure 3.1. A 300 nm thick layer of thermal SiO2 was
grown on a p- type doped silicon wafer. Subsequently, the gate
regions were defined using deep ultra-violet (DUV) lithography. The
thermal SiO2 layer was etched away by 1/2 of its original thickness
with hydrofluoric acid (HF), and a thick layer of TiN (150 nm) was
then deposited by physical-vapor- deposition (PVD) onto the
trenched oxide. A chemical-mechanical-planarization (CMP) step was
used to remove the excessive TiN, making fully planarized surface
as the receiving structure for the layered nanosheets (h-BN and
graphene). Another step of patterning and oxide etching then
creates a trench for alignment marks which are filled with gold.
These alignment markers help with e-beam patterning in the
subsequent steps. 3.2.2 Graphene/h-BN FET fabrication
Highly-oriented pyrolytic boron nitride (HOPBN) was exfoliated onto
the substrate, making nanosheets of thin h-BN multilayer on the
interdigitated TiN gate electrode lines. Graphene is grown using
the CVD method as discussed in Section 2.2.1 and transferred to the
target sample using the same process as described in Section 2.2.2.
In this configuration, h-BN ends up serving as both, the gate
dielectric as well as the supporting layer for graphene. The
transferred CVD-graphene is patterned by e-beam lithography (EBL)
using a negative resist (Hydrogen silsesquioxane), followed by O2
plasma etching to form the active channels of FETs. The final step
includes patterning, metal deposition, and lift-off to form
source/drain contacts (10 nm Ti / 50 nm Au). All electrical
measurements were carried out in vacuum by a Lakeshore Cryogenics
probe-station and a semiconductor parameter analyzer (Agilent
Technologies
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