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2014
Hysteretic controlled DC-DC converters Hysteretic controlled DC-DC converters
Shweta Chauhan Wright State University
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HYSTERETIC CONTROLLED DC-DC
CONVERTERS
A thesis submitted in partial fulfillment
of the requirements for the degree of
Master of Science in Engineering
By
Shweta Chauhan
B. E., Jawaharlal Nehru Technological University, Hyderabad, AP, India-500072
2014
Wright State University
i
WRIGHT STATE UNIVERSITY
SCHOOL OF GRADUATE STUDIES
Nov 17, 2014
I HEREBY RECOMMEND THAT THE THESIS PREPARED UNDER MYSUPERVISION BY Shweta Chauhan ENTITLEDHYSTERETIC CONTROLLED DC-DC CONVERTERS BEACCEPTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTSFOR THE DEGREE OF Master of Science in Engineering.
Marian K. Kazimierczuk, Ph.D.
Thesis Director
Brian D. Rigling Ph.D.
Professor and Chair,Director of Sensor Systems Research
Department of ElectricalEngineering
College of Engineering andComputer Science
Committee onFinal Examination
Marian K. Kazimierczuk, Ph.D.
Kuldip Rattan, Ph.D.
Yan Zhuang, Ph.D.
Robert E.W. Fyffe, Ph.D.Vice President for Research and Dean of the Graduate School
Abstract
Chauhan, Shweta. M.S.Egr, Department of Electrical Engineering, Wright State
University, 2014. Hysteretic controlled DC-DC converters.
Switched-mode DC-DC converters are widely used in applications requiring step-
up and step-down of DC voltages or currents. These converters find their use in
portable applications such as laptops and smart phones, radio-frequency power am-
plifiers, as light emitting diode (LED) drivers, etc. The power converters consist
of a switching network, energy storage elements such as inductors and capacitors,
and a load resistor. Transformers are used in converters, which require isolation.
The switching network comprises of MOSFETs and diodes. With improvement in
the VLSI technology, smaller MOSFETs with increased power handling capability
are pushing the speed of operation of these power converters to the gigahertz (GHz)
range. Operation at such high frequencies not only require energy-efficient semicon-
ductor switches, but also demand for faster control mechanisms. Amongst the various
power converter control schemes studied in literature for high-frequency applications,
the hysteretic control scheme is given high importance. The hysteretic controller em-
ploys a basic operational amplifier (op-amp) and works similar to the Schmitt trigger
with hysteresis. Also, the bandwidth of op-amps is theoretically infinite and can be
designed with ease for many applications, making the hysteretic controller scheme,
simple and widely used method. This thesis focuses on understanding the operation
and characteristics of the hysteretic control scheme. Initially, a buck DC-DC pulse-
width modulated (PWM) converter is used as the power stage and the hysteretic
controller is designed to ensure proper regulation of the output voltage of the buck
converter. Two different types of hysteretic control mechanisms, namely (a) dual-
charging mode and (b) capacitive-charging mode are investigated. The equations
necessary to design the controller for both modes are derived. Extensive simulations
are performed in order to evaluate the load and line regulation with and without
iii
the controller. Further, similar analysis is performed using a boost DC-DC PWM
power converter as the power stage. Various characteristics such as percentage load
regulation (LOR), percentage line regulation (LNR), and total harmonic distortion
(THD) are estimated for buck converters.
iv
Contents
1 Introduction 2
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Motivation for Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Thesis Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Buck Converter 7
2.1 Operation Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Time Interval 0<t ≤ DT . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Time Interval DT<t≤T . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Design of Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6 Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.7 Synchronous Buck Converter . . . . . . . . . . . . . . . . . . . . . . . 22
2.8 Synchronous Buck Converter- Simulation and Results . . . . . . . . . 25
3 Buck Converter with Hysteretic Control 30
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 Hysteretic Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3 Buck converter with Hysteretic control(using dual control mode) . . . 36
3.4 Load and Line Regulation of Hysteretic controlled Buck Converters . 42
4 Buck converter with hysteretic control uisng capacitive charging and
steady state analysis 46
4.1 Steady-state Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2 Simulation and Results . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.3 Load and Line Regulation of Hysteretic controlled Buck Converters . 55
4.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
v
5 Boost Converter 60
5.1 Open loop Boost Converter . . . . . . . . . . . . . . . . . . . . . . . 60
5.2 Closed loop Boost converter . . . . . . . . . . . . . . . . . . . . . . . 60
5.3 Operation of the Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.4 Simulations and Results . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6 Conclusion 68
6.1 Results and Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7 Future Work 71
8 Bibliography 72
vi
List of Figures
2.1 Circuit diagram of a buck converter. . . . . . . . . . . . . . . . . . . 8
2.2 Inductor current waveforms for both CCM and DCM mode of operation. 9
2.3 Key switching waveforms of the buck converter in CCM. . . . . . . . 10
2.4 Circuit of the buck converter at time t =0. . . . . . . . . . . . . . . . 11
2.5 Circuit of the buck converter at time t = DT . . . . . . . . . . . . . . 12
2.6 Inductor voltage waveform. . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7 Drain current, drain-to-source voltage and gate-to-source voltage of the
MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.8 Diode switching voltage and current. . . . . . . . . . . . . . . . . . . 21
2.9 Inductor current and voltage across the capacitor. . . . . . . . . . . . 21
2.10 Circuit diagram of a synchronous buck converter. . . . . . . . . . . . 22
2.11 Drain current, drain voltage and gate voltage of the n-type MOSFET. 25
2.12 Drain current, drain voltage and gate voltage of the p-type MOSFET. 26
2.13 Waveforms of output voltage, current and the inductor current with
the changes in load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.14 Waveforms of output voltage, current and inductor current with the
changes in line voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.15 Load resistance vs. output voltage. . . . . . . . . . . . . . . . . . . . 28
2.16 Load resistance vs. output current. . . . . . . . . . . . . . . . . . . . 28
2.17 Input Voltage vs. output voltage. . . . . . . . . . . . . . . . . . . . . 28
2.18 Input Voltage vs. output current. . . . . . . . . . . . . . . . . . . . . 28
3.1 Block diagram of DC-DC converter with hysteresis control. . . . . . . 31
3.2 Block diagram of open loop PWM DC-DC converter. . . . . . . . . . 31
3.3 Waveform representing the operation of Schmitt trigger. . . . . . . . 32
3.4 Block diagram representing DC-DC converter with hysteretic control. 32
vii
3.5 Circuit of the Schmitt trigger. . . . . . . . . . . . . . . . . . . . . . . 33
3.6 Hysteretic characteristics curve. . . . . . . . . . . . . . . . . . . . . . 34
3.7 Output and input voltages of the Hysteretic comparator. . . . . . . . 35
3.8 Buck converter with hysteretic control using dual control mode. . . . 36
3.9 Start-up logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.10 Waveforms during the initial start-up of buck converter. . . . . . . . . 39
3.11 Voltages and currents across the MOSFETs for the start up pulse. . . 39
3.12 Input and output voltages of the comparator with the hysteretic con-
troller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.13 Drain current, voltage and gate to source voltage of n MOSFET. . . . 41
3.14 Drain current, voltage and gate to source voltage of p MOSFET. . . . 41
3.15 Steady state waveforms of the buck converter. . . . . . . . . . . . . . 42
3.16 Waveforms of inductor current, gate to source voltage and output volt-
age for changes in load resistance. . . . . . . . . . . . . . . . . . . . . 43
3.17 Load resistance vs. output voltage. . . . . . . . . . . . . . . . . . . . 43
3.18 Load resistance vs. output current. . . . . . . . . . . . . . . . . . . . 43
3.19 Waveforms of inductor current, gate to source voltage and output volt-
age for changes in line voltage. . . . . . . . . . . . . . . . . . . . . . . 44
3.20 Input voltage vs. output voltage. . . . . . . . . . . . . . . . . . . . . 45
3.21 Input voltage vs. output current. . . . . . . . . . . . . . . . . . . . . 45
4.1 Buck converter with hysteretic control technique-capacitive charging. 47
4.2 Simplified circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.3 Waveforms of buck converter during the initial charging of the capacitor. 53
4.4 Output Voltage, VO and the Gate-to-source voltage, VGS waveform of
the converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
viii
4.5 Waveforms of the inductor current indicating frequency of operation
and output and input power indicating efficiency. . . . . . . . . . . . 54
4.6 Waveforms of the inductor current, duty cycle, output and input volt-
age for changes in line voltage. . . . . . . . . . . . . . . . . . . . . . . 55
4.7 Waveforms of the inductor current, input voltage. . . . . . . . . . . . 56
4.8 Output voltage vs. input voltage. . . . . . . . . . . . . . . . . . . . . 56
4.9 Output current vs. input voltage. . . . . . . . . . . . . . . . . . . . . 56
4.10 Waveforms of the output voltage and duty cycle for changes in load
resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.11 Waveforms for inductor current for changes in load resistance. . . . . 58
4.12 Output voltage vs. load resistance. . . . . . . . . . . . . . . . . . . . 58
4.13 Output current vs. load resistance. . . . . . . . . . . . . . . . . . . . 58
5.1 Open loop boost converter. . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2 Waveforms of open loop boost converter. . . . . . . . . . . . . . . . . 62
5.3 Closed loop boost converter with hysteretic control technique. . . . . 63
5.4 Output voltage and current and inductor current of boost converter in
open loop configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.5 Steady state waveforms of closed loop boost converter. . . . . . . . . 65
5.6 Input power and output power of closed loop boost converter. . . . . 65
5.7 Simulated waveforms of the boost converter for changes in input voltage. 66
5.8 Simulated waveforms of the boost converter for changes in load resistance. 67
6.1 Load Resistance vs. output voltage. . . . . . . . . . . . . . . . . . . . 69
6.2 Load Resistance vs. output current. . . . . . . . . . . . . . . . . . . . 69
6.3 Input Voltage vs. output voltage. . . . . . . . . . . . . . . . . . . . . 69
6.4 Load Resistance vs. output current. . . . . . . . . . . . . . . . . . . . 69
ix
Acknowledgement
I would like to express my heartfelt gratitude to my advisor Dr. Marian K.
Kazimierczuk, whose support, patience, and kindness has helped me benefit the most
out of this thesis. He was much more than a technical adviser and I will always
cherish his guidance. I wish to thank my committee members, Dr. Kuldip Rattan
and Dr. Yan Zhuang, for giving me valuable suggestions and advice on this thesis.
My sincere regards to my parents, Sandeep Chauhan and Sunchita Chauhan and
my brother, Siddhartha Chauhan whose support and encouragement have been in-
valuable.
The present research would not have completed without the support and guidance
and motivation by my fellow colleague Agasthya Ayachit. My heartfelt thanks and
best wishes to him.
Last but not the least, my thanks to Abhishek Devgan and all my friends and
relatives who have helped me be at the right place and at the right time.
1
1 Introduction
1.1 Background
Switched mode DC-DC converters are a class electronic devices which convert input
voltage from one level to the other. These types of converters are useful in portable
electronic devices that consists of many different sub circuits, each of which requires its
own voltage level which is different from that supplied by an external source or battery.
The switched mode DC-DC converters convert the DC voltage from one level to
another. This is done by storing energy temporarily from the input and then releasing
that energy to the output at a different voltage level. These kind of converters operate
in two different modes, continuous conduction mode and discontinuous conduction
mode. In continuous conduction mode, the inductor current flows continuously during
the entire part of cycle.However, in discontinuous conduction mode, the inductor
current is continuous only for some part of the cycle and discontinuous for the other
part.
The DC-DC converters are improved by using synchronous rectification where the
Flywheel diode is replaced by a MOSFET thereby incurring less losses and thus more
efficiency. Multiple chip vendors implement these switching converters on different
chips. There are different types of DC-DC converters used: buck converter, boost
converter, buck boost converter, fly back converter, inverting converter etc. To achieve
a proper regulated output, most of the DC-DC converters are used in closed loop
configuration with different types of control mechanisms [1].
Switching transistors are driven by a duty cycle that is proportional to the control
voltage. This technique is equivalent to voltage mode control and it uses the control
voltage which is a difference of actual output voltage and a reference chosen. This
generates the pulse train used to drive the switches. Another technique known as
current mode control is used where the peak current of the inductor is used as a control
2
technique. Each of these techniques have its own advantages and disadvantages. The
earlier forms of Bang bang controllers have been reinvented by researchers due to its
advantages of fast transient response and less losses and a lesser component count
observed by power electronics researcher and this technique is known as hysteretic
control [2].
The operational amplifiers used in this design are the hysteretic comparators also
formally known as Schmitt triggers [3]-[4]. The Schmitt trigger uses a dynamic thresh-
old which prevents any noise signal to affect the duty cycle of the signal generated at
the output of a comparator [4]. The duty cycle of the pulse at the output of Schmitt
trigger can be easily controlled by changing the two threshold levels of the Schmitt
trigger. The design of hysteretic control techniques based on a synchronous rectifier
and Schmitt trigger in a buck converter is mostly used due to the simpler design and
the fast transient response and ease of modelling the equations both in steady state
and dynamic analysis. As compared to other control techniques, where a separate
sawtooth voltage is applied to one of the terminals of the comparator externally, the
hysteretic control technique uses the saw tooth waveforms generated as part of induc-
tor current or by the output voltage to generate the required levels of comparison for
the comparator to compare and generate pulses to drive the gates of the MOSFET.
The use of only a single comparator in a hysteretic control not only reduces the com-
ponent count but also reduces the losses in the circuit thereby increasing the efficiency
of the circuit. The use of a simple RC network helps the converter provide excellent
transient performances and the stable switching action [5]. In a hysterteic control
buck converter including synchronous rectification, a RC network is superimposed on
the output voltage to the sensed output voltage at the input of hysteretic comparator
[6]. The steady state and dynamic analysis of these converters [7] was done theoreti-
cally to show how frequency and duty cycle are dependent on the converter and the
3
comparator parameters and how these parameters can be changed to desired levels.
The techniques of feed-forward and feedback control [8] were implemented to ensure
better results for load and line regulation. These techniques show that theoretical
and practical results are almost similar and an increase in the frequency and control
of the circuit. The next improvements were made in making the hysteretic control as
an adaptive frequency circuit to be used in portable devices. This technique imple-
mented a differentiators and a window control to achieve the ultra fast switching of
the proposed converter[9].
The hysteretic control employs a fast transient response and stable operation with-
out using any error amplification or phase compensation technique. The techniques
discussed for Buck converter using a hysteretic control can also be applied to its coun-
terpart Boost converter. As mentioned previously, both feed forward and feedback
techniques have been used with Boost converter to ensure proper operation and good
efficiency and steady state and dynamic performance as mentioned in [10]. Most of
the techniques used in boost control is based on inductor current information and
output voltage. The only reason for this is that the inductor current and output
voltage ripple are out of phase in case of a boost converter and therefore only the
output voltage can only not be used for feedback as mentioned in [11].
One of the techniques as mentioned in [12] uses dual control modes for the proper
operation of the hysteretic controlled boost converter. This technique uses voltage
mode hysteretic conversion instead of current mode. The voltage mode is used due
to its simplicity in design and stable performance and fast response. This technique
has a start up period where a pulse voltage source with a specified duty cycle controls
the circuit. Once the desired output is reached, the control passes to the hysteretic
mode and thus regulate the output. The hysteretic control technique is effectively
implemented.
4
1.2 Motivation for Thesis
Implementing a proper control technique for DC-DC converters has always been chal-
lenge for power electronics researchers. Hysteretic controlled power converters which
are simple to design and have an extremely fast transient response make the power
supply design easier. They respond to changes in line or load right after the tran-
sient takes place. These converters also do not require any closed loop compensation
network components. As with the world shrinking down to integrated circuits, space
on the circuit board becomes a major concern while designing any circuit. With
improvements in VLSI technology, the use of smaller MOSFETs and with increased
power handling capabilities are pushing the operation of DC-DC converters to the
(GHz) range. With hysteretic control technique it can be readily achieved. Operation
at these high frequencies require not only energy efficient semiconductor switches but
also faster control techniques.
Thus with the course of time and and literature survey, the control technique
describing its operation, methods of implementation on different types of DC-DC
converters was studied. The steady state response of the control technique imple-
mented on both buck and boost converters were studied.
1.3 Thesis Objectives
In Chapter 2, the buck converter in open loop configuration is introduced along
with its operation and design characteristics. Difference between a synchronous and
asynchronous buck converter is also discussed in Chapter 2. Chapter 3 discusses
a the operation of hsyteretic control technique. Closed loop buck converter with
hysterteic controlled technique using start up pulse is also discussed. The line and load
regulation provided by the above technique is also discussed in Chapter 3. Chapter 4
discusses the operation of closed loop buck converter with hysteretic control technique
5
using capacitive charging technique. A comparison is made between the line and load
regulation characteristics of closed loop buck converter with hysteretic control using
both the methods as discussed in chapter 3 and 4 and open loop converter is made.
Chapter 5 discusses the implementation of the hysteretic control technique to boost
converter and discusses characteristics like percentage load and line regulation of the
converter.
6
2 Buck Converter
A DC-DC converter is an electronic circuit which helps convert from one DC voltage
level to other and from one current level to another. These are a class of power
converters. Many small DC-DC converters are used in military, aerospace, and other
areas which require greater reliability. DC-DC converters are also used in portable
electronic devices like cellular phone, laptop computers, which get their power from
batteries. Electronic devices consist of many different types of sub circuits which
require their own voltage level which is different from that supplied by the external
supply or battery. The different kinds of DC-DC converters used in practice are
buck, boost, buck-boost, flyback and forward converters. The main advantages of
using DC-DC converters are:
• These converters offer switched mode operation with a high efficiency.
• These converters can be used for step down, step-up or both, or inversion op-
erations.
• These converters can be operated at high output power.
This chapter discusses about buck converters, which is a switched mode power sup-
ply. A buck converter is a step-down DC-DC voltage converter and current step-up
converter. Buck converter circuit consists of a power MOSFET and diode which work
as switches. Here, the power MOSFET is used as a switch which is controllable. It
also consists of an inductor L, a capacitor C and a load resistor RL. The switch
and the diode forms the switching network and the inductor, capacitor and the load
resistor forms the low-pass filter. The circuit is sometimes also known as a ’chopper’
because the LC switching network chops the dc input voltage, VI
7
Figure 2.1: Circuit diagram of a buck converter.
2.1 Operation Buck Converter
The circuit diagram of a buck converter is as shown in Figure 2.1. In the figure,
the switch is represented by the symbol S, the diode is denoted by the symbo D,
inductor as L, capacitor as C and load resistance as RL. There are two modes
of operation of a buck converter, they are the continuous conduction mode(CCM)
and the discontinuous conduction mode(DCM). In continuous conduction mode, the
inductor current is continuous during the entire cycle. In DCM the Inductor current
flows only during a part of the cycle and then falls to zero, remains at zero for
sometime and then starts to increase in the successive cycle. The waveforms of
the inductor current showing the operation in continuous conduction mode and also
discontinuous conduction mode are shown in Figure 2.2. In this section continuous
conduction mode is discussed and the operation of Buck converter is analyzed for
continuous conduction mode. The Figure 2.3 shows the wave forms for the operation
of the buck converter in CCM. The MOSFET is given a gate-to-source pulse voltage
source and it is turned ON and OFF. The input is applied to the drain of the MOSFET
8
Figure 2.2: Inductor current waveforms for both CCM and DCM mode of operation.
and the output is taken from the source. The gate is supplied with the pulse waveform.
When the pulse goes high the MOSFET is on and thus the MOSFET turns on which
then charges the inductor and thereby current to flow through the load resistor. The
time interval for which the pulse turns ON is called the on time of the MOSFET
which decides the duty cycle of the converter and it is given by.
D =ton
T(2.1)
D =ton
ton + toff
(2.2)
D = fston (2.3)
where ton is the interval of time when the MOSFET turns ON and toff is the
interval of time when the MOSFET turns OFF.
As the duty cycle of the drive voltage vGS varies, the duty cycle of other wave
forms too vary during any changes in input or output conditions.
9
Figure 2.3: Key switching waveforms of the buck converter in CCM.
10
Figure 2.4: Circuit of the buck converter at time t =0.
When the pulse given to the transistor is high, the switch turns ON and the diode
is OFF and when the pulse goes low, the switch is OFF and the diode turns ON.
At t = 0, the MOSFET is turned ON by the gate-to-source voltage. This causes the
diode, D to be reversed biased by introducing a voltage of −VI across it. The voltage
across the inductor is given by VI − VO, which causes the inductor current to increase
linearly. The current flowing through the switch is same as that flowing through the
inductor i.e. is = iL. Thus energy of the DC input voltage source is transferred to
the inductor L, capacitor C, and the load resistance RL. The circuit depicting this
operation is shown in Figure 2.3.
At time t = DT , the MOSFET gets turned off by the gate-to-source drive voltage
vGS. Now inductor current does not go to zero as soon as the MOSFET gets turned
off as the current flowing through the inductor is continuous i.e. it never reaches 0, it
flows in the same direction thus acting as a current source The circuit depicting this
operation is shown in Figure 2.4.
In this case the input voltage source is disconnected from the output.
Thus, the input voltage which is a dc signal is converted to a square wave signal
from the switching network and this square wave signal acts as an input to the LC
11
Figure 2.5: Circuit of the buck converter at time t = DT .
network then passes through it. The LC network acts as a low pass filter of second
order and then removes the ripples from the waveform. This converts the square wave
signal to a dc voltage that has lower ripple. The duty cycle controls ON time of the
switch,S and thus the duty cycle may be varied form 0 to 100%.
2.2 Assumptions
To analyze the operation of Buck Converter, the following assumptions were made.
• The MOSFET and the diode are assumed to be ideal switches.
• To neglect the switching losses, the output capacitance of the transistor, diode
and their lead inductance is assumed zero.
• The passive components are assumed to be linear, time invariant, and frequency
independent.
• The impedance at the output of the input voltage source VI is zero for both AC
and DC components.
• It is also assumed that the Buck converter is operating in steady-state.
12
• It is assumed that the time constants of the reactive components is much larger
than the switching period T = 1fs
.
The operation of the buck converter for time interval 0 < t ≤ DT and for the
time interval DT < t ≤ Ts is described as follows.
2.3 Time Interval 0<t ≤ DT
The MOSFET is turned ON and the diode is turned OFF during the time interval
0<t ≤ DT . From the Figure 1.4, it can be observed that when the switch is on, the
input voltage source, VI is connected to the output. The diode D is reverse biased
with a voltage across the diode vD is equal to −VI . The voltage across the switch, vS
and the diode current, iD are zero. Inductor voltage vL is given by
vL = VI − VO = LdiL
dt(2.4)
Thus the current flowing through the inductor, iL and the switch, iS is given by
iS = iL =1L
∫ T
0vL dt + iL(0)
iS = iL =VI − VO
L
∫ t
0dt + iL(0) =
VI − VO
Lt + iL(0)
Here iL(0) is the initial value of current in the inductor at time t = 0. Thus the
peak inductor current iL is given by
iL(DT ) =(VI − VO)DT
L+ iL(0) (2.7)
and the peak-to-peak value of the ripple current of the Inductor, ∆iL is
13
∆iL = iL(DT ) − iL(0) =(VI − VO)DT
L=
VID(1 − D)fSL
(2.8)
The diode voltage is given by
vD = −VI (2.9)
The peak value of the diode reverse voltage is given by
VDM = VI (2.10)
The peak value of the switch current is given by
ISM = IO +∆iL
2(2.11)
where IO is the output current.
Therefore, in the time interval between 0 to DT , the increase in the magnitude of
energy in the inductor is given by
∆WL(in) =12
[i2L(DT ) − i2
L(0)] (2.12)
After the time interval DT , gate-to-source voltage vGS turns OFF the MOSFET.
2.4 Time Interval DT<t≤T
The MOSFET is turned OFF and the Diode is turned ON in the time interval
betweenDT<t ≤ T . From the Figure 2.5, it can be observed that when the switch is
off, the input voltage source, VI is disconnected to the output. When the MOSFET is
turned OFF, the inductor current, iL(DT ) is non zero as it is continuous function of
time which turns the diode ON. At this instant, the current, iS through the MOSFET
and the voltage, vD across the diode are zero. The voltage, vL across the inductor is
given by
14
vL = −VO = LdiL
dt(2.13)
The current flowing through the inductor L and the diode D is given by
iD = iL =1L
∫D
T tvL dt + iL(DT ) =−VO
L
∫D
T t dt.
+ iL(DT ) = −VO
L(t − DT ) + iL(DT )
iL(DT ) is the current of the inductor L at t = DT . The peak to peak ripple
current flowing through the inductor is given by
∆iL = iL(DT ) − iL(T ) =VOT (1 − D)
L=
VO(1 − D)fsL
(2.15)
iLmax =VO(1 − Dmin)
fsL(2.16)
The peak value of the switch voltage VSM is
VSM = VI (2.17)
The peak value of the diode and the switch currents is
IDM = IO +∆iL
2(2.18)
Therefore, the decrease in the magnitude of the stored energy in the inductor in
the time interval DT to T is given by
∆WL(in) =12
[i2L(DT ) − i2
L(T )] (2.19)
After the time interval, t = T the gate-to-source voltage vGS turns ON the MOS-
FET. During the steady state operation, the maximum voltage and current of the
15
Figure 2.6: Inductor voltage waveform.
diode and the switch is given by
VSMmax = VDMmax = VImax (2.20)
and the current stress is
ISMmax = IDMmax = IOmax +∆iLmax
2= IOmax +
VO(1 − Dmin)2fsL
(2.21)
The inductor voltage waveform can be represented as shown in Figure 2.6.
The area of the waveform enclosed by the positive part, A+ equals the area of the
waveform enclosed by the negative part, A−. Thus
A+ = A− (2.22)
where A+ is given by
A+ =∫ DT
0vL dt
16
and A− is given by
A− = −∫ T
DTvL dt
Therefore,
(VI − VO)DT = VO(1 − D)T (2.25)
The above equation simplifies to the form
VO = DVI (2.26)
Thus the DC voltage transfer function of the loss less buck converter is given by
MV DC =VO
VI
=II
IO
= D (2.27)
The range of MV DC is
0 ≤ MV DC ≤ 1 (2.28)
The DC current transfer function of the loss less buck converter is given by
MIDC =IO
II
=1D
(2.29)
The equations derived above explain the operation of the buck converter in CCM.
Thus a buck converter can be designed using the equations derived for steady state
operation of buck converter CCM.
2.5 Design of Buck Converter
The following specifications are considered for the design of buck converter. Input
Voltage, VI = 28±4V, Output voltage, VO = 12V, Output current, IOmin = 1A,
17
IOmax = 10A, Switching frequency, fs = 100kHz, Voltage ripple, Vr/VO ≤ 1A The dc
output power is
POmax = VOIOmax = 12 × 10 = 120W (2.30)
POmin = 12 ∗ 1 = 12W (2.31)
The load resistance is
RLmin =VO
IOmax
=1210
= 1.2Ω (2.32)
RLmax =VO
IOmin
=121
= 1.2Ω (2.33)
The dc voltage transfer function is
MV DCmin =VO
VImax
=1232
= 0.375 (2.34)
MV DCnom =VO
VInom
=1228
= 0.43 (2.35)
MV DCmax =VO
VImin
=1224
= 0.5 (2.36)
It is also assumed here that the converter efficiency η = 85%. Thus the duty cycle
is
Dmin =MV DCmin
η=
0.3750.85
= 0.441 (2.37)
Dnom =MV DCnom
η=
0.430.85
= 0.506 (2.38)
Dmax =MV DCmax
η=
0.50.85
= 0.588 (2.39)
Also it is given that the switching frequency is 100kHz. So for CCM operation
the minimum inductance L required is
Lmin =RLmax(1 − Dmin)
2fs
=12 ∗ (1 − 0.441)
2 ∗ 105= 33.54µH (2.40)
18
Assuming L ≥ Lmin = 40/0.05Ω.
The ripple current in the inductor is
∆iLmax =VO(1 − Dmin)
fsL=
12 × (1 − 0.441)105 × 40 × 10−6
= 1.677A (2.41)
The ripple voltage is
Vr =VO
100=
12100
= 0.12V (2.42)
The maximum ESR of the filter capacitor is
rcmax =Vr
∆iLmax
= 120 × 10−31.677 = 71.56mΩ (2.43)
Assume rc = 50mΩ. The minimum filter capacitance is
Cmin = Dmax2fsrc =0.588
2 ∗ 105 ∗ 50 ∗ 10−3= 58.8F (2.44)
Assume Cmin = 100µF/25V/50mΩ. The voltage and current stresses of the power
MOSFET and the diode are
VSMmax = VDMmax = VImax = 32V (2.45)
ISMmax = IDMmax = IO +∆iLmax
2= 12 +
1.6772
= 10.839A (2.46)
Thus the buck converter is designed and the values of all the components in the
circuit are calculated. This buck converter is also known as an asynchronous buck
converter. This buck converter was simulated using SABER circuit simulator software
and tested. The following results and analysis are obtained.
19
t(s)
10.76m 10.77m 10.78m 10.79m 10.8m 10.81m 10.82m 10.83m 10.84m 10.85m 10.86m
(A
)
−2.0
−1.5
−1.0
−0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
(V
)
0.0
5.0
10.0
15.0
20.0
25.0
30.0
(V
)
−2.5
0.0
2.5
5.0
7.5
10.0
(A) : t(s)
i(d)
(V) : t(s)
vds_mosfet
(V) : t(s)
vgs_mosfet
Figure 2.7: Drain current, drain-to-source voltage and gate-to-source voltage of theMOSFET.
2.6 Results and Analysis
The buck converter was simulated and the following waveforms were observed. The
required output signal of 10V was obtained with the nominal duty cycle and the
switching waveforms of the MOSFET and the diode are shown in Figure 2.7 and
Figure 2.8 respectively.
Thus as can be seen from the Figure 2.7 and Figure 2.8, both the MOSFET and
the diode turn on and off alternately depending on the on and off time of the duty
cycle, D and the inductor current, iL. The inductor current and the capacitor voltage
are plotted to verify the switching frequency and the output ripple voltage across the
capacitor. These waveforms are as shown in Figure 2.9. From the waveform results,
it can be verified that the buck converter is operating at the switching frequency. The
power loss across the lossy components like inductor, capacitor and load resistor were
calculated and the total power loss is given by
PLS = 0.5663W (2.47)
20
t(s)
10.76m 10.77m 10.78m 10.79m 10.8m 10.81m 10.82m 10.83m 10.84m 10.85m 10.86m
(A
)
−2.0
−1.0
0.0
1.0
2.0
3.0
(V
)
−30.0
−20.0
−10.0
0.0
10.0
(A) : t(s)
i_diode
(V) : t(s)
vd_diode
Figure 2.8: Diode switching voltage and current.
t(s)
10.76m 10.77m 10.78m 10.79m 10.8m 10.81m 10.82m 10.83m 10.84m 10.85m 10.86m
(A
)
−1.0
0.0
1.0
2.0
3.0
4.0
(V
)
11.95
12.0
12.05
12.1
(A) : t(s)
i_L
(V) : t(s)
v_C
freq: 100000.0
PK2PK: 0.07139
Figure 2.9: Inductor current and voltage across the capacitor.
21
Figure 2.10: Circuit diagram of a synchronous buck converter.
The output power of the buck converter at full load is
POmin = 12.107W (2.48)
Therefore, at full load the efficiency of the buck converter is
η =PO
PO + PLS
=12.10712.7733
= 94% (2.49)
Hence the open loop buck converter is analyzed.
2.7 Synchronous Buck Converter
An asynchronous buck converter or the conventional buck converter has the diode and
the MOSFET working as switches in its circuit topology where as in a synchronous
buck converter the diode is replaced by a MOSFET and thus it consists of two MOS-
FETs operating as switches. The circuit diagram of the synchronous buck converter
is given in the Figure 2.10.
Thus in the figure diode D is replaced by a MOSFET, S2. Now since there are two
MOSFETs in the circuit, the MOSFET S1 is called the high side MOSFET and the
MOSFET S2 is called the low side MOSFET. During steady state operation, when
22
one switch is on, the other switch is off. Thus VO is regulated by the complimentary
turning ON and OFF of both the MOSFETs in steady state.
In the synchronous buck converter topology, the lower on resistance of the low
side MOSFET from drain-to-source, rDSon helps in reducing the losses significantly
thereby optimizing the overall conversion efficiency of the buck converter. The asyn-
chronous topology has more voltage drop in the diode and thus greater losses. Thus
the asynchronous topology dissipates more power as compared to the synchronous
topology.
Output voltage is another key factor for determining the best topology. The lower
is the output voltage, VO, The closer it is to the voltage drop of the bottom side diode.
Thus a lower VO means higher loss. The comparison between the synchronous and
asynchronous factors are as discussed.
• Duty Cycle: The duty cycle D is the same for both synchronous and asyn-
chronous buck converters. Considering the above design example, the nominal
duty cycle is Dnom = 0.506. This means that 50.6% of the converter time is
spent in switching mode while 49.4% of the converter time is spent in the free-
wheel mode using the bottom side switch. When operating in asynchronous
mode, the power loss of the asynchronous converter at 10A during freewheel
mode is given by
PLOSS = VDiodedrop ∗ (1 − Dnom) ∗ IOut = 0.4 ∗ 49.4% ∗ 10 = 1.976W (2.50)
When operating in the synchronous mode, the power loss of the synchronous
converter at 10A during freewheel mode is given by
PLOSS = VMosfetdrop ∗ (1 − Dnom) ∗ IOut = 0.1 ∗ 49.4% ∗ 10 = 0.494W (2.51)
23
Thus considering the duty cycle, the power loss in the synchronous converter is
lesser than that of the asynchronous converter.
• Percent Power Loss
The percent power loss of the asynchronous converter is given by
PLS = VDiodedrop ∗ (1 − Dnom)/VOut = 0.4 ∗ 49.4/12 = 1.6467% (2.52)
The percent power loss in the synchronous converter is given by
PLS = VMosfetdrop ∗ (1 − Dnom)/VOut = 0.1 ∗ 49.4/12 = 0.41167% (2.53)
Thus the percent power loss in case of a synchronous converter is lesser than
the asynchronous converter.
The disadvantages of the synchronous buck converter is that, the low side MOS-
FET will not turn on automatically. An additional drive circuitry is needed within
the control IC so as to turn it on and off. In case of the asynchronous buck converter,
the polarity reversal of the inductor current automatically forward biases the diode,
D. Thus this extra drive circuitry in the case of a synchronous buck converter in-
creases the die area of the chip on which it is used. Therefore a synchronous converter
topology comes at a cost penalty. A synchronous buck converter has the same set of
design equations for the inductor, L and the capacitor, C as that for an asynchronous
buck converter. The difference lies in the overall efficiency of both the converters.
Due to replacement of the diode with the MOSFET, the losses are reduced and thus
it improves the efficiency in case of a synchronous buck converter.
The synchronous buck converter topology was simulated in saber circuit simulator
and the following wave forms were obtained.
24
t(s)
10.76m 10.77m 10.78m 10.79m 10.8m 10.81m 10.82m 10.83m 10.84m 10.85m
(V
)
−10.0
−5.0
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
(V
)
−10.0
−7.5
−5.0
−2.5
0.0
2.5
5.0
7.5
10.0
(A
)
−2.0
−1.0
0.0
1.0
2.0
3.0
4.0
(V) : t(s)
vds_ntype
(V) : t(s)
vgs_ntype
(A) : t(s)
id_ntype
Figure 2.11: Drain current, drain voltage and gate voltage of the n-type MOSFET.
2.8 Synchronous Buck Converter- Simulation and Results
The waveforms of the gate to source voltage, drain voltage and drain current of both
the types of MOSFETs i.e. the n-type and the p-type are as shown in Figure 2.11
and Figure 2.12 respectively.
Since the waveforms across the inductor, capacitor and the load resistor are sim-
ilar to that obtained through asynchronous buck converter so those waveforms are
not plotted here. Finally the total losses were calculated for the synchronous buck
converter and the following results were obtained.
PLS = 0.185976W (2.54)
Thus the total losses across all the components have reduced as compared to the
asynchronous buck converter as obtained using (2.49). The output power of the buck
converter at full load is given by
PO = 12.91W (2.55)
25
t(s)
10.76m 10.77m 10.78m 10.79m 10.8m 10.81m 10.82m 10.83m 10.84m 10.85m
(V
)
−35.0
−30.0
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
5.0
10.0
(V
)
−10.0
−7.5
−5.0
−2.5
0.0
2.5
5.0
7.5
10.0
(A
)
−3.0
−2.0
−1.0
0.0
1.0
2.0
3.0
4.0
(V) : t(s)
vds_ptype
(V) : t(s)
vgs_ptype
(A) : t(s)
id_ptype
Figure 2.12: Drain current, drain voltage and gate voltage of the p-type MOSFET.
Therefore the efficiency of the buck converter is given by
η =PO
PO + PLS
=12.91
13.095976= 98% (2.56)
Therefore as compared to (2.51), there is a 4% improvement in efficiency. In this
case, there is a lesser improvement due to the use of ideal MOSFETs and diode. But
practically when real time MOSFETs and diodes are used, there is a large difference
seen in this efficiency. Thus the synchronous buck converter is also simulated and
its results are verified both practically and theoretically. Also the improvement in
efficiency using the synchronous buck converter is observed.
Now since this is the open loop case without a controller and feedback network,
there is a very poor load and line regulation in the circuit. The changes in the output
voltage waveform with the change in load and line are as shown in Figure 2.13 and
Figure 2.14 respectively. Thus whenever there is a change in the load, the output
voltage and the current changes as the load changes without regulating the output.
When there is a change in line voltage, the output also changes with it and thus
shows no regulation of the output.
26
(O
)
0.0
50.0
100.0
150.0
t(s)
0.0 2.0m 4.0m 6.0m 8.0m 10.0m 12.0m 14.0m 16.0m 18.0m 20.0m
(V
)
−10.0
0.0
10.0
20.0
Ave: 12.001
Ave: 12.542
(A
)
−1.0
0.0
1.0
2.0
(A
)
−2.0
0.0
2.0
4.0
6.0
8.0
10.0
(O) : t(s)
R_L
(V) : t(s)
Vout
(A) : t(s)
I_O
(A) : t(s)
iL
Figure 2.13: Waveforms of output voltage, current and the inductor current with thechanges in load.
Graph0
(V
)
20.0
30.0
40.0
50.0
60.0
70.0
80.0
t(s)
0.0 2.0m 4.0m 6.0m 8.0m 10.0m 12.0m 14.0m 16.0m 18.0m 20.0m
(V
)
−10.0
0.0
10.0
20.0
30.0
40.0
(A
)
−1.0
0.0
1.0
2.0
3.0
(A
)
−20.0
−10.0
0.0
10.0
20.0
(V) : t(s)
V_in
(V) : t(s)
V_O
(A) : t(s)
I_O
(A) : t(s)
iL
Figure 2.14: Waveforms of output voltage, current and inductor current with thechanges in line voltage.
27
10 20 30 40 50 60 70 800
5
10
15
20
25
30
VO
(V)
RL (Ω)
Figure 2.15: Load resistance vs. out-put voltage.
10 20 30 40 50 60 70 800
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
I O (A
)
RL (Ω)
Figure 2.16: Load resistance vs. out-put current.
10 20 30 40 50 60 70 800
10
20
30
40
50
60
70
80
VO
(V)
VI (V)
Figure 2.17: Input Voltage vs. outputvoltage.
10 20 30 40 50 60 70 800
1
2
3
4
5
6
7
8
I O (A
)
VI (V)
Figure 2.18: Input Voltage vs. outputcurrent.
The line and load regulation waveforms were also plotted on MATLAB. The MAT-
LAB plots for load regulation indicating change in load resistance vs. output voltage
and current are shown in Figure 2.15 and Figure 2.16. This was done to effectively
compare open and closed loop circuits as discussed in next chapters.
The MATLAB plots for line regulation indicating change in Input voltage vs.
output voltage and output current are shown in Figure 2.17 and Figure 2.18.
Thus the disadvantages of this circuit have been discussed. These disadvantages
are overcome by using the feedback loop with the hysteretic controller as discussed
in the next chapter. Thus the proposed buck converter topology with hysteretic
buck converter as discussed in the next chapter uses a synchronous buck converter
28
as losses and efficiency of the converter are the major criteria that are taken into
consideration.
29
3 Buck Converter with Hysteretic Control
3.1 Introduction
A buck converter with hystertic control is one of the closed loop control technique.
This control scheme consists of a buck converter as its power stage and the hysteretic
control circuit in its feedback loop. This control scheme has gained attention due to
its fast transient response, simple design due to the presence of a single hysteretic
comparator, higher efficiency as compared to other control techniques like voltage
mode control, current mode control etc. This control scheme is immune to unwanted
fluctuations that may occur due to the use of Schmiitt trigger as a hysteretic com-
parator. The block diagram of the control scheme is shown in Figure 3.1.
3.2 Hysteretic Comparator
Every DC-DC PWM converter requires a pulse signal of appropriate duty cycle to
switch the MOSFETS to ensure appropriate operation of the converter. In open
loop PWM converter, this pulse is generated by a comparator whose inverting and
non inverting inputs are connected to a voltage reference and a sawtooth voltage
respectively which generates a pulse signal as required by a PWM DC-DC converter.
The basic block diagram of the circuit is as shown in Figure 3.2.
A comparator generally changes its output states when the voltages between its
inputs cross through approximately zero volts. However noise can cause voltage fluc-
tuations at the inputs. This can cause undesirable rapid changes between the two
output states. This unwanted rapid transitions can cause switching of the converter
at undesirable instances of time. To prevent this unwanted output oscillation, a
small hsyteresis is added to a comparator. A hysteresis comparator has two switch-
ing points: one for rising and other for falling voltages. Hysteresis is added to a
comparator by adding a positive feedback. The block diagram for this comparator
30
Figure 3.1: Block diagram of DC-DC converter with hysteresis control.
Figure 3.2: Block diagram of open loop PWM DC-DC converter.
31
Figure 3.3: Waveform representing the operation of Schmitt trigger.
Figure 3.4: Block diagram representing DC-DC converter with hysteretic control.
along with the waveforms is as shown in Figure 3.3.
In this circuit an inverting Schmitt trigger is used, which behaves like a comparator
with Hysteresis. This circuit has a positive feedback applied from the non inverting
input of the comparator to the output. This circuit thus converts an analog input
signal to a digital output signal. This positive feedback is implemented by adding
a part of the output voltage to the non inverting input. This circuit has a positive
feedback which means that its overall loop gain will be greater than one. The block
diagram of a DC-DC converter with hysteresis is as shown in Figure 3.4.
32
Figure 3.5: Circuit of the Schmitt trigger.
Therefore, the output helps the input. In an inverting schmitt trigger, when the
input voltage crosses the threshold in one direction, the same circuit changes its own
threshold to the opposite direction. Thus a part of the output voltage gets subtracted
from the threshold which is same as adding it to the input voltage. ’Hysteresis’
basically means that the current operating state of the system controls the threshold
voltage. This current operating state means the output voltage of this circuit i.e.
either positive saturation or negative saturation level. In this circuit, positive feedback
is used. This kind of feedback helps in transitions of the threshold voltage. The circuit
of an inverting Schmitt trigger is as shown in Figure 3.5. The hysteresis characteristics
curve is shown in Figure 3.6. The threshold voltage, Vth+ > 0 when the output voltage
is high and the threshold voltage, Vth− < 0 when the output voltage is low. In the
circuit, the value of Vth can be obtained by calculating the voltage across the voltage
divider consisting of the resistors, R1, R2, R3 and Vref . Whenever there is a change
in the threshold voltage of the circuit, there is a corresponding change in the output
voltage. Once the output goes high in response to the input, which has passed below
the threshold voltage, the threshold voltage is changed to a higher value, Vth+. But
when the input voltage passes above the level Vth+, the output then changes to its
33
Figure 3.6: Hysteretic characteristics curve.
low state causing the threshold to be set to a lower value defined by Vth−.
The values of Vth+ and Vth− are determined by the following set of equations.
Vth+ =R123Vref
R2
+R123Vu
R3
(3.1)
Vth− =R123Vref
R2
−R123Vu
R3
(3.2)
where
R123 =1
R1
+1
R2
+1
R3
(3.3)
The Schmitt trigger was circuit was simulated separately to observe its output
when a triangular source is given at the input. The waveforms are shown in Figure
3.7.
Thus from the Figure 3.3 and 3.7, it is observed that as there is a change in Vin
which causes to trigger a transition, small noise signal in the input cannot cause vin
to reverse its course enough to cross the Hysteresis gap. Thus undesired reversal of
the output state can be prevented. A complete immunity to noise from the input
signal can be made possible by increasing the Hysteresis gap. The hysteresis gap is
defined by the term ∆hys and is given by the equation
∆Hys = Vth+ − Vth− (3.4)
34
Graph for the input and output voltages of a hystertic comparator
t(s)
7.154m 7.156m 7.158m 7.16m 7.162m 7.164m
(V
)
4.4
4.6
4.8
5.0
5.2
5.4
5.6
(V
)
−20.0
−10.0
0.0
10.0
20.0
(V) : t(s)
Vin_noninv
Vin_inv
(V) : t(s)
Vout
Figure 3.7: Output and input voltages of the Hysteretic comparator.
The other advantage of using the Schmitt trigger with a positive feedback is that
with changes in the output, the feedback increases the difference between the op-amp
input voltages, accelerating the change in its output even if the open loop gain of the
op-amp is not that high. Thus due to the positive feedback action, the output voltage
will change at an increasing rate even if the op-amp slew rate limit is reached.
Therefore, from the waveforms we can observe the exact behavior of the Schmitt
trigger and the change in threshold levels. In the closed loop circuit, the output of a
buck converter which is similar to a sawtooth signal is applied to the inverting input
of the comparator and the non inverting input if provided with the reference signal
and also the positive feedback through the feedback resistors, R1, R2 and R3. This
generates a square pulse at the output which helps in producing the required duty
cycle to turn on and off the transistors.
35
Figure 3.8: Buck converter with hysteretic control using dual control mode.
3.3 Buck converter with Hysteretic control(using dual con-trol mode)
The buck converter circuit using synchronous rectifier with hysteretic control scheme
is as shown in Figure 3.8. This feedback path consists of a comparator U with
externally introduced hysteresis and feedback resistors.
The equations for the hysteretic comparator are given below. The equivalent
resistors connecting the non inverting terminal of the comparator is R123 = R1 ‖ R2 ‖
R3.
VH =R123Vref
R3
+R123VCC
R2
(3.5)
VL =R123Vref
R3
−R123VCC
R2
(3.6)
The input voltage V+ of the Buck converter depends on Vref , Vo, R1 and R2. The
36
hysteretic comparator switches from one threshold level to the other threshold level.
When the converter initially starts up, the inverting input of the op-amp has a small
positive value abd this value is less than V+. The amplifier saturates so that V+ = Vcc
and thus the switch is turned on. After some time when the levels of VO becomes
comparable to V+, the comparator enters into the linear region of its operation. VO
then decreases and also V+ decreases until the op-amp again enters into its saturation
region. When the output voltage or input voltage increases, the current through the
capacitor increases when it is charging at on mode while at the off mode, the current
through the capacitor decreases when it is discharging. Thus, there is a reduction in
the on time pulse duration while there is an increases in the off time pulse duration.
Due to the charging and discharging action, the converter gets into an oscillatory
mode where it generates pulses and once it reaches steady state, hysteretic control
takes place. Thus the switching duty cycle changes and the output voltage can be
regulated. The operation is described as below.
During the initial start up, a single pulse with the value of duty cycle as obtained
by theoretical calculations is applied as a gate-to-source voltage to the MOSFET.
This pulse switches the power transistors and charges the inductor and capacitor.
This starts the circuit and once the converter achieves steady state, the hysteretic
control takes over. The circuit diagram of start-up circuit is shown in Figure 3.9.
This control scheme requires a triangular like voltage ripple for a stable operation.
Thus the esr (equivalent series resistance) of the output capacitor has to be high so
that once the capacitor is charged, it generates the required ripples for the hysteretic
comparator to compare the threshold levels in phase. The operation of the circuit
with the start up pulse is as explained below.
Initially when the start up pulse flows through the converter, then due to the
digital logic stage as described in the above sections, the high side MOSFET gets
37
Figure 3.9: Start-up logic.
turned on and the low side MOSFET is turned off. This charges the capacitor thus
creating a ramp waveform at the output of it for the appropriate levels of comparison
for the comparator. Thus when the high side MOSFET gets turned on, the inductor
current, IL increases linearly with a slope of VI−Vo
L. Thus energy from the DC input
voltage source, VI gets transferred to the inductor, capacitor and the load. The
inductor current, output voltage and waveforms at the two inverting and non inverting
inputs of the hysteretic comparator are as shown in the Figure 3.10. Also during the
start-up pulse, when the feedback loop is disconnected, the voltages across both the
MOSFETs are as given in Figure 3.11.
In this circuit, there is no error detection, else every new pulse generated helps
in the generation of more pulses and thus due to the oscillatory action, the circuit
functions well and thus the output is maintained within the desired limits and hence
regulated.
Thus after the start up pulse has generated sufficient ramp signal at the output of
buck converter for the comparator to generate sufficient comparison levels, such that
once the feedback voltage, Vf exceeds the higher threshold level, VH , the output of
38
Graph0
(A
)
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
t(s)
1.0m 1.25m 1.5m 1.75m 2.0m 2.25m 2.5m 2.75m 3.0m
(V
)
9.0
9.5
10.0
10.5
11.0
11.5
12.0
12.5
13.0
(V
)
4.2
4.25
4.3
4.35
4.4
4.45
4.5
4.55
Ave: 12.122
Ave: 1.0076
(A) : t(s)
i_L
(V) : t(s)
VO
(V) : t(s)
V_inv
v_noninv
Figure 3.10: Waveforms during the initial start-up of buck converter.
Graph for voltages and currents across both the mosfets
t(s)
−1.0m 0.0 1.0m 2.0m 3.0m 4.0m
(V
)
−2.0
0.0
2.0
4.0
6.0
(V
)
0.0
10.0
20.0
30.0
40.0
(A
)
−1.0
0.0
1.0
2.0
(V
)
−30.0
−20.0
−10.0
0.0
10.0
(A
)
−1.0
0.0
1.0
2.0
(V) : t(s)
pulse_source
(V) : t(s)
vds_n−type
(A) : t(s)
i(d)_n−type
(V) : t(s)
vds_p−type
(A) : t(s)
i(d)_p−type
Figure 3.11: Voltages and currents across the MOSFETs for the start up pulse.
39
(V
)
5.0
5.5
6.0
6.5
t(s)
20.2m 20.3m 20.4m 20.5m 20.6m 20.7m 20.8m 20.9m 21.0m
(V
)
−20.0
−10.0
0.0
10.0
20.0
(V) : t(s)
V_inv
V_noninv
(V) : t(s)
V_U
Figure 3.12: Input and output voltages of the comparator with the hysteretic con-troller.
the comparator goes high, turning on the high side MOSFET and when the feedback
voltage, Vf goes below the lower threshold level, VL, the output of the comparator
goes low, turning on the low side MOSFET. The steady state operation of the buck
converter with the hysteretic control is shown the following waveforms. The waveform
of Figure 3.12 represents the input and output voltages of the comparator.
The Figure 3.13 and Figure 3.14 represents the gate and drain voltage and the
drain currents of n-type MOSFET and p-type MOSFET respectively.
Now since this circuit has a hysteretic comparator, the values of resistors must
be chosen such that the hysteresis window size is large to avoid any kind of noise
interference with the threshold levels. The inductor current can be used to verify the
frequency of operation and the gate to source voltage going into the gates of both
the MOSFET can be used to calculate the duty cycle. Thus the Figure 3.15 shows
the gate to source voltage, VGS of the MOSFET and input power, PI and output
power,PO of the buck converter. Thus a voltage mode control, hysteretic comparator
circuit is implemented.
40
Graph0
(A
)
−0.5
0.0
0.5
1.0
1.5
2.0
2.5
t(s)
13.0m 13.2m 13.4m 13.6m 13.8m 14.0m 14.2m 14.4m
(V
)
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
(V
)
−1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
(A) : t(s)
iD_nmos
(V) : t(s)
vds_nmos
(V) : t(s)
vgs_nmos
Figure 3.13: Drain current, voltage and gate to source voltage of n MOSFET.
Graph0
t(s)
13.0m 13.2m 13.4m 13.6m 13.8m 14.0m 14.2m 14.4m
(V
)
−30.0
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
5.0
(A
)
−1.0
−0.5
0.0
0.5
1.0
1.5
2.0
2.5
(V
)
−1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
(A) : t(s)
iD_pmos
(V) : t(s)
vds_pmos
(V) : t(s)
vgs_pmos
Figure 3.14: Drain current, voltage and gate to source voltage of p MOSFET.
41
Graph0
(V
)
−1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
t(s)
12.64m 12.65m 12.66m 12.67m 12.68m 12.69m 12.7m 12.71m 12.72m 12.73m
(W
)
−200.0
−150.0
−100.0
−50.0
0.0
50.0
100.0
(W
)
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
Ave: −13.365
(V) : t(s)
vgs(irf540.irf540_1)
(W) : t(s)
power(v_dc.v_dc5)
(W) : t(s)
power(r.r8)
Ave: 12.484
freq: 73599.0duty: 0.49118
Figure 3.15: Steady state waveforms of the buck converter.
3.4 Load and Line Regulation of Hysteretic controlled BuckConverters
Load regulation is the capability of a circuit to maintain a constant output voltage
(or current) on the output channel of a power supply circuit despite the changes in
load (in this case the change in load resistance). Every practical circuit has a certain
amount of load variations. This circuit has a good load regulation. The waveforms
in Figure 3.16 show the output voltage of the buck converter for changing loads. The
waveforms MATLAB plots for output voltage and current for changes in load are as
shown in Figure 3.17 and 3.18.
This load regulation is due to the fact that, the output of the buck converter is
directly connected to the inverting input of the hysteretic comparator. Now whenever
there is a change in the level of output voltage due to changing load, the threshold
levels, VH and VL of the hysteretic comparator changes, thereby changing the duty
cycle, that drives the gate of the MOSFETs to regulate the output voltage, VO.
Thus the output voltage waveform is regulated for changes in the load. But this
circuit has a disadvantage that with varying loads, the ripples in the output voltage
42
t(s)
0.0 2.0m 4.0m 6.0m 8.0m 10.0m 12.0m 14.0m 16.0m 18.0m 20.0m 22.0m 24.0m 26.0m 28.0m 30.0m
Ave: 12.599
duty: 0.49045
duty: 0.48977
duty: 0.49286duty: 0.48973duty: 0.51269
(O
)
0.0
50.0
100.0
150.0
(V
)
0.0
10.0
20.0
30.0
40.0
50.0
(A
)
0.0
0.5
1.0
1.5
2.0
2.5
(V
)
−10.0
0.0
10.0
20.0
30.0
40.0
(O) : t(s)
R_L
(V) : t(s)
V_O
(A) : t(s)
i_L
(V) : t(s)
V_GS
freq: 9917.5
Minimum: 0.051144
freq: 7459.7
freq: 10335.0
freq: 9481.8
freq: 10382.0
PK2PK: 3.1204PK2PK: 1.1661 PK2PK: 6.904
PK2PK: 2.1248
PK2PK: 4.0934
Figure 3.16: Waveforms of inductor current, gate to source voltage and output voltagefor changes in load resistance.
10 20 30 40 50 60 70 8010
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
VO
(V)
RL (Ω)
Figure 3.17: Load resistance vs. out-put voltage.
10 20 30 40 50 60 70 800
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
I O (A
)
RL (Ω)
Figure 3.18: Load resistance vs. out-put current.
43
Graph0
(V
)
20.0
30.0
40.0
50.0
60.0
70.0
80.0
t(s)
5.0m 7.5m 10.0m 12.5m 15.0m 17.5m 20.0m 22.5m 25.0m 27.5m
(V
)
10.0
15.0
20.0
25.0
30.0
(A
)
1.0
1.5
2.0
2.5
(V
)
−2.0
0.0
2.0
4.0
6.0
freq: 72820.0
freq: 78818.0
freq: 70660.0
freq: 44698.0
freq: 76217.0
Ave: 1.0208
Ampl: 0.03064
Ave: 12.238
Ampl: 0.19342
Ampl: 0.39833
Ampl: 0.24486
(V) : t(s)
VI
(V) : t(s)
vo
(A) : t(s)
i_L
(V) : t(s)
vgs(irf540.irf540_1)
Figure 3.19: Waveforms of inductor current, gate to source voltage and output voltagefor changes in line voltage.
increases as the load increases. This may burn components when dealing with small
power supplies. Also at every variation in load, there is a peak in the output voltage
waveform indicated by VO and this peak increases as the load resistance, RL increases.
This increases in ripples is due to the change in inductor current, iL which changes
the voltage across the capacitor and thus increases the ripples.
Line regulation is the capability of a circuit to maintain a constant output voltage
(or current) on the output channel of a power supply circuit despite changes in the
input voltage level. In real world, supply voltages do not always remain constant
and there are fluctuations in the input voltage. This control scheme has a good line
regulation. The output does remains regulated i.e. the output remains constant even
when there are changes in the input voltage. It is as shown in the Figure 3.19. As
observed from the waveforms, the ripples in the output circuit increase with change
of input voltage. However, output voltage does not get affected by the changes in
input and thus remains at a constant DC level. Thus as can be observed from the
waveforms of Figure 3.19, the frequency of the gate-to-source voltage varies by a small
44
10 20 30 40 50 60 70 800
5
10
15
20
25
30
35
40
45
50
VO
(V)
VI (V)
Figure 3.20: Input voltage vs. outputvoltage.
10 20 30 40 50 60 70 800
1
2
3
4
5
6
7
8
I O (A
)
VI (V)
Figure 3.21: Input voltage vs. outputcurrent.
amount .The average value of the output voltage almost remains constant, however
there is an increase in the output ripple. The MATLAB plots were obtained for
changes in output voltage and output current with change in input voltage and the
results are shown in Figure 3.20 and Figure 3.21. Thus as seen from all the simulation
results, the hysteretic controlled buck converter is a fast, simple low cost circuit with
a good load and line regulation. However, the disadvantages of this circuit is that this
control scheme requires a triangular like voltage ripple for a stable operation. Also
the other disadvantage is that the hsyteretic window size needs to be controlled and
an additional start up circuit is required. The next chapters discuss the methods of
improving the disadvantages of the hysteretic controlled buck converter.
45
4 Buck converter with hysteretic control uisng ca-
pacitive charging and steady state analysis
Buck converter with hysteretic control technique using start-up circuit has been ex-
plained in the previous chapter. However, the circuit uses an additional start up
pulse. Thus control schemes like Buck converter with capacitive charging have been
developed. A hysteretic voltage mode control scheme requires a triangular like ripple
for the stable operation of the circuit as shown in the previous section. The same
triangular ripple resembling the inductor current can be generated using different
techniques like using a series sense resistor with the inductor, or filtering the voltage
across the inductor to sense its current, or using current sensing FETs like SENSE-
FETs in parallel with the power MOSFETs to sense the current information. The
technique that is used in this section is using a capacitor that generates a charging
and discharging path similar to the inductor current information depending on the
output voltage of the buck converter. This can be generated by connecting a RC
network at the input of a comparator for stable operation. The start-up circuit can
be eliminated in this case and this scheme also helps in the analysis of the model
theoretically. This control scheme consists of a comparator implemented with exter-
nal hysteresis using some feedback resistors thus reducing the number of components
used. This is a stable control technique due to the absence of a an error amplifier in
the feedback path.
The buck converter with hysteretic control using capacitive charging technique is
shown in Figure 4.1.
The inverting terminal of the hysteretic comparator is connected to the output
voltage, VO of the buck converter. The non inverting terminal is connected to a a
reference voltage source, Vref . The use of Rf connected from Vf to VC changes the
voltage level to which we are comparing VO. The combination of resistors R and Rf ,
46
Figure 4.1: Buck converter with hysteretic control technique-capacitive charging.
a capacitor Cf at the non inverting terminal help in the formation of a triangular like
ripple at the non inverting input of the comparator thus preventing the use of any
start up circuit and reducing the number of components used. The main advantage
of the circuit is that the duty cycle can be controlled by the reference voltage source.
The relationship between duty cycle and the threshold voltages of the hysteretic
comparator are proved below. The circuit was simulated on saber and the results
showed that it has an efficiency of 80% and a switching frequency of 80KHz. The
simulated results were verified on MATLAB using the equations proved below.
4.1 Steady-state Analysis
The steady-state analysis starts with considering all the elements of the circuit to be
ideal. The voltage which flows across the feedback capacitor is assumed to be Cf . VH
and VL indicate the higher threshold level and the lower threshold level respectively
of the comparator. The voltage at the output of the comparator is assumed to be Vu.
Suppose the switching interval begins at t = 0.
• State1: 0 <t <TON
47
Figure 4.2: Simplified circuit
In this case initially the output voltage, Vu is in high level and the equations can
be derived as below from the simplifies circuit as shown in Figure 4.2. Applying
Kirchoff’s voltage law at the node, Vf , the following equations can be derived.
Vf − Vref
R+ i +
Vf − Vu
Rf
= 0 (4.1)
The current i flows through the capacitor, Cf and (3.1) can be written as
Vf − Vref
R+ Cf
dVf
dt+
Vf − Vu
Rf
= 0 (4.2)
Cf
dVf
dt=
Vref − Vf
R+
Vu − Vf
Rf
(4.3)
Cf
dVf
dt+ Vf
R + Rf
RRf
=Vref
R+
Vu
Rf
(4.4)
Assume that
RP =RRf
R + Rf
(4.5)
Thus (3.4) can be written as
dVf
dt+
Vf
CfRP
=Vref
CfR+
Vu
CfRf
(4.6)
The above differential equation can be solved by using the Integrating factor as
e
∫1
Cf RP . Thus (4.6) can be written as
48
∫ d
dt[e
∫1
Cf RP Vf ] =∫
[Vref
CfR+
Vu
CRf
]e∫
1
Cf RP (4.7)
et
Cf RP Vf = (Vref
CfR+
Vu
CfRf
)RP Cfet
Cf RP + x (4.8)
Vf = Vref
RP
R+ Vu
RP
Rf
+ xe−t
Cf RP (4.9)
The equation (4.9) can be solved under the initial condition of Vf (0) = VL and
thus can be solved as
VL − Vref
RP
R− Vu
RP
Rf
= x (4.10)
Thus (4.9) can be simplified by substituting the value of x in it under the initial
condition.
Vf = VLe−t
CRP + Vref
RP
R(1 − e
−tCf RP ) + Vu
RP
Rf
(1 − e−t
Cf RP ) (4.11)
Now to ensure that the state of the comparator is inverted, it is necessary that
Vf should be greater than VH , thus the following equations can be obtained.
VH>Vref
RP
R+ Vu
RP
Rf
(4.12)
Thus on time, TON is found by substituting Vf = VH and also the time, t = ton
in (4.11). Thus the equations can be simplified as
e−ton
Cf RP =VH − Vref
RP
R− Vu
RP
Rf
VL − VrefRP
R− Vu
RP
Rf
(4.13)
Thus the equation for ton can be written as
ton = CfRP lnVL − Vref
RP
R− Vu
RP
Rf
VH − VrefRP
R− Vu
RP
Rf
(4.14)
49
The equation can thus be simplified as
ton = CfRP
VH − VL
VH − VrefRP
R− Vu
RP
Rf
(4.15)
• State2: TON <t <TS
During this time interval, the output signal of the comparator is at a lower level
and thus the following equations can be obtained. As seen from the simplified
Figure 4.2, and using Kirchoff’s voltage rule,
Vf − Vref
R+ i +
Vf − (−Vu)Rf
(4.16)
Vf − Vref
R+ Cf
dVf
dt+
Vf + Vu
Rf
(4.17)
Cf
dVf
dt=
Vref − Vf
R−
Vf + Vu
Rf
(4.18)
As assumed in (4.5), the above equation can be reduced to
dVf
dt+
Vf
CfRP
=1
Cf
(Vref
R−
Vu
Rf
) (4.19)
The above differential equation can be solved by using the Integrating factor as
e
∫1
Cf RP .
Thus (4.19) can be written as
∫ d
dt(e
∫Cf RP dtVf ) =
1Cf
(∫ Vref
R−
Vu
Rf
)e∫
Cf RP (4.20)
Thus equation (4.20) can be reduced to
Vf = (Vref
R−
Vu
Rf
)RP + x1 (4.21)
50
where x1 is a constant Now during the initial condition, Vf (Ton) = VH , the
following equations can be obtained.
VH = (Vref
R−
Vu
Rf
)RP + x1 (4.22)
The above equation can be solved to obtain the value of the constant x1.
x1 = VH −VrefRP
R+
VURP
Rf
(4.23)
Therefore substituting the value of x1 in (4.22), we get
Vf =VrefRP
R−
VuRP
Rf
+ (VH − Vref
RP
R+ Vu
RP
Rf
)e−t
Cf RP (4.24)
The above equation can be rearranged as
Vf = VHe−t
Cf RP + Vref
RP
R(1 − e
−tCf RP ) − Vu
RP
Rf
(1 − e−t
Cf RP ) (4.25)
Thus from the above equation , we can observe that Vf decreases and this
decrease is from
VHtoVrefRP
R−
VuRP
Rf
(4.26)
Now Vf should have a smaller value than VL to ensure that the output of the
comparator gets inverted. Thus the condition for inversion can be written as
Vref
RP
R− Vu
RP
Rf
<VL (4.27)
Therefore, substituting Vf = VL and t = Toff in the equation 4.25 we get,
VL = VHe−toff
Cf RP + Vref
RP
R(1 − e
toff
Cf RP ) − Vu
RP
Rf
(1 − e−toff
Cf RP ) (4.28)
51
The off time can be obtained from the above equation as follows
toff = CfRP lnVH − Vref
RP
R+ Vu
RP
Rf
VL − VrefRP
R+ Vu
RP
Rf
(4.29)
If it is assumed that VH − VL <<VH − VrefRP
R+ Vu
RP
Rf, the equation (4.28) can
be reduced as
toff = CfRP
VH − VL
VL − VrefRP
R+ Vu
RP
Rf
(4.30)
The equation for both the on time and off time are obtained as shown in (4.15)
and (4.29). These equation can further be solved to evaluate the duty cycle and
frequency as mentioned below.
The total time period is given by T = ton + toff and therefore the frequency can
be calculated as f = 1T
.
f =(VH − Vref
RP
R− Vu
RP
Rf)(VL − Vref
RP
R+ Vu
RP
Rf)
CfRP (VH − VL)(VH + VL − 2VrefRP
R)
(4.31)
The duty cycle can be calculated from D = ton
T.
D =VL − Vref
RP
R+ Vu
RP
Rf
VH + VL − 2VrefRP
R
(4.32)
4.2 Simulation and Results
The circuit is simulated on SABER the simulation results are in agreement with the
theoretical results on MATLAB. The simulation results for the converter are as shown
below. The waveforms indicating the operation of the buck converter implemented
with hysteretic control technique when the capacitor is initially charging are shown in
Figure 4.3. These waveforms indicate inductor current waveform, iL, output voltage
52
Graph0
t(s)
1.0m 1.2m 1.4m 1.6m 1.8m 2.0m
(V
)
11.0
11.25
11.5
11.75
12.0
12.25
12.5
(V
)
5.525
5.55
5.575
5.6
5.625
5.65
5.675
(A
)
−0.5
0.0
0.5
1.0
1.5
(V) : t(s)
vinv
vnon_inv
(A) : t(s)
i_L
(V) : t(s)
V_O
Ave: 0.92119
Figure 4.3: Waveforms of buck converter during the initial charging of the capacitor.
waveform, VO and voltages at the inverting and non inverting inputs of the hysteretic
comparator and are as shown in Figure 4.3.
The output voltage, VO waveform and the gate to source, VGS voltage waveform
indicating duty cycle of the proposed buck converter during steady state operation
as obtained on saber is as shown in Figure 4.4.
The open loop buck converter used in this configuration is designed at an switch-
ing frequency of 100KHz. The simulated results of the closed loop buck converter
show an operating frequency of 80KHz. The efficiency of the circuit at the highest
operating frequency is 80%.
53
(V
)
−20.0
0.0
20.0
40.0
t(s)
15.7m 15.75m 15.8m 15.85m 15.9m 15.95m 16.0m 16.05m 16.1m 16.15m 16.2m
(V
)
10.6
10.8
11.0
11.2
11.4
11.6
(V) : t(s)
n_2315
(V) : t(s)
v_o
duty: 0.46804
Ave: 11.278
Figure 4.4: Output Voltage, VO and the Gate-to-source voltage, VGS waveform of theconverter.
(A
)
0.92
0.93
0.94
0.95
0.96
0.97
0.98
t(s)
20.15m 20.175m 20.2m 20.225m 20.25m 20.275m 20.3m 20.325m 20.35m
(W
)
10.4
10.6
10.8
11.0
11.2
11.4
11.6
(W
)
−70.0
−60.0
−50.0
−40.0
−30.0
−20.0
−10.0
0.0
10.0
(A) : t(s)
i(p)
(W) : t(s)
output power
(W) : t(s)
input power
freq: 80022.0
Ave: 10.901
Ave: −13.575
Figure 4.5: Waveforms of the inductor current indicating frequency of operation andoutput and input power indicating efficiency.
54
Graph0
t(s)
0.0 5.0m 10.0m 15.0m 20.0m 25.0m 30.0m 35.0m 40.0m
(V
)
10.0
15.0
20.0
25.0
30.0
(V
)
−20.0
0.0
20.0
40.0
60.0
80.0
100.0
(A
)
0.5
1.0
1.5
2.0
2.5
(V
)
20.0
30.0
40.0
50.0
60.0
70.0
80.0
(V) : t(s)
vo
(V) : t(s)
vgs
(A) : t(s)
i_L
(V) : t(s)
v_in
Figure 4.6: Waveforms of the inductor current, duty cycle, output and input voltagefor changes in line voltage.
4.3 Load and Line Regulation of Hysteretic controlled BuckConverters
The circuit is simulated on SABER for changes in load and line voltages. The results
are as shown in Figure 4.6 and 4.7. The waveforms represent the output voltage, VO,
inductor current, iL, drain to source voltage, VDS for changes in input voltage, VI .
The circuit reacts well to changes in line voltage and shows a proper regulation as
the duty cycle is automatically adjusted by the changing levels of input voltage due
to change.
The efficiency at changing input voltages range from 63% to 82% and the frequency
ranges from 39KHz to 41KHz as shown in the Figure 4.7.
The values of output voltage and output current were plotted for change in line
voltage using MATLAB and the results obtained are given in Figure 4.8 and 4.9.
The circuit was simulated on SABER fro changes in load resistance, RL. The
closed loop buck converter with hsyteretic control technique shows a good load reg-
ulation. The simulated waveforms for inductor current, iL, output voltage, VO, drain
55
Graph0
t(s)
0.0 2.5m 5.0m 7.5m 10.0m 12.5m 15.0m 17.5m 20.0m 22.5m 25.0m 27.5m 30.0m 32.5m 35.0m 37.5m 40.0m
(A
)
0.0
1.0
2.0
3.0
(V
)
20.0
40.0
60.0
80.0
freq: 40868.0
freq: 34750.0
freq: 39123.0
freq: 38459.0
freq: 41521.0
freq: 45190.0
(A) : t(s)
i_L
(V) : t(s)
vin
Figure 4.7: Waveforms of the inductor current, input voltage.
10 20 30 40 50 60 70 8011.5
11.6
11.7
11.8
11.9
12
12.1
12.2
12.3
12.4
12.5
VO
(V)
VI (V)
Figure 4.8: Output voltage vs. inputvoltage.
10 20 30 40 50 60 70 800.7
0.75
0.8
0.85
0.9
0.95
1
I O (A
)
VI (V)
Figure 4.9: Output current vs. inputvoltage.
56
Graph
(V
)
0.0
5.0
10.0
15.0
20.0
25.0
30.0
t(s)
0.0 2.5m 5.0m 7.5m 10.0m 12.5m 15.0m 17.5m 20.0m 22.5m 25.0m 27.5m 30.0m 32.5m 35.0m 37.5m 40.0m
(O
)
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
(V
)
−5.0
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
duty: 0.48381
duty: 0.49314
duty: 0.45833
duty: 0.46368
duty: 0.50655
duty: 0.46829
duty: 0.46864duty: 0.47982
(V) : t(s)
vo
(O) : t(s)
R_L
(V) : t(s)
n_2315
Figure 4.10: Waveforms of the output voltage and duty cycle for changes in loadresistance.
to source voltage, VDS with changes in load resistance are shown in Figure 4.10 and
4.11. The values of output voltage and output current for changes in load resistance
were plotted on MATLAB and the simulation results are shown in Figure 4.12 and
4.13.
The inductor current waveforms, input and output waveforms are also observed
for changes in load resistance from 12 to 50. Th efficiency varies form 77% to 80%
and the frequency ranges form 40KHz to 80KHz as shown in Figure 4.10.
4.4 Conclusions
The theoretical results and the simulations results for the control scheme are in agree-
ment with each other. The operating frequency of this circuit is 80KHz and the
efficiency is 80%. The circuit has good regulation characteristics for changes in load
resistance and input voltage however with the changes, the efficiency decreases and
the operating frequency too. The efficiency is high for high loads and is high for light
loads. The operating frequency and efficient also changes for change in input voltage.
However this control scheme is more suitable since it is easy to manipulate the duty
57
Graph
t(s)
0.0 2.5m 5.0m 7.5m 10.0m 12.5m 15.0m 17.5m 20.0m 22.5m 25.0m 27.5m 30.0m 32.5m 35.0m 37.5m 40.0m
(O
)
10.0
20.0
30.0
40.0
50.0
(A
)
0.0
1.0
2.0
3.0
freq: 38464.0
freq: 44765.0
freq: 37106.0
freq: 63134.0
freq: 36497.0
freq: 61509.0
freq: 70892.0
freq: 76810.0
(O) : t(s)
R_L
(A) : t(s)
i_L
Figure 4.11: Waveforms for inductor current for changes in load resistance.
10 20 30 40 50 60 70 8010
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
VO
(V)
RL (Ω)
Figure 4.12: Output voltage vs. loadresistance.
10 20 30 40 50 60 70 800
0.5
1
1.5
I O (A
)
RL (Ω)
Figure 4.13: Output current vs. loadresistance.
58
cycle of the circuit and thus the output by changing the resistors and the capacitors
connected to the non inverting terminal of the comparator.
59
5 Boost Converter
5.1 Open loop Boost Converter
A boost converter is another class of DC-DC converters which has an output greater
than the input. It is also known as a step up converter. As per the rules of conser-
vation of energy, power must be conserved and it is given by, P = V I/. The circuit
diagram of a boost converter is shown in figure 5.1. These types of converters are
widely used in battery operated applications. It consists of a an inductor, L, a mosfet,
a diode, a capacitor, C and load resistor, RL.
The circuit works as follows, the MOSFET turns ON during the time interval
0 <t <Ton, and the diode turns OFF due to a negative voltage across the diode.
As a result, the inductor current increases linearly and the thereby increasing the
magnetic energy. At this time, the MOSFET current is equal to the drain current.
The MOSFET is turned OFF by the gate-to-source voltage at time,t = DT . During
this time, diode is turned ON due to the inductor which acts as a current source. This
reduces the inductor current with a slope of (VI − VO)/L. Thus energy is transferred
from the inductor to the capacitor and the load resistor, thus increasing the output
voltage. The relevant waveforms representing the operation of boost converter are
shown in Figure 5.2.
5.2 Closed loop Boost converter
The open loop converter works fine as long as the input voltage is fixed and there are
no variations in the load. However when any of the aforementioned quantity changes,
it becomes difficult to regulate the output voltage and at this time, the closed loop
converter comes into picture. The closed loop here is implemented with the help of
hysteretic control technique. The main reason of using hysteretic control technique is
that it provides fast response and stable operation without the need to use any phase
60
Figure 5.1: Open loop boost converter.
compensation technique.The circuit diagram of the boost conveter with the hysteretic
control technique is shown in Figure 5.3.
The previous chapters show the implementation of buck converter with a hysteretic
control loop. The hysteretic loop consists of a comparator with hysteresis employing
high gain. When a high gain operational amplifier is used, it also causes an increase
in the phase lag of the feedback circuit.
The control to output function of a boost converter has a positive zero which
results in an unstable response and a phase intersection at −180. In the previously
analyzed buck converter topology, the voltage mode hysteretic control was used and
a RC network to generate initial ripples was used. This control scheme provides
good stable steady state performance. However when the same kind of control is
implemented to a boost converter, it does not work. The primary reason for this
is that the inductor current and output voltage ripple in case of a boost converter
are not in phase with each other and therefore the hysteretic control technique using
the ripple of the output voltage can not be applied since it will not provide the
appropriate control mechanism. Thus in this scheme both feedback and feed forward
control mechanisms are implemented. The circuit and its operation is explained in
the next section.
61
Figure 5.2: Waveforms of open loop boost converter.
62
Figure 5.3: Closed loop boost converter with hysteretic control technique.
5.3 Operation of the Circuit
The circuit shown in Figure 5.3 uses feed-forward and feedback using hysteretic con-
trol. As in the case of hysteretic control techniques, the inductor current needs to be
sensed or a triangular wave needs to be generated in order to initiate the operation of
the circuit. This technique senses the inductor filter circuit across the incutor which
is then given to the RC integral network in the control path. Instead, to generate
the triangular and the hysteretic window voltage, two resistors and a RC integral
network is added. To generate the feed-froward signal, an RC low pass filter circuit is
added across the inductor and current is sensed across the sense resistor, RS. In the
feedback path, a triangular voltage waveform which is same as the inductor current is
generated using the combination of resistor and capacitorR2 and C1 as per the output
of the comparator, VU . The ac component through this combination is then fed to
the inverting input of the comparator using the capacitor, C2 which is a DC blocking
capacitor. The duty cycle of the MOSFET is automatically adjusted. This sets the
output voltage, VO within the hysteretic range. The circuit is simulated on saber and
the steady state waveforms are obtained as shown below.
63
t(s)
5.24m 5.25m 5.26m 5.27m 5.28m 5.29m 5.3m 5.31m 5.32m
(V
)
27.1
27.15
27.2
27.25
27.3
27.35
27.4
27.45
27.5
27.55
27.6
(A
)
1.695
1.7
1.705
1.71
1.715
1.72
1.725
(A
)
−5.0
0.0
5.0
10.0
15.0
20.0
(V) : t(s)
Vo
(A) : t(s)
IO
(A) : t(s)
iL
Ave: 1.7071
Ave: 27.313
Ave: 3.515
Figure 5.4: Output voltage and current and inductor current of boost converter inopen loop configuration
5.4 Simulations and Results
The open loop boost converter is designed and then the closed loop boost converter is
designed. The open loop Boost converter is designed with the following specifications:
VI = 14V,VO = 24V , D = 0.5, C = 100, L = 25, fs = 100KHz
The circuit is simulated on saber in open loop configuration and the waveforms
are shown in Figure 5.4 The closed loop boost converter is then simulated on SABER
and the steady state waveforms are shown in Figure 5.5
As observed from the Figure 5.5, the duty cycle of the gate to source voltage
is automatically adjusted to 0.52 as per the design specifications. The input and
output power for the converter in the steady state were plotted and it shows that the
efficiency of this circuit is around 85%. The simulated results for the same are shown
in Figure 5.6 below.
Thus it can be seen that the circuit hysteretic control technique is performing
the closed loop operation properly and the results obtained theoretically are similar
to those obtained through simulations. To verify, if the closed loop also responds to
64
Graph0
(V
)
22.8
22.9
23.0
23.1
23.2
t(s)
11.62m 11.63m 11.64m 11.65m 11.66m 11.67m 11.68m
(A
)
−20.0
0.0
20.0
40.0
60.0
(V
)
−20.0
−10.0
0.0
10.0
20.0
(V
)
−20.0
0.0
20.0
40.0
60.0
Ave: 3.0677
Ave: 23.041
duty: 0.52446
(V) : t(s)
V_O
(A) : t(s)
i_L
(V) : t(s)
vgs(idealmos.idealmos1)
(V) : t(s)
v_inv
v_noninv
Figure 5.5: Steady state waveforms of closed loop boost converter.
Graph0
t(s)
11.62m 11.63m 11.64m 11.65m 11.66m 11.67m 11.68m
(V
)
−20.0
−10.0
0.0
10.0
20.0
(W
)
32.0
32.5
33.0
33.5
(W
)
−80.0
−60.0
−40.0
−20.0
0.0
Ave: −37.203
(V) : t(s)
vgs(idealmos.idealmos1)
(W) : t(s)
P_O
(W) : t(s)
P_I
Ave: 33.179
duty: 0.52446
freq: 99905.0
Figure 5.6: Input power and output power of closed loop boost converter.
65
Graph0
(V
)
12.0
12.2
12.4
12.6
12.8
t(s)
2.5m 5.0m 7.5m 10.0m 12.5m 15.0m 17.5m 20.0m 22.5m 25.0m 27.5m
Ave: 1.4378
(A
)
0.0
1.0
2.0
3.0
4.0
(V
)
−20.0
−10.0
0.0
10.0
20.0
(V
)
10.0
20.0
30.0
40.0
50.0
(V) : t(s)
v(v_pwl.v_pwl2)
(A) : t(s)
i(p)
(V) : t(s)
vgs(idealmos.idealmos1)
(V) : t(s)
n_186
duty: 0.5207
duty: 0.5189
duty: 0.51687
duty: 0.51069
duty: 0.49982 duty: 0.49592
Ave: 23.005
Figure 5.7: Simulated waveforms of the boost converter for changes in input voltage.
changes in line and load, the circuit was simulated on SABER with varying values of
input voltage and load resistance. The simulated waveforms for line and load regula-
tion are shown in Figure 5.7 and 45.8 respectively. The simulated results show that
the line regulation is 2.1%. The waveforms in Figure 5.8 show the inductor current,
iL, gate-to-source voltage, VGS, Output voltage, VO for changes in load resistance.
The percentage load regulation for this circuit is 1.234%.
5.5 Conclusion
The hysteretic control technique using feed-forward and feedback technique for a
boost converter has been implemented and the steady state simulations are found to
be in agreement with the theoretical results. The current sensing technique to track
the inductor current information has been successfully implemented. The circuit
offers a line regulation of 2.1% and a load regulation of 1.234%. This technique can
be further improved and implemented to other types of converters whose pole zero
responses are similar to a boost converter like buck-boost, flyback converters etc.
66
Graph0
t(s)
2.5m 5.0m 7.5m 10.0m 12.5m 15.0m 17.5m 20.0m 22.5m 25.0m 27.5m 30.0m
(V
)
10.0
20.0
30.0
40.0
50.0
(O
)
15.0
20.0
25.0
30.0
(V
)
−20.0
−10.0
0.0
10.0
20.0
duty: 0.51976
duty: 0.52308
duty: 0.52678
duty: 0.53346 duty: 0.53429 duty: 0.53637
Ave: 23.653
Ampl: 0.07252
(A
)
0.0
1.0
2.0
3.0
4.0
5.0
(O) : t(s)
r(pwlr.pwlr1)
(V) : t(s)
n_186
(V) : t(s)
vgs(idealmos.idealmos1)
(A) : t(s)
i(p)
Figure 5.8: Simulated waveforms of the boost converter for changes in load resistance.
67
6 Conclusion
6.1 Results and Summary
The hysteretic control technique was simulated for both open loop and closed loop
converters. The MATLAB plots for both open loop buck converter and the buck
converter implemented with hysteretic control is shown in Figure 6.1 , Figure 6.2 and
Figure 6.3, Figure 6.4. These plots show the behavior of open loop and closed loop
converters and it is evident from the plots that closed loop converters have good load
and line regulations characteristics as compared to open loop converters.
• The hsyteretic control scheme has been analyzed and its operations, advantages
and disadvantages and its application to circuits have been studied.
• The operation and design of Open loop buck converter is discussed. The simu-
lations for the deisgned circuit are performed on SABER and ways to improve
the dynamic response of the circuit is discussed.
• The Buck converter with hsyteretic control using start-up technique is imple-
mented. The operation of the circuit is discussed. The circuit is simulated using
SABER circuit simulator and results are verified with that of the theoretical
results. The circuit is also tested for line and load regulation. The advantages
and disadvantages of the control technique are discussed.
• Another method of application of hysterteic control using capacitive charging
technique is discussed. The steady state waveforms for the converter are derived
and the relationship between the frequency and duty cycle of the converter with
respect to the hsyteretic window voltages is derived. The circuit is simulated
using SABER circuit simulator and the theoretically derived waveforms are
found to be in agreement with the practical results.
68
10 20 30 40 50 60 70 8010
12
14
16
18
20
22
24
26
28
30
RL (Ω)
VO
(V)
without feedbackwith feedback(dual mode)with feedback(capacitive charging)
Figure 6.1: Load Resistance vs. out-put voltage.
10 20 30 40 50 60 70 800
0.2
0.4
0.6
0.8
1
1.2
1.4
RL (Ω)
I O (A
)
without feedbackwith feedback (dual mode)with feedback (capacitive charging)
Figure 6.2: Load Resistance vs. out-put current.
10 20 30 40 50 60 70 805
10
15
20
25
30
35
40
VI (V)
VO
(V
)
without feedbackwith feedback (dual mode)with feedback (capacitive charging)
Figure 6.3: Input Voltage vs. outputvoltage.
10 20 30 40 50 60 70 800
0.2
0.4
0.6
0.8
1
1.2
1.4
RL (Ω)
I O (
A)
without feedbackwith feedback (dual mode)with feedback (capacitive charging)
Figure 6.4: Load Resistance vs. out-put current.
69
• The efficiency and the load and line regulation characteristics using hysteretic
control of buck converter using start-up circuit and hysteretic control of buck
converter using capacitive charging are discussed and analyzed. The MATLAB
plots for both the methods of control are compared to the open loop configu-
ration of buck converter and verified for improvement. The highest frequency
of operation for the circuit as obtained in the simulation results is 80KHz and
the efficiency is 80%.
• The hyeteretic control scheme has also been implemented to a boost converter.
Both feed-forward and feedback are used. The both inductor current informa-
tion and artificially generated ripple are used for the control technique. The
open loop and the closed loop configuration are compared and the efficiency of
the closed loop circuit obtained is 82%.
70
7 Future Work
The circuits have been simulated for both buck and boost converter with the same
control scheme with small modifications for both. The control scheme offers enormous
advantages since it does not require any phase compensation technique, secondly the
control scheme is easy to design and offers fast transient response. The control scheme
has been discussed in the draft and applied to buck and boost switched mode DC-DC
converters. This thesis discusses the application of hysteretic control scheme using
voltage mode control technique for a buck converter and using both feedback and
feed-forward technique for a boost converter.
A further research can be carried out on the following things.
• Small signal analysis of hsyteretic control loop.
• Small signal analysis of boost converter with hsyteretic control technique and
methods to improve the component count and regulation characteristics.
• Implementing methods to provide a better control over the hysteretic loop in
case of boost converter.
• Application of the control scheme to other kinds of DC-DC converters like buck-
boost, fly-back, forward converters.
• Integrating the control technique to higher end applications like LED display
panels and lighting.
The control scheme for the boost converter can be studied in further detail. The
regulation characteristics for the Boost converter can be studied in further detail for
both line and load. The application of the same control scheme for other different
DC-DC converters can be studied.
71
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74
