A 45nm SOl-CMOS PLL with a Wideband LC-VCO

Kun-Seok Lee, Sungho Beck, Hamhee Jeon, Y oungchang Y oon, Jaehyouk Choi, Chang-Ho Lee, and J. Stevenson Kenney

Georgia Institute of Technology Atlanta, USA

leeksO l@gatech.edu

Abstract - A 45nm SOl-CMOS PLL with a wideband LC-VCO is presented. The proposed PLL uses the advantage of SOl

technology such as small parasitic capacitance and high Q­factor. The frequency range of the PLL is maximized because of a high maximum-to-minimum capacitance ratio of a capacitor bank. Measurement results show that the VCO generates 4.87-

to-9.65GHz frequency signals with 65.8% frequency coverage. Fabricated chip occupies O.09mm2 of active area and consumes less than 7mA current from single 1.0V supply.

I. INTRODUCTION

Wideband phase-locked loops (PLLs) supporting multiple standards with a single voltage-controlled oscillator (VCO) are very attractive because die area can be saved by circumventing multiple VCOs and complex local oscillator (LO) plans [1][2]. However, it is not easy to realize wideband PLLs in deep sub-micron technologies because bulk CMOS technologies are optimized for highly integrated digital circuits and the highly conductive substrate degrades the quality (Q)-factor of passive components [3]. Moreover, the large parasitic capacitances of drain/source areas make it difficult to increase the oscillation frequency and tuning range of VCOs. Especially, switches to control capacitor banks are critical because they determine the capacitance variation range of the capacitor banks. Scaling down to the deep sub-micron CMOS technologies gives some benefits such as high integration capability, faster transistor, better geometrical matching, and low power consumption. However, the dynamic range reduction with lower supply voltages is a stringent design challenge [4]. The reduced available voltage swing limits compliance voltages, the maximum and the minimum voltages of a current source operating properly, of charge pump PLL (CP PLLs) and VCO tuning voltage range.

This paper presents a PLL with a wide frequency range. The proposed PLL uses a 45nm SOl-CMOS technology, so the parasitic capacitance of a capacitor bank can be minimized, increasing the frequency range of the PLL. Section II explains design challenges due to dynamic range reduction in deep sub­micron CMOS technologies. The design concept of the proposed wideband LC-VCO and the parasitic capacitance effect on the frequency range are presented in Section III. Section IV shows the proposed PLL. Measured results and

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Figure 1. A phase-locked loop with a wideband LC-VCO.

conclusion are provided in Section V.

II. DYNAMIC RANGE REDUCTION IN DEEP SUB-MICRON

TECHNOLOGY

Figure 1 shows a typical PLL with a wideband VCO. To increase the total frequency range of the VCO, a capacitor

bank is generally adopted and many transfer curves are generated by changing capacitance because voltage tuning

range is limited by supply voltage. The total frequency range of the VCO is given by

(1)

where Kvco, ..d V_tune, and N are VCO gain, tuning voltage

range, and the bit number of the capacitor bank, respectively. As the minimum pitch size of a transistor is scaled down, the supply and threshold voltages are also scaled down with thinner oxide layers. Since the tuning voltage range is proportional to the supply voltage, the total frequency range also decreases as scaling down is accelerated. Therefore, dynamic range reduction means the total frequency range reduction.

978-1-61284-857-0/11/$26.00 <92011 IEEE

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III. DESIGN CONCEPT AND PARASITIC CAPACITANCE

EFFECT ON FREQUENCY RANGE

The strategy of this design is to increase the oscillation frequency of the VCO because of two reasons. First, die area can be saved by using a smaller inductor. And second, high Q­factor can be obtained because the Q-factor of an inductor is proportional to the oscillation frequency. The oscillation frequency of the VCO can be expressed by

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C = Cfixed + Cvariable

= Cfixed + Cmin - Cfixed + Cmax (2)

where L and C are inductance and capacitance of a LC-tank. The capacitance consists of two parts, fixed capacitance and variable capacitance. The fixed capacitance is the sum of the parasitic capacitances of switching transistors, inductor, routing metal lines, and fine tuning varactors. Vari able capacitance is contributed by the on/off capacitance of the capacitor bank. The minimum capacitance, Cmin> and the maximum capacitance, Cman of the capacitor bank are determined in according to the control voltage of the MOS switches in the capacitor bank as shown in Figure 2(b). The Cmin is closely related to the parasitic capacitance between

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drain/source and bulk. Cmax corresponds to the lowest frequency and Cmin to the highest one. Since the total frequency range is highly dependent on the Cmax/Cmin ratio, the ratio should be maximized to increase the total VCO frequency range.

In a SOl-CMOS technology, the Q-factor of passive components is higher than that of a bulk CMOS technology due to the higher resistance of substrate and a buried oxide layer. Since the buried oxide layer and shallow trench isolation (STI) separate source/drain regions from the substrate as shown in Figure 2(a), the parasitic capacitance can be reduced significantly. Therefore, the MOS devices using SOl processes are highly desirable for the switches of wideband VCOs, because of the higher Cmax to Cmin ratio of the capacitor bank (Figure 2(b)). Frequency coverage is given by

Frequeny Coverage (%) =

F. - F . max mm X 100, Fcenter (3)

where F max, F min> and Feenler are maximum, mmlmum, and center frequencies of the VCO, respectively. If the VCO is designed to cover from 5GHz to 10GHz, the frequency coverage should be 66.7%. And the PLL can cover a continuous frequency range from 625MHz to 10GHz with simple divider-by-2 circuits. Figure 3(a) shows the relationship between Cmax/Cmin ratio and frequency coverage.

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609 MHz - 1.206 GHz

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Measure Out (1.22-2.41 GHz)

Figure 4. Block diagram of the proposed PLL with a wideband veo and a simple frequency plan for multi-standards.

With 600pH inductance and O. lpF fixed capacitance, the simulation result shows that more than 4.75 of CmaiCmin ratio is required to obtain 67% coverage. But it is not easy to realize more than 4 of CmdCmin ratio with a bulk CMOS technology. Also, the influence of fixed parasitic capacitance on frequency coverage is critical. With 600pH inductance and 4.5 CmaxlCmin ratio, Figure 3(b) shows that less than 40fF fixed capacitance is required to have 67% coverage. Compared with sub-micron technologies, the 45nm process has a benefit of small parasitic capacitance because smaller switching transistors can supply enough negative resistance to the LC-tank with smaller threshold voltages. SOl technology also enables to achieve a large CmaxlCmin ratio because of small parasitic capacitances in MOS devices. Therefore, the 45nm SOl-CMOS technology provides low parasitic capacitance and high CmaxlCmin ratio.

IV. PROPOSED WIDEBAND PLL

A simplified block diagram of the proposed PLL with a wide band LC- VCO is illustrated in Figure 4. The PLL consists of the wideband VCO, buffers, a phase-switching prescaler, dividers, a phase frequency detector (PFD)/CP, and a passive loop filter. The VCO generates 4.875-9.65 GHz frequency signals in the VCO core. 4 different phase signals of 1.22-2.41 GHz are created through buffers and divide-by-2 circuits. A 4/4.5 divider realizes 0.5 division ratio using the phase-switching technique [6]. The signals are fmally fed back to the PFD. The PFD/CP generates continuous pulse trains and force to lock after a certain time. A 26 MHz reference signal is supplied from an off-chip voltage-controlledltemperature­compensated crystal oscillator (VCTCXO) for high spectral purity. To support multiple standards, a simple LO plan is suggested as shown in Figure 4. For high frequency applications, the signals from VCO buffers are directly used as

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LO signals or carriers for transmission, while the output signals of the devider-by-4 block are exploited for low frequency applications. Figure 4 also shows the proposed wideband VCO. The VCO incorporates a spiral inductor, a capacitor bank, a fme tuning varactor, and a current control block. To maximize the CmdCmin ratio and simplify the structure, a CMOS type VCO core is employed. With this architecture, any blocking capacitors and biasing circuits between oscillation nodes and the capacitor bank (or the AMOS varactor) are not used_ The binary-weighted capacitor bank is controlled by a 6-bit digital code_ The small spiral inductor is used to generate higher oscillation frequencies to save area. The minimum controllable capacitance per bit is as small as 40-tF. Thanks to the excellent matching characteristic of deep sub-micron technology, the monotonicity of the capacitor bank is guaranteed. The tuning range of the analog AMOS varactor is set to cover the frequency range of two least significant bits (LSBs) to ensure stable frequency locking.

V. MEASURED RESULTS AND CONCLUSION

The proposed FS is designed and fabricated in a 45-nm deep sub-micron SOl-CMOS technology. The VCO frequency range is characterized under open-loop conditions. As expected, a very wide frequency range up to 4.78 GHz is supported with a single VCO. The tuning frequency is from 4.87 GHz to 9.65 GHz and the frequency coverage is 65.8%. The PLL can cover from 6 lOMHz to 9.65GHz with the simple frequency plan except 90MHz range_ Shown in Figure 5(a) is the measured frequency range according to each code when the tuning voltage is set to O.5V. The code is inversely proportional to the capacitance of the capacitor bank_ Therefore, the oscillation frequency increases with the code. Figure 5(b) shows fme tuning curves for each code depending on the tuning voltage. Each code has enough overlapping regions with adjacent codes to make sure stable locking. The measured results show the in-band phase noise of -10 1 dBclHz. From a 1.248 GHz carrier, the out-band phase noise values are - l lO.81, 123.6, -135.58 and -145.2 dBc/Hz at the offset

frequencies of 400KHz, 1 MHz, 3MHz, and lOMHz, respectively. The loop bandwidth is 200 KHz as shown in Figure 6. The PLL consumes less than 7mA current from a 1.0V supply. Measured reference level is -78.51dBc. Figure 7 shows the micrograph of the prototype chip fabricated in a 45nm SOl-CMOS process. The active area is 0.138mm2, including serial peripheral interface (SP!) block occupying 0.016mm2 for test. The PLL can support multiples standards including all cellular band such as GSM, EDGE, WCDMA, L TE, and almost all WLAN and WiMax bands. Measurement results demonstrate the PLL is a good solution for multi­standard mobile communication systems.

REFERENCES

[I] V. Giannini et aI., "A 2mm2 0.1-5GHz SDR Receiver in 45nm. Digital CMOS," ISSCC Dig. of Technical Papers, Feb. 2009.

[2] R. Sadhwani et aI., "Multi-band multi-standard local oscillator generation for direct up/down conversion transceiver architectures supporting WiFi and WiMax bands in standard 45nm CMOS process," in Radio Frequency Integrated Circuits (RFIC) Symposium, 2010 IEEE, 2010, pp. 149-152.

[3] 1. Aguilera et aI., DeSign and Test of Integrated Inductors for RF Applications: Kluwer Academic Publishers, 2003.

[4] Y. Chiu et aI., "Scaling of analog-to-digital converters into ultra-deep­submicron cmos". In Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, pages 375 - 382, September 2005.

[5] 1. 1. Rael et aI., "Physical processes of phase noise in differential LC oscillator," in Proc. CICC May 2000, pp. 569-572.

[6] S. Keliu et aI., "A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 866-874, Jun. 2003.

Figure 7. Micrograph of the fabricated chip.