Integrated Passive Component Technology

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INTEGRATED PASSIVECOMPONENT TECHNOLOGY



IEEE Press445 Hoes Lane

Piscataway, NJ 08854

IEEE Press Editorial Board

Stamatios V. Kartalopoulos, Editor in Chief

M. Akay M. E. El-Hawary M. Padgett

J. B. Anderson R. J. Herrick W. D. Reeve

R. J. Baker D. Kirk S. Tewksbury

J. E. Brewer R. Leonardi G. Zobrist

M. S. Newman

Kenneth Moore, Director of IEEE Press

Catherine Faduska, Senior Acquisitions Editor

John Griffin, Acquisitions Editor

Anthony VenGraitis, Project Editor

IEEE Components, Packaging & Manufacturing Technology Society, Sponsor

CPMT Liaison to IEEE Press, Joe E. Brewer



INTEGRATED PASSIVE

COMPONENT TECHNOLOGY

Edited by

RICHARD K. ULRICH

LEONARD W. SCHAPER

University of Arkansas

IEEE Components, Packaging & Manufacturing Technology Society, Sponsor

A JOHN WILEY & SONS, INC., PUBLICATION

IEEE PRESS



Copyright © 2003 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

Published simultaneously in Canada.

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Library of Congress Cataloging-in-Publication Data:

Integrated passive component technology / edited by Richard K. Ulrich, Leonard W. Schaper.

p. cm.

Includes bibliographical references and index.

ISBN 0-471-24431-7 (cloth)

1. Passive components. 2. Integrated circuits—Design and construction. 3. Printed

circuits—Design and construction. I. Ulrich, Richard K., Ph.D. II. Schaper, Leonard W.

TK7874.147145 2003

621.3815—dc21 2003041102

Printed in the United States of America.

10 9 8 7 6 5 4 3 2 1



To Dan and Joy Ulrich, the best teachers I ever had

and

To the late Len Schaper Sr., who taught me

that it was OK to get my hands dirty







2.1.3 Temperature Effects 37

2.1.4 Value Stability 38

2.2 Resistance in Electronic Materials 40

2.2.1 Resistivity and Charge Carriers 402.2.2 Semiconducting Oxides 41

2.2.3 Tunneling 43

2.2.4 Temperature, Composition, and Morphology Effects 43

2.3 Sizing Integrated Resistors 45

2.3.1 Thermal Issues 46

2.3.2 Parasitic Capacitance between Meanders 49

2.3.3 Parasitic Capacitance to Ground 51

2.3.4 Lumped Versus Distributed Performance 52

2.4 Trimming 52References 53

3 Integrated Resistor Materials and Processes 55

Richard K. Ulrich

3.1 Single-Component Metals 56

3.2 Metal Alloys and Metal–Nonmetal Compounds 58

3.2.1 Tantalum Nitride 59

3.2.2 Titanium Oxy-Nitride 603.2.3 Nickel Phosphide 60

3.3 Semiconductors 61

3.3.1 Silicon 61

3.3.2 Semiconducting Oxides 61

3.4 Cermets 61

3.5 Polymer Thick Film 63

3.6 Ink Jet Deposition 65

3.7 Commercialized Processes 66

3.7.1 Ohmega-Ply® 66

3.7.2 Dupont Interra™ 66

3.7.3 MacDermid M-Pass™ 68

3.7.4 Polymer Thick Film 70

3.7.5 Shipley Insite™ 70

3.8 Summary 70

References 73

4 Dielectric Materials for Integrated Capacitors 75

Richard K. Ulrich

4.1 Polarizability and Capacitance 76

4.2 Capacitance Density 79

4.3 Temperature Effects 82

4.4 Frequency and Voltage Effects 83

viii CONTENTS



4.5 Aging Effects 84

4.6 Composition and Morphology Effects 85

4.7 Leakage and Breakdown 86

4.8 Dissipation Factor 894.9 Comparison to EIA Dielectric Classifications 91

4.10 Matching Dielectric Materials to Applications 93

4.10.1 Decoupling and Energy Storage 96

4.10.2 Analog Functions 96

4.10.3 Termination of Transmission Lines 96

References 97

5 Size and Configuration of Integrated Capacitors 101

Richard K. Ulrich

5.1 Comparison of Integrated and Discrete Areas 101

5.2 Layout Options 105

5.3 Tolerance 106

5.4 Mixed Dielectric Strategies 107

5.5 CV Product 108

5.6 Maximum Capacitance Density and Breakdown Voltage 109

References 111

6 Processing Integrated Capacitors 113

Richard K. Ulrich

6.1 Sputtering 114

6.2 CVD, PECVD and MOCVD 116

6.3 Anodization 117

6.3.1 Benefits of Anodization for Capacitor Dialectics 118

6.3.2 Film Formation During Anodization 118

6.3.3 Ta Anodization 120

6.3.4 Dielectrics from Anodized Ta 1216.3.5 Patterning Ta and Ta2O5 123

6.3.6 Ferroelectrics by Anodization 124

6.4 Sol-Gel and Hydrothermal Ferroelectrics 124

6.5 Thin- and Thick-Film Polymers 126

6.6 Thick-Film Dielectrics 127

6.6.1 Ferroelectric Powder Dispersed in Polymer 127

6.7 Interlayer Insulation 129

6.8 Interdigitated Capacitors 130

6.9 Capacitor Plate Materials 1316.10 Trimming Integrated Capacitors 131

6.11 Commercialized Integrated Capacitor Technologies 132

6.11.1 DuPont Interra™ 132

6.11.2 3-M C-Ply 133

CONTENTS ix



6.11.3 Dupont HK4 133

6.11.4 Motorola’s Mezzanine Capacitor 135

6.11.5 Sanmina BC2000™ 135

6.11.6 nChip 1356.12 Summary 135

References 138

7 Defects and Yield Issues 145

Richard K. Ulrich

7.1 Causes of Fatal Defects in Integrated Capacitors 145

7.2 Measurement of Defect Density 146

7.3 Defect Density and System Yield 147

7.3.1 Predicting Yield from Defect Density 148

7.4 Yield Enhancement Techniques for Capacitors 149

7.5 Conclusions 150

References 151

8 Electrical Performance of Integrated Capacitors 153

Richard K. Ulrich and Leonard W. Schaper

8.1 Modeling Ideal Passives 154

8.2 Modeling Real Capacitors 1548.3 Electrical Performance of Discrete and Integrated Capacitors 158

8.3.1 Inductance of the Capacitor Alone 158

8.3.2 Inductance of the Capacitor’s Leads and Contacts 164

8.3.3 Equivalent Series Resistance 165

8.3.4 Capacitors as Distributed Devices 165

8.4 Dissipation Factor of Real Capacitors 166

8.5 Measurement of Capacitor Properties 166

8.5.1 ESR and ESL Measurement with an 167

Impedance Analyzer 8.5.2 ESR and ESL Measurement with a 170

Network Analyzer

8.6 Summary 174

References 175

9 Decoupling 177

Leonard W. Schaper

9.1 Power Distribution 1779.2 Decoupling with Discrete Capacitors 181

9.3 Decoupling with Integrated Capacitors 183

9.4 Dielectrics and Configurations for Integrated Decoupling 185

9.5 Integrated Decoupling as an Entry Application 187

References 189

x CONTENTS



10 Integrated Inductors 191

Geert J. Carchon and Walter De Raedt

10.1 Introduction 191

10.2 Inductor Behavior and Performance Parameters 192

10.2.1 Inductor Layouts and Values 192

10.2.2 Inductor Operating Principles 194

10.2.3 Equivalent Circuit 196

10.2.4 Extraction of the Equivalent Circuit Parameters 198

10.2.5 Figure of Merits: Q L, Q LC , FOM L 200

10.2.6 Spiral Inductor Layouts 206

10.2.7 Improving Q L by Technology and Layout Parameters 208

10.3 Inductor Performance Prediction 216

10.3.1 Transmission Line Inductor 217

10.3.2 Spiral Inductors 217

10.4 Integrated Inductor Examples 224

10.4.1 Inductors Integrated on 10–20-cm Si Substrates 224

10.4.2 GaAs MMIC Inductors 224

10.4.3 MCM-D Inductors 226

10.4.4 LTCC 230

10.4.5 Integration of On-Chip Si Inductors through 231

Wafer-Level Packaging Techniques

10.5 Use of Inductors in Circuits: Examples 23210.5.1 Filters 233

10.5.2 Voltage-Controlled Oscillators 235

10.5.3 Size-Reduction Techniques 235

10.5.4 Coupled Spiral Inductors 237

10.6 Conclusions 238

Acknowledgments 238

References 238

11 Modeling of Integrated Inductors and Resistors for 247

Microwave Applications

Zhenwen Wang, M. Jamal Deen, and A. H. Rahal


11.1.1 Miniature Hybrid Microwave Integrated

Circuit (MHMIC) 248

11.1.2 Goals of this Chapter 248

11.2 Modeling of Spiral Inductors 249

11.2.1 Geometry of the Spiral Inductor 249

11.2.2 Inductor Circuit Model 250

11.2.3 Calculation of Inductance 250

11.2.4 Ground Plane Effect on Inductance 252

11.2.5 Series Resistance 253

11.2.6 Parasitic Capacitance 254

CONTENTS xi



11.2.7 Summary of Spiral Inductor Model 257

11.2.8 Quality Factor of a Spiral Inductor 257

11.2.9 Inductor Synthesis 258

11.2.10 Design and De-Embedding of Inductor Test Structure 25911.2.11 Measurement Setup and Calibration Specifications 261

11.2.12 Experimental Verification 261

11.2.13 Low-Pass Filter 263

11.2.14 Extension of the Model to Spiral Inductors on

Silicon Substrates 265

11.3 Modeling of Thin-Film Resistors 271

11.3.1 Step Discontinuity in Microstrip Width 273

11.3.2 High Sheet Resistance Microstrip Model 274

11.3.3 Experimental Verification 27811.3.4 S-parameter Measurement Setup 278

11.3.5 Measurement Calibration 278

11.4 Conclusions 282

References 282

Appendix: Characteristics of Microscript Lines 284

A.1 Chareristic Impedance Z L and Effective Dielectric Constant 234

eff under Static TEM Approximation

A.2 Dispersion Models of Effective Dielectric Contant eff and 286

Characteristic Impedance Z LA.3 Lumped-Element Model of a Microstrip Line 288

A.4 Microstrip Losses 288

12 Other Applications and Integration Technologies 293

Elizabeth Logan, Geert J. Carchon, Walter De Raedt,

Richard K. Ulrich, and Leonard W. Schaper

12.1 Demonstration Devices Fabricated with Integrated Passives 294

12.1.1 RC Terminators 294

12.1.2 Voltage Dividers 29712.1.3 Reliability Test Structures 298

12.1.4 Filters and RF Devices 299

12.1.5 Functional Modules and Subsystems 305

12.2 Commercialized Thin-Film Build-Up Integrated Passives 313

12.2.1 Capacitor Arrays 314

12.2.2 Termination 315

12.2.3 Intarsia 316

12.2.4 SyChip 318

12.2.5 Telephus 32012.3 Other Integrated Passive Technologies 320

12.4 Summary 322

Acknowledgments 323

References 323

xii CONTENTS



13 The Economics of Embedded Passives 327

Peter A. Sandborn


13.2 Modeling Embedded Passive Economics 329

13.3 Key Aspects of Modeling Embedded Passive Costs 332

13.3.1 Board Size and Routing Calculations 332

13.3.2 Recurring Cost Analysis 336

13.3.3 Throughput 338

13.3.4 Trimming Embedded Resistors 341

13.3.5 Yield and Test 343

13.3.6 Life Cycle Costs 345

13.4 Example Case Studies 347

13.4.1 Picocell Board Application 348

13.4.2 NEMI Hand-Held Product Sector Emulator 352

13.4.3 Fiber Channel Card 354

13.5 Summary 356

Acknowledgments 357

References 357

14 The Future of Integrated Passives 361

Richard K. Ulrich

14.1 Status of Passive Integration 361

14.2 Issues for Implementation on Organic Substrates 362

14.2.1 Electrical Design Issues 362

14.2.2 Board Design Issues 363

14.2.3 Fabrication and Manufacturing Issues 364

14.3 Progress on Board-Level Implementation 365

14.3.1 Advanced Embedded Passives Technology 366

Consortium (AEPT)

14.3.2 National Electronics Manufacturing Initiative (NEMI) 36614.3.3 The Embedded Capacitance Project 367

14.4 Three Ways In for Organic Boards 367

14.4.1 Decoupling 367

14.4.2 Replacement on FR4 369

14.4.3 High Density Interconnect 369

14.5 Conclusion 369

Index 373

About the Editors 381

CONTENTS xiii





CONTRIBUTORS

GEERT J. CARCHON, IMEC—MCP Division, Belgium, [email protected]

JAMAL DEEN, Electrical and Computer Engineering Department,

McMaster University, Hamilton, Ontario, Canada, [email protected]

ELIZABETH LOGAN, Consultant, Danville, California, [email protected]

WALTER DE R AEDT, IMEC—MCP Division, Belgium, [email protected]

A. H. R AHAL, Nanowave Technologies Inc., Etobicoke, Ontario, Canada

PETER A. SANDBORN, Department of Mechanical Engineering, University of

Maryland, College Park, Maryland, [email protected]

LEONARD W. SCHAPER , Department of Electrical Engineering, University of

Arkansas, Fayetteville, Arkansas, [email protected]

R ICHARD K. ULRICH, Department of Chemical Engineering, University of

Arkansas, Fayetteville, Arkansas, [email protected]

ZHENWEN WANG, Electrical and Computer Engineering Department, McMaster

University, Hamilton, Ontario, Canada

xv





PREFACE

The purpose of this book is to provide an overview of the technology, potential ap-

plications, motivations and problems associated with integrating passive compo-

nents such as resistors, capacitors, and inductors into circuit boards instead of

mounting them as discrete components on the surface. It was written primarily for

the engineer or scientist in industry who wants to determine if passive integration is

a viable option for a particular product. Thus, when explaining the various aspects

of integrated passives throughout this book, we have sought to address a basic set of

questions concerning the tradeoffs between discrete and integrated approaches suchas:

What are the advantages and disadvantages of integrated passives?

What sort of processing would be required?

Is this processing compatible with existing substrates?

Can integrated passives be made with conventional PWB fabrication equip-

ment?

What are the performance and/or form factor advantages of integration?

How do the electrical characteristics of integrated passives differ from dis-

cretes?

Can existing equipment and materials be used?

Can all of the passive components be integrated?

How are integrated passives designed?

What are the tolerance and repeatability limits?

To what extent is yield an issue?

Is reworkability possible?

What must be considered in the economic analysis?

Because passives have been integrated into ceramic substrates for decades, the

focus of this book is on the organic substrate and buildup materials more closely as-

sociated with the consumer sector, such as FR-4 and flex. Passive integration is

xvii



only beginning for these materials and, at present, there is very little established

methodology. The lessons learned from integrated passives in ceramics were com-

bined with contemporary work on consumer-level substrates in order to project

what is possible and practical for organic boards. We are aware of no other book dedicated to integrated passives so we pulled together information from many

sources and locations outside of our own work at the University of Arkansas. Al-

though we wrote most of this book, outside experts have been used wherever we

could find them for both contributions and reviews to help ensure adequate cover-

age of important topics.

We assume that the reader is familiar with the basics of board-level fabrication,

specifically with regard to conductor definition, via formation, surface-mount as-

sembly, thin- and thick-film processing, photolithography, and etching. An elemen-

tary knowledge of the electrical aspects of resistance, capacitance, and inductancewill also be required to appreciate the performance advantages of passive integra-

tion. Both materials science and electrical engineering issues are presented in clear-

ly delineated sections throughout the book so readers can pick those parts that are

most beneficial to them.

Chapter 1 sets forth the important issues that will be covered individually in de-

tail in subsequent chapters. After reading this chapter, the reader should be able to

select chapters of interest and read them as stand-alone works with a minimum of

referencing previous chapters for background information.

Whether to organize individual chapters around materials or around processesturned out to be a fundamental question. They are intimately connected, but it is im-

possible to discuss separately all the permutations of deposition methods, patterning

techniques, and materials. The best choice seemed to group materials under the var-

ious processes. For instance, there is a section on sputtering that includes how to de-

posit TaNx rather than a section on TaNx that discusses sputtering. This approach

seems better, since most existing manufacturers are more likely to be organized

around various types of processes than around various types of materials.

A board shop looking to get into passive integration has to begin manufacturing

components that it previously purchased ready-to-use. Therefore, it must have afundamental understanding of the relationship between the materials in passives

and their electrical performance. The electrical properties of materials are reviewed

in context with the various passive devices and their manufacturing processes in or-

der to help the uninitiated make this connection.

Again, the purpose of this book is to disseminate the state of the art in passive in-

tegration to help the practicing engineer evaluate the possibility of using this tech-

nology in their products. Since this technology is rapidly developing, the next edi-

tion of this book should contain fewer fundamentals and more commercially

implemented processes. It is our hope that we are promoting that evolution.The editors are grateful to many people for helping to make this book possible

including Julia Busch, Louise Schaper, David Nelms, Tim Lenihan, Matt Leftwich,

Errol Porter, Kaoru Maner, and all the graduate students who have worked on inte-

grated passive projects at the University of Arkansas. Thanks to colleagues Bill

Brown, Simon Ang, Hameed Naseem, and others associated with the High Density

xviii PREFACE



Electronics Center at the University of Arkansas, as well as to the departments of

Chemical Engineering and Electrical Engineering for providing some of the time

and support necessary for such a large undertaking. Thanks to Erik Brandon and

other researchers at JPL for their support through the years. Also, we benefited from review work on various chapters by many people including Istvan Novak, Bill

Borland, David McGregor, Thomas Lantzer, Joel Peiffer, Robert Croswell, and

Kim Fjeldsted.

R ICHARD K. ULRICH

LEONARD W. SCHAPER Fayetteville, Arkansas

April 2003

PREFACE xix





1

CHAPTER 1

INTRODUCTION

RICHARD K. ULRICH

Integrating passive components directly into the circuit board is a well-establishedidea but an immature practice. To put this into perspective, compare two technolo-gies familiar today: the laser and color TV. The laser came about comparativelysuddenly in the early 1960s, taking much of the technological community by sur-

prise. It was an unanticipated invention, to most, whose utility became obvious

when the technology was revealed. In contrast, color TV was anticipated for decades. Its potential benefits and anticipated implementation problems were wellestablished long before its common usage in the industry. Debate ensued for yearsover the most effective and economical solutions to the numerous interrelated tech-nical issues. It was an engineered system, not an invention, developed to augment awell-established technology, and it was not clear how much of that old technologyit would displace.

Integrated passives are like color TV. Those in the electronics business have afirm idea of the benefits integrated passives can bring as well as the problems of im-

plementing them into one of the largest and most established industries in theworld. There are a large number of candidate materials and processes but littleagreement as of yet over which, if any, are superior to the rest. The purpose of this

book is to identify these potential payoffs and problems and to provide an overviewof the current technologies available in order to help the engineer choose the bestoptions for integrating passive components in a given application.

This first chapter will provide a summary of the state of surface-mount passives,an introduction to the concept, benefits, and problems of integrated passives, andsome coverage of the fabrication and materials technologies involved. As many rel-

evant references as possible are included to help the reader follow up on a topic of interest. The organization of this book is such that the introduction provides a gen-eral overview for readers of just about any level of familiarity with the subject andthe rest of the chapters are more specific to individual topics. The reader should atleast skim this first chapter, and then choose subsequent chapters of special interestfor further study.

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper

Copyright © 2003 Institute of Electrical and Electronics Engineers.

ISBN: 0-471-24431-7



1.1 STATUS AND TRENDS IN DISCRETE PASSIVE COMPONENTS

Tremendous progress has been made in the past four decades in miniaturizing and

integrating transistors and capacitors for logic applications onto silicon. By compar-ison, passive components (resistors, capacitors, and inductors) at the circuit-boardlevel have made only incremental advances in size and density. Consequently, pas-sive components occupy an increasingly larger area and mass fraction of electronicsystems and are a major hurdle to the miniaturization of many electronic systems.This is particularly true for analog and mixed-signal applications that use a larger number of passives than typical digital systems. Almost no through-hole, axial-leaded resistors and disk capacitors are used anymore; they have been replaced withsmaller, rectangular surface-mount components with solder joints at both ends. The

size of these modern discretes is described by a number such as 0603, which indi-cates a size of 60 × 30 mils (1.5 × 0.75 mm). The 0402 (1.0 × 0.5 mm) size is com-monly used, and the smallest discrete passives today are 0201 (0.50 × 0.25 mm),which represents a considerable challenge in handling, attachment, and inspection.Figure 1.1 shows a cell phone RF section that utilizes 0402 resistors and capacitorssurrounding a 6 ×x 6 mm packaged integrated circuit. About a trillion passive de-vices were placed in electronic systems in 2000, with the vast majority utilizing sur-face-mount technology. Today, each mounted passive costs about half a U.S. centto purchase, and about 1.3 cents for conversion (assembly, testing, inspection, and

rework), for a total installed cost of around 1.8 cents [1]. The present total marketfor passive devices is around $18 billion annually.In terms of numbers, there are more passive devices than active devices in just

about any application. An Ericsson CF388 PCS 1900 cell phone has 380 compo-nents, including 322 passives and 15 ICs, for a passive-to-active ratio of 21:1. Digi-

2 INTRODUCTION

Figure 1.1 Cell phone RF section utilizing surface-mount passives.



tal systems, such as desktop and laptop computers, have somewhat lower ratios: be-tween 5 and 15 passives for every IC (see Table 1.1) [2]. An Apple G4 has 230 ca-

pacitors, 218 resistors, 9 inductors, and 8 diodes [3] mounted on the motherboard,

together with 42 integrated circuits.In terms of area, an individual surface-mount passive is almost always smaller

than any packaged IC and usually has only two connections, so the relative totalfootprints and total number of device-to-board connections are closer to equal. Fig-ure 1.2 shows part of a board from a Nokia 6161 cell phone with the location andfootprint of surface-mount discrete passives marked in white. Typical passive com-

ponent density in hand-held wireless applications is about 20/inch2, which, at 2cents/component, amounts to $0.40/inch2 for passives alone [5].

A breakdown of the 405 individual passive components by number and value for

this same phone is shown in Table 1.2 [6]. Additionally, there are 15 ICs and 40miscellaneous surface-mount devices such as power transistors and diodes for ESD protection, all mounted onto 6.2 square inches of board area for an average passivedensity of 85/inch2.

1.1 STATUS AND TRENDS IN DISCRETE PASSIVE COMPONENTS 3

Table 1.1 Passive and IC count for portable consumer products [4]

System Total Passives Total ICs Ratio

Cellular PhonesEricsson DH338 Digital 359 25 14:1Ericsson E237 Analog 243 14 17:1Philips PR93 Analog 283 11 25:1 Nokia 2110 Digital 432 21 20:1Motorola Md 1.8 GHz 389 27 14:1Casio PH-250 373 29 13:1Motorola StarTAC 993 45 22:1Matsushita NTT DOCOMO I 492 30 16:1

Consumer PortableMotorola Tango Pager 437 15 29:1Casio QV1O Digital Camera 489 17 29:11990 Sony Camcorder 1226 14 33:1Sony Handy Cam DCR-PC7 1329 43 31:1

Other CommunicationMotorola Pen Pager 142 3 47:1Infotac Radio Modem 585 24 24:1Data Race Fax-Modem 101 8 13:1

PDASony Magic Link 538 74 7:1

ComputersApple Portable Logic Board 184 24 8:1Apple G4 457 42 11:1



The number of discrete passives in a model series of desktop computers over theyears is given in Table 1.3 [7, 8]. Some trends are clear: a rapid increase in the totalnumber of passives utilized, a total switch from leaded to SMT components, and theinitiation of the use of passive arrays—multiple passives in one package. Mobilewireless, including cell phones, will account for the largest share of the increase in

passive usage in coming years but other significant new markets include Bluetoothand automotive applications. The 2000 National Electronic Manufacturing Initia-tive (NEMI) roadmap predicts that cell phone sales will reach one billion units an-nually by 2004, which will require replacing half the cell phones in use today, andthere should be two billion Bluetooth devices operating by 2005. Telecommunica-tions has replaced computers as the top user of printed wiring boards.

An analysis of two cell phones, one GPS receiver, and two two-way radios pro-duced the resistor and capacitor distributions shown in Figures 1.3, 1.4, and 1.5 [9].The required values extend over many orders of magnitude for resistors and capaci-tors. Inductors range in value from about 1 to 50 nH, but there are usually far fewer inductors than capacitors and resistors in most consumer microelectronic products.It has been observed that 40% of capacitors in a cell phone are under 1 nF [2] and80% of inductors in hand-held products are less than 200 nH [5].

4 INTRODUCTION

Figure 1.2 Cell phone board showing the footprints of surface mount passive componentsmarked in white.



5

Table 1.2 Distribution of sizes and values for surface-mount passive components in a Nokia 6161 cell phone

Size Values Quantity

Capacitors0402 <100 pF 1000402 1 nF 370402 15 nF 200603 30 nF 220603 100 nF 290805 250 nF 20805 1 F 121206 2 F 21310 9 F 2

electrolytic 10 F 6Total: 232

Resistors0402 1–10 M 109

0402 dual-array 1–20 M 180603 1–22 M 160805 1–22 M 41206 1–22 M 2

Total: 149

Inductors

0603 1–100 nH 160805 2–500 nH 31206 <220 H 5

Total: 24

Total Passive Components: 405

Table 1.3 Number and type of passive components in personal computers

486 Pentium 120 Pentium 200 Pentium II Pentium III

Leaded MLC 58 0 0 0 0SMT MLC 0 151 190 300 600Cap Arrays (4) 0 0 32 140 200Leaded Tantalum 15 1 0 0 0SMT Tantalum 0 0 0 37 80Aluminum 0 7 32 11 15Feedthrough 0 0 3 0 0Disks 0 0 0 4 0

Leaded Resistors 92 0 0 0 0SMT Resistors 0 146 188 635 1000Resistor Arrays (×2) 0 0 0 10 0Resistor Arrays (×4) 0 64 148 336 300

Total Passives 165 369 593 1,473 2,195



6

Figure 1.3 Distribution of resistor values in portable consumer equipment.

Figure 1.4 Distribution of capacitor values in portable consumer equipment.

Figure 1.5 Distribution spectrum of capacitors by product type, 1996 [5].





made with one alignment and mounting. This is the lowest level of passive

integration and may involve the same manufacturing techniques used for discretes.

Integrated Passive Networks —Multiple passive components of more than onefunction are formed on the surface of a separate substrate and packaged in asingle SMT case. This case is then mounted on the primary interconnect sub-strate of the system. (See Figure 1.8.) These typically have some internal con-nections to form simple functions such as terminators or filters. The number of leads can vary with functionality and the number of internal elements. Thisapproach generally does reduce the number of leads to be connected sincesome passive-to-passive connections are made within the package. (See Fig-ure 1.9.)

8 INTRODUCTION

Figure 1.6 Embedded passive components in the primary interconnect substrate.

Figure 1.7 Integrated passive arrays.



Both passive arrays and networks of various types are available from sev-eral manufacturers and are in common use in all types of electronic systems

as surface-mount components as small as 0402. They are particularly usefulin digital systems in which parallel data buses require RC termination or

pull-up/pull-down resistors for many lines in a small footprint. Their com-mercial penetration is probably less than 5% at this time but is expected toincrease.

Integrated Passive Subsystems —These are similar to but more complex than passive networks and may include some active devices to form a functionalsubsystem module that can be surface mounted onto the primary interconnect

board. Figure 1.10 shows a voltage-controlled oscillator from Intarsia thatconsists of integrated passives featuring several visible square-format inte-grated inductors and planar capacitors, along with three wire-bonded actives.The solder balls enable the network to be flipped and mounted onto a primaryinterconnect substrate, made possible by the low profile of the integrated pas-sives. It may be feasible to provide subsystems as complex as GPS or Blue-tooth this way, so that a manufacturer could add them as desired to a primaryinterconnect board of another product.

1.2 DEFINITIONS AND CONFIGURATIONS OF INTEGRATED PASSIVES 9

Figure 1.8 Integrated passive network.

Figure 1.9 Hierarchy of integrated passive components.





nections were eliminated and changes in layout could be made by simply changingartwork. Initially, there was some concern that large-scale integration could never

be realized because of yield issues; absolutely every gate must work for the system

to function since there is no possibility of rework. For instance, to obtain a chipyield of at least 80% for an IC with 10 million transistors, the number of defectiveindividual transistors must average no more than about one in 44 million. However,the status of present-day thin film formation, photolithography, and etching routine-ly achieve these numbers and better. Although chip size is somewhat constrained byyield concerns, the density of active devices on a chip is not; that is more a functionof the ability to expose and etch fine features. Since the invention of the integratedcircuit, continuous improvements in yield and gate density have resulted in a steadyincrease in the functionality of a single chip. The result, as described by Moore’s

law, is that on-chip logic density has doubled about every 18 months for decadesand will do so for at least another one. The resulting orders-of-magnitude increasesin function per unit cost, volume, and mass are well known, and, in fact, still drive alarge portion of our economy.

The status of passive components today is similar to that of active devices almosthalf a century ago. Many of the same well-known motivations and concerns relateto passive integration; the task is to determine which of these apply to this new sce-nario and what they mean to the rate of acceptance, ultimate configurations, and de-gree of replacement of discrete components. There are several differences in the

two situations; the most important is that passive components cannot be scaleddown in size to the extent that active devices can be. Since logic devices such astransistor-based gates and memory cells can, in principle, operate with individualelectrical quanta; they can be scaled down to the submicron dimensions that areubiquitous today. However, the signals processed in analog systems or digital sig-nals at the board level cannot be reduced in amplitude arbitrarily. They may be RFsignals going to an antenna, the input for A/D conversion, or bursts of hundreds of watts of power to a single chip during a clock cycle. As a result, increases in inte-grated passive component density can only come about when the passive is made

smaller while maintaining the same value of Ohms, Farads or Henrys (Figure 1.11).As will be frequently pointed out in this book, the need for higher values of resis-tance and capacitance per unit area is a limiting factor in the implementation of in-tegrated passives, underscoring the importance of fundamental materials research inthis area.

1.4 SUBSTRATES AND INTERCONNECT SYSTEMS FOR

INTEGRATED PASSIVES

There is a vast array of materials, processing methods, and configurations in use asinterconnect substrates, from resin-impregnated paper with printed conductors on thelow end to single-crystal silicon with photolithographic thin-film built-up layers onthe high end. In between there are FR4, ceramic, polymer film, and rigid inorganics,

1.4 SUBSTRATES AND INTERCONNECT SYSTEMS FOR INTEGRATED PASSIVES 11



each of which can be composed of a multitude of specific materials and processed in

dozens of ways [10, 11]. The number of possible interconnect substrates times thenumber of processes used to achieve them times the number of materials and process-es for integrated passives equals an impossible number to describe individually. Inorder to make this manageable, the types of substrates must be grouped.

The first natural division is into organic and inorganic designations. “Organic”means that there is a polymer material, either thermoset or thermoplastic, in the

board, even if it makes up a small fraction by mass. This will limit the maximumtemperature for any processing to around 200–300°C and possibly lower for somesteps. For instance, polyimide can withstand temperatures well over 250°C without

decomposing, but mil-thick sheets may be permanently distorted if the temperatureduring sputtering exceeds about 100°C [12]. Inorganic substrates can withstandwell over 700–1000°C and are usually limited by the softening point of the metals.

1.4.1 Organic Substrates

1.4.1.1 FR4. This is the ubiquitous green rigid circuit board material found inalmost every consumer system. The polymeric component is at least one, and usual-ly more, layers of glass-fiber-reinforced epoxy about 0.5–1.5 mm (20–60 mils)

thick with 17 or 34 micron Cu (½ oz or 1 oz Cu) patterned as the conductor. Multi- ple layers are laminated with heat and pressure.

1.4.1.2 Flex. These are laminated stacks of polyimide (Kapton), polyester, liq-uid crystal, or layers of any other free-standing polymer films, each from 1–5 milsthick. These can be obtained with Cu already laminated on one or both sides for

12 INTRODUCTION

Figure 1.11 The second generation of integration.



subtractive patterning, or processing can be through sputtering, plating, and pho-tolithographic techniques. Higher interconnect density than with FR4 is achievabledue to thinner insulating films, which enable smaller vias, and through the use of

thin-film processes, but at higher cost per square inch of the resulting board.

1.4.1.3 Build-Up. A rigid material such as glass, silicon, or plastic is used as a base, and alternating layers of conducting and insulating layers are deposited andetched one at a time in the same manner as fabrication for the interconnect layersfor an IC. These are similar to thin-film techniques and, in most technologies, nomechanical lamination is performed, although vacuum processing is used exten-sively. The organic portion is either the insulating dielectric, which is either spin-onor cast coatings of BCB, polyimide or some other liquid-state precursor that is then

thermally cured, or the rigid material that forms the base for the build-up. Metalsare sputtered or plated, then etched photolithographically. Vias are made by plasmaetching, laser drilling, or photodefinition. This provides the highest interconnectdensity of the three organic approaches because there is generally no lamination, al-lowing via catchpads to be smaller. Removing half the vias from a board will nothave as much beneficial effect on wiring density as reducing the diameter of thesecatchpads by half [10].

FR4 is by far the most mature and utilized organic substrate, representing 85%of the resin systems used to produce copper-clad laminate [1]. At present (mid

2002), there are perhaps four or five commercial technologies for integrated resis-tors and capacitors spread between about that many vendors, but more are in devel-opment and should appear soon. As will be described below, there are more factorsto overcome in integrated passive implementation than just process development,including design, standardization, testing, reliability, and understanding the eco-nomic tradeoffs. However, all of these issues are being addressed in academia, in-dustry, and consortia so that it is expected that integrated passives will becomecommon in FR4 over the coming years. Most of the papers from microelectronic

journals and proceedings since about 1995 involve various flex substrates, microvia

methods on thin laminates, and build-up processes. These have the possibility toachieve high-density interconnection, perhaps reflecting the feeling that integrated

passives would be more economically feasible on a more expensive and higher-per-formance platform or else that it might be easier to introduce integrated passivesinto an interconnect technology that is itself under development. As HDI flex in-creases its share of the total market, integrated passives will probably be present insome fraction. Buildup processing with organic dielectrics on substrates like sili-con, alumina, and glass was known as MCM-D a decade ago but, as is the nature of the electronics business, the same thing has a different name today: system-in-a-

package (SIP). Intarsia (now defunct) built a variety of integrated passive networkson glass using thin-film BCB interlayer insulation. IMEC, the Belgian developmentorganization, builds a similar technology and cooperates with European partners.Today, even taken together, embedded passives on organic substrates/layers makeup an insignificant portion of the total sales of passives, but that is expected tochange soon.

1.4 SUBSTRATES AND INTERCONNECT SYSTEMS FOR INTEGRATED PASSIVES 13



1.4.2 Inorganic Substrates/Layers

1.4.2.1 Cofired Ceramic. Layers of “greentape” uncured ceramic with screen- printed metallization paste and metal-filled punched vias are collimated, stackedand fired, typically at 700–1100°C, to form an interconnect board. This is a verymature technology, dating back to the early 1960s. The materials used then werealumina ceramic and tungsten or molybdenum metal, which had to be fired at veryhigh temperature. Today, low-temperature cofired ceramic (LTCC) is used withcopper, silver, or gold metallization. Other pastes are used to form resistors and ca-

pacitor dielectrics.Ceramic substrate technology accounts for only about 10% of the boards pro-

duced worldwide [1]. Established methodology for integrated passives is widelyavailable from the design phase through reliability assessment. The infrastructurefor ceramics is so entrenched that a new company need only contact the vendors toestablish a process. However, integrated passives in ceramic substrates cannot becontrolled to tight tolerances and cannot be easily trimmed.

1.4.2.2 Front-End Silicon. These are standard IC manufacturing techniqueson silicon that utilize either sputtered TiNx, CrSi, or doped Si resistors along withSiOx or SiNx capacitors. There are no active devices fabricated. The insulation lay-ers are SiO2 and the metal is Al, which limits processing temperature to about500°C. n-Chip (now Flextronics) employed an anodized alumina decoupling capac-itor built into a silicon substrate that was used as an MCM-D substrate.

Integrated passive sales are currently around 3% of the total and almost all of that comes from the inorganic category in the form of passive arrays and networks.These are manufactured either by using extensions of the fired ceramic and thin-film technologies used to make discrete passives or else by the front-end silicon

process described above.

1.5 FABRICATION OF INTEGRATED PASSIVES

The overall situation is that neither the optimal materials nor methods for fabricat-ing integrated passives on organic substrates have been established, which limitstheir use in the most common substrates. Integrated passives are well established oninorganic substrates, but problems exist with regard to tolerance for those in cofiredceramics and with value range on silicon.

Due to the planar nature of integrated passives, the formation and patterning of films are central to this technology. There are three broad classes of films required:

conductive, resistive, and dielectric. Conductive films are those that are needed for carrying current with a minimum of voltage loss, such as the top and bottom platesof capacitors and the spiral windings of a planar inductor. There is no advantage tohaving parasitic resistance in this type of film; that would only degrade the perfor-mance of the capacitor or inductor. Therefore, these would normally be metals or else very conductive metal-filled polymer thick films with resistances less than

14 INTRODUCTION



about 0.1 /square. Narrow tolerance and repeatability is not a major issue as longas the overall resistance is low enough for the application. Of course, it would bedesirable for integrated passives to utilize the same metal used as the interconnect

on the substrate. Resistive films would be used in making integrated resistors only,and would be specified on the basis of providing predictable, reproducible values of resistance in a sufficiently small footprint. A wide variety of materials could beused for this, ranging from resistive alloys (NiCr, CrSi, TaNx, TiNxOy) to ceram-ic–metal nanocomposites (cermets) to carbon-filled polymers. Resistivities of 100to 10,000 /square are required. Dielectric films would be used to form integratedcapacitors, and a vast array of materials with a wide range of dielectric constants arefeasible, from simple unfilled polymers for small-valued capacitors (k = 2–5) toamorphous metal oxides (k = 9–50) to highly ordered mixed oxides for the highest

possible dielectric constants (k > 1000). There are essentially no fabrication issuesfor inductors; they are simply shaped conductors made from the interconnect metal-lization already present in the boards.

These three types of films can be formed subtractively or additively by sputter-ing, CVD, evaporation, anodization, dry oxidation, sol–gel, spin-on, doctor-bladecoating, chemical conversion, and many other techniques. Etching options includeliquids and a variety of reactive and unreactive, directed or nondirected plasmas.They can be modified by annealing, exposure to chemicals, or an array of surfacetreatments. A classification scheme of films based on manufacturing methods is

shown in Table 1.4.Integrated passives are not a new idea; they have been used for decades in ce-ramic and some organic substrates under the name “hybrids.” Thick-film pastes of conductors and dielectrics are used to form resistors, capacitor dielectrics, and spi-ral inductors that are fired simultaneously with the green tape of the insulatinglayers. However, the firing requirements mean that this technology is not transfer-able to heat-sensitive organic substrates. Glass has been used for integrated pas-sive substrates by Intarsia, and silicon had a brief period of use as an MCM sub-strate; Bell Labs and nChip utilized an integrated decoupling capacitor as part of

the build-up over a silicon substrate for their MCM designs. Organic substratesmake up the vast majority of interconnect boards due to their low cost, and it ishere that integrated passive efforts are most important. Because organic boardscannot tolerate temperatures much above about 250°C, many processing optionsare not possible, including all involving fired ceramic thick films. Also, vacuum

processing is not available in many board shops. Whatever methods and materialsare chosen must be compatible with the board’s conductors and insulation layersalready in place, integrated passives already in place, and any subsequent fabrica-tion.

A search of the literature reveals that most papers for integrated resistors and capacitors on organic boards involve a demonstration of a specific film technology(often sputtered) on a specific substrate, generally leading to either a test structureto measure film properties or to a simple system such as a filter or a terminator, pos-sibly with an inductor thrown in to complete the device. Integrated inductors poselittle fabrication and material challenges, so most papers on them concentrate on

1.5 FABRICATION OF INTEGRATED PASSIVES 15



their design. Few papers have addressed the full integration of resistance, capaci-tance, and inductance (R, C, and L) on one substrate. Although an exact count of the papers has not been performed, some generalizations can be made. Most of thereported efforts that involve organic substrates employ sputtering of the resistor material or capacitor dielectric. TaNx is the clear favorite among sputtered resistor materials due to its advantageous combination of properties that were well known

before integrated passives became an issue: appropriate material resistance, ease of processing, and stability with time and temperature. TaNx, together with CrSi, NiCr, and a few other sputtered alloys, cover the range of resistance up to a fewhundred /square. A higher range is necessary for resistors up to a M, requiring

perhaps as much as 10,000 /square. Much less integrated resistor developmenthas occurred there, but sputtered cermets such as CrSiO or TiNxOy seem to be the

most feasible. For capacitor dielectrics, the situation is much less clear. Almost anydielectric that can be formed has been investigated, so many that their discussionwill be left to three chapters later in this book. The materials and fabrication of ca-

pacitor dielectrics is the major hurdle in the development of fully integrated pas-sives on organic substrates.

16 INTRODUCTION

Table 1.4 Comparison of electronic film technologies

Thin Film Polymer Thick Film Ceramic Thick Film

Sputtering, CVD, evaporation. Spin-on, cast, screen print, Cast, screen print, or stencilSimilar to IC technology. or stencil polymer materials glass paste, functional filler,Requires vacuum with functional filler, then and organic binder, then fire

cure polymer to remove binder

100–250°C 100–250°C 600–1000°C

Subtractive processing Usually additive processing Additive processing

Thickness < few microns Thickness = few microns Thickness = few micronsto mils to mils

Metals, oxides, but rarely Filled polymers Filled glasses, oxides polymers

Higher capacitance as they Lower capacitance as they Medium capacitance as theyare thin are thick are thick, but has high k

Capable of smaller width and Widths and spaces down Widths and spaces downspaces down to microns to mils to mils

Better dimensional tolerance Less controllable tolerance Less controllable tolerance

Most have stable values with Reliability and stability a Stable values with timetime and humidity limiting concern for many, and humidity

and a major area of R&Don these materials

Most expensive Least expensive In between



1.6 REASONS FOR INTEGRATING PASSIVE DEVICES

Although it is tempting for engineers to look only at the technical aspects, these is-

sues should only serve as inputs to business models to determine the ultimate worthof changing technologies. Deciding which engineering option will provide a higher return on each dollar invested cannot be based solely on the goal of lowering thecost to make the same product; the implications are much more nebulous and in-clude concepts such as increased functionality, added product value, higher con-sumer appeal, and the ability to make products that cannot be realized with the old-er technology. Some of these issues are difficult to quantify; for instance, what isthe added dollar value to a cell phone that is made 20% smaller? There is a realworth to this type of improvement, but it is a function of consumer psychology,

which is notoriously hard to enumerate. The merely technical issues often can bequantified fairly accurately. For integrated passives, the reasons in favor of integra-tion can be broken down into these motivations:

1. Reduced system mass, volume and footprint. Individual packages areeliminated and passives can go “underground,” leaving more room on thesurface for ICs.

2. Improved electrical performance. Integrated passives can have lower para-sitics, particularly, much lower inductance in capacitors.

3. Increased design flexibility. The component’s resistance, capacitance, or in-ductance can be sized to any desired value within the technology’s range.

4. Improved reliability. Solder joints are eliminated.

5. Reduced unit cost. Integrated passives can be formed simultaneously andwith very low incremental cost. Also, they are inherently lead-free.

These issues will be introduced briefly below, and then examined at length indi-vidually later in this book.

Not all integrated passives have smaller footprints than the surface mount de-vices they might replace. In fact, the higher values of integrated capacitors and in-ductors would occupy a much larger area. For example, a 100 nF integrated capaci-tor formed by sputtering 3000 Å of Al2O3 onto a circuit board would require almost4 cm2 of area, compared to only 0.01 cm2 for an 0402 surface mount capacitor plusits associated keep-away distance [13]. Similarly, a 50 nH planar spiral inductor could be made from five turns of 5 mil conductor, but would have an outer diameter of 3.3 mm. Furthermore, this inductor would require a keep-away distance on alllayers of the substrate, not just one like a capacitor or a resistor, about equal to itsradius to avoid interference from other metal with its electromagnetic field, which

would reduce its effective value. Its total area would be 0.34 cm2 and would be ef-fectively multiplied times the number of layers in the substrate that must be keptclear. Integrated resistors and small-valued capacitors are much closer to, or evensmaller than, their surface-mount size. The reduction in system form factor with in-tegrated passive technology would come from the fact that integrated passives, re-

1.6 REASONS FOR INTEGRATING PASSIVE DEVICES 17



gardless of their footprint, can be fabricated under the surface of the board, whichfrees up top-surface area that was formerly occupied by surface-mount passives.Since many wireless and mixed-signal systems have something like half of the

board surface occupied by passives, the footprint reduction can be significant. Ad-ditionally, system mass may be reduced by stripping an integrated resistor, capaci-tor, or inductor down to only its electrically active portions, leaving less than a mil-ligram of metal and/or dielectric. The integrated passive would depend on thesubstrate for mechanical support and the layers above and below it for environmen-tal protection, eliminating the mass and volume of the individual package.

The price paid for this is that additional board layers may be required to accom-modate these passives in their integrated form, adding cost and complexity to themanufacturing process, which can offset some of the benefits of freeing up surface

area and reducing volume or mass. This is an important trade-off in passive integra-tion and will be a major driving force in the economic viability of any integrated approach. It is not clear that more layers will always be required for integrated passives;savings in wiring and, especially, vias required to route all passive connections to thesurface may be significant if the passives can be placed on any desired layer. As pre-viously mentioned, active logic devices can be scaled down to nanometer scales,

principally by improvements in processing technology, since they can operate witharbitrarily few electrical quanta. But passives may have to maintain values of resis-tance, capacitance, and inductance regardless of their size, and footprint reduction

can come about only be improvements in materials to give higher specific values per unit area. This is particularly problematic for integrated capacitors.Due to their simplified structure and lack of leads and contacts, integrated capac-

itors and resistors tend to have considerably less parasitic inductance than their sur-face-mount counterparts. Also, short leads to the integrated capacitor or inductor can result in less parasitic resistance. As a result, integrated passives tend to be“purer” components with less undesired properties to be taken into account in thedesign phase. Lower parasitic inductance is particularly important for capacitors inhigh-frequency applications such as decoupling and RF filtering since, above the

self-resonance frequency, the inductive properties of the capacitor dominate thecomponent’s behavior, making it act completely like an inductor. Integrated capac-itors can be fabricated that have far higher self-resonant frequencies and, therefore,a larger usable frequency range, than is possible with any discrete capacitor, nomatter how much the latter is optimized for low inductance. This is a major motiva-tion for integrating capacitors, as will be discussed in the section of this book deal-ing with decoupling applications.

An additional electrical advantage comes about because the value of integrated passives can be specified exactly (Figure 1.12). If an 18.2 nF capacitor, a 2360

resistor, and a 14.6 nH inductor are needed for a design, the integrated passives can be sized to give those values (within tolerance limits); it is not necessary to choosethe next closest value from a catalog of discrete passives or to have to create thevalues by stringing together discretes in series and/or parallel. Using multiple dis-cretes may take up a large amount of board space, require a large number of lead-attach steps, and exacerbates problems associated with parasitics.

18 INTRODUCTION





Issues regarding lower unit cost were briefly addressed in the previous section.Because integrated passives can be formed simultaneously, the incremental cost of

producing just one more is nearly zero. This characteristic is attractive for systems

requiring dense placement of passives, which is the direction most systems areheading in. A major issue in business models for integrated passives is whether allof them can be integrated or only some. If they can all be integrated, then there is noneed for any pick-and-place equipment for surface-mount passives, just for the ICs,and the cost model needs to consider only one technology set for passives: integra-tion. However, if only most of them can be integrated, then it would seem more dif-ficult to be cost-competitive since the manufacturing facility must support bothtechnologies at once. Some passives, such as large-value capacitors and inductors,may be very challenging to integrate due to their large footprints, even in buried

layers, and may be best left as surface mounts. On the plus side, integrated passivesare inherently lead-free. At present, economic analysis to determine the feasibilityof integrated passives is specific to both the application and the integrated passivetechnology.

1.7 PROBLEMS WITH INTEGRATING PASSIVE DEVICES

The problems with implementing integrated passives on organic boards are as well

understood as their potential benefits. These include:

1. Indecision on materials and processes. Research continues on many resis-tor materials and capacitor dielectrics.

2. Lack of design tools, for both component sizing and system layout.

3. Requires vertical integration. The same company must manufacture bothsubstrates and passives.

4. Yield issues. One bad component can lead to scrapping the entire board.

5. Tolerance issues. Integrated passives cannot be presorted prior to inclusion

on the board.6. Lack of standardization. The various segments of the integrated passive in-

dustry aren’t speaking the same language [14].

7. Surface-mount technology is improving —moving towards 01005.

8. Lack of costing models. It is not easy to tell when integrated passives might be more cost effective.

It is not that it cannot be done; scores of research projects have shown that the full

required range of R, C, and L values are achievable on just about any substrate. The problem is that the optimal materials and processes have not been identified, if theyexist for a given substrate, and that the infrastructure does not yet exist in the indus-try for their design and manufacture. The vast number of material and processchoices was the major reason for writing this book. The physical integration of pas-sive components into circuit boards necessitates the integration of the correspond-

20 INTRODUCTION



ing business units. For example, a manufacturer that previously made only boards but now expands into integrated passives finds itself in the business of making pas-sive components instead of simply buying them from a catalog. That means having

to understand issues of passive performance, fabrication, sizing, tolerance, para-sitics, and reliability, which were previously taken care of by a separate entity.

There are two main aspects to the design issue: designing the individual compo-nents and designing the components into a system. Taking the narrower one first,designing individual integrated resistors and capacitors is easy but dependent on thematerials used, since this will influence the value density of the structure, such asthe number of nF/cm2 for an integrated capacitor. If the ohms/square of the resistor film or the nF/cm2 of the dielectric film are known, then it is a simple matter to sizethe component for a required overall value. Therefore, the component’s material

and processing technology have to be established before components can be sized.For inductors, the design situation is much more complex. Accurate sizing of a spi-ral inductor from first principles requires solving Maxwell’s equations for a spiralshape on a Cartesian geometry with various other conductors from the eventual sys-tem layout present to distort the magnetic field. Although there are some excellentapproximate design tools for isolated spirals, described later in this book, the pres-ence of other conductive materials nearby means that the design of the integratedinductor usually can’t be done as a stand-alone component. Trial and error with

physical prototypes will sometimes be required.

With regard to overall layout, only a few programs are capable of taking inte-grated passives into consideration by incorporating them from SPICE-like electricalmodels and autorouting around them or optimizing their placement on and amonglayers. Doing all of these by hand is possible but can be quite tedious, and very fewdesigners are experienced with integrated passives to the point of knowing the per-tinent layout issues necessary for taking advantage of their unique electrical andsize characteristics. However, progress is being made in this area by design and lay-out software vendors, and there is no major technological hurdle to enabling these

programs to utilize integrated passives effectively and with the same ease of opera-

tion as they do for surface mount boards. Again, the processes must be establishedfirst.On the assembly side, attachment of surface-mount discretes is one of the last

steps to be performed on a circuit board prior to its inclusion in the overall system.All of the layers and conductors are fully formed and tested before the passives goon. The only concession made by the board designers to the eventual presence of the surface-mount passives, and ICs for that matter, is that proper attachment metal-lurgy be available and that the board be able to withstand the temperatures associat-ed with the attachment process. The attachment process is typically reflowed or

wave soldering, requiring about 250°C for up to a few minutes; or conductive epox-ies, which usually have even milder thermal requirements. However, if integrated passives are utilized, they will be fabricated as part of the board’s manufacturingflow and the portions of the board already formed will have to be able to withstandnot only the thermal stresses that a particular integrated passive technology re-quires, but also any chemical and mechanical exposures that are involved. Subse-

1.7 PROBLEMS WITH INTEGRATING PASSIVE DEVICES 21



quent interconnect/insulator processing must not degrade any integrated passivesthat are already in place and any integrated passive processing must not degrade the

board layers already in place. Not only are the passives integrated into the board,

their processing requirements are mixed in as well.The same yield problem exists for integrated passives that is well known for in-

tegrated circuits: one bad component out of many can cause the entire board to bescrapped. The problem might not be apparent until the substrate is completed, so aconsiderable amount of fabrication may be wasted if the bad component is formedearly on. Rework might be possible but few procedures for this have been devel-oped or reported in the literature. This same problem was identified and solved for active integration, enabling tens of millions of components to be formed on siliconwith IC yields routinely over 75%. The same issue impacts tolerance; discrete pas-

sives may be presorted by value, whereas the values for planar integrated passiveswill be ruled by sizing tolerances associated with film patterning or printing. In thecase of integrated capacitors, because they are area-ruled, the resulting variation invalue will be higher than the variation in one-dimensional sizing. Attempting tomake smaller integrated passives will result in less exact values. Trimming technol-ogy for integrated passives requires further development. The use of singulated andembedded passives might help alleviate these problems by enabling sorting for yield and tolerance.

Meanwhile, surface-mount technology continues to improve. On the average,

surface-mount passives have decreased by about one case size every four years [1].Sizes as small as 0201 (0.50 × 0.25 mm) are in use and, although it is hard to imag-ine them becoming much smaller, there is work in progress for 01005 components.With a 10 mil keep-away distance, the theoretical density for 0402s is 107 compo-nents/cm2 and for 0201s it’s 270/cm2. However, in some instances, integrated pas-sives may be the only way to make the product possible. This situation is rapidlyapproaching in the case of decoupling upcoming generations of microprocessorsthat will draw very high bursts of current from the board’s power and ground

planes. Surface-mount capacitors may exhibit too much inductance to do the job

and integrated capacitors may be the only way to enable these chips to function.

1.7.1 Cost Modeling

The greater the detail necessary to accurately model a system, the less general andmore application-specific are the results [2, 15]. This is the situation with integrated

passives on organic boards. Because the specific processes and materials have notyet been reduced to a manageable number, it is not currently possible to say when

passive integration is and is not economically feasible. No generalized models exist

to aid the manufacturer. This sounds like a chicken-and-egg problem, but it can besolved by first assuming a specific and feasible material and process set for the ex-isting manufacturing infrastructure and for the potential product, and then perform-ing the costing based on that [16–19].

What is the impact of passive integration on an existing board design that utilizessurface mounts? Of primary importance is that the number of layers will probably

22 INTRODUCTION



increase due to the need to accommodate subsurface passives. Also, if reduced board form factor is desired, this will also add pressure to increase the number of layers simply to accommodate the interconnects. PWB cost increases about linearly

with the number of layers. Adding another signal layer to a controlled-impedance board actually requires the addition of two layers since a ground or power layer hasto be added as well between the signal planes [20]. The decrease in board area willresult in a more compact product, but the benefit of this is harder to put into termsof dollars than is the cost. It does have the advantage of increasing throughput sincethere can be more boards per panel, but board yield will probably decrease, for rea-sons discussed earlier in this section. There may be some decrease in wiring and,

particularly, via density due to the reduced need to route to specific areas on the sur-face to accommodate surface-mount units. Instead, it may be possible to put the

passive in any given layer and position where they are needed. Overall, each designneeds to be considered on a case-by-case basis, at least until a lot more experiencewith these designs has been accumulated.

1.8 APPLICATIONS FOR INTEGRATED PASSIVES

In principle, integrated passives can replace discretes in any application, but in whatforms will they find widespread use? Except for decoupling, the circuit schematic

will not generally change if integrated passives are used instead of discretes, exceptthat slightly fewer integrated passives may be used if exact component values can be made in one unit instead of having to string discretes together in series or paral-lel to achieve a specific value. Therefore, replacement of resistors and most capaci-tors will be one-to-one. This section will discuss some of the most likely initial ap-

plications and describe what factors will motivate the switch from surface mount tointegration.

1.8.1 Replacing Surface Mount Discretes with Arrays and Networks

Individual surface mount discrete passives can be replaced with a smaller number of passive arrays or networks, resulting in significant conversion cost savings with aminimum of design and process changes. Arrays will have the same number of totalcontacts but are achieved with fewer component placements. Passive networks con-tain internal connections that result in fewer mounted components and contacts. Notonly are there fewer components to mount, but each one is bigger than the individ-ual units it replaces, and therefore easier to handle, with a smaller total footprint onthe board than the group it replaces. Since this brings almost all of the advantages of

passive integration with few of the problems, both listed above, this trend is wellunderway and represents the majority of integrated passive usage today, especiallyfor units mounted on organic boards. The reason this approach has gained rapid ac-ceptance is that it maintains the separation between passive integration issues andsubstrate issues. The only concession for the board is that pads be moved to accom-modate the layout of the integrated surface-mount units. The board maker does not

1.8 APPLICATIONS FOR INTEGRATED PASSIVES 23



have to be in the passive manufacturing business and the integrated units can be presorted and tested to avoid yield and tolerance problems.

Numerous configurations of R + C networks are available in quantity from rep-

utable vendors and custom arrangements are possible. Integrated inductors are alsoavailable. Off-the-shelf versions include filters, terminators, and low-inductancedecouplers. With diodes and transistors added to silicon substrates, networks caninclude ESD protection, oscillators, and amplifiers. RC termination is a popular ap-

plication for passive networks since densely packed groups of resistors and capaci-tors are required to terminate wide bus lines. Integrated RC termination networkscan be formed in single packages with footprints to match the physical bus width onthe board and will require only half the number of pads since there are internal R–Cconnections within the unit.

There is much more to be squeezed out of this approach as the passive networks become merged with active devices to form what NEMI refers to as “functionalmodules,” which could include, for instance, Bluetooth or GPS subsystems mount-ed as surface units on the primary interconnect board. There is tremendous potentialflexibility with little downside. For example, a cell phone maker could include aGPS receiver in the form of a surface-mount module that would include integrated

passives, integrated antennas, as well as integrated transistors on one piece of sili-con in a single chip-scale package. They would not have to worry about going intothe business of manufacturing GPS systems and could also upgrade or switch ven-

dors when required, possibly with the same surface-pad layout. At this point, thedistinction between which is the primary interconnect substrate and which is theadd-on module becomes blurred. In the limit, the main board may have no passivesat all and simply provide interconnection among various functional modules.

1.8.2 Decoupling

High-frequency operation of digital logic circuitry places severe demands on power distribution systems to supply stable, noise-free power during the clock-driven si-

multaneous switching of millions of transistor gates. Decoupling capacitors are nec-essary to supply these large current surges, ramping as fast as 500 A/ns, to high- power microprocessor and logic ICs during the switching portions of the clock cycles. The purpose of this is to ensure that unacceptable drops in logic voltage lev-els do not occur due to the high current demands on a power supply that may be lo-cated many inches away down narrow conductor paths. Between cycles of currentdemand, the power distribution system recharges these capacitors in preparation for the next switching cycle. It is not too simplistic to think of the capacitors as actually

providing the power to run the chips with the power supply merely acting as a bat-

tery charger during low-demand periods. In other words, the impedance of the pow-er supply is too high to prevent voltage drop during high-demand periods, so the capacitors must provide low-impedance power to the chip.

Figure 1.13 shows a large group of surface-mount decoupling capacitors on theopposite side of an FR4 board from a PowerPC microprocessor. The two main re-quirements for these capacitors are that they provide sufficient charge to run the

24 INTRODUCTION



chip for one clock cycle and that they provide that power at low impedance to pre-vent excessive voltage drop during moments of high current draw by the chip. Of

these two criteria, the low-impedance issue is the more challenging to surface-mount capacitors. The inherent parasitic inductance of surface mounts requires thatmany separate capacitors be arranged in parallel in order to lower the overall induc-tance, resulting in a large number of small capacitors instead of a few large-valuedunits. That means using more board area near the microprocessor, where space is ata premium anyway, and more solder joints. Also, the temperature extremes arehigher near the chip, which can cause a variety of reliability problems, includingfailure of those solder joints.

The much lower parasitic inductance of integrated capacitors, the ability to bury

them beneath the surface of the board, and the lack of solder joints makes them veryattractive for replacing surface-mount capacitors in decoupling. It is an importantenough application to warrant an entire chapter in this book. Because of their inher-ently low inductance, there is no need to use multiple capacitors in parallel; a singlelarge integrated capacitor will suffice. The inductance is so low that, when using in-tegrated capacitors, the designer must consider the inductance of the vias and inter-

1.8 APPLICATIONS FOR INTEGRATED PASSIVES 25

Figure 1.13 Surface-mount decoupling capacitors competing with escape conductors onthe opposite side of the board from a microprocessor.



connects from the power/ground planes to the capacitor, whereas these contribu-tions are usually negligible compared to the inductance of surface-mount capaci-tors. The major unknown in replacing surface-mount decoupling capacitors is how

much capacitance is needed. With surface mounting, an excess of capacitance isusually present because of all the units placed in parallel to lower the total induc-tance, but with integrated capacitors, probably much less will suffice. Exactly howmuch less is not fully understood and can only be determined with a combination of modeling and power/ground voltage measurements with a variety of integrated ca-

pacitor values.

1.8.3 DC/DC Conversion

One application of integrated capacitors, either on a substrate or on the ICs them-selves, is as charge storage elements in DC-to-DC converters. An example made bythe University of Arkansas for NASA’s Jet Propulsion Laboratory is shown in Fig-ure 1.14. For example, charging capacitors in series and discharging them in paral-lel achieves a step-down function. If the switching frequency is high enough, rela-

26 INTRODUCTION

Figure 1.14 Integrated capacitors over the passivation layer of an integrated circuit chip toform a DC/DC converter [21].



tively small capacitors can be used for small (~1 W) converters. Localized power conversion of this type becomes more and more important as IC supply voltages de-crease and large currents must be supplied.

1.8.4 Passive Replacement in FR4

Developing passive integration for commodity FR4 will open up a huge market.Because it is such a large target, there is a concerted effort to solve the problems as-sociated with integration onto this platform. In October 1998, NIST funded the Ad-vanced Embedded Passives Technology Consortium (AEPT) to develop the materi-als, design, and processing technology for embedding passive devices into circuit

board substrates. This combination of industrial partners and associations are tack-

ling the parallel issues of processing, materials, design software, cost modeling,standardization, testing, and reliability for FR4. They made this task manageable byselecting a small number of integration technologies (materials and processes) and

building the modeling, reliability, and costing efforts around those. As their resultsand products come onto the market over the next few years, many of the obstacleswill be solved or made manageable, enabling integration to penetrate this market.

1.8.5 Passive Replacement in HDI

The various forms of HDI interconnect will employ processing steps not commonin the FR4 domain, such as sputtering, build-up, spin-on, dry etching, and more. Awider spectrum of metals and dielectrics will also be used. This provides the oppor-tunity to employ a variety of possible integrated passive processes and materialsinto this maturing technology. If these are all developed in parallel, integrated pas-sives will arrive as part of the infrastructure instead of as add-ons.

1.9 THE PAST AND FUTURE OF INTEGRATED PASSIVES

Integrated RC networks on ceramic substrates consisting of barium titanate overlaid by a resistive conductor date back as far as the late 1940s. The first volume applica-tion was in the IBM 360, which utilized integrated resistors and RC terminators,also on ceramic substrates [22]. From there, development of integrated passives inceramic substrates grew along with advances in interconnect technology to the pre-sent day. One of the most important pioneers was Robert Berry of Bell Labs, whodescribed in the February 1963 issue of the Bell Laboratories Record the idea of us-ing Ta simultaneously as the basis of the interconnect metal, resistors, and capacitor

dielectrics of a single system [23]. He recognized the unique combination of physi-cal, chemical, and electrical properties of Ta for integrated passives, such as itschemical stability, ability to be anodized into an excellent capacitor dielectric, andsuitability as an integrated resistor when combined with nitrogen, and noted thatTa-based resistors could be trimmed to close tolerances through anodization. He re-

ported on prototypes of modem boards containing 10 resistors from 65 to 5000

1.9 THE PAST AND FUTURE OF INTEGRATED PASSIVES 27



and two capacitors of 20 nF each, and clock boards with 88 resistors and 14 capaci-tors using this technology. His 34-year-old book on thin-film processing is excel-lent reading even today [24]. Few articles on integrated passives outside of ceramic

substrates appear before the mid 1990s.Of the over one trillion passive devices mounted on organic boards in 2003, less

than 3% will be surface-mounted passive arrays and passive networks, and almostnone will be fully integrated into the primary interconnect substrate. Although theshare of passive integration is increasing and will continue to grow, the technologyis too new to project trends accurately very far into the future. However, the factorsinfluencing the rate of growth are easily identified and are mainly technical in na-ture. The broad application of integrated passives will be possible only when thereare established materials and fabrication methodology for all three components. For

inductors, this is not an issue. For resistors, several technologies are available for components under about 10 k and are under development for higher values. Butcapacitors have a long way to go, principally because of the difficulty in finding di-electric materials that are easy to process on organic substrates and provide suffi-cient specific capacitance to make the component footprints small enough for eco-nomical layout without excessive numbers of layers. (See Table 1.5.)

28 INTRODUCTION

Table 1.5 Issues and status of integrated components

Design Issues Fabrication Issues Current Status

Resistors Easy if /square Several thin-film and PTF Small amount of marketis known materials available penetration, increasing

for FR4 and flex steadilyLong-established on PTF promising and

ceramic substrates inexpensive, but reliability problems remain

Higher values needed forthin film processes

Capacitors Easy if nF/cm2 Lack of established Little usage at this time onis known materials and fabrication organics due to fabrication

procedure limits usage issueson organic boards Unfilled and filled polymer

Long-established on can only replace lowceramic substrates values due to low specific

capacitance

Inductors Difficult Very Easy In useRequires solution Requires no new

of magnetic technology tofield in an implementenvironmentof interferingconductors



The vital first step is to decide on a materials and processing technology for agiven substrate. After that is done, detailed design and cost modeling can be accom-

plished, enabling a determination of when passive integration is worthwhile for a

given product. This was accomplished decades ago for ceramic substrates, but theymay have reached their limit in terms of values and tolerance. Also, ceramics makeup only a very small fraction of total board sales. For organic substrates, the largenumber of potential materials and processes have yet to be reduced to a manageablelist of realistic candidates. This is farther along for FR4 than for other organic

boards, and significant market penetration is expected in coming years.As integrated passives begin to work their way into accepted practice, there will

initially be minimal changes to existing board materials and procedures. Integrated passives will be perceived as something added to the kinds of circuit boards that

have been manufactured for many years. As they gain acceptance, hopefully byshowing their worth in terms of performance, form factor, and the associated finan-cial benefits, board fabrication and materials will be altered to enable more latitudein integrated passive implementation in order to further take advantage of their unique characteristics. Probably the best way to foresee what these concessionsmay be is to gain a thorough understanding of the technologies required for passiveintegration and see how these fit in with current interconnect substrate practices.With the advent of new substrate materials, such as various flex films, and the de-velopment of high-density interconnect line and via sizes, there is an opportunity to

dovetail with other process modifications such as passive integration.

1.10 ORGANIZATION OF THIS BOOK

The purpose of this introductory chapter has been to describe some of the advan-tages and challenges of integrated passives in one place. Various researchers haveidentified almost all the important issues of design, fabrication, and utilization over the past few years, so the challenges are clear. The rest of this book will concentrate

on addressing these issues individually and in depth in order to assist in their solu-tion, leading to more widespread use of integrated passive components.When attempting to describe a developing technology area in electronics, there

is a fundamental decision to be made between basing the writing on materials or on processes. The authors have organized around materials and placed the candidate processes in context around them. This is a less limiting approach in case new processes become available to create the materials described. There are probablyfewer unknown materials to be discovered than processes.

For the individual passive components—resistors, capacitors, and inductors—

the treatment will start with a description of how the various performance parame-ters of the components are quantified, such as value (ohms, farads, henrys) and theeffects of various operating parameters on value (temperature, frequency, voltage,etc.). The purpose of doing so is to provide a language for discussing the relation-ships among materials, integrated passive configuration, and resulting electrical

performance. This is followed by component-level design rules that relate the

1.10 ORGANIZATION OF THIS BOOK 29



shape, size, and footprint of integrated passives to these performance parameters.Then, for resistors and capacitors, there is a brief theoretical treatment of the resis-tance and dielectric properties of films that are pertinent to integrated passives. Af-

ter that, the candidate materials are listed with a discussion of the composition andmorphology effects on component performance and the processing options for making integrated passives from them.

Chapters are provided on two important topics relating to integrated capacitors:yield issues and electrical performance. Because integrated capacitors will be large-area film structures, they are particularly susceptible to defects that can result in theloss of the entire board, so a detailed treatment of these problems is appropriate. In-tegrated capacitors enjoy a considerable inductance advantage over surface-mountdiscretes to the point that it can be difficult to actually measure quantitatively. This

is followed by chapters on electrical measurement techniques and models, a surveyof current integrated passive applications, and a cost analysis.

REFERENCES

1. National Electronic Manufacturing Initiative Roadmap, 2000 edition, Chapter 22, “Pas-sive Components,” p. 1, 2000.

2. J. Rector, “Economic and Technical Viability of Integral Passives,” In Proceedings of

the 48th Electronics Components and Technology Conference, Seattle, WA, p. 218, May1998.

3. Passive Component Industry Magazine, p. 8, May/June 2001.

4. R. Ladew and A. Makl, “Integrating Passive Components,” In ISHM ‘95 Proceedings, p.59, 1995.

5. J. Rector et al., “Integrated and Integral Passive Components: A Technology Roadmap,”In Proceedings of the 47th ECTC Conference, p. 713, 1997.

6. M. Leftwich, Between the Layers—A Case Study of PWB Design Options from Current

Surface Mount Component Technology to Embedded and Integral Component Technolo-

gies. Master’s thesis, University of Arkansas, p. 9, 2001.

7. D. Liu et al., “Integrated Thin Film Capacitor Arrays,” In Proceedings of the Interna-

tional Conference and Exhibition on High Density Packaging and MCMs, IMAPS, p.431, 1999.

8. J. Dougherty et al., “The NEMI Roadmap Perspective on Integrated Passives,” Ad-vanced Embedded Passives Technology Website: aept.ncms.org/papers.htm, 2001.

9. H. Kapadia et al., “Evaluating the Need for Integrated Passive Substrates,” Advancing

Microelectronics, 26, 1, 12, Jan/Feb 1999.

10. C. Coombs (ed.), Printed Circuits Handbook, 5th ed., McGraw-Hill, p. 1.17, 2001.

11. W. Brown (ed.), Advanced Electronic Packaging, IEEE Press, 1999.

12. M. Nielsen et al., “Demonstration of Integral Passives on Double Sided Polyimide Flex,”In Proceedings of the 2000 International Conference on High-Density Interconnect and

Systems Packaging, p. 351, 2000.

13. M. Thakre, Integral Planar Inductors. MS thesis, Dept. of Chemical Engineering, Uni-versity of Arkansas, December 2000.

30 INTRODUCTION



14. D. McGregor, “Standard Development Efforts for Embedded Passive Materials,” Ad-vanced Embedded Passives Technology Website: aept.ncms.org/papers.htm, 2001.

15. P. Sandborn, B. Etienne, and D. Becker, “Analysis of the Cost of Embedded Passives in

Printed Circuit Boards,” Advanced Embedded Passives Technology Website:aept.ncms.org/papers.htm, 2001.

16. B. Etienne and P. Sandborn, “Application-Specific Economic Analysis of Integral Pas-sives,” In Proceeding of the IMAPS Advanced Packaging Materials Processes, Proper-

ties and Interfaces Symposium, Braselton, GA, pp. 399–404, March 2001.

17. M. Realff and C. Power, “Technical Cost Modeling for Decisions in Integrated vs. Sur-face Mount Passives,” In Proceedings of IMAPS 3rd Advanced Technology Workshop

on Integrated Passives Technology, Denver, CO, April 1998.

18. D. Brown, “The Economics of Integrated Passive Component Technologies—An Ongo-ing Exploration of a Life Cycle Cost Analysis,” Advancing Microelectronics, 25, 3, 55,1998.

19. M. Scheffler et al., “Assessing the Cost-Effectiveness of Integral Passives,” Microelec-

tronics International, 17, 3, 11, 2000.

20. C. Coombs (ed.), Printed Circuits Handbook, 5th ed., McGraw-Hill, New York, p. 1.21,2001.

21. M. Wasef, Fabrication of Anodized Tantalum Oxide Integrated Capacitors on Singulat-

ed Chips with Active Devices. Ph.D. dissertation, Dept of Chemical Engineering, Univer-sity of Arkansas, May 2001.

22. R. Cote, “Back to the Future—Integrated Passive Devices,” Advancing Microelectron-

ics, p. 20, Jan/Feb 1999.23. R. Berry, “Tantalum Thin-Film Circuitry and Components,” Bell Laboratories Record,

Feb. 1963.

24. R. Berry, P. Hall and M. Harris, Thin Film Technology, Van Nostrand, New York, 1968.

Additional References

The following are overview articles on integrated passives.

S. Bhattacharya and R. Tummala, “Next Generation Integral Passives: Materials, Processesand Integration of Resistors and Capacitors on PWB Substrates,” Journal of Materials

Science: Materials in Electronics, 11, 253, 2000.

R. Frye, “Integrated Passive Components: Technologies, Materials and Design,” Internation-

al Journal of Microcircuits and Electronic Packaging, 20, 4, 578, 1997.

R. Frye, “Passive Components in Electronic Applications: Requirements and Prospects for Integration,” International Journal of Microcircuits and Electronic Packaging, 19, 4,483, 1996.

E. Logan et al., “Advanced Packaging of Integrated Passive Devices for RF Applications,” In

Proceedings RAWCON ‘98, 1998 IEEE Radio and Wireless Conference, IEEE, p. 289,1998.

K. Paik, “Studies on Thin Film Integral Passive Components for Mixed Mode MultichipModule (MCM) Applications,” In Proceedings of 1995 Japan International Electronic

Manufacturing Technology, 1995 Japan IEMT Symposium, p. 365, 1996.

C. Power, M. Realff, and S. Battacharya, “A Decision Tool for Design of Manufacturing

REFERENCES 31



Systems for Integrated Passive Substrates,” In Proceedings of IMAPS 4th Advanced

Technology Workshop on Integrated Passives Technology, Denver, CO, April 1999.

J. Rector, Jr. et al., “Future Trend Towards Integral Passives,” In 17th Capacitor and Resis-

tor Technology Symposium, CARTS ‘97, p. 1, 1997.R. Tummala et al., “SOP Microelectronics for the 21st Century with Integral Passive Integra-

tion,” Advancing Microelectronics, 27, 1, 13, 2000.

32 INTRODUCTION



33

CHAPTER 2

CHARACTERISTICS

AND PERFORMANCE

OF PLANAR RESISTORS

RICHARD K. ULRICH

The treatment of integrated resistor technology is split into two chapters. This one isa discussion of issues common to all such components including layout patterns of

planar resistors, the metrics used to describe the resistivity of materials, the effectsof temperature, time and film morphology, a brief treatment of electrical conduc-tion in resistive materials, and issues important in sizing integrated resistors, suchas heat dissipation, tolerance, and parasitic capacitance. Chapter 3 uses this generalinformation to analyze the performance characteristics that can be expected fromthe various candidate integrated resistor materials and describes the process optionsfor making them. It concludes with a listing of the commercialized technologies for integrated resistors.

2.1 PERFORMANCE PARAMETERS

2.1.1 Resistance of Planar Resistors

Integrated resistors are fabricated either by depositing and patterning a layer of re-sistive material or by printing resistive paste in series with an interconnect line onan insulating substrate. In keeping with the concept of a planar, stacked assembly,the resistor will be a film of material, probably between a few hundred angstromsand a few microns thick (Figure 2.1).

Assuming that all of the resistance is in the resistor material and not in the inter-connects, the resistance of the structure is

R = L

Wt



ISBN: 0-471-24431-7



where: R = resistance, = resistivity of the material, -cm L = length of the strip, cmW = width of the strip, cmt = thickness of the strip, cm

The resistivity of a material is an intrinsic property and is a function of composi-tion and microstructure. For thin films, the resistivity can be somewhat differentfrom that of bulk materials, and is generally higher. The reciprocal of resistivity isconductivity in (-cm) –1, sometimes referred to as “Siemens.”

Sheet resistance is defined by

R = = R s N s

where: R s = /t = sheet resistance, /square N s = L/W = the number of squares L = length of the strip, cm

The sheet resistance is the resistance of a square of material ( L = W ) when the elec-trical contacts cover opposite edges completely, as in the second part of Figure 2.2.The size of the square is irrelevant as long as length equals width and the contactscompletely cover two opposing sides. When long, narrow materials are used, the re-sistor is thought of as squares in series.

Resistors consisting of many squares are usually formed in a serpentine patternto fit into an allocated substrate area with corner squares counted as somewhatless than a full square (0.556 squares) since the current does not have to traversethe entire side-to-opposite-side distance. Thus, a material with a resistivity of 1m-cm that is 1 µm thick would have a sheet resistance of 10 /square and this

L

W

t

34 CHARACTERISTICS AND PERFORMANCE OF PLANAR RESISTORS

Figure 2.1 Layout for a simple integrated resistor.



number, multiplied by the number of squares, would give the value of the resistor in ohms. The benefit of expressing films of resistor materials in /square is that itdoesn’t matter what the resistivity or the thickness is as long as it gives the desiredsheet resistance. For example, in sputtering TaNx resistors, the sputtering condi-tions such as vacuum level, temperature, power, gas composition, etc. may be var-ied to affect both the material’s film thickness and resistivity. It may be impossi-

ble to change conditions so that only resistivity or film thickness is adjusted todesired values due to the inevitable cross-dependencies of processing conditions.However, if the sheet resistance is the target variable, processing conditions can

be optimized to give the desired value of /square without having to measure or specify both the thickness and resistivity. Also, the sheet resistance is a quantityeasily measured with standard four-point probes or from simple test structuressuch as those in Figure 2.3, again without having to measure either of its two con-stituent variables.

2.1.2 Resistivity of Materials

Required resistor values in common electronic systems span a large range: fromless than 10 to well over 1 M. It’s practical to build a serpentine integrated re-sistor with between about 0.1 and perhaps a hundred squares; resistor patterns withmore squares may require excessive footprints, are more prone to yield and toler-ance problems, and tend to show greater parasitic capacitance at high frequencies

2.1 PERFORMANCE PARAMETERS 35

Figure 2.2 Resistor geometries expressed as numbers of squares.



due to coupling between the meandering strips. Taking these as the boundaries of the design envelope, a 10 resistor fabricated from 0.1 squares would require amaterial with 100 /square, whereas a 1 M resistor with 100 squares would re-quire 10,000 /square. It would be possible to cover this range with integrated re-sistors if they could be made with two different materials:

1. Resistor material with about 100 /square for values from 10–10,000 2. Resistor material with about 10,000 /square for values from 10,000–1 M

If these two materials are utilized, then resistances from 10 to 1 M can be cov-ered with 0.1 to 100 squares. For resistances outside of this range, integrated resis-tors may not make sense. In fact, depending on the application and the number of extreme-value resistors required, it may only make sense to use one material, and touse SMT discretes for the rest. It should also be noted that it’s possible to makevery-low-valued resistors from the interconnect metallization. For example, 2 mi-

crons of Cu gives about 10 m/square, so 100 squares would give only 1 . Sub-ohm values are often used for current sensing.

It is presumed that the integrated resistors will be in the form of thick or thinfilms since it is desired to embed them between layers of substrate insulating lay-ers. To achieve 100 and 10,000 /square with 1 micron films would require 0.01and 1.0 -cm materials, whereas with 100 Å films, would require 10 –4 and 10 –2

-cm. It then seems that, for integrated resistors, the range of interest in resistiv-ity is between about 10 –4 and 1 -cm. Figure 2.4 shows various materialsarranged according to their resistivities along with this approximate range of in-

terest for integrated resistors. This provides a first cut of the possible materials for integrated resistors.

Although many materials fall into this range of acceptable values, some of themare difficult to deposit or etch, or have resistivities that are insufficiently stable withrespect to temperature or time to be utilized in a practical manner.


Figure 2.3 Serpentine thin film sputtered CrSi resistor test structures on flex.



2.1.3 Temperature Effects

The temperature coefficient of resistivity (TCR) is defined as the temperature deriv-ative of dimensionless resistivity and is usually expressed in ppm/°C:

TCR = =

For resistor materials instead of the resistors themselves, the values of R may be replaced by the material’s resistivity in-cm [1]. For most applications, the ideal val-ues of TCR would be zero so that the value of the resistor is constant under any op-erating temperature. As a general guideline, the percent variation in resistance over the standard military operating range of –55 to +125°C is the TCR in ppm/°C times

0.018, assuming that the TCR is constant. Therefore, if a resistor has a TCR of 100 ppm/°C, it will increase by 1.8% over this range or, with a TCR of –300 ppm/°C, itwould decrease by 5.4%. In some applications, such as thermistors used to measuretemperature, the TCR is made purposefully large and reproducible. Also, in RC net-works where the capacitors have a slightly positive temperature coefficient of ca-

RT 2 – RT 1

T 2 – T 1

1

RT 1

R

T

1

R


Figure 2.4 Electrical resistivities of various materials.



pacitance (TCC), a correspondingly negative TCR is sometimes used to maintain aconstant RC time constant. For example, the coefficient for a Ta2O5 capacitor isabout +200 ppm/°C, so the coefficient for TaNx resistors can be set to –200 ppm/°C

by optimization of the sputtering conditions. Some materials, such as pure metals,cannot be made to have a negative TCR and could not be used as a temperature-compensating resistor against a capacitor with a positive TCC.

The voltage coefficient of resistance (VCR) is similarly defined:

VCR = =

V 2 = 50 V and V 1 = 5 V are commonly used [2]. Significant levels of VCR are only

observed when the voltage drop over the resistor is large, and even then it is usuallyless than about 5 ppm/volt.The noise index is a measure of the voltage fluctuations over a resistor that is be-

ing driven by a purely DC voltage and is expressed in dB:

Noise Index = 20 log where the noise voltage is measured in microvolts. By this measure, an rms noise of

1 µV at 1 V DC would give 0 dB of noise. Noise indices under –30 db are typical.Smoother substrates and resistor materials result in less noise.

2.1.4 Value Stability

The stability of a resistor refers to how its resistance changes with time under con-ditions of temperature, humidity, current, etc. These changes may be due to recrys-tallization, hydration, oxidation, and other chemical alterations of the resistor mate-rial as well as effects at the conductor–resistor interface. The value can drift up or down, depending on the mechanisms involved. For instance, it would increase withtime if a metal alloy resistor were oxidized, even just on the surface, due to contactwith humidity and temperature, or it might drop if high operating temperaturescaused recrystallization of the metal lattice resulting in a more regular structure.Figure 2.5 shows the upward value drift with temperature for plated NiP resistorsintended for use in FR4. TaNx is a popular material for resistors in part because thehigh melting point of Ta (2996°C) implies that the TaNx microstructure will bemore resistant to crystal change at slightly elevated temperatures than metal com-

pound resistors made from metals that melt at lower temperatures. Metals with highmelting points and low reactivities, especially to oxidation, are preferred compo-

nents for integrated resistors. Oxidation of interconnect/resistor interfaces would re-sult in increased values, which is a major concern with the use of carbon-filled

polymer thick-film resistors that make contact with Cu or Al metallization.Although the tendencies of the various resistor materials to be chemically

changed with time, temperature, and humidity can be ranked, it is not possible to

V 2no ise

V DC

RV 2 – RV 1

V 2 – V 1

1

RV 1

R

V

1

R




use that information to predict quantitatively how the value will change for a re-

sistor that has been integrated, due to the influences of the resistor’s resulting ther-mal and packaging environment. This is much easier for discrete resistors that are

packaged in the same type of enclosure every time. Since it is also not usually practical to wait for years to evaluate their behavior in field usage conditions,standard accelerated testing procedures may be used to give some indication of theamount of drift expected. Typical accelerated tests for integrated resistors shouldinclude the same ones used for reliability testing, such as 1000 hrs at 150°C and1000 hrs of 85°C + 85% relative humidity. The acceleration factors, the ratio of corresponding field usage time to accelerated testing time, are notoriously hard to

quantify, but it is agreed that they are exponential in temperature in accordancewith the Arrhenius rate expression. The acceptable amount of value drift fromthese tests depends on the tolerance required by the application. Heat treatmentscan accelerate this aging process and provide much better subsequent stability.Resistor values are sometimes purposely set below the desired values at manufac-ture and then raised to a more stable value through a short temperature treatment;5 hours at 250°C is typical [3]. This treatment might be on the high end of whatsome organic boards could withstand. There are no reports found in the literatureof rapid thermal aging using halogen lamps or lasers, but this should be investi-

gated due to possible advantages of low thermal stress on the parts and highthroughput. Various passivation schemes are often used with discrete resistorssuch as overcoats of SiO2, SiN, or polymer, and these should be effective on inte-grated resistors as well. Some materials, such as TaNx, may be surface oxidizedon purpose to prevent further changes. Integrated resistors may not require a pas-


Figure 2.5 Resistor drift with time and temperature for Ohmega-Ply®-plated NiP on FR4.



sivation layer if they are buried deep enough in the substrate so that the board it-self provides protection.

Other factors such as film stress and adhesion are important to yield and stabili-

ty, particularly for thin-film resistors. If the resistive material is much thinner thanthe interconnect material, the resistor must go down onto the substrate first to avoidhaving to step over a large ledge with a thin material. Resistor thicknesses of under 1000 Å are typical, in comparison with 20,000 Å of sputtered conductor or evenmore for plated metals. This usually means that the conductor metal will have to beetched after the resistor material is patterned and, as a result, the thin film of resistor material must be unaffected by the metal etch to maintain tolerance. Tensile stress-es can lead to resistor cracking, especially if a thin, low-CTE resistor material suchas a metal alloy (CrSi, TaNx) is deposited on a thick, high-CTE substrate such as a

polymer and exposed to elevated operating temperatures.

2.2 RESISTANCE IN ELECTRONIC MATERIALS

2.2.1 Resistivity and Charge Carriers

This section will present a brief explanation of conduction theory in order to helpthe reader qualitatively understand the effects of composition, microstructure, and

temperature on the integrated resistor’s behavior. This is a rich and well-developedarea of materials science, and there should be no trouble finding deeper treatmentsin both the cited literature and in a variety of books on electronic materials scienceof whatever specific topics are of interest [4].

The conductivity of a material is the sum of the conductivities of all mobilecharge carriers:

= = (1.60 × 10 –19) (| z i|C ii)

where: = conductivity, 1/-cm = resistivity of the material, -cm z i = absolute value of the charge on charge carrier i

C i = concentration of charge carrier i, charges/cm3

i = mobility of charge carrier i, (cm/sec)/(volt/cm)

Except for optical transparency, there may be no intrinsic material property that

varies over such a wide range as electrical resistivity. Not even counting supercon-ductors, the span between silver, aluminum, copper, and gold at around 10 –6 -cmand fluorocarbon polymers, silicon nitride and NaCl at around 10 –18 -cm is 24 or-ders of magnitude, as shown in Figure 2.4. In resistive materials, the charge carriersare typically electrons, metal cations, and nonmetal anions, in order of decreasingmobility. Free electron mobilities are many orders of magnitude higher than the dif-

1




fusive hopping mobilities of the much larger and more massive cations and anions.As a result, even a small concentration of electrons will dominate the conductionmechanism; electrons are the only charge carriers that must be considered when at-

tempting to explain the resistive behavior of the material. At one extreme of thistrend are metals and their alloys, in which each atom in the material contributes atleast one, and maybe as many as five, electrons to the conduction band, resulting inthe lowest resistivities of any room temperature solid. In the middle, an ionic oxidesuch as TiO2 has a potential charge carrier in every Ti+4 and every O –2, but the vastmajority of conduction comes from a much smaller concentration of free electrons,maybe only one per millions of TiO2 molecules. Since TiO2 has a much lower freeelectron concentration than metals, its resistivity is much higher. At the other endare the purely ionically conducting solids, such as NaCl, which have almost no free

electrons and utilize only Na+

and Cl –

ions as charge carriers. These are some of themost resistive materials known. Materials that rely exclusively on ionic conductionare far too resistive to be used as integrated resistors, so electrons are the onlycharge carriers that need be considered when evaluating candidate materials. At theother extreme, all pure metals and almost all metal alloys are too conductive to beused as integrated resistors. It should be noted that the conductivity of oxides variesover almost the entire span in Figure 2.4, from tens of m-cm for cadmium oxideto over 1015 -cm for aluminum oxide, whereas polymers, pure semiconductorsand metals cover a much smaller range. This is due to the wide range of electron

concentrations for the various oxide materials.Simple conduction by free electrons moving under the influence of an electricfield requires no further explanation, but there are a couple of variations on this thatare more complex but germane to integrated resistors.

2.2.2 Semiconducting Oxides

When free electrons are present, the fraction of current carried by ions is usuallynegligible by comparison—less than about 1/1000 for NiO and CuO. These types of

conductors fall into two categories: metal-excess semiconductors and metal-defi-cient semiconductors. As an example, consider the metal-excess semiconductor ZnO shown in Figure 2.6. Stoichiometric ZnO would achieve charge balance byhaving exactly one Zn+2 for every O –2 but if there is an excess of Zn+2, there willhave to be free electrons to balance the extra cations.

This material would be considerably more conductive than stoichiometric ZnO,with electrons carrying almost all the current. Other examples of this type areTa2O5, TiO2, WO3, and SnO2. The addition of small amounts of cations with other valances can produce large changes in the resistivity of these kinds of materials. For

instance, the addition of 1 mole percent of Al2O3 to the ZnO example shown abovewill increase its conductivity considerably, whereas addition of Li2O will lower it.The reason lies in the semiconducting nature of the compounds and follows thesame logic as doping for semiconductors. If Li2O is added to ZnO, Li+, which has alower positive charge than Zn+2, will replace a Zn ion somewhere but will requireone less electron for charge balance (Figure 2.7).

2.2 RESISTANCE IN ELECTRONIC MATERIALS 41



As a result, the number of free conduction electrons is decreased, moving thematerial closer to a purely ionic conductor with higher resistivity. Adding elementsof higher valances, such as Al+3, works in the opposite manner, requiring extra freeelectrons for charge balance, thus decreasing the resistivity. The same principlescan be extended to metal-deficient semiconducting oxides, such as NiO, Cu2O, andAg2O, except that the dopant ions work in the opposite direction. For these materi-als, adding ions with lower valances, such as Li2O, would decrease the resistivity,whereas Al+3 would increase the resistivity [5]. Since these are almost completely

extrinsic semiconductors (all charge carriers are due to doping), the conductivity isnot nearly as large a function of temperature as it is in intrinsic semiconductors like

pure undoped Si.Metal-excess and metal-deficient semiconduction are sometimes referred to as

Wagner mechanisms, conduction that is predominately cationic or anionic arecalled Frenkel mechanisms, and roughly equal cationic and anionic contributionsare called Schottky mechanisms. The above explanation is a very brief summary of a broad and interesting field of physical science. One immediate application to inte-grated capacitor dielectrics would be to add small amounts of cations to thin metal-


Figure 2.6 ZnO, a metal-excess semiconductor.

Figure 2.7 The number of free electrons in ZnO is decreased by adding small amounts of Li2O.



excess or metal-deficient dielectrics in order to decrease their leakage. This appearsto have been investigated when the Lanthanide rare earth Dy+2 was added to TiO2 inorder to decrease the leakage current of this dielectric without significant change to

its dielectric constant [6].

2.2.3 Tunneling

Resistor materials known as cermets consist of metallic particles, as small as 50Å, embedded in a matrix of insulating material such as SiO2. As long as the par-ticles are separated, conduction through this type of matrix will be controlled bytunneling through the insulator between the particles. In this case, the identity of the metal has little effect on the resistivity of the material, but the percent of filler

has a major influence because it sets the insulator thickness between the particles.Very high resistivities along with low temperature dependencies can be achievedthis way.

2.2.4 Temperature, Composition, and Morphology Effects

Increased temperature decreases the mobility of electrons by creating a higher concentration of lattice vibrations (phonons) to interact with them, causing morefrequent scattering. If the number of charge carriers remains constant with tem-

perature, then the TCR will be positive for this reason. For conduction through a pure metal with a perfect lattice, resistivity is caused primarily by interactions of the electrons with lattice vibrations and, based on the Debye theory of phonon fre-quency distribution, the resistance near room temperature would be directly pro-

portional to the absolute temperature. If that were the case, then the TCR would be:

TCR for pure perfect metals = =

At room temperature, 1/T is about 3400 ppm/°C, in close agreement with the mea-sured values of 4200 for Cu, 3700 for Al, and 3900 for Au. If higher temperatureslead to increased numbers of charge carriers, then their concentration may risefaster than their mobility decreases, resulting in a negative TCR. The extreme caseof this would be undoped semiconductors which, because of the exponential depen-dency of n and p concentrations on temperature, exhibit very highly negativeTCR’s, such as –73,000 ppm/°C for Si.

Two other mechanisms can increase the resistivity of a material in ways appli-

cable to materials suitable for resistor integration. The addition of impurities andthe inclusion of defects in the lattice will both result in increased electron scatter-ing and higher resistance. Actually, both of these are similar in action since theyeach change the crystal structure from the regular ideal periodic arrangement.Adding a metal to another pure metal to produce an alloy normally results in amore resistive material than either pure component since the added metal is seen

1

T

T

1

2.2 RESISTANCE IN ELECTRONIC MATERIALS 43



as an impurity that modifies the original crystal lattice. For instance, the resistivi-ty of Ag is 1.47 -cm and Au is 2.44 -cm, but as Au is added to Ag, the re-sistivity increases smoothly to a maximum of about 11 -cm at a 50–50 atomic

mixture, then decreases smoothly back to the resistivity of pure Au. The other ef-fect, increased resistivity due to structural defects, may be brought about by mak-ing the film polycrystalline or by introducing vacancies, interstitials, and disloca-tions.

There is an important advantage to decreasing the conductivity of a material inthis way for use as a resistor. Pure metals are generally too conductive to be used asintegrated resistors but mixing them with nonmetallic elements such as N or Si in-creases their resistance by decreasing the number of free electrons and has theadded advantage of decreasing the TCR, sometimes to near zero. The reason that

this happens is that the total resistance can be considered to be a combination of dif-ferent electron scattering phenomena: thermal, compositional, and structural. If thescattering mechanism is completely thermal, as it is for pure metals with perfect lat-tices, the TCR will be very high but if the resistance is instead dominated by non-thermal mechanisms so that the vast majority of electron-scattering collisions arewith lattice defects whose concentration is not a function of temperature, this mech-anism will dominate and the resulting resistivity will be only a weak function of temperature. As a result, several metal-based compounds exist with sufficientlyhigh resistivity and low TCR to be useful in integrated resistors, including CrSi,

TaNx, and NiCr. Purposely depositing resistor films with a high concentration of crystalline defects will lead to high resistivity but at the risk of poor time stability.Large amounts of defects are thermodynamically out of equilibrium with a perfectlattice and, with time, can precipitate out to phase boundaries, resulting in loweredresistance with time. Thermal annealing steps following resistor formation can ac-celerate this process and stabilize the films against further changes during field us-age.

The mean free path of electrons in common electronic metals at room tempera-ture is about 200–400 Å and when film thicknesses approach these values, resistivi-

ties can significantly exceed bulk values due to scattering of conduction electronsoff the top and bottom film surfaces. Figure 2.8 shows the effect of both this andsurface roughness on the resistivity of various thicknesses of TiNx. Utilizing this ef-fect to increase the value of an integrated resistor can be difficult to control due tothe strong dependency of sheet resistance on thickness in this regime. To convertthe data in Figure 2.8 into sheet resistance, the resistivities needs to be divided bythe thickness, adding even more sensitivity. Very thin films, less than a few 10s of Å, can have even higher resistivities due to the lack of a continuous film structure.These films are deposited, typically sputtered or evaporated, only until the nucle-

ation islands are on the verge of agglomerating into a continuous film. TCR valuesfor these types of resistors are very low since the metal islands have a positive TCR and electron transfer between islands has a negative TCR. However, these films aredifficult to make within a few percent of the desired resistance values and also tendto be unstable, exhibiting falling values since the islands tend to conglomerate withheat and time.




2.3 SIZING INTEGRATED RESISTORS

Once a resistor material and process is selected, it is a simple matter to determinethe length/width ratio to give any required value of resistance from the ohms/squareof the material. However, to separate these two measures out of the ratio and estab-lish the actual footprint of the resistor, other factors must be considered such as:

Heat Dissipation. Integrated resistors must be designed so that the tempera-ture rise during use will not heat them to the point where their value drifts sig-nificantly or failure mechanisms are accelerated to the point of affecting their reliability. Large-area resistors are favored regardless of their number of squares.

Tolerance. Tolerance and precision improve for larger areas.

Parasitic Capacitance. Long serpentine resistors will exhibit characteristicsof capacitors at high frequencies due to coupling between adjacent strips, re-sulting in a drop in resistor impedance. Small numbers of squares and largestrip spacing are favored regardless of the total area.

Standing Waves and Internal Reflections. The resistor will act as a lumpedrather than a distributed component only if its length is shorter than about 1/5the wavelength, which can considerably simplify its modeling [8]. Small

2.3 SIZING INTEGRATED RESISTORS 45

Figure 2.8 Variation of tantalum nitride film resistivity with film thickness and surfaceroughness [7].



numbers of squares or narrow widths, either of which can result in shortlengths, are favored.

Reflections at the Resistor/Interconnect Interface. The resistor width

should match the interconnect width to decrease the effects of size disconti-nuities that would lead to reflections of high-frequency signals [8].

Heat dissipation and tolerance are usually the most important considerations, andthe resistor will be sized to be just large enough to satisfy the more critical of thetwo.

2.3.1 Thermal Issues

The following will usually be known when sizing an integrated resistor:

The required value of the resistor, R

The sheet resistance of the resistive material, R s /square

The required heat dissipated from the resistor, P = (V )2/ R = I 2 R watts

The maximum allowable heat flux from the resistor, P / A = q watts/cm2

Depending on the application, the designer will know either the current through the

resistor or the voltage drop required. In either case, these may be conveniently expressed as the power in watts to be dissipated by the component.

The maximum allowable heat flux, by convention, is expressed as the flux as if the heat were emerging from only one surface of the planar resistor. In reality, theactual distribution of heat from each of the two sides may be just about anything,depending on the proximity of each surface to the outside of the substrate and theeffects of interconnect metal and other nearby heat-producing devices. Variousrules of thumb exist for resistors on the surface of interconnect substrates; 10–30W/cm2 are typical. To put these heat fluxes into perspective, maximum sunlight is

about 0.10 W/cm2

and the surface of a 100 W light bulb is about 1 W/cm2

, so resis-tor-level fluxes can result in a considerable temperature rise. Moreover, integratedresistors will be buried beneath the surface of a substrate that consists of materialsthat are typically considered to be thermal insulators. Materials that are poor con-ductors of electricity are also poor conductors of heat for the same reason: lack of free electrons that can efficiently transport both electric current and heat. Assumingfor the moment that the maximum power dissipation from the resistor material isestablished (q W/cm2), the length and width may be separated as follows:

W = cm

L = W = N sW cm R

R s

PR s

qR




As an example, consider a 1000 resistor using TaNx with a sheet resistance of 100 /square, which will dissipate a total of 0.025 W with an upper heat flux limitof 10 W/cm2. Applying the above equations shows that the 10-square resistor

should have the minimum dimensions of 0.16 mm wide and 1.6 mm long (6.2 ×62.0 mils). These dimensions are far larger than the lower limit of thin films pho-tolithographic patterning, and achievable for thick-film by screen printing. The totalarea is slightly smaller than a surface mount 0402.

Of course, it is not the heat flux that’s important, but the temperature [9]. The preceding analysis was appropriate when the resistor was at or near the surface, en-abling the relationship between the flux and temperature to be straightforward. Thesituation of heat transfer from a solid surface to air, whether free or forced convec-tion, is simple enough and has been studied sufficiently to allow accurate predic-

tions of component temperature based on heat flux. However, the situation is far more complex for integrated resistors inside the substrate because of the variabledistance from component to surface, the complex arrangement of insulating andconductive board materials, the presence of other heat-producing integrated resis-tors nearby, and the presence of heat-producing ICs on the surface on top of them.As a result, simple rules of thumb based on the heat flux will rarely apply to inte-grated passive systems, particularly when they are densely packed in order to bemore economically viable. The same heat flux that gives an acceptable temperaturerise on the surface may seriously overheat the component if it is buried, especially if

other components are nearby, producing their own thermal fields. In systems denseenough to benefit from integrated passives, three-dimensional finite-element mod-eling of the temperature distribution will probably be necessary. Many software

packages are available for this purpose.Figure 2.9 shows a finite element simulation of the two-dimensional width

cross-sections of three integrated resistors in a flex circuit board. The board was 0.8mm thick and the three resistors were 0.3 mm wide. Each resistor dissipated 250mW, and two were placed 0.3 mm from the top surface, whereas one was placed 0.3mm from the bottom surface. Board-level cooling was provided by a 3.5 m/s air

flow initially at 20°C both above and below the surfaces of the flex board. The air had a heat capacity of 29 W/kg K and a thermal conductivity of 2 W/m K. The air was assumed to have a laminar profile that rose to the maximum velocity through adistance of 1.5 mm. The figure was generated by solving and coupling the

Navier–Stokes equations to heat transfer in FEMLAB®; it shows the isotherms andthe temperature profile through the circuit board.

Even without a proper, detailed thermal analysis, some general trends can benoted. To give some idea of the amount of thermal resistance of common substratematerials, consider the 10 W/cm2 heat flux from the above example. Using thermal

conductivity values from Table 2.1, the temperature drop required to push this heatflux through only 1 mil of the various materials would be 8.4°C for typical FR4,13°C for BCB, and 17°C for polyimide.

Metal thermal conductivities are typically about 1000 times higher than those of polymeric board materials. Metal interconnects and, especially, power and ground planes will tend to spread heat more strongly in the lateral direction rather than in





Figure 2.9 Thermal profile through a circuit board containing integrated resistors.

Table 2.1 Thermal conductivities of various materials

Thermal ConductivityMaterial (W/cm K)

Air 0.0003Polyimide (Kapton) 0.0015Silicone 0.0016BCB 0.0020Teflon 0.0025FR4 0.002–0.004Epoxy, unfilled 0.001–0.002Epoxy, silver-filled 0.020Al2O3 0.20–0.35Si 0.84Al 2.37Cu 3.98



the z axis, since there is much more continuous metal laterally than vertically. Withhigh interconnect density and/or continuous planes, the metal layers may dominatethe lateral heat transport to the point where the composition and thickness of the in-

sulating layers is of little consequence to the lateral temperature distribution. Theinterconnects to the resistor can also carry away a significant amount of heat fromthe ends of the component. The effect will be to even out the thermal flux at the sur-face of the board, but there can still be high temperature gradients in the vicinity of the integrated resistor since it is surrounded by insulator. Figure 2.10 shows thetemperature rise of an Ohmega-Ply® resistor on one side of a circuit board with andwithout Cu cladding on the other, illustrating the large influence of heat spreading

by the Cu plane.

2.3.2 Parasitic Capacitance between Meanders

Adjacent segments of a serpentine integrated resistor can capacitivly couple, result-ing in a drop in component impedance at high frequencies. The effect is like havinga small capacitor in parallel with the resistor. Figure 2.11 shows the measured im-

pedance of five CrSi integrated resistors with various numbers of meandering seg-ments using line widths and spacings of about 5 mils [10]. The impedances of thelarger resistors drop at high frequencies because of the larger number of nearby seg-ments in the serpentine structure. The resistance of the component does not affect

the amount of capacitive coupling, but it does influence the frequency at which it begins to show up on the component’s impedance. Straight resistors show muchless capacitance, but it can be important at very high frequencies [11].


Figure 2.10 Temperature rise for 250 integrated resistors with and without Cu cladding.



The frequency in Hz at which capacitive effects begin to cause a decrease in

overall impedance is

f =

where C is the capacitive coupling between segments in F.Values of 0.084 pF/mm for 4 mil lines separated by 4 mil spaces were measured

in the author’s laboratory. Figure 2.12 shows that the number of capacitors is equalto one less than the number of segments ( N ), in this case there are six segments and

five capacitors.

1

2 RC


Figure 2.11 Measured impedance of CrSi integrated resistors with various numbers of me-andering segments.

Figure 2.12 Five capacitive couples for six meandering segments.



The effective length of the coupled capacitor is

capacitive length =

(resistor length)

As an example, consider a 20 k resistor to be fabricated from 5-mil-wide sputteredTaNx with a sheet resistance of 100/square. The length of the resulting 200 squareswould be 1000 mils (2.54 cm). If this is to be fit into a square footprint, the size is eas-ily calculated from the total required area. The area of the resistor material itself is 5× 1000 = 5000 mils2 and, using equal width and spacing, the area of the gaps betweenmeanders will be the same for a total footprint area of 10,000 mils2. Taking the squareroot gives 100 mils to a side. Since the pitch is 10 mils, there will be 100/10 = 10 me-

ander segments or, calculated another way, the total length of the resistor is 1000 milsdivided into segments 100 mils long, which also gives 10 segments. The capacitivelength is, then, (9/10)(1000 mils) = 900 mils or 23 mm. This is all somewhat approx-imate since the single squares that link the meanders have been ignored and since thetop and bottom of the footprint will both have resistor material, not resistor materialon top and a space on bottom (think of the red stripes of the American flag), but theseare small effects when the number of squares is large. 23 mm at, say, 0.084 pF/mmgives a total capacitance of 1.9 pF. Based on this analysis, the impedance of this re-sistor would be expected to remain constant at 20 k until about 4.2 MHz, at which

time it will drop due to current bypassing the resistor through the parasitic capacitor.

2.3.3 Parasitic Capacitance to Ground

The previous section dealt with the issue of parasitic capacitance between adjacentserpentine resistor segments, but, for integrated resistors, there is another even moretroubling parasitic: the parasitic capacitance from the resistor film to a nearbyground or power plane. Depending on the geometry of the resistor, the verticalspacing between the resistor and a ground or power plane, the dielectric constant of the board material, and the frequency of the signal across the resistor, this effectcould be minor or serious.

The parasitic capacitance in question can be determined from the usual parallel plate capacitor model (see Chapter 5) using the total area of the resistor and its ter-minals as the area of the plates, assuming a continuous ground or power plane.However, if the width of the resistor stripe is less than five times the distance be-tween the resistor material and the ground plane, there will also be significant fring-ing capacitance and the parallel plate model will not give an accurate result.

For example, a resistor 1 mm square, separated from a ground plane by a 50 µm(the thickness of flex) dielectric with a dielectric constant of four, would have a par-asitic capacitance to ground of 0.7 pF. For equivalent circuit purposes, this should

be considered as a 0.35 pF capacitor from each terminal of the resistor to ground. Insome applications, this would seriously affect circuit performance, and in others itwould not matter at all. But the circuit designer must be aware of this effect whendesigning with integrated resistors.

N – 1

N




2.3.4 Lumped Versus Distributed Performance

If the resistor length is less than about 1/5 the wavelength, then it will act as alumped component, but when larger than this, it begins to act as a distributed set of R, C, and L’s, complicating its modeling. A 1 GHz signal propagating at half thespeed of light through a board has a wavelength of 15 cm. One-fifth of this is 3 cm,which would be considered quite large for an integrated resistor. For most compo-nents in laminate boards, this will not be an issue, though certainly the designers of microwave hybrids deal with this problem all the time.

2.4 TRIMMING

Integrated resistors can be trimmed in much the same way that they are in hybridcircuits or discretes, using simultaneous value measurement and laser cutting. Thisis especially important because they cannot be presorted for value nor can they beremoved and replaced. A wide variety of thick and thin film materials can betrimmed, but care must be taken to avoid damage or even perforation of insulatingmaterials below. Figure 2.13 shows a NiP resistor trimmed with an IR laser systemmanufactured by Electro Scientific Industries (ESI) and Figure 2.14 shows how thesame process can convert a wide bell curve of resistor values into a much smaller range. Of course, laser trimming can only increase the resistance, so the units that

were higher than the target remain at their original values.Table 2.2, from an article by Fjeldsted and Chase [12], gives the sources of error

for some integrated resistor materials on FR4 showing how the various contribu-tions add up to overall tolerances of around 10%. For thin-film sputtered and etchedsystems, the contribution from the interconnect geometry would probably be negli-gible, enabling tolerances close to 5% to be achieved without trimming


Figure 2.13 Laser-trimmed Ni–P integrated resistor.



Some accommodations need to be made to facilitate trimming, namely the prop-er size and placement of test pads. The exact requirements will be specific to thetrimming equipment but, in general, the pads should be in a systematic x–y layoutwith a repeated pattern, close enough to the resistors to provide accurate values butfar enough from the resistors to allow the laser unhindered access. Suggested padsize for ESI equipment is a minimum of 5 mils. Their laser spot is 2–7 mils across

and the minimum recommended resistor size for trimming to high tolerance is 10 ×10 mils. Resistors below 200 may require four-point Kelvin probing for 1% accu-racy.

Laser trimming changes the value of integrated resistors from low to higher val-ues but they can also be trimmed from high to lower values by using a process

based on ink jet printer technology to deposit conductive polymer over the top of resistors in place. This has been demonstrated with a filled polyimide that is de-

posited over the resistor, forming a parallel conductive path. This approach can beused to repair resistors that were overtrimmed by laser methods [13].

REFERENCES

1. K. Coates et al., “Highly Reliable Embedded Thin Film Resistors in Cu/PI MCM-D’s for Aerospace Applications,” In Proceedings of the 49th ECTC Conference, p. 93, 1999.

REFERENCES 53

Figure 2.14 Value distributions of PTF resistors before and after laser trimming.

Table 2.2 Error sources for resistors on FR4

Specific Resistor CuResistor Type Resistivity Thickness Geometry Geometry Total

PTF 1% 5% 1–5% 5% 12–16%Metal thin film 1% 3% 1–5% 5% 10–14%Thin film on foil 1% 1% 1–5% 5% 8–12%



2. J. Sergent and C. Harper, Hybrid Microelectronics Handbook, McGraw-Hill, New York, pp. 3–74, 1995.

3. R. Berry, P. Hall, and M. Harris, Thin Film Technology, Van Nostrand, New York, p.

271, 1968.4. J. Watkins, Modern Electronic Materials, Butterworths, London, p. 22, 1971.

5. O. Kubaschewski and B. Hopkins, Oxidation of Metals and Alloys, Butterworths, Lon-don, p. 26, 1953.

6. G. Alers et al., “Advanced Amorphous Dielectrics for Embedded Capacitors,” 1999

IEEE IEDM 99-797, p. 33.3.1, 1999.

7. R. Petrovic et al., “Electrical and Structural Properties of Tantalum Nitride Thin FilmsDeposited by Sputtering,” Thin Solid Films, 57, p. 333, 1978.

8. P. Chahal et al., “Electroless Ni-P/Ni-W-P Thin-Film Resistors for MCM-L Based Tech-

nologies,” In Proceedings of the 48th Electronic Components and Technology Confer-ence, IEEE, p. 232, 1998.

9. D. Brandler, “The Effect of Miniaturization on Embedded Resistors in High Density In-terconnecting Substrates,” In Proceedings of the 2001 IMAPS International Symposium

on Microelectronics, p. 464, 2001.

10. T. Lenihan and L. Schaper, “Integrated Passives Developments,” In Proceedings of the

1996 ISHM Advanced Technology Workshop, 1996.

11. S. Demurie and G. Mey; “Parasitic Capacitance Effects of Planar Resistors,” IEEE

Trans. Components, Hybrids. Manufacturing Tech., CHMT-12, p. 348, September 1989.

12. K. Fjeldsted and S. Chase, “Embedded Passives: Laser Trimmed Resistors,” CircuiTree,

March 2002.

13. V. Shah and D. Hayes. “Trimming and Printing of Embedded Resistors Using Demand-Mode Ink-Jet Technology and Conductive Polymer,” In IPC Printed Circuit Expo 2002,

p. 1, 2002.




55

CHAPTER 3

INTEGRATED RESISTOR MATERIALS

AND PROCESSES

RICHARD K. ULRICH

The previous chapter covered the generalities of integrated resistor configuration,values, performance, and sizing. This chapter will describe the various resistor ma-terials and processes that can be used to form those components. A resistor’s perfor-

mance is at least a direct function of its composition, microsegregation of composi-tion, crystal structure, film thickness, temperature, and voltage. These, in turn, are afunction of processing conditions such as pressure, temperature, power, gas flow,etc. for sputtering, CVD, or evaporation of thin films and cure time and temperaturefor thick films. Subsequent anneals, which alter crystal structure and compositionmicrosegregation, are often used to modify resistor properties. Some useful reviewsof this topic are available [1, 2].

Much of the information in this chapter will be familiar to those in the businessof manufacturing discrete resistors, but there are compelling reasons to make itavailable here. First, integrating the materials means manufacturing them in a newsetting with different substrates and different connection methods. Second, the de-veloping technology of integrated passives is inherently interdisciplinary, requiringknowledge of both the electrical engineering and materials engineering aspects todetermine what combination of performance and processibility is optimal for a giv-en application. Much of the information presented here is from the published resultsof many investigations into integrated resistors and indicates what materials thosegroups preferred and how they processed them. The intent is to combine the old andnew information to help the engineer select a suitable technology for his specificapplication.

The use of integrated resistors, and capacitors and inductors for that matter, re-quires that the design and process engineers work together to an extent that is notnecessary when off-the-shelf discretes are used. The selection of an integrated resis-tor technology for a given application requires the simultaneous consideration of electrical performance issues (resistivity, temperature effects, stability), and com-



ISBN: 0-471-24431-7



patibility with the materials and processing of other parts of the substrate/intercon-nect/passive assembly. No resistor material should be considered that cannot be de-

posited, cured and/or patterned by techniques and chemicals that do not harm the

preexisting substrate, interconnects, and other passive components in place. For these reasons, the integrated-passive engineer must understand the potential resistor film materials and processing methods, how those methods affect the compositionand structure of the films, and how the resulting composition and structure affectsthe electrical properties.

All of the materials and processes in this chapter are suitable for use on organicsubstrates. That is, the resistors can be processed at under about 250°C and withoutusing chemical steps that would harm polymer board materials or buildup layers. Of course, these same technologies could also be used on inorganic substrates such as

glass, silicon, or ceramic since these are typically more thermally and chemicallyrobust than polymer. There are two restrictions to transferring the technology fromthis chapter to ceramic substrates: the ceramic surface may be significantly rougher than organic surfaces, resulting in yield and tolerance problems with thin-film de-vices; and ceramic substrates are fired at temperatures usually exceeding 600°C,which may not be tolerated by some of the materials described here.

3.1 SINGLE-COMPONENT METALS

The resistance behavior of elemental metals is fairly predictable since it is not afunction of composition and is a weaker function of crystal structure than for mostcompound materials. Every atom in the metal contributes integer numbers of con-duction electrons—generally 1, 2, or 3—which are unbound and free to movethroughout the material with high mobility. Ionic conduction is completely unim-

portant. Because the density of charge carriers is high, on the order of the atomicdensity (~1022 cm –3), and because electrons are very mobile, metal conductivitiesare the highest of any materials at room temperature, ranging from about 1.7 -

cm for Cu and 2.7 for Al. The high end is represented by Ti at 43, Mn at 140, and beta-Ta at 180. First-order electron scattering theory indicates that metal resistivi-ties should be inversely proportional to molecular weight and this is found to beroughly true in practice, which is one reason that Al is so conductive. Typical resis-tivities for thin metal films, or any other material, are somewhat higher than bulk values because of microstructure differences between thin films and bulk materials,roughness of the substrate, and columnar grain growth influenced by the two-di-mensional surface structure of the underlying material.

The concentration of charge carriers in single-component metals is not a strong

function of temperature since each metal atom already contributes an integer number of electrons for conduction reflected by the valance states in the periodic table,and it would require much higher than room temperature to liberate more. There-fore, resistivity typically increases with temperature due to electron scattering off lattice vibrations, which are more numerous at higher temperatures, resulting in

56 INTEGRATED RESISTOR MATERIALS AND PROCESSES



TCR’s of typically a few 1000 ppm/°C. Metal films may be sputtered as thin as afew 100 Å for applications as low-valued resistors for current-sensing applications,or plated to almost unlimited thickness for use as low-loss interconnects. 1000 Å

films of pure metals would give sheet resistances of only 0.2 to 4 /square, whichwould not be practical for resistors above a few hundred ohms. Cu metallizationgives about 10 m/square for 2 microns of sputtered material and around 1 m/square for ½ oz layers.

Of the single-component metals studied for integrated resistor applications, Ta isa favorite due to its relatively high resistivity, stability with time, and the ability toanodically trim it to precise values. Ta has a high melting point (2996°C) comparedto other electronic metals, which implies that its crystal structure will not changemuch at slightly elevated temperatures, resulting in stable resistance values with

time and temperature. A corollary to this is that annealing to stabilize the propertiesis usually unnecessary since Ta responds little to temperatures that organic sub-strates can withstand. It is, however, a reactive metal and pure Ta films can be hardto make consistently, due to easy contamination with gases during sputtering. It istoo refractory for easy evaporation. Ta is a valve metal, which means it forms atenacious protective oxide when heated in air or exposed to anodic voltage in a con-ductive aqueous solution. This oxide may be used to protect the resistor from fur-ther reaction with oxygen or nitrogen, stabilizing its value against exposure to thesegases. Ta resistors may also be trimmed by anodizing, using a DC voltage to an-

odize the metal while simultaneously using an AC voltage to measure the resis-tance. Tolerances well under 1% can be achieved this way [3]. Of course, this pro-cedure may be complicated for integrated resistors since the component might beelectrically connected to other passives.

In bulk form, Ta has a resistivity of 14 -cm and a TCR of 3800 ppm/°C, typi-cal of single-component metals. Sputtering can produce two forms. The “alpha”form is bcc, the same as the bulk structure, which, like most materials, has a resis-tivity slightly higher than bulk at 20–40 -cm and a TCR slightly lower at500–1800. The “beta” form is easily sputtered under conditions that exclude conta-

minants. This is a tetragonal configuration with the same density as bcc but consid-erably higher resistivity—180 -cm and an attractive TCR of –100 to +100. BetaTa is not stable in bulk form [4]. There is also an unusual low-density form at 12gm/cm3 compared to the bulk value of 16.6 that is formed by lowering the cathodevoltage of the sputtering equipment from 5000 V to around 1500 V. It is also bcc

but very porous, with numerous voids and channels between crystallites that are20–50 Å across, giving it a surface area estimated to be 15 times as high as a high-density bcc film, a void volume of 27%, and a very high resistivity at about 4000-cm. Its TCR is considerably lower than the bulk material and can approach zero

under some processing conditions. Its appearance is not sudden; it comes on slowlywith lowered voltage, enabling a variety of intermediate forms to be produced. The problem with low-density Ta as a resistor material is that it is very sensitive to oxi-dation due to very large surface area. Heating in air increases resistance somewhat

but can drop TCR significantly; 2 hrs at 200°C has been seen to change the TCR

3.1 SINGLE-COMPONENT METALS 57



from 0 to –300 ppm/°C [5, 6].

3.2 METAL ALLOYS AND METAL–NONMETAL COMPOUNDS

Mixtures of metals exhibit higher resistivities than single-component materials,some as high as 160 -cm, due to mutual distortion of the single-metal lattices.They also typically have lower TCR because of electron band overlap between thetwo elements that causes an increase in conduction electrons with increasing tem-

perature, which somewhat offsets increased phonon scattering. But mostmetal–metal alloys, like elemental metals, have resistivities too low for use as inte-grated resistors. Many binary metal-containing compounds have been investigated

that could serve at the low end of the required resistance range, and three seem themost practical: NiCr, TaNx, and CrSi. TaNx may be the best of the group due to itsease of processing, low TCR, and stability, but all three have been demonstrated asintegrated resistors for organic substrates.

A TCR of –40 ppm/°C has been measured for sputtered CrSi films on polyimide,and postdeposition stabilization for 250 hrs at 125°C resulted in the loss of onlyabout 0.6% of its initial resistance value, after which it was stable at that tempera-ture [7, 8] (Figure 3.1). Ni0.8Cr 0.2 has a resistivity of around 100 -cm, dependingon its microstructure, and a TCR of –55 to +100. 200 Å of this would give 50

/square and is useful into the k range without excessive numbers of squares.Various annealing treatments at hundreds of degrees are used to modify and stabi-lize NiCr resistor properties; 250°C for 5 hrs is typical. NiCr is known to be sensi-tive to moisture conditions, and passivation layers may be used to stabilize its valueagainst time and humidity. SiO2 and polymer coatings have been used for this pur-

pose but, for integrated applications, being buried beneath layers of substrate mate-rial may suffice.


Figure 3.1 Integrated resistors made from 10-mil-wide CrSi on flex.



3.2.1 Tantalum Nitride

TaNx, formed by reactive sputtering of Ta in a nitrogen-containing atmosphere, isone of the most practical integrated resistor materials. At zero nitrogen levels, thefilms are, of course, bcc Ta with a resistivity of about 13–20 -cm (or beta with180 -cm) and a positive TCR in the high hundreds or low thousands, typical of elemental metal thin films. As the nitrogen levels increase, the resistivity rises to a

plateau at about 250 -cm and, simultaneously, the TCR falls to a plateau of around –75 ppm/°C, as shown in Figure 3.2. In this region, conductivity is thoughtto be due to tunneling through nitrogen-rich grain boundaries, which would explainthe low TCR. This wide plateau region is one of the features that make TaNx so at-tractive as a resistor; a wide range of processing conditions results in the same film

behavior that, fortunately, has good values of resistivity and TCR. Typical deposi-tion conditions are 10–20 mTorr of 10–20% N2, resulting in 100–1000 -cm,2000 Å films, and < 200 ppm/°C. Multivariable studies of TaNx properties with re-spect to sputtering parameters have correlated film resistivity, TCR, and stress(buckling and cracking) [9].

TaNx is more immune to recrystallization with temperature and time than NiCr or CrSi. It can be surface anodized in a controlled fashion for trimming and passiva-tion. Subsequent high-temperature annealing processes, both with and without oxy-gen, are used to stabilize these properties. 250°C for 5 hours in air will increase theresistance by 0.5–2%. TaNx can be wet etched in a mixture of nitric and hydrofluo-

ric acid or dry etched with CF4 in an RIE.Reactively sputtered films of oxygen-rich tantalum oxide offer sheet resistivities

of 27 to 25,400 ohms/square and TCR values of –3 to –1280 ppm/°C, which would be useful for high-valued resistors. However, the high-resistivity films were veryunstable and exhibited large resistance increases with time and temperature—+21%after 2 hrs at 300°C [10].

3.2 METAL ALLOYS AND METAL–NONMETAL COMPOUNDS 59

Figure 3.2 Resistivity and TCR of sputtered TaNx as a function of nitrogen content.



3.2.2 Titanium Oxy-Nitride

Various stoichiometries of titanium oxy-nitride (TiNxOy) can, like cermets, provideresistivity values near the top of the required range for integrated resistors. SputteredTiNxOy films have exhibited 15–5,000/square with TCR ± 100 ppm/°C [11]. Theywere formed by the DC magnetron reactive sputtering of Ti in N2 + 0.5 ppm O2 at1–10 mTorr and a substrate temperature of 150°C over both Si and FR4 substrates.With identical sputtering conditions, the resulting values, as N2 partial pressure wasvaried, were 15–2,000 /square over Si and 30–5,000 /square over FR4, as shownin Figure 3.3. TCR values decreased with increasing N2 partial pressure, reachingzero for films around 2000 -cm. Material resistivity appeared to vary from 200 to3000-cm. Annealing at 685°C for one hour raised the resistivity by only 4.5% for films on Si, and 1000 hrs at a heat flux of 80 W/cm2 resulted in a 5% increase, whichmight indicate good time/temperature stability at normal usage temperatures.Deposition repeatability was within 5% and the films may be wet etched with anaqueous solution of ammonia and hydrogen peroxide with good selectivity betweenTiNxOy and Cu. The resistor material can act as an adhesion layer between Cu and Si.

3.2.3 Nickel Phosphide

Although most thin-film compounds demonstrated for integrated resistor applica-tions are sputtered, it is also possible to electroplate various materials such as


Figure 3.3 Sheet resistivity for sputtered TiNxOy as a function of nitrogen pressure.



NiP and Ni–W–P, which are both thoroughly reviewed by Chahal et al. [12]. Thesematerials can be electrolytically or electrolessly plated to give up to 170 m-cmwith a TCR of about 100 ppm/°C for 12–14% P in Ni, and up to 150 m-cm with a

TCR of –5 to +60 ppm/°C for Ni–W–P. The resulting sheet resistances in this studyranged from 5 to 50 /square [13, 14]. Electroplated NiP is also used as the resis-tive material for Ohmega-Ply®, one of the few mature commercialized integrated

passive systems, providing up to 250 /square, and for MacDermid’sM-Pass™, providing up to 100 /square. These are described in more detail later inthis chapter. Ohmega-Ply® is produced by a subtractive process in which the Ni–Pis electrolytically plated and M-Pass™ is produced by an additive process that usesselective electroless plating over areas pretreated with a catalyst [15].

3.3 SEMICONDUCTORS

3.3.1 Silicon

Undoped semiconductor materials, on the average, contribute only one charge car-rier (electron or hole) per billions or trillions of atoms. As a result, resistivities aremuch higher than for metals; that of undoped Si is 250,000 -cm, almost a trilliontimes that of Cu. However, the concentration of charge carriers is a strong functionof temperature and impurity levels, which makes many of these materials too vari-able for use. Since increasing temperature liberates charge carriers in exponentialamounts, the TCR is strongly negative, about –73,000 ppm/°C for pure Si at roomtemperature. Furthermore, their resistivity is a strong function of trace amounts of impurities, which is a key feature in making integrated circuits possible. Polycrys-talline Si can be sputtered onto organic substrates, but its extreme TCR behavior would make it useful for thermistor applications only.

3.3.2 Semiconducting Oxides

There are semiconductor oxides that are by virtue of their low TCR, such as rutheni-um dioxide, which is widely used as a fired thick-film material on ceramic substrates.However, it can also be sputtered as a thin film from 32 to 500 -cm [16]. The sput-tering conditions that give near zero TCR for RuO2 yields about 150-cm. Tin ox-ide is a n-type semiconductor that can give a wide range of resistivities depending onhow it is doped; antimony is routinely added to it to decrease both resistivity andTCR, whereas indium has the opposite effect. 200 /square is possible at 1000 Å.

3.4 CERMETS

Most of the resistor materials described above are useful at only the lower end of the range required for common systems. High-value resistors, above about 100 k ,made from reasonably small numbers of squares require films with sheet resis-

3.4 CERMETS 61



tances in excess of 1000 /square; this is not achievable with metal–metal or metal–nonmetal alloys. Stable high-resistivity materials may be obtained by com-

bining a metal and a ceramic insulator into a two-phase structure known as a “cer-

met.” These are nano-structured compounds, with metal being the distributed phaseand ceramic the continuous phase. They are commonly used on ceramic substrates,where they are made by firing metal–glass pastes, but they may also be sputtered atmuch lower temperatures.

The most commonly used of these is Cr plus SiO, which can provide useful re-sistors with high values, low TCR, and good stability. 70% Cr in SiO gives 1100-cm and TCR = 0, whereas 55% approaches 10,000 -cm, as shown in Figure3.4. One disadvantage of the Cr system is that it is hard to dry etch; W-SiO is easier [17]. Because cermets are nano-structured compounds, the TCR of these materials

is complex, but tends to go negative and stay there once the metal particles are fullycoated, which seems to happen above about 40–50% ceramic [18]. The microstruc-ture of these films consists of grains of Cr, maybe with some dissolved Si, in a ma-trix of SiO. The conduction seems to be due tunneling between conductive grainsthrough the insulating matrix. The metal grains are around 50 Å in diameter, de-

pending on the temperature of the substrate during deposition. The low TCR is a re-sult of the need to thermally activate electrons to cross insulating barriers. Cermetsshow two limiting regimes of behavior:

1. Low resistivity and positive TCR at high metal fractions. Although the metalstill exists only in grains, there is a continuous metal network due to direct particle–particle contact. Conductivity is similar to that of metals.

2. High resistivity and negative TCR at low metal fractions. The metal grainsare isolated in the ceramic matrix and conduction is by tunneling. This is thearea of interest for high-value integrated resistors.


Figure 3.4 Resistivity of Cr–SiO cermet films sputtered at 200°C [19].



Attempting to raise the resistivity to very high values, near 1 -cm, by lowering themetal fraction to less than around 30% results in a high sensitivity of resistance andTCR to processing conditions, to the point that useful tolerance is difficult toachieve.

The tunneling mechanism is supported by the fact that the resistivity of cermetmaterials has been found to correlate well when plotted against the volume percentof ceramic, independent of the identity of the metal added—above about 40%, atwhich packing theory indicates that the metal grains would start to be separated byinsulator. Figure 3.5 shows this relation for a resistivity range of over 14 orders of magnitude for a variety of metals combined with SiO or SiO2 [20].

3.5 POLYMER THICK FILM

Polymer thick film (PTF) materials are a very promising technology for integratedresistors due to their low cost of materials and processing, wide range of resultingresistance, and low-enough curing temperature for organic substrates; but there aresignificant problems with value drift and reliability to overcome before they can bewidely used. Most PTF systems under development are epoxy-based polymers withmicron-scale carbon or graphite fillers, and the conduction mechanism is contact

3.5 POLYMER THICK FILM 63

Figure 3.5 Resistivity of cermet materials correlated with the volume percent of the insu-lating phase.



bridging between filler particles. They are provided as viscous liquids that may bescreen printed or stenciled, then cured at temperatures generally below 200°C. Oneavailable product cures in 45 minutes at 165°C or may be snap cured with IR in

only 5 minutes. The result is a film of several microns thickness with a practicalwidth no smaller than about 3–5 mils due to limitations in screen printing or stencil-ing, although 1 mm is a more common lower limit due to heat removal considera-tions. Not only is the processing simple and suitable for FR4 and flex, but theachievable sheet resistances also cover a very wide range, from 1 to 107 /square.There is rarely a need to use more than 10 squares due to the wide range of resistiv-ities supplied by the manufacturers, so resistor footprints can be quite compact. Fig-ure 3.6 shows some typical screen printed resistors on FR4 from Parlin Industries.Advertised TCR values are around 200 ppm/°C. As printed, their tolerance is no

better than about 5–10%, but they can be laser trimmed. Solder will not wet them,due to the epoxy polymer binder, so they can be printed and cured before other sur-face-mount components are added without the need for solder masking. PTF is in-herently solder-free, and is selectively added only where it is needed with no pat-terning and etching required. The films are generally 1–2 mils thick wet and abouthalf that dry, and a single gram may cover 200–400 cm2 with little waste. Several

board shops offer PTF as an option, although generally only for non-critical appli-cations in which some drift is not harmful, such as in rheostats.

The problem with these materials is that the resistivity tends to increase with

time both in the bulk of the material and at the metal/polymer interfaces, especiallyin humid environments. There are several reasons for this, including oxidation atthe Cu/polymer interface, delamination from the contacts, swelling of the polymer material with moisture, cracking of the polymer material due to CTE mismatch, and

possibly others [21, 22]. Better contact stability may be obtained by using larger


Figure 3.6 Screen printed PTF resistors on FR4.



contact areas, by using Au- or Ag-filled epoxy materials over the Cu termination asa transition material, or by applying proprietary oxidation inhibitors, all at addition-al cost [23]. Considerable research is being performed on this class of materials to

solve these limitations. Most efforts are centered on various additives such as corro-sion inhibitors and oxygen scavengers to prevent metal contact oxidation and to im-

prove mechanical properties. Some manufacturers recommend using conductivesilver-filled ink between the contact pad and the PTF resistor. Allowable heat flux-es are a bit lower than for thin-film resistors; a maximum of 5–8 W/cm2 are cited inmanufacturing literature. Larger square size (lower heat dissipation) and higher cure temperatures give better value stability. Screen printing is more of an art than ascience, and requires careful process control and skilled personnel for accurate tol-erance and reproducibility. As supplied, the inks are in the range of tens of thou-

sands of cP, but can be thinned with appropriate solvents to some degree. 200 meshscreen is recommended by some manufacturers. Similar technologies are under de-velopment such as low-resistance solder-free attach materials for surface-mount

parts and printable interconnect inks with resistivities less than about 150m/square [24]. Such films are filled with metal flakes, generally Ag, in order tomaximize their conductivity, but they also suffer from value drift problems similar to those exhibited by PTF resistors.

Some of these stability problems are solved by using a system of low-meltingmetals in a polymer matrix in which the metal particles are sintered together into a

continuous but porous network. This eliminates the problems with unconnected particles moving relative to one another during temperature changes. The samestrategy has been used to make conductive pastes used for mounting components.The main constituents of these materials are selenium, solder powder, and epoxyresin, and the resulting sheet resistance is from 1 to 2000 /square with TCR’saround 300 ppm/°C. Cures are typical of epoxies—around 215°C for 15 minutes[25].

Several companies offer PTF products and services, but value stability should beevaluated under the conditions of the intended use and not extrapolated from the

company’s test conditions. If issues related to long-term stability and reliability can be resolved, PTF should become a major player in integrated resistors [26, 27].

3.6 INK JET DEPOSITION

This technology comes directly from ink jet printers, but is better described as “ma-terial jetting” since a wide variety of fluids can be deposited this way, includingcurable polymer resins and solder. There are two types of deposition: continuous

droplets and droplets on demand. In continuous mode, droplets are produced at aconstant rate and caught in a deflector when not wanted on the substrate. For droplets on demand, a small, rapid volume change is made to a fluid reservoir usinga pulse of voltage to a piezoelectric material, a pulse of voltage through a resistor resulting in partial vaporization, or focused acoustic energy. This forces a singledroplet as small as 10 m out of an orifice at rates as high as 20,000 drops/second.

3.6 INK JET DEPOSITION 65



Printed resistors have been made from conductive polymers that resulted in about100 /square and geometries as small as 20 mils. The advantages of this method in-clude the ability to change resistor values, shape, and placement in software, and

the possibility of performing repairs. As described in the previous chapter, ink jet-ting can also be used to trim resistors from high to lower values, the opposite direc-tion from laser trimming, by selectively coating the top of the existing resistor witha less conductive material until it is within specification [28, 29].

3.7 COMMERCIALIZED PROCESSES

3.7.1 Ohmega-Ply ®

Ohmega-Ply® is an integrated resistor technology, primarily for organic substratesor laminates, that consists of 0.1 to 0.4 m thick electroplated NiP on one side of Cu foil. It is laminated, resistor material down, to the substrate, followed by twomask steps and three etch steps to form both circuitry and resistors for that layer, asshown in Figure 3.7. It can be used on most resin systems including high-Tg epox-ies, polyimides, BT blends, cyanate esters, PTFE (Teflon), and ceramic-filledresins. It is not applicable to LTCCs, MCM-Cs, or any cofired ceramics or ceramichybrids.

Once etched, the layer consists of either Cu with Ohmega under it where a con-ductor will be, or Ohmega with the Cu etched away from on top of it where a resis-tor will be. This provides both a variety of possible resistor values and arbitrary pat-terns of Cu interconnects on a rigid substrate, which can then be laminated into thestack just like any other material and connected to other layers with vias. Multiplelayers of Cu/Ohmega can be used to place integrated resistors anywhere in thestack. This technology is advertised as being applicable for values up to 10,000

from sheet resistances of 25, 50, 100, and 250 /square with 1000 /square under development. The company claims that cost benefits begin if the resistor density isapproximately 3–4 discrete resistors per square inch of board area [30–32] (Table3.1).

3.7.2 DuPont InterraTM

DuPont is developing a lanthanum boride (LaB6) based material that is screen print-ed as a paste in the desired shapes on one side of Cu foil, fired at 900°C to convertthe paste into resistor material, then laminated onto the board with the resistorsdown. The Cu is then etched to form the interconnects, as shown in Figure 3.8

[33–35]. Up to 10 k /square with ± 200 ppm/°C can be achieved with thickness of approximately 10–12 microns. The choice of this system was based on chemistrythat would be resistant to the etching solutions used to make cores and boards. Also,LaB6 has been used as a resistor material on ceramic substrates for many years andis known to be highly reliable and stable. Scattered resistance due to etching of theconductive phase was experienced with other resistor systems that were evaluated.




3.7 COMMERCIALIZED PROCESSES 67

Figure 3.7 Ohmega-Ply® integrated resistor processing flow.

Table 3.1 Performance specifications for Ohmega-Ply® integrated resistors

Max PowerSheet Resistance TCR after 1000 hrs Dissipation at 40°C

(/square) Tolerance (ppm/°C) at 70°C Ambient (W/cm2)

25 5% –50 0.50% 3950 5% –60 0.75% 31

100 5% –80 1.0% 23250 10% +100 1.0% 16



The copper foil is first conditioned by printing and firing a thin layer of copper/glass paste over one side of its surface. This conditioning process has beenfound essential in developing good adhesion of both the resistor to the foil and thefoil to the epoxy prepreg adhesive. A protective layer is applied to the resistors be-fore being flipped on the prepreg that protects the board during laser trimming. Thevacuum lamination to FR4 is done at 150°C, so other parts of the boards never seehigh-temperature processing.

3.7.3 MacDermid M-Pass™

M-Pass™ employs a selective thin-film, electrolessly plated NiPx material to formintegrated resistors of 25–100 ohm/square. Processing is additive; the material is se-lectively plated only where it is needed through the use of a palladium catalyst and

photoresist to define the plating areas. The process fits into traditional PWB fabri-cation equipment and procedures. The process is shown in Figure 3.9.


Figure 3.8 DuPont’s InterraTM fired lanthanum boride integrated resistor processing flow.



Resistivity of the deposit is controlled by plating time; longer times create athicker deposit that is less resistive. The final films are less than a few hundred

angstroms thick. Multiple masking and plating time variation allows multiple resis-tor values on the same layer. Solder mask or screened dielectric material is used to protect the final resistor to maintain the “as trimmed” value through subsequenthandling and lamination. The resulting resistors have a lower-size limit of 250 mwhen ½ oz Cu foil and conventional dry resist are used, an upper limit of 100/square, and an untrimmed tolerance of about 10%. By successive imaging steps,

3.7 COMMERCIALIZED PROCESSES 69

Figure 3.9 M-Pass™ integrated resistor processing flow.



it would be possible to form resistors of values from 25 to 100 ohms/square on thesame layer. Finished and passivated resistors show less than 2% value drift over 1000 hours at 85°C and 85% RH or 500 cycles of –35 to +125°C. MacDermid’s de-

velopment goals for this product include increasing the as-plated precision to 5%and produce higher /square materials to enable higher-value resistors [15].

3.7.4 Polymer Thick Film

PTF materials for screen printing integrated resistors were described earlier in thischapter but are included briefly here since they are commercialized products. PTFink vendors include Metech, Acheson Colloids, and Electra. Metech and several

board shops offer this as a process option. Although the materials handling and cur-

ing steps are easy and inexpensive, the key to success lies in the screen printing process, which can be a complex and sensitive procedure. Also, company claimsabout value stability should only be taken as general guidelines; users should evalu-ate this under their own testing conditions. Motorola has demonstrated the printingof resistors from 18 to 10 M with the same family of PTF inks [23]. They havedeveloped a proprietary material to go between the Cu termination and the PTF ma-terial that diminishes the tendency for pad oxidation to increase the resistance withtime and temperature.

3.7.5 Shipley Insite™

Shipley is developing a resistor material they describe as consisting of thin-filmdoped platinum deposited directly on copper foil by combustion chemical vapor de-

position (CCVD). This combination of material and process allows high values of sheet resistivity (up to 1000 /square) and a TCR value less than 100 ppm [36].SEM photos show what appears to be a cermet-type structure consisting of 50 Ågrains surrounded by another phase, possibly an insulator. Processing is much likeOhmega-Ply®; it is deposited onto one side of Cu foil, flipped onto the board, and

etched. As of the date of this writing, it has not been commercially released.

3.8 SUMMARY

Table 3.2 gives an overview of the values of resistivity, reasonable film thickness,and resulting sheet resistances for a variety of materials useful for integrated re-sistors. Interconnect metals are shown for comparison. The resistivities given for elemental metals are bulk values; thin-film values will be somewhat greater and

are given as ranges for alloys and metal–nonmetal compounds since their specificvalues are dependent on their exact composition, processing, and annealing condi-tions. TCR values for metals are maximums for perfect crystals but, in practice,would not be much lower. Film thicknesses are set at 2 m for interconnect ma-terials, which is practical for sputtered films, and 500 Å for the sputtered resistor materials, which is a practical lower limit. Resistors as thin as 200 Å have been




used, giving sheet resistances 2.5 times higher than shown for thin-film resistor

materials, but tolerance and yield become more difficult as the films become thin-ner. Commercialized technologies are shown with whatever thickness and perfor-mance data is known.

As described in the previous chapter, most integrated passive resistor applica-tions can be realized using two ranges of sheet resistance—about 100 /square andabout 10,000 /square. The lower range can be obtained using any one of several

3.8 SUMMARY 71

Table 3.2 Resistance properties of materials useful for integrated resistorsand interconnects

Resistivity

Range Film Sheet Resistance TCR Material (-cm) Thickness (/square) (ppm/°C)

Ag 1.6 2 m 0.0080 4100

Cu 1.7 2 m 0.0085 4330

Au 2.4 2 m 0.0120 4000

Al 2.7 2 m 0.0135

Ni 6.9 2 m 0.0345 6750

Ta bcc: 13 beta: 180 500 Å 2.6 3800

Cr 13 500 Å 2.6 3000

Ti 42 500 Å 8.4

TaNx, CrSi, NiCr, 100–500 500 Å 20–100 ± 50 with processTiNx, NiP optimization

NiP ~2000 1000–4000 Å Up to 250 0–100(Ohmega-Ply®) 1000 in

development

NiP Up to 100(MacDermid) higher in

development

TiNxOy Up to 7000 500 Å Up to 1400 ± 100 with process

optimization

LaB6 107 10 m 10,000 ±200(DuPont)

PTF Very wide, 1–2 mil 10–107 ~200(several vendors) depending on filler

Cermets 104 –1010 depending 1 m 100–108 Close to zero oron metal/glass ratio slightly negative



materials, including TaNx, CrSi, NiCr, and TiNx, and the high end of the resistancerange can be covered by cermets or, perhaps, TiNxOy and LaB6. Polymer thick films can accommodate the entire range, but problems with value stability exist at

this time. Table 3.3 shows the status of these materials on organic substrates. Itshould be remembered that these films, formed by any method, cannot subsequent-ly be annealed at high temperature on organic substrates for the purposes of modi-fying their structure and properties.


Table 3.3 Processing limitations for various integrated resistor materials on organic andinorganic substrates

Practical Range Processing on

Material of Resistance Organic Substrate Processing Issues

Low- metals Resistivity too low for Sputtering to ~2 m Well-established(Cu, Al, Au) almost any resistor Plating to >100m

applications, useful asinterconnects andcontact metal to resistors

High- metals <100 Sputtering to ~2 m Well-establishedPlating to >100 m

TaNx, CrSi, Useful to around Sputtered thin film Well-established, NiCr, TiNxOy 100 k ; TiNxOy may be may requirehigher with development passivation or

thermal stabilization

Electrolytic NiP Useful to around 100 k Electrolytically plated Commercialized asonto Cu foil, laminated Ohmega-Ply® in theonto board, Cu and form of plated foil NiP etched to shape

Electroless NiP Useful to around 100 k Dielectric surface is Under developmentcatalyzed for selective by MacDermid plating, fully additive

LaB6 Useful over wide range LaB6 paste printed to Under developmentshape on Cu foil, fired, by DuPontlaminated onto board,Cu etched to shape

cermets Useful for high range, Sputtered thin film Experimentalup to M

PTF Very wide range Screen print or stencil Very attractive

epoxy-based paste, technology due tocure <250°C flexibility and lowcost, once valuedrift and reliability problems are solved



REFERENCES

1. R. Kennedy, “Materials for Thin Film Resistors,” Advancing Microelectronics, p. 12,

Sept/Oct 1999.2. L. Maissel and R. Glang, Handbook of Thin Film Technology, McGraw-Hill, New York,

1970.

3. R. Berry, P. Hall, and M. Harris, Thin Film Technology, Van Nostrand, New York, p.344, 1968.

4. P. Catania, R. Roy, and J. Cuomo, “Phase Formation and Microstructure Changes inTantalum Thin Films Induced by Bias Sputtering.” Journal of Applied Physics,74, 2,1008, 1993.

5. B. Vromen, “Low-Density Tantalum,” Bell Laboratories Record, p. 327, Nov. 1968.

6. H. Schuetze, H. Ehlbeck, and G. Doerbeck, Transactions of the 10th National VacuumSymposium, p. 434, 1963.

7. T. Lenihan et al., “Embedded Thin Film Resistors, Capacitors and Inductors in FlexiblePolyimide Films,” International Journal of Microcircuits and Electronic Packaging, 20,

4, 474, 1997.

8. K. Fairchild et al., “Reliability of Flexible Thin-Film Embedded Resistors and Elec-trical Characterization of Thin-film Embedded Capacitors and Inductors,” In Pro-

ceedings of the 1997 Electronic Components and Technology Conference, p. 730,1997.

9. K. Coates et al, “Development of Thin Film Resistors for Use in Multichip Modules,” In1998 International Conference on Multichip Modules and High Density Packaging,

IEEE, p. 490, 1998.

10. R. Clark and C. Orr, “Reactively Sputtered Tantalum Resistors and Capacitors for Sili-con Networks,” IEEE Trans. Parts, Materials Pack., PMP-1, 31–44, June 1965.

11. A. Shibuya et al., “Embedded TiNxOy Thin-Film Resistors in a Build-Up CSP for 10Gbps Optical Transmitter and Receiver Modules,” In Proceedings of the 51st Electronic

Components and Technology Conference, IEEE, p. 847, 2001.

12. P. Chahal et al., “Electroless Ni-P/Ni-W-P Thin-Film Resistors for MCM-L Based Tech-nologies,” In Proceedings of the 48th Electronic Components and Technology Confer-

ence, IEEE, p. 232, 1998.13. S. Yamada, et al., “Electroless Ni-P Resistors for Fusing Roll,” IEEE Transactions on

Components, Hybrids and Manufacturing Technology, 13, 3, 576, 1990.

14. M. Fernandez, J. Martinex-Duant, and J. Albella, “Electrical Properties of Electroless NiP Thin Films,” Electrochemica Acta, 31, 1, 55, 1986.

15. J. D’Ambrisi, D. Fritz, and D. Sawoska, “Plated Embedded Resistors for High SpeedCircuit Applications,” In IPC Fall Annual Meeting, Orlando, FL, Oct. 11, 2001.

16. Q. Jia et al., “Development and Fabrication of RuO2 Thin Film Resistors,” Materials

Science and Engineering, B18, p. 220, 1993.

17. N. Kim et al., “Development of Multi-Chip Modules with Integrated Thin Film PassiveElements,” In Proceedings of the 1997 Interenational Symposium on Microelectronics,

p. 157, 1997.

18. V. Fronz et al., “Electrical and Structural Properties of Cr-SiO Thin Films,” Thin Solid

Films, 65, p. 33, 1980.

REFERENCES 73



19. L. Maissel and R. Glang, Handbook of Thin Film Technology, McGraw-Hill, New York, p. 13-3, 1970.

20. Neugebauer, “Resistivity of Cermet Films Containing Oxides of Silicon,” Thin Solid

Films, 6, p. 443, 1970.21. A. Xiao, Q. Tong, and A. Savoca, “Polymer Thick Film Materials for Integral Resis-

tors,” In Proceedings of the 49th ECTC Conference, p. 88, 1999.

22. Xi, Xiaomei et al., “Metal-Containing Polymer-Based Composites for Resistor andThermistor Applications,” In Proceedings of the International Symposium on Microelec-tronics, San Diego, CA, p. 453, Nov. 1998.

23. J. Savic et. al., “Embedded Passives Technology Implementation in RF Applications,”In Proceedings of the IPC Printed Circuit Expo, Long Beach, CA, March 24–28, 2002.

24. P. Harrey, P. Evans, and D. Harrison, “Integrated Capacitors for Conductive Lithograph-

ic Film Circuits,” IEEE Transactions on Electronics Packaging Manufacturing, 24, 4,333, 2001.

25. H. Hwang et al., “Polymer Thick Film Resistor with a Dual Curing System,” In Pro-

ceedings of the 1999 International Symposium on Microelectronics, p. 489, 1999.

26. D. Lu and C. P. Wong, “Development of a Conductive Adhesives for Solder Replace-ment,” IEEE Transactions on Components and Packaging Technologies, 23, 4, 620,2000.

27. K. Gilleo, Polymer Thick Film, SMT Plus Inc., 1996.

28. V. Shah and D. Hayes, “Trimming and Printing of Embedded Resistors Using Demand-Mode Ink-Jet Technology and Conductive Polymer,” In Proceedings of the IPC Printed

Circuits Expo 2002, Long Beach, CA, March 24–28, 2002.

29. D. Hayes, W. Cox, and M. Grove, “Micro-Jet Printing of Polymers and Solder for Elec-tronics Manufacturing,” Journal of Electronics Manufacturing, 8, 3 & 4, 209, 1998.

30. G. Walther, “Tolerance Analysis of Ohmega-Ply® Resistors in Multilayer OWB De-sign,” CircuiTree, p. 64, March 2001.

31. “Ohmega-Ply® Cost Analysis,” a white paper from Ohmega Technologies Inc., Culver City, CA, www.ohmega.com

32. D. Cullen et al., “Effects of Surface Finish on High Frequency Signal Loss Using Vari-ous Substrate Materials,” In Proceedings of the IPC Expo Conference, April 2001.

33. W. Borland and J. Felten, “Thick Film Ceramic Capacitors and Resistors inside PrintedCircuit Boards,” In Proccedings of the 34th International Symposium on Microelectron-

ics (IMAPS), Baltimore, MD, Oct. 9–11, 2001.

34. W. Borland and S. Ferguson, “Embedded Passive Components in Printed WiringBoards,” CicuiTree, p. 24, March 2001.

35. J. Felten, R. Snogren, and J. Zhou, “Embedded Ceramic Resistors and Capacitors inPWB: Process and Performance,” In Proceedings of the Fall IPC Meeting, Orlando, FL,October 11, 2001.

36. P. Chinoy, M. Langlois, and J. Schemenaur, “High Ohmic Value Embedded Resistor

Material,” CircuiTree, March 2002.




75

CHAPTER 4

DIELECTRIC MATERIALS FOR

INTEGRATED CAPACITORS

RICHARD K. ULRICH

It will be shown in this chapter that a very wide range of capacitor dielectric materi-als are potentially useful for integration. Ideally, their dielectric constant should beflat with regard to frequency, temperature, voltage, and time. The dielectric should

be capable of being bent and stretched to a reasonable degree so that it will not suf-fer from the effects of CTE mismatch with other board materials during normaltemperature excursions and so it can be used in applications with little packagingsuch as smart cards. It should be amendable to mass production at an economic costusing common materials and patterning techniques that do not harm other parts of the board or components already in place. Certainly, all of the technologies de-scribed in this chapter will compromise on some of these issues, which is why noone perfect integrated capacitor dielectric has yet to have been identified from thehundreds of journal and proceedings articles to date.

The fact that so many different dielectric materials have been evaluated in justthe past few years for applications as integrated capacitors is indicative of the un-certainty in this area. Scores of dielectrics representing all classifications of thesematerials (oxides, polymers, ceramics, etc.) have been evaluated experimentally inorder to identify their technical advantages and disadvantages with regard to fabri-cation, electrical performance, and reliability as an integrated component. In anynew technology, this is a necessary procedure to both cull out the materials that areclearly impractical and to provide the information to establish the economical via-

bility of those that are feasible. The list includes almost every material that has ever been used as a capacitor dielectric as well as one class of material that was inventedspecifically for the purpose: ferroelectric powders dispersed in curable epoxy. As itturns out, very few out of this multitude are completely impractical for use as in in-tegrated capacitors, which means that there is a large number of choices that have

passed the technical challenges and remain to be evaluated economically. There-fore, a review of the fundamentals of capacitance as well as the materials science



ISBN: 0-471-24431-7



behind dielectrics is in order for the purpose of understanding these issues suffi-ciently to make informed decisions about their applicability to integration.

This is such a large and important topic that it will be broken down into three

chapters: this one addresses the types of dielectric materials available for integratedcapacitors, Chapter 5 covers the sizes and configurations attainable with these ma-terials, and Chapter 6 deals with processing issues. This chapter begins with a de-scription of the mechanisms and metrics of a dielectric’s performance in a capaci-tor, such as the dielectric constant, dissipation factor, leakage, breakdown, andtemperature effects. This is followed by a listing of the major materials that have

been evaluated in integrated capacitors, sorted by type. One of the main purposes of this chapter is to compare the two major classes of dielectric materials—para-electrics and ferroelectrics—then show how one or the other of these might be more

suitable for certain integrated capacitor applications such as decoupling, filtering,A/D, and signal termination. It will be shown that the fundamental difference in theway the two materials store charge is very important to their respective suitabilityfor these applications. It will also be shown that selecting the dielectric with thelargest k is not always the optimal choice. Little regard is given in this chapter tohow the films might be formed on various substrates; the following chapters willaddress that.

There is a tremendous amount of research currently underway on high specificcapacitance materials and structures, not only for integrated passives, but also for

gate dielectrics and memory cells for ICs [1]. Many of the same goals are soughtfor all capacitor development programs: high specific capacitance, low leakage,high breakdown, and sufficient stability. However, what are considered good

properties is very much a function of application. A gate dielectric with a leakageof a mA/cm2 at 5 V may be considered a low-leakage material for that application,

but this is a tremendous amount of leakage for an integrated passive capacitor used in, for instance, an A/D converter. Similarly, a capacitor that might be con-sidered very stable against frequency for energy storage applications might be far too variable to be used as a filter element. There are several excellent overviews

of dielectric materials, some written long before integrated passives were con-ceived [2–5].

4.1 POLARIZABILITY AND CAPACITANCE

The ability of a dielectric material to store energy under the influence of an electricfield results from the field-induced separation and alignment of electric charges.Polarization occurs when the field causes a separation of the center of charge of the

positives and negatives in the material. The larger the dipole moment arm of thischarge separation in the direction of a field and the larger the number of thesedipoles, the higher the material’s dielectric constant. There are several possible con-tributions to this polarizability, which, depending on the mechanisms operative in agiven dielectric, determine not only the value of k but also how it varies with fre-quency, temperature, bias, impurity concentration, and crystal structure [6–8].

76 DIELECTRIC MATERIALS FOR INTEGRATED CAPACITORS



The three general mechanisms important to candidate materials for integratedcapacitors are electronic, atomic, and ionic polarization (Figures 4.1–4.3). Electron-ic polarization involves charge symmetry distortion of single atoms. Under the in-

fluence of an applied field, the nucleus and the negative charge center of the elec-trons shift in opposite directions, creating a small dipole. This induced dipole effectoccurs in all materials, including air, but is usually very small compared to other

polarization mechanisms since the moment arms of these dipoles are very short,usually a fraction of the size of an atom. Atomic polarization occurs in substancesmade up of more than one type of nonionic atom because the different elements willnot normally share the electron cloud equally; it will be shifted toward the moreelectronegative atoms, resulting in a permanent dipole. The electric field will then

produce forces on various parts of the molecules, causing these dipoles to align to

some extent. It is the aligning with the field that creates enhanced capacitance, notthe presence of permanent dipoles; if these randomly oriented permanent dipoleswere somehow not capable of movement and alignment, there would be no dielec-tric constant for that material resulting from atomic polarization. Therefore, k is afunction of the material’s structure and lattice flexibility as well as its composition.Ionic polarization is similar to atomic polarization but involves the shifting of ionicspecies under the influence of the field. This shift can be considerable and can leadto very high dielectric constants, up to several thousand.

All materials exhibit electronic polarization because they all have atoms, where-

as atomic and ionic polarization require specific types of structures to be present.Purely electronic polarization would result in low dielectric constants, perhaps up to2–4. Atomic and, especially, ionic polarization are responsible for much larger di-electric constants.

The two major classes of dielectric materials—paraelectrics and ferroelectrics— both exhibit electronic, atomic, and ionic polarization; the two classes of materialsare not distinguished from one another in that regard. The distinguishing feature isthat ferroelectric materials do not lose all of their ionic polarization when the fieldis removed but paraelectrics do. Because of lattice hindrances in ferroelectrics, the

electric field can pull the ions into configurations that do not revert back to the pre-

4.1 POLARIZABILITY AND CAPACITANCE 77

Figure 4.1 Electronic polarization.



vious state once the field is removed. As a result, ferroelectrics, analogous to ferro-magnetic materials, can possess a residual polarization after the field is turned off.Furthermore, this residual polarization can be oriented in one direction or the other depending on the direction of the last field, which is the trait that gives them utilityin nonvolatile memories. Paraelectric materials are those that cannot be left with a

residual polarization once the field is removed because they do not have a mobilecharged atom with more than one stable lattice position.The classic example of a ferroelectric is barium titanate (BaTiO3), shown in Fig-

ure 4.4. Above its Curie temperature of 120°C, barium titanate is a cubic crystalwith a lattice constant of 4.01 Å and a dielectric constant characteristic of para-electrics at around 15–40, but below this temperature it converts to the tetragonalform with unequal side lengths: 3.98 and 4.03 Å. Because of this asymmetry of thecrystal, the Ti+4 ion has two stable positions it can occupy, neither in the center of the cell. Since the center of positive and negative charges are no longer in the same

place, a permanent dipole moment exists that can be changed by moving the Ti+4

from one position to the other, and it will remain after the field is off. Although the


Figure 4.2 Atomic polarization.

Figure 4.3 Ionic polarization.



distance between the two positions is small (a fraction of an angstrom), this dis- placement, together with the +4 charge on the cation, results in a substantial dipolemoment that gives crystalline barium titanate a dielectric constant in the thousands,depending on the quality and alignment of its crystal structure. This residual polar-izability defines ferroelectric and paraelectric materials but, while important in non-volatile memories, this feature is irrelevant to any projected substrate-level integrat-ed capacitor application. The important difference from the point of view of

integrated passives is that ferroelectrics generally have much greater dielectric con-stants than do paraelectrics, sometimes by as much as three orders of magnitude,

because of their mobile ionic charge.

4.2 CAPACITANCE DENSITY

Table 4.1 is a list of the dielectric constants for various paraelectrics and ferro-electrics clearly showing the wide difference between them. The name “dielectricconstant” is somewhat of a misnomer since it is not necessarily constant withregard to temperature, frequency, voltage, and time. The k s given for the ferro-electrics are maximum amounts because their specific values depend on grainsize, crystal orientation, electrical bias, frequency, and film thickness. Fer-roelectrics must possess a crystal structure in order to exhibit these high dielectricconstants, otherwise their k s are no higher than typical paraelectrics. The dielectricconstant of amorphous barium titanate is comparable with paraelectrics at a valueof about 17 because the polarization contribution of the Ti+4 moving in the crys-tal cage is lost when there is no crystal structure to support it [9]. The values for ferroelectrics in Table 4.1 are for completely oriented bulk material single crystalsat low frequency and no bias. Therefore, they represent maximum ranges of val-ues for these materials. The dielectric constant for ferroelectrics is so highly de-

pendent on processing and measurement conditions that it is not possible to bemore specific but the values given for paraelectrics are only weakly dependent

4.2 CAPACITANCE DENSITY 79

Figure 4.4 Barium titanate becomes ferroelectric below 120°C




Table 4.1 Dielectric constants for paraelectric and ferroelectric dielectrics

Dielectric Dissipation TCCComposition Constant Factor (%) (ppm/°C) Reference

Teflon 2.0 0.02 –100 11Polyethylene 2.3 0.02 12BCB 2.7 0.1 12, 13Parylene 2.7 0.01–0.1 11Low e BT Resin 2.7 0.2 12BPA Cyanate 3.1 0.4 12Polycarbonate 3.1 0.1 11Mylar 3.2 0.4 11SiO2 3.7 0.03 <100 11, 14

Polyimide 3–4 0.2–1.0 12Epoxies 3–6 0.4–0.7 11Epoxy resin for FR4 3.9 1.2 12FR4 3–5 0.5–1.5 12S glass 4.8 0.2 12E glass 5 0.09 12SiO 5.1 0.01 ~200Si3 N4 7–9 12, 15BeO 7–9 <0.1ZnO 8 11

AlN 9 14Al2O3 9 0.4–1 390 11, 14Si3 N4 9.4 <1 11MgO 9.5 11YOx 12–17 16BaTiO3 (amorohous) 17 NbOx 20 11Ta2O5 (amorohous) 24 0.2–1 200 11, 15, 17, 18SnO2 25 14 11PbO 26 11

SiC 40 14HfO 23, 40 ~1 125 11WO2 42 0.6 11Ta2O5 (polycrystalline) 50 18TiO2 31 (anatase) 2–5 300 11, 15, 19

78 (brookite)117 (polycrst)~40–60 (film)

BaTiO3 (tetragonal) Up to thousands 5 Highly variable 11, 20, 21

BaSrTiO3 Up to thousands Highly variable 20, 22PbZr xTi1–xO3 Up to thousands Highly variable 23, 24, 25Ba0.8Pb0.2(Zr 0.12Ti0.88)O3 Up to thousands Highly variable 26



on how they are fabricated or how the k s are measured and represent typicallyachieved values. Only a few paraelectrics exist in multiple crystal forms such asamorphous and hexagonal Ta2O5 [1, 10].

Because integrated capacitors are planar and area-ruled, the best way to expresstheir value is as capacitance per unit area or “specific capacitance.” The followingequation uses convenient units:

specific capacitance in = 0.885

One of these factors is a function of the dielectric material itself and the other depends on its form (film thickness). This chapter will be concerned mainly with the

dielectric constant, what influences its intrinsic value, and how it is affected by op-erating conditions. Factors affecting film thicknesses are more specific to processibility and reliability are covered in the next chapter.

The energy stored in a capacitor is:

E = CV 2

where:

E = energy stored, JC = capacitance, FV = voltage

Table 4.2 shows the specific capacitances that might be expected from some com-mon dielectric materials in thin but attainable thicknesses.

1

2

dielectric constant

dielectric thickness in m

nF

cm2

4.2 CAPACITANCE DENSITY 81

Table 4.2 Specific capacitances and energy storage density of some common dielectrics

Specific Energy DensityDielectric Thickness Capacitance at 5 V

Dielectric Constant (m) (nF/cm2) (J/cm2)

Unfilled laminated polymer 4 25 0.14 0.002Ferroelectric-filled polymer 50 25 1.8 0.023Spin-on BCB 2.7 2.0 1.2 0.015SiO2 3.7 0.2 16 0.20SiO 6 0.2 27 0.34Al2O3 9 0.2 40 0.50Ta2O5 24 0.2 110 1.40TiO2 40 0.2 180 2.30Barium titanate ~2000 1.0 1800 22



4.3 TEMPERATURE EFFECTS

The temperature coefficient of capacitance (TCC), is defined as the temperature de-

rivative of dimensionless capacitance and is usually expressed in ppm/°C:

TCC = =

A TCC of under about 200 ppm is considered low. In the absence of significantchanges in film thickness with temperature, the capacitances may be replaced withdielectric constants to give a measure of TCC for the dielectric material only. TCCstend to be positive due to the effect of greater interatomic spacing at higher tempera-

ture, which allows a larger dipole moment in the presence of an electric field. TheTCC of paraelectrics tends to be fairly constant with temperature, in the neighbor-hood of 100–300 ppm/°C. Temperature has a greater effect on the dielectric constantof most ferroelectrics than paraelectrics because their polarization mechanisms aredependent on the crystal structure itself and is affected by phase transitions in thecrystalline materials, which occur at specific temperatures. Figure 4.5 shows the ef-

C T 2 – C T 1

T 2 – T 1

1

C T 1

C

T

1

C


Figure 4.5 Effect of temperature on the dielectric constant of paraelectric and ferroelectricmaterials.



fects of temperature on two ferroelectrics and one paraelectric, demonstrating thewidely varied types of temperature-driven behavior ferroelectrics can exhibit [25, 27,28]. The peaks in the BaTiO3 data are due to crystal transitions such as the tetrago-

nal-to-cubic conversion at 120°C described above. Some ferroelectrics can be modi-fied with additives to reduce or favorably tailor these temperature dependencies.Additives called “shifters” move the k versus T peaks to a certain temperature range,and “broadeners” widen the peaks in order to decrease the temperature dependencesomewhat. [26, 29]. Common paraelectrics, such as SiO2, Ta2O5, Al2O3, and BCB,do not show phase transition behavior within expected microelectronic operationtemperatures of –50 to +150°C.

4.4 FREQUENCY AND VOLTAGE EFFECTS

Frequency and bias can affect the dielectric constant of both paraelectric and ferro-electric dielectrics by acting through the relevant polarization mechanisms. For in-stance, for a material to exhibit a constant k value with frequency, the dipole must re-verse direction at the same rate for the polarization to remain in synchronization withthe field. As the frequency increases, it may outrun the ability of the particular dipoleto keep up with the reversals, resulting in the dipole arm being effectively shortenedand a decrease in dielectric constant with frequency. Of the charge storage mecha-

nisms described above, only the ionic motion in ferroelectrics, such as the Ti+4

in theBaO3 –4 cage, is affected at frequencies below the infrared range. Figure 4.6 shows the

ratio of the dielectric constant measured at various frequencies to the value at low fre-

4.4 FREQUENCY AND VOLTAGE EFFECTS 83

Figure 4.6 Effect of frequency on the dielectric constant of paraelectric and ferroelectricmaterials.



quencies for three ferroelectrics and three paraelectrics [26, 30, 31]. Although the paraelectrics show no significant decrease and the ferroelectrics show a sharpdropoff, it should be remembered that ferroelectrics may start with such a high k that,even at GHz frequencies, they may still have much higher dielectric constants. Thisfact is important in matching dielectric materials to integrated capacitor applications.These curves for BaTiO3 and BST are for sintered particles, whereas the PZT is a

sol–gel thin film. The actual degree of this dropoff, where it begins in frequency and,for that matter, the dielectric constant of the ferroelectrics, are highly dependent uponcrystal structure and orientation. Amorphous BaTiO3 gives a k of only 17, similar to

paraelectrics, and also has flat frequency response [9, 32].Figure 4.7 shows k versus bias for Ta2O5 and BST [33]. Many ferroelectrics ex-

hibit a marked decrease in dielectric constant with increasing DC bias, which may be used to advantage in fabricating a variable capacitor for tuning applications butmay be a distinct disadvantage for some integrated capacitor applications.

4.5 AGING EFFECTS

Capacitors made with ferroelectric formulations can display a decrease of capaci-tance with time, number of charge cycles [16] and temperature [34]. This phenome-non, called “dielectric fatigue” or “aging,” occurs due to crystallographic changes


Figure 4.7 Effect of bias on the dielectric constant of paraelectric and ferroelectric materi-

als.



related to the relaxation of lattice strain energy and does not occur with amorphous paraelectric materials to any measurable degree [29]. The rate of decay is logarith-mic:

k = k 0 – m(log t )

The quantity “m” is sometimes expressed in percent per decade-hour. These effectsare reversible with temperature and/or applied field and not all ferroelectrics exhib-it them; PZT seems to show cycle fatigue but SrBi2Ta2O9 does not [34]. The loss of capacitance by ferroelectric materials can be completely reversed by heating abovethe Curie temperature, which turns the material into a paraelectric crystallographicform then, upon cooling, back to a refreshed ferroelectric form.

4.6 COMPOSITION AND MORPHOLOGY EFFECTS

The dielectric constant of most ferroelectric materials is a function of film stoi-chiometry [29, 25], crystal structure, substrate characteristics [27], interfacial reac-tions, microstructural heterogeneities, lattice defects, mechanical stresses, film thick-ness [24], and electrode material [16]. Amorphous paraelectrics are largely immuneto all of these effects except composition, but at the cost of a much lower k [35].

Figure 4.8 shows the measured dielectric constant of sputtered ferroelectric PZTand BST films deposited on Pt as a function of film thickness along with paraelectric

4.6 COMPOSITION AND MORPHOLOGY EFFECTS 85

Figure 4.8 Dielectric constant versus film thickness.



Ta2O5. Substrate effects such as stress, defects, grain size, and interdiffusion restrictthe ferroelectric’s dielectric constant to values below those of the bulk material untilthe film is at least a few thousand angstroms thick [23]. There is no film thickness or

substrate composition dependencies for paraelectrics in general as long as the filmsare thick enough to be continuous [36]. For this diagram, the dielectric constant val-ues have not been normalized in order to illustrate the large gap between them.

4.7 LEAKAGE AND BREAKDOWN

Leakage across a dielectric is a measure of the current in the z-axis through a repre-sentative thickness of the film due to a DC voltage, whereas breakdown is the volt-

age at which the film suffers an irreversible high-current condition. These are simply measures of how good an insulator the material is, but through very thinsections where the conduction may not be strictly ohmic. Resistivities of the dielec-tric in bulk form are not usually measured or cited in capacitor applications becausethey often don’t relate to thin films; the current is almost always larger than would

be expected from bulk properties. That is because leakage and breakdown throughthin films are influenced, even controlled, by phenomena at pinholes and other filmdefects that are not present in the materials in bulk form. Amorphous dielectricfilms generally have lower leakage currents, higher breakdown voltages, and are

less sensitive to impurities. Since paraelectrics are usually amorphous, they mayhave an advantage in these areas over the same thickness of crystalline ferro-electrics. Figure 4.9 shows the leakage curves through anodized Ta2O5 for a varietyof film thicknesses.

The data may be displayed in other ways, such as leakage currents through vari-ous thicknesses at 5 V over various substrates, as shown in Figure 4.10. The accept-able amount of leakage is application-specific; the metric of under 1 A/cm2 at 5 Vis often cited; this might be a large leakage for an analog-to-digital application but asmall leakage for decoupling. It should be noted that, for most anodized oxides, the

leakage current is somewhat higher in one direction than the other. Figure 4.10shows the low-leakage direction with the positive plate on the same side as the an-odized metal, passing current in the same direction as in the anodization process.Sputtered, CVD, sol–gel, and other deposition methods do not usually make rectify-ing oxides like this.

Breakdown results in permanent damage to the film so that its leakage remainsvery high even at lower voltages. Most dielectric materials, inorganic or organic,have a breakdown strength of around 105 –107 V/cm. In thin films, breakdown is de-fect-driven by pinholes, cracks, and other flaws. There are two general mechanisms:

1. Thermal Breakdown—Current flows at a defect causing localized heatingwhich, in turn, results in more current until an avalanche breakdown occurs.

2. Electronic Breakdown—Conduction electrons are accelerated by the poten-tial field until they reach ionizing energies, resulting in an avalanche break-down of the material. This usually happens preferentially at defects.




4.7 LEAKAGE AND BREAKDOWN 87

Figure 4.9 Leakage curves through anodized Ta2O5 dielectric films.

Figure 4.10 Leakage current through anodized Ta2O5 films at 5 V.



Breakdown voltage decreases with increased temperature and frequency. The breakdown voltage falls off rapidly for most dielectrics over about 100°C. Thechoice of electrode metals can affect breakdown voltage due to roughness, injection

of other carriers, and interfacial field effects [37]. Breakdown voltages for anodizedand sputtered Ta2O5 are shown in Figures 4.11 and 4.12 [38–42]. The reader must

be cautioned that reported values of leakage current and, especially, breakdownvoltage vary widely in the literature for the same films even when allegedly pre-

pared in the same way. The measured values are a function of the number and sizeof pinholes and thin spots in the films which, in turn, is a function of the specifics of the deposition conditions and the surface roughness of the substrate. The break-down field, expressed as MV/cm, will usually be higher for thicker films due to thedecreased influence of flaws and pinholes; this is probably the case in Figure 4.12.

Breakdown itself can be very locally destructive, resulting in visible holes in theoverlaying plates and splashed metal. One interesting observation is that if the topelectrode is thin (less than about 1500 Å), defects will vaporize an area of electrodemetal that is larger than the defect in the dielectric so that the resulting damage will

be nonshorting. [41, 42]. This has been used in polymer film discretes as a way toactually clear out weak spots in a capacitor. These capacitors have sputtered metalelectrodes on the polymer layers that can be as thin as 300 Å. Such thin electrodesare used because many layers are typically stacked in parallel to give a high capaci-tance, and using thin metal allows more layers to be placed in a given height. Since

the electrodes are also in parallel, their overall resistance is low. As an additional


Figure 4.11 Breakdown voltages for anodized and sputtered Ta2O5 films over various sub-strates.



benefit, these metal films are thin enough to be burned away from defects by highlocal current density and are, therefore, self-healing.

The maximum working voltage is defined as the potential that results in either the highest acceptable capacitor failure rate or the maximum allowable leakage cur-rent and is usually set well below the breakdown voltage. If the capacitor lifetime isthe limiting factor, the maximum working voltage is very hard to quantify with cer-tainty, since field failure data may take so long to accumulate that it is never known

precisely. Accelerated testing, with voltage and/or temperature, may only give arough idea of the average lifetime in actual usage. If the maximum working voltageis set by the maximum allowable leakage current, this may be adjusted by changingthe dielectric thickness.

Figure 4.13 shows that, as a general trend, the breakdown field is lower for mate-rials with higher dielectric constants, although even the high-k ferroelectrics exhibit

breakdown fields of over 100 V for a 1 micron film (1 MV/cm) [16, 43]. Under high field conditions, the log of time to breakdown is proportional to applied fieldfor ferroelectrics, as shown in Figure 4.14 [16, 23], whereas paraelectrics do notshow this tendency.

4.8 DISSIPATION FACTOR

The dissipation factor is a measure of how much energy is lost in the dielectric dur-ing AC operation. If the mobile charges in the dielectric cannot respond fast enough

4.8 DISSIPATION FACTOR 89

Figure 4.12 Breakdown voltages for thin Ta2O5 films plotted as electric fields.




Figure 4.13 Relationship between breakdown field and dielectric constant.

Figure 4.14 Relationship between applied field and time to breakdown for ferroelectrics.



to the changing fields or if there are resistive losses in the dielectric or capacitor plates, then the current and voltage deviate from exactly the ideal value of 90° outof phase. This angular difference is called the loss angle and usually has the symbol

. The tangent of the loss angle is called the dissipation factor, and is zero for a capacitor that dissipates no wasted energy. The reciprocal of the dissipation factor isthe quality factor, Q. A dissipation factor under 0.1% (tan = 0.001) is consideredto be quite low and 5% is high. If the entire capacitor is considered, the dissipationfactor must also include losses due to leakage through the dielectric and resistivelosses in the plates and leads. This is explained in more detail in Chapter 8. Gener-ally, very low dissipation factors are desired for RF applications in which signallosses must be avoided, but much higher values can be tolerated for energy storageapplications such as decoupling.

4.9 COMPARISON TO EIA DIELECTRIC CLASSIFICATIONS

The Electronics Industry Association (EIA) classifies capacitor dielectrics accordingto their dielectric constant, their value stability against temperature, and their toler-ance. These codes are commonly used in the catalogs to describe discretes, providinga language for specification between the designer and the supplier. Dielectrics for in-tegrated capacitors are not yet standardized to the point that they are assigned these

codes, but this will certainly become necessary as the technology develops. To aidthe transition, it might be instructive to list the codes here and suggest how they might be linked to various candidate dielectrics for integrated capacitors.

The EIA temperature codes, shown in Table 4.3, give the suggested temperaturerange for the dielectric and the maximum amount its value would be expected tochange over that span. As examples, three common classifications are:

X7R: Operating temperature = –55°C to +125°C, maximum capacitance change= ±15%

Y5V Operating temperature = –30°C to +85°C, maximum capacitance change =+22% to –82%

Z5U: Operating temperature = +10°C to +85°C maximum capacitance change =+22% to –56%.

Consider the performance of two capacitors, each listed at 10 nF, but one is in X7R and one is in Z5U. Due to their very different temperature responses at 85°C, theX7R could be as low as 8.5 nF, whereas the Z5U could drop to 4.4 nF. A second setof codes are used for “temperature compensating” capacitors, which have little or

no temperature dependency. Examples include NPO, COG, N150, N750, and SL.A second stability issue arises from the degradation of the dielectric constant

with time, as described in Section 4.5. Gradual changes in the crystal structure of ferroelectrics causes their k to decrease, an effect not observed in paraelectrics sincethey are almost all amorphous. This decline begins as soon as the film is formed and

4.9 COMPARISON TO EIA DIELECTRIC CLASSIFICATIONS 91



exhibits a logarithmic behavior. For instance, if the degradation is quoted to be 3% per decade, then the capacitance will drop 3% from 100 hours to 1000 hours, andanother 3% from 1000 to 10,000 hours. It’s the nature of ferroelectrics that raisingtheir temperature past their Curie point resets the crystal structure, raising the di-electric constant back up to its original value and resetting the degradation clock to

zero. Since most high-k discretes are based on various formulations of barium ti-tanate, this reset temperature is around 120°C.

The EIA then groups these various behaviors into dielectric classes:

Class 1 (low dielectric constant, ultrastable)—Usually employs a dielectric witha k of less than 100 and almost always carries the EIA coding of C0G, whichmeans it operates from –55 to 125°C, and changes no more than 30 ppm over the entire temperature range. The aging effect is negligible.

Class 2 (medium dielectric constant, stable)—Dielectric constant is 2000–5000

and temperature stability is code A to R, up to ±15%. Aging is up to 3% per decade. Example: X7R.

Class 3 (high dielectric constant, stable)—Dielectric constant is 4000–20,000and temperature stability is code T to V, +22% to –82%. Aging is up to 6%

per decade. Example: Z5U.

In the world of discretes, Class 1 dielectrics are paraelectric in composition and behavior, and Class 2 and 3 are ferroelectrics, usually based on barium titanate.Class 2 may have various additives to moderate the behavior of the dielectric rela-

tive to Class 3.With the EIA designations now defined, how do they relate to the emerging inte-

grated dielectrics? Class 1 will include all of the paraelectrics listed in Table 4.1 byvirtue of their low k , temperature stability, and lack of aging effect. Class 3 will in-clude the pure, single-crystal ferroelectrics. The author’s literature search revealed


Table 4.3 Electronics Industry Association (EIA) temperature codes

Low Temperature High Temperature % Change

X –55°C 2 +45°C A +1.0%Y –30°C 4 +65°C B ±1.5%Z +10°C 5 +85°C C ±2.2%

6 +105°C D ±3.3%7 +125°C E ±4.7%

F ±7.5%P ±10%R ±15%S +22%T +22% to –33%

U +22% to –56%V +22% to –82%



no integrated capacitor dielectrics that purposely included additives intended tomoderate the ferroelectric behavior of a Class 3 material into Class 2, but somethin-film ferroelectrics described achieved Class 2 status due to imperfect crystal

structure as formed. One type of dielectric that might always be Class 2 is the combination of a high-k ferroelectric powder dispersed in a matrix of curable polymer,which is described in detail in Chapter 6. The idea behind this approach is to per-form the high-temperature annealing on a powdered material, then combine it withan easily cured polymer, typically an epoxy, so that it can be easily processed on anorganic board. Since it contains both Class 1 and Class 3 materials, its overall be-havior is mixed. It’s dielectric constant is under 100, typical of Class 1, but its tem-

perature stability and aging effects put it in Class 2 or the lower part of Class 3, depending on its formulation.

Finally, the EIA defines a set of tolerance codes as follows:

A ±0.05%

B ±0.10%

C ±0.25%

D ±0.50%

F ±1%

G ±2%

J ±5%K ±10%

M ±20%

Both the literature and the author’s experience indicate that it is difficult to do much better than ±5% on a consistent basis for either thick or thin processing.

As integrated capacitors come into more general usage, it might be important touse these codes in order to provide a bridge between the two technologies, discreteand integrated.

4.10 MATCHING DIELECTRIC MATERIALS TO APPLICATIONS

Table 4.4 is a summary of the relative dielectric properties of paraelectrics and fer-roelectrics. Ferroelectrics such as BaTiO3, PbxZr 1–xTiO3, and BaxSr 1–xTiO3 can ex-hibit dielectric constants up to three orders of magnitude higher than those of para-electric materials such as SiO2, Al2O3, Ta2O5, and BCB. However, the dielectric

properties of ferroelectrics are typically a stronger function of temperature, frequen-

cy, film thickness, and bias, resulting in significant nonlinearities in their perfor-mance. Also, the dielectric constant of some ferroelectrics degrades with time. Allof these factors must be kept in mind when determining what dielectric material isright for a specific application.

Required capacitor values for electronic systems can cover an enormous range,

4.10 MATCHING DIELECTRIC MATERIALS TO APPLICATIONS 93



from about 1 pF to thousands of F. Table 4.5 gives approximate values and re-quirements for acceptable leakage and stability for various capacitor applications.

These trends are approximate but serve to show that, typically, lower-valued capacitors require more stringent leakage and stability behavior. As a result, certain

types and thicknesses of dielectrics are more suitable than others for the various applications expected for integrated capacitors. The following subsections will giveguidelines for selecting dielectrics for these applications, assuming that they could

be fabricated on the substrates. The following two chapters deal more with the is-sues of how to fabricate these materials into practical integrated capacitors. Some of the more important applications for integrated capacitors, such as decoupling, will

be addressed individually and in much more detail in subsequent chapters.

4.10.1 Decoupling and Energy Storage

The ubiquitous need for high-frequency decoupling capacitors to supply the tran-sient current requirements of fast logic devices is well documented [44–48]. Since


Table 4.4 Comparison of paraelectric and ferroelectric dielectrics

Paraelectrics Ferroelectrics

k 2–50 Up to 1000sk vs. T Little dependence, Can be highly dependent due to<500 ppm/°C crystal phase transitions and

ion mobilityk vs. frequency Little dependence Decreases significantly, typically

above a few GHzk vs. film thickness No dependence since Highly dependent due to effects

amorphous on crystal structurek vs. bias No dependence Decreases with DC biasDielectric fatigue None k can decrease significantly with

cycles and timek vs. film structure Little or no dependence Film must be crystallineCure requirements None May require up to 700°C in O2

Table 4.5 Values and requirements for capacitor applications

Tolerance Acceptable Stability AcceptableApplication Value Range Requirements Leakage Required Parasitics

Filtering, timing 1 pF–100 pF High Low Moderate Filtering: lowTiming: higher

A/D conversion 1 pF–10 nF High Low Very high Higher Termination 50–200 pF Lower Higher Lower Higher Decoupling 1 nF–100 nF Lower Higher Lower Very lowEnergy storage 1 F and up Lower Higher Lower Lower



the purpose of decoupling capacitors is to provide low-impedance power for a sin-gle clock cycle, their most important characteristics are high capacitance and lowinductance. The values of these capacitors will typically be among the largest on the

substrate, from perhaps 20 to 1000 nF. Even higher capacitor values may be re-quired for other energy storage applications such as DRAM backup power. The in-ductance of an integrated capacitor is not a function of the dielectric material and istypically much lower than can be obtained with surface-mount discretes, making in-tegrated capacitors ideal for this purpose.

Tolerance is not important as long as they provide a minimum amount of capac-itance. The resulting capacitance of the structure as a function of film composition,morphology, and thickness as well as the capacitance as a function of frequency,

bias, and time is not an issue as long as the minimum capacitance level is main-

tained under all operating conditions. Ferroelectric films or ferroelectric powders inepoxy generally exhibit less stable and predictable electrical performance in all of these respects than paraelectrics but their much higher dielectric constant can en-able enough extra capacitance to be designed in from the start to make up for theseshortcomings. Paraelectric materials are much more stable and predictable but can-not achieve the high capacitance of ferroelectrics. As a result, the unstable nature of ferroelectrics is not so important in decoupling and energy storage, whereas their high capacitance density is an advantage.

Table 4.6 shows the length in mils required for the side of a square integrated ca-

pacitor to provide 100 nF. Film thicknesses of 2000 Å were chosen for most materi-als in this comparison because this thickness may be practically achieved by depo-sition (sputtering or CVD), anodization, and sol–gel, although deposited films maysuffer from yield problems when they are this thin [49]. From Table 4.6, low-k spin-on paraelectrics such as BCB or silica glasses result in unacceptably large struc-tures, whereas the higher-k anodized or deposited paraelectrics can provide 100 nFin areas which are larger than the footprint of a discrete but will fit in the area under a chip. A 3 micron layer of cured epoxy plus ferroelectric powder falls into the mid-

4.10 MATCHING DIELECTRIC MATERIALS TO APPLICATIONS 95

Table 4.6 Square plate size to provide 100 nF for various integrated capacitor technologies

Specific Length of Side forDielectric Thickness Capacitance Square 100 nF Cap

Dielectric Constant (m) (nF/cm2) (mils)

BCB 2.7 2 1.2 3600Spin-on glass 3.7 1 3.3 2200SiO2 3.7 0.2 16 970Al2O3 9 0.2 40 620Ta2O5 24 0.2 110 380TiO2 50 0.2 220 270Epoxy + ferroelectric paste 90 3 27 760High-k ferroelectric 2000 0.2 8900 40



dle of the range of thin-film paraelectrics. Only thin-film ferroelectrics can producea decoupling capacitor that is smaller than a discrete of similar capacitance but, of course, footprint is a secondary consideration since the integrated component will

not be on the surface anyway and will exhibit far less parasitic inductance.As an example, 1500 Å anodized Ta2O5 film would require 0.71 cm2 to provide

100 nF and, under 5 V bias, would leak approximately 1 A/cm2. The resulting power loss due to leakage is then only about 3.6W, which would not overheat thecapacitor or overtax the power supply. A similar calculation for high-k ferro-electrics is even more favorable since the films can be thicker to give the same spe-cific capacitance, which will result in less leakage per unit area, and/or the platescan be made smaller in area.

4.10.2 Analog Functions

In many analog functions such as RF/wireless, A/D conversion, and filtering andtiming applications, required capacitor values range from about 1 to 100 pF, severalorders of magnitude below those needed for decoupling. For these values, capacitor dielectrics that give high specific capacitance due to either high k or thin filmsshould be avoided if the resulting plate size would be so small that precision would

be unobtainable with board-scale lithographic resolution. For example, a 1 pF capacitor realized with 3000 Å of anodized Ta2O5 (about the thickest the film can be

anodized) would be only about 1.5 mils on a side but the same capacitor made from3 microns of BaTiO3 with k = 2000 would be 0.5 mils across. Achieving 5% toler-ance on a 1 × 1 mil capacitor plate requires a photolithographic tolerance of 0.025mils or 0.6 m. Thus, the use of thick layers of relatively low dielectric constantmaterials (<10) may be better for these low-valued components so that the resultingdevices are large enough to be fabricated with sufficient dimensional tolerance to

provide acceptable value tolerance. BCB and SiO2 dielectrics are feasible di-electrics for this; 5 microns of BCB would require 18 × 18 mils to give 1 pF, whichrequires 0.44 mils or 11 m for 5% tolerance. Thicker films are also favored for

most analog applications since leakage is very important and higher yields will re-sult. It may be possible to use the interlayer dielectric for these small capacitors,thus saving a masking step.

Besides problems with capacitor size, ferroelectrics are not as suitable as para-electrics in these applications because of their lack of stability and predictabilitywith respect to frequency, film thickness, film morphology, temperature, bias, andtime. Paraelectrics also tend to have a lower dissipation factor, which can be impor-tant in RF applications. However, the decrease in k with frequency and bias for some ferroelectrics has been used as a tuning feature.

4.10.3 Termination of Transmission Lines

As system bus speeds increase, a significant number of lines must be terminated toavoid signal reflection. In CMOS systems, purely resistive termination may con-sume unacceptable amounts of DC power. Thus, an AC termination scheme con-




sisting of series resistance and capacitance is preferred. Over 2000 discretes areused on a Pentium III mother board for termination [50]. Integrating R/C series ter-minators such as 50 /100 pF or 100 /50 pF into either passive networks or the

mother board itself is highly desirable.Exact tolerance of these capacitors is not critical, as long as they have a signifi-

cantly lower impedance than the series resistor at the frequencies of interest. 5%tolerance is much tighter than what is required. Leakage is also not an issue for ca-

pacitors in R/C terminations as the expected leakage currents are very low compared to the drive capabilities of buffer outputs that are required to drive transmis-sion lines in the 50 range. Therefore, the choice of dielectrics for termination isdriven by the same considerations for decoupling, except that less capacitance is re-quired.

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9. W. Liu et al., “Low-Temperature Fabrication of Amorphous BaTiO3 Thin-Film BypassCapacitors,” IEEE Electron Device Letters., 14, 7, 320, 1993.

10. Y. Park, X. Li, et al., “Effects of Annealing on O2 and N2 on the Microstructure of MetalOrganic Chemical Vapor Deposition Ta2O5 Film and the Interfacial SiO2 Layer,” Jour-

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11. L. Maissel and R. Glang, Handbook of Thin Film Technology, McGraw-Hill, New York, p. 16, 1970.

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13. P. Garrou, “Polymer Dielectrics for Multichip Module Packaging,” Proceedings of the

IEEE, 80, 12. 1992.

14. J. Sergent and C. Harper (eds.), Hybrid Microelectronics Handbook, 2nd ed., McGraw-Hill, New York, pp. 1–4, 1995.

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16. L. Manchanda and M. Girvitch, “Yttrium Oxide/Silicon Dioxide: A New DielectricStructure for VLSI/ULSI Circuits,” IEEE Electron Device Letters, 9, 4, 1988.

17. B. Lai and J. Lee, “Leakage Current Mechanism of Metal-Ta2O5-Metal Capacitors for Memory Device Applications,” Journal of the Electrochemical Society, 146, 1, 266,1999.

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State Letters, 2, 6, 291, 1999.

19. R. Kambe, R. Imai et al., “MCM Substrate with High Capacitance,” In Proceedings of

the MCM ’94 Conference, 1994.

20. A. Gitellson et al., “Physical Properties of (Ba,Sr)TiO3 Ferroelectric Thin Films in Weak Electric Fields,” Soviet Physics Solid State, 19, 7, p. 1121, 1997.

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24. N. Tohge, S. Takahashi, and T. Minami, “Preparation of PbZrO3-PbTiO3 FerroelectricThin Films by the Sol-Gel Process,” Journal American Chemical Society, 74, 1, 67,1991.



26. U. Syamaprasad et al., “A Modified Barium Titanate for Capacitors,” Journal American

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27. A. Gitellson et al., “Physical Properties of (Ba,Sr)TiO3 Ferroelectric Thin Films in Weak

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101

CHAPTER 5

SIZE AND CONFIGURATION OF


RICHARD K. ULRICH

The chapter begins with an analysis of the required footprints of integrated capaci-tors based on the dielectric properties discussed in the previous chapter and a shortdiscussion of capacitor layout options and tolerance issues. This is followed by an

evaluation of the advantages of using two dielectrics to cover the entire typical re-quired range of capacitor values. Finally, the theoretical limits of capacitance and breakdown voltage are discussed.

5.1 COMPARISON OF INTEGRATED AND DISCRETE AREAS

Table 5.1 shows the case sizes of surface-mount discretes, including a 10 mil keep-away distance, along with maximum capacitance values commonly available today.The capacitance densities on an area basis for the larger case sizes are much higher than are attainable from any integrated dielectric. The best that can be achieved for integrated components would be with about 2000 Å of ferroelectric with k = 3000,which would give only 13 F/cm2, whereas surface mounts can beat this by one or two orders of magnitude. High-k ferroelectrics require high-temperature processing;the best that can be achieved with a process that can be tolerated by an organic boardwould be a few tenths of a F/cm2. Integrated capacitors cannot compete purely onthe basis of specific capacitance per footprint area but, of course, they do not sincethey could be buried and would take up zero surface space. (See Table 5.2.)

An 0805 Ta capacitor as of the writing of this book can provide 20 F. It con-tains on the order of 100 cm2 of dielectric area, about the same as a sheet of note-

book paper, in a volume of only a few cubic millimeters. It is beyond the scope of this book to review discrete capacitor technology but, in the case of Ta capacitors,anodized powder technology makes it possible to fold this kind of area into verysmall spaces, resulting in high volumetric capacitances.



ISBN: 0-471-24431-7



Figure 5.1 shows the length required for the side of a square integrated capacitor to provide a given amount of capacitance for various dielectric materials. The x-

axis is the total capacitance of the structure, not the specific capacitance, and the y-axis is the required length of one side of the square plate of dielectric material inmils. Since integrated capacitors are area-ruled, the lines have a slope of 1/2 on log-log coordinates. A few representative dielectrics are shown for some practicalthicknesses. Other dielectric materials of known dielectric constant and thicknessmay be interpolated into the diagram to show their required sizes. The four horizon-tal dashed lines represent the areas of common surface-mount components alongwith a 10 mil keep-away distance. For comparison purposes, these surface-mountcomponents were converted to square areas so that the “square plate width” for

these units is the average side length required (Figure 5.1).It is also clear from Figure 5.1 that integrated capacitors do not necessarily havea smaller footprint than their surface-mount counterparts. For instance, using 2000Å of a paraelectric such as Al2O3 or Ta2O5 would result in a smaller footprint onlyfor capacitor values below a few nF. For micron thicknesses of BCB, polyimide,SiO2, or SiN, the crossover is around 10–100 pF. Figures 5.3 and 5.4 show the rela-tive sizes of planar integrated capacitors and surface-mount discretes for values of 50 pF and 50 nF, respectively. The surface mounts are shown with a 10 mil keep-away distance around them. The median size of a capacitor in a cell phone is about

1–10 nF.

102 SIZE AND CONFIGURATION OF INTEGRATED CAPACITORS

Table 5.1 Approximate capacitance values for surface-mount discretes

Size with 10 mil Approximate MaximumSize Code Keep-Away (mm × mm) Maximum Capacitance Capacitance per Area

0805 2.5 × 1.75 100 F 2300 F/cm2

0603 2.00 × 1.25 10 F 400 F/cm2

0402 1.50 × 1.00 1 F 67 F/cm2

0201 1.00 × 0.75 10 nF 1.3 F/cm2

Table 5.2 Capacitance values for integrated capacitors

Dielectric Specific CapacitanceDielectric Thickness Capacitance in 0805 Area

Dielectric Constant (m) (nF/cm2) (nF)

FR4 4 75 0.047 0.0003Mylar 3.2 50 0.057 0.0038

BCB 2.7 0.5 4.8 0.32Ferroelectric particles in epoxy 70 5 12 0.81SiO2 3.7 0.1 33 2.2Al2O3 9 0.1 80 5.4Ta2O5 24 0.1 210 14Crystalline ferroelectric 2000 0.5 3500 240



103

Figure 5.1 Square plate sizes required for various integrated capacitor technologies.

Figure 5.2 Small-valued capacitors made from 5 microns of benzocyclobutene.




Figure 5.3 Relative sizes of integrated and surface-mount capacitors to give 50 pF.

Figure 5.4 Relative sizes of integrated and surface-mount capacitors to give 50 nF.



5.2 LAYOUT OPTIONS

There are two basic configurations for integrated capacitors, parallel and floating

plate, as shown in Figure 5.5. The floating plate design has the possible advantagesin that connections need to be made to only the top level of metal, avoiding the ne-cessity of making a via down to the bottom plate. Also, this configuration avoidshaving a higher leakage current in one direction than in the other if the dielectric issomewhat rectifying, as many anodized oxides are. The drawback of the floating

plate capacitor is that it has four times less capacitance per unit area than the paral-lel configuration because the floating plate is actually two capacitors in series, eachusing only one-half the available area. An interesting aspect of these two configura-tions is how they respond to dielectric defects. If a parallel plate capacitor suffers a

dielectric defect that shorts out the component, the capacitor simply disappears and becomes a DC conductor, although probably a high-resistance one. But a floating plate integrated capacitor that suffers a short in one side becomes a capacitor of double its original value! The author uses this phenomenon as an exam question inhis microelectronics class every semester.

The layouts in Figure 5.5 are somewhat schematic; a more accurate representa-tion is shown for a built-up integrated capacitor in Figure 5.6. There are three mainconfigurations for the top plate connection that can be used depending on the natureof the capacitor dielectric. Robust dielectric materials such as polymers thicker than

about a micron should have no trouble tolerating a via directly on the top plate butvery thin ceramics, such as submicron oxides, may be perforated by either the process or subsequent uneven mechanical stresses caused by thermal excursionsduring use. If the dielectric is thick enough to provide step coverage over the bot-tom plate, the middle configuration can be used. Some sputtered and even anodizedfilms can do this, especially if the bottom plate has a slope to it due to purposefulundercutting of the mask when it was etched. If the dielectric is so thin that it cannot

5.2 LAYOUT OPTIONS 105

Figure 5.5 The two basic configurations of integrated capacitors.



provide the step coverage needed to separate the top and bottom plates, then anoth-er deposition and pattering step may be required to deposit some interlevel dielec-tric in between them.

5.3 TOLERANCE

Since the value of an integrated capacitor is proportional to its area, the scatter in re-sulting capacitor values are a function of the square of the feature width variation of the patterning technique. As shown in Figure 5.7, if an area of L2 is desired for thecomponent, then to achieve a 5% tolerance of this area, the patterning techniquemust have no more than 2.47% uncertainty.

In general, the patterning tolerance must be significantly better than the requiredvalue tolerance. How much better depends on the size of the capacitor relative tothe standard deviation of the patterning technology:

Component tolerance = 2

to 2

where: L = desired length of one side sd = standard deviation of the patterning technique

L – sd

L

L + sd

L


Figure 5.6 Connection options for built-up integrated capacitors.



5.4 MIXED DIELECTRIC STRATEGIES

Board-level capacitor values in common microelectronic systems cover a very widerange, from about 1 pF to many F. If a single dielectric is used for all integratedcapacitors, their areas would range over a million and their linear sizes would span

a thousand. If that dielectric were 1000 Å of Ta2O5, the 1 pF capacitors would beonly 22 microns on a side but the 1 F capacitors would be 21.7 mm. To achieve5% tolerance on the small capacitor, the plate widths must be controlled to abouthalf a micron, which is not practical for board-level patterning. At the other ex-treme, if 4 m BCB is used for all capacitors, the 1 pF would be 417 m to a side,which would require width control to about 10 microns for 5% tolerance, which isquite practical, but the 1 F would be very large (417 mm to a side). A capacitor over a foot wide could not be realistic even if split between several layers.

One solution is to combine two dielectrics, one with low k and one with high k ,

to cover the entire range of integrated capacitor values. The vast majority of capaci-tors will fall into a range that can be covered with this strategy, whereas the fewvery large energy storage capacitors, maybe larger than a few F, would be left assurface discretes. The dielectric for the low values could be the interlayer insulatingmaterial, which is available on the board already. As an example, consider the twodielectrics in the preceding paragraph: 4 m BCB with a specific capacitance of 0.575 nF/cm2 and 1000 Å of sputtered Ta2O5 that gives 212 nF/cm2 (Figure 5.8).Perhaps the BCB is being used as a dielectric for an HDI flex substrate. The capac-itor range requirement is 1 pF to 1 F.

As mentioned above, the smallest cap, 1 pF, will be 0.417 mm to a side andwould require a patterning reproducibility of 10 microns to achieve 5% value vari-ance. Since this is the smallest capacitor size required, switching over to the higher-k dielectric at this same size for the higher-capacitance material would minimize thetotal capacitor area on the board. A Ta2O5 capacitor 0.417 mm on a side would havea value of 260 pF. As a further benefit, the low-value capacitors are made with the

5.4 MIXED DIELECTRIC STRATEGIES 107

Figure 5.7 Relationship between patterning tolerance and capacitor tolerance.



thicker dielectric, which gives lower leakage in applications where that is impor-tant, such as RF functions and A/D conversion. A similar strategy could be em-

ployed with FR4 if it were made very thin. Intarsia used this approach for its built-up passive modules on glass. They used anodized Al2O3 with 0.5 nF/cm2 for largecapacitors and 5 m BCB for those under 5 pF [1].

5.5 CV PRODUCT

The CV product is a measure of the efficiency of a dielectric film to store charge.The voltage used is generally the rated voltage or the maximum voltage, which areconsiderably below the breakdown voltage. For a discrete capacitor, this is usuallyexpressed as CV per gram of internal dielectric and metal in order to reflect a massefficiency. For discrete capacitors based on anodized Ta powder, CV products of 80,000 F-V/gram are on the market. A capacitor filler with this CV product using1000 Å of anodized Ta2O5 and a rated voltage of 10 V would have a dielectric areaof about 38,000 cm2 per gram, a square almost two meters on a side. Since 1000 Åof Ta2O5 has a specific capacitance of 212 nF/cm2, this gram of material wouldhave a capacitance of 8000 F. For integrated capacitors, CV per unit area would

be more appropriate. That same 1000 Å of Ta2O5 rated at 10 V would have 2.12F-V/cm2. Other measures related to the CV product are found in the integrated ca-

pacitor literature, such as the product of specific capacitance and breakdown fieldor the product of dielectric constant and breakdown field.


Figure 5.8 Two dielectrics of widely separated specific capacitances may be used to cover a wide capacitor range with reasonable patterning requirements.



5.6 MAXIMUM CAPACITANCE DENSITY AND

BREAKDOWN VOLTAGE

A study by Rymaszewski and Jain uses an empirical correlation between the dielec-tric constant of a material and its breakdown voltage in order to suggest the limits of what is possible in capacitance density and maximum voltages for integrated capac-itors [2]. It has long been known that the breakdown voltage is lower for dielectricmaterials with higher dielectric constants. They plotted the two quantities from lit-erature [3] as shown in Figure 5.9 and determined that the maximum breakdownvoltage for a wide range of dielectrics can be fitted by the empirical relationship

E bd = MV/cm

where E bd = breakdown field, MV/cmk = dielectric constant

This data is for a wide range of film thicknesses and that combined with the factthat breakdown is defect driven probably accounts for the scatter below the line.The form of the empirical fit, kE 2bd = constant, implies that all the dielectrics will

have the same maximum energy density before breaking down, but the theoreticalreasons for this are unclear. Rymaszewski and Jain utilized this observation to pre-

20

k

5.6 MAXIMUM CAPACITANCE DENSITY AND BREAKDOWN VOLTAGE 109

Figure 5.9 The breakdown field is lower for materials with higher dielectric constants.



dict the limits of integrated capacitor performance. Remembering that the capaci-tance density is

= 0.885 nF/cm2

the following relations can be derived by eliminating t, k, or capacitance density:

V bd = 2000 Volts

V bd = 1770 Volts

V bd = 1880 Volts

whereC / A = specific capacitance, nF/cm2

k = dielectric constantt = thickness, m

V bd = breakdown voltage, Volts E bd = breakdown field = V bd /t , MV/cm

Finally, the area-specific CV product using the maximum breakdown voltage isfound to not be a function of film thickness since both capacitance and breakdownvoltage use thickness with opposite exponents. Remember that this relationship isfor the maximum observed breakdown voltages. Actual breakdown voltages are de-fect-driven and depend on the quality of the film and the roughness of the substrate.Also, it is more common to use the working voltage, which is derated from the

breakdown voltage by at least 50%:

= 1770 k

If the relationship between breakdown field and dielectric constant is true, thenthese equations provide the design space for deciding which dielectric to use(through the dielectric constant) and the film thickness to provide a given capaci-tance density at a required breakdown voltage. Referring back to the measured

breakdown data for Ta2O5 films in Chapter 4, Figure 4.12, it can be seen that theseequations predict a breakdown field at least twice as high as observed with500–2000 Å films of anodized Ta2O5 but are much closer for films thicker than 0.5m, in which defects would not be expected to play such a large role.

It must be emphasized that this is an empirical observation but is based on alarge amount of data from various sources reporting on films that are candidates for

nF Volts

cm2

CV bd

A

t

C / A

k

C / A

t

k

k t

C

A




integration. However, there are reports of data points that lie well above the line inFigure 5.9 [4].

REFERENCES

1. H. Clearfield, S. Wijeyesekera et al., “Integrated Passive Devices using Al/BCB ThinFilms,” In Proceedings of the 1998 International Conference on Multichip Modules and

High Density Packaging, IEEE Press, New York, p. 501, 1998.


3. L. Maissel and R.Glang, Handbook of Thin Film Technology, 1st ed., McGraw-Hill, New

York, chapt. 16, pp. 21–33, 1983.4. A. Kingon, North Carolina State University, private communication.

REFERENCES 111



113

CHAPTER 6

PROCESSING INTEGRATED

CAPACITORS

RICHARD K. ULRICH

The various dielectric materials for integrated capacitor applications were discussedin Chapter 4 with no regard to how these materials could be formed or how thick the films might be, and Chapter 5 was concerned with the footprint and dielectric

thicknesses required to reach specific values of capacitance and operating voltage.In this chapter, the overlay of effects brought about by the various fabricationmethodologies is added in. The sections in this chapter are organized around pro-cessing techniques—sputtering, anodization, CVD, MOCVD, spin-coating, sol–gel,

pulse-laser deposition, dry calcination, hydrothermal, etc.—and the various dielec-tric materials are listed in those sections. The integrated capacitor must be thoughtof not as an object, but as a technology with many facets, including composition,

processing, and resulting performance, all of which contribute to the acceptance or rejection of that technology for a given application.

The integrated capacitor literature was the primary source of information for thischapter although, from looking at the section headings, it might appear that thesource was actually everything ever published about capacitors. That is because al-most every dielectric material that can be made has been investigated for integratedcapacitor applications. This is indicative of how far away the field is from settlingon a few materials and processes based on a combination of performance, process-ability, and economics. A measure of progress in this area might be that this chapter may be much shorter in the next edition of this book. There are a large number of references in this chapter in order to enable the reader to access literature on the ap-

plications of specific dielectrics to integrated components.This chapter will concentrate on processes amenable to organic boards, which

means a maximum processing temperature of about 250°C. That is not to say thatdielectrics requiring high-temperature anneal cannot be used, just that the annealingmust be done prior to attachment to the organic material. An example of this would

be DuPont’s process of firing a ferroelectric dielectric onto the surface of Cu foil at



ISBN: 0-471-24431-7



900°C and then laminating that to FR4. This technology is also described since it isapplicable to organic boards.

6.1 SPUTTERING

Dielectric films from a few hundred angstroms to a few microns may be formed bysputtering. Almost all paraelectrics may be formed as useful dielectrics by sputter-ing with no further processing, but most ferroelectric films must be annealed at hightemperature following sputtering in order to achieve the correct crystallographicform and orientation to exhibit the very high k values of which they are capable [1].Metal oxide films can be achieved in two ways: by direct sputtering with a target

having the same composition as the desired film and by reactive sputtering, whichinvolves using a metal target and an oxygen-containing gas in the chamber. For re-active sputtering, the sputtered metal atoms will combine with oxygen in the gas

phase to form the oxide on the substrate. In practice, pure direct sputtering may behard to optimize since it may even be necessary to have some small amount of oxy-gen present to offset losses of volatile oxygen from the target out through the vacu-um pump. In either case, the deposition rate depends on many factors including RF

power density, gas pressure, gas composition, gas flow rate, chamber geometry, andtemperature. Sputtering has the advantage over CVD that it can generally be per-

formed at lower temperatures but has the disadvantages of requiring a hard vacuumand not giving as conformal a deposition.For sputtered dielectrics of any sort, the roughness of the bottom electrode is

critically important because steep slopes might not be sufficiently covered, result-ing in unacceptable leakage or even shorts. It is not a problem having to do with

peaks sticking up through a flat sea-like layer of sputtered material; sputtering is nota planar process. The concern is coverage of steep slopes of the rough bottom platemetal. Most investigations of implementing a sputtering procedure for integratedcapacitors end up being fixated on this issue in order to bring the yield up to accept-

able levels. As a result, obtaining acceptable yields for sputtered integrated capaci-tors with either dielectric type on Kapton and alumina substrates is more difficultthan it is on Si due to the inherently higher roughness of these materials [2–7].However, even over rough substrates, yield may be increased by utilizing plated Cu

bottom plates for which the plating conditions have been optimized to give asmooth surface [8].

Ta2O5 may be sputtered to make dielectric films with dielectric constants of around 23, which would give about 100 nF/cm2 for a 2000 Å film [8, 9]. SputteredTa2O5 can be somewhat compressive, but annealing in oxygen at 425°C for 30 min-

utes removes the stress and the film is still amorphous. Significant stress reduction begins around 200°C. Further annealing over 550°C gives polycrystalline Ta2O5

(orthorhombic) which has a much higher dielectric constant, nearly 50, but also has porous grain boundaries, allowing diffusion and penetration of etchants. Ta2O5 an-nealed in this way over Si lifted off after a few hours in BHF due to penetration of the liquid directly through the thin film, whereas nonannealed amorphous films

114 PROCESSING INTEGRATED CAPACITORS



withstood BHF for 100 hrs [10]. Direct-sputtered Ta2O5 may be oxygen deficient,so annealing in oxygen can regain proper stoichiometry and lower the leakage [11],or a higher partial pressure of oxygen in the sputtering chamber can be used. In or-

der to improve the leakage characteristics, nitrogen may be added to the deposits bysputtering from a Ta2O5 target in Ar mixed with N2. This addition lowers the di-electric constant but improves leakage characteristics [12–15].

There has been some noteworthy work on various mixtures of Ta2O5/TiO2 mate-rials to optimize the combination of dielectric constant, leakage, and breakdown.Table 6.1 shows the results of the pure components, a homogeneous mixture, and amultilayer composite consisting of sputtered alternating layers tens of Å thick. Thefilms were 2600 to 4000 Å so the leakage measurements at 0.50 MV/cm amountedto 13 to 20 V [16]. The heterogeneous alternating layers seemed to provide the

combined benefits of the high dielectric constant of TiO2 and the low leakage andhigh breakdown voltage of Ta2O5.Alers, van Dover, et al. have studied various amorphous materials as dielectrics.

The Zr-Sn-Ti-O system (aZTT) is a well-known microwave filter dielectric that isdeposited as an amorphous film with multitarget reactive sputtering at 200°C on Pt,Al, Au, and Ag electrodes. The best composition for capacitor dielectrics was foundto be Zr 2Sn2Ti6Ox, which gave k = 62, breakdown = 4 MV/cm, and leakage = 1nA/cm2 at 1 MV/cm. The addition of Sn was the factor identified as lowering theleakage current. This material contains only metals with volatile halides, so it can

be easily dry-etched. Because it’s amorphous, it is smoother than most ferro-electrics and can, therefore, be thinner. Another candidate is the class of Ti-lan-thanide rare earths–O systems, which might be easier to process since they are bina-ry alloys. An example of this is Ti0.9Dy0.1O2 which has a dielectric constant of 47, a

breakdown voltage of 3.5 MV/cm, and a leakage less than 10 nA/cm2 at 1 MV/cm,which is orders of magnitude lower than pure TiO2 films [17].

Sputtered thin film SiO2, SiO, and SiNx are used in integrated passive arrays andnetworks consisting of Si substrates on which either capacitor arrays or simple de-vices, such as RC terminators, are formed on the surface using front-end tech-

niques. These are usually packaged in the same manner as flip-chips and surfacemounted to the board. The combination of gang bonding and internal passive-to- passive connections provides cost and space savings over traditional SM discretes, but less than integrating all of the components into the primary interconnect board.

6.1 SPUTTERING 115

Table 6.1 Dielectric properties of sputtered combinations of Ta2O5 and TiO2

Leakage at BreakdownDielectric 0.5 MV/cm Voltage

Dielectric Constant (A/cm2) (MV/cm)Ta2O5 22 0.005 5.0TiO2 67 10 0.9Homogeneous composite 38 1.2 2.3Heterogeneous composite, alternating layers 44 0.034 2.3



These are low-capacitance-density processes, providing 10–20 nF/cm2 with 2000 Ålayers, which should have a breakdown potential of some tens of volts.

6.2 CVD, PECVD, AND MOCVD

CVD-based methods require that the reactants be introduced into a low-pressure re-action chamber as a gas. The activation energy for deposition is overcome by ther-mal means or by the high electron energy of plasma. Looking back at the list of po-tential dielectrics in the previous chapters shows that almost all of them containmetal ions, which are difficult to create in gaseous form. One way to get metals intothe chamber is in the form of a metallo-organic compound, which usually requires

expensive liquid bubblers or solid sublimers along with thermally wrapped tubingand careful temperature control. On the beneficial side, metallo-organics can be dis-sociated at a sufficiently low temperature to be used with organic boards. They areusually called metallo-organic CVDs (MOCVDs) in order to distinguish their spe-cial reagents and low-temperature processing. These compounds are available froma wide range of chemical product vendors but may cost hundreds of dollars per gram. MOCVD is considered to be one of the most expensive ways to deposit a thinfilm. It has been used to deposit Ta2O5 [18, 19] and mixed oxides of Bi2O3 andTa2O5 with dielectric constants of 20 to 40, depending on the Bi content, at 40–50

Å/min in a mixture of 60–90% gaseous oxygen and vaporized Bi(thd)3 and Ta(O-isopropoxide)4(thd), where thd is 2,2,6,6-tetramethyl-3,5-heptanedionato. Over very smooth substrates arising from single-crystal Si, the films can be made defect-free down to less than 100 Å and exhibit hundreds of nF/cm2 with leakage currentsof under 1 A/cm2 [20, 21]. The films are amorphous since they never see tempera-tures high enough to achieve even a polycrystalline state, and so the dielectric con-stants can never approach those of ferroelectric materials.

Diamond-like carbon can be deposited by more traditional CVD techniques.DLC refers to amorphous hydrogenated carbon, as opposed to carbon with a short-

range ring structure that is known as graphite-like carbon, and can be depositedwith PECVD using a RIE type configuration. The ion energy affects the propertiesof the resulting film; higher energies tend to give more graphitic carbon. DLC may

be etched in oxygen plasma. There are two varieties—hard and soft—and the hardDLC is, indeed, much harder and more resistant to scratching. Hard DLC may bevery leaky; 5 V over 1000 Å at 0.5 MV/cm gave almost 0.10 A/cm2, whereas theleakage through soft DLC was less than one nA/cm2. But the hard variety is moreresistant to mechanical damage. 1000 Å of CVD DLC gave 30–40 nF/cm2, whichamounts to a dielectric constant of 3.4–4.5 [22, 23]. DLC can also be deposited with

PECVD from methylethylkeytone. It was found to have better adhesion to Ti or Mothan to Cu so a few hundred angstroms of either was sputtered over Cu. The entirecapacitor stack was formed—bottom plate, dielectric, and top plate—then dry-etched all at once [24].

Combustion chemical vapor deposition (CCVD) involves dissolving the dielec-tric in a combustible solvent and spraying it as fine droplets with oxygen to make a




flame. Passing the substrate through the flame can deposit crystalline ferroelectricsdirectly, at lower cost than sputtering. 1000 Å/min of strontium titanate, k = 263, ata substrate temperature of 600–800°C has been reported [25]. Ta and Hf oxide

nanolaminates have been deposited by atomic layer CVD epitaxy in the form of six-teen layers alternating 30 Å of each. The resulting dielectric constant was the sameas Ta2O5 —23—but leakage was low at 5 A/cm2 for a 500 Å film at 5 V, whichgave 400 nF/cm2 and a TCC = 135 ppm/°C [26].

6.3 ANODIZATION

The aqueous-phase electrochemical oxidation of Ta is the most important method

of forming capacitor dielectrics today due to the combination of ease of processingand the excellent properties of the resulting dielectric [27–30]. Anodized Ta2O5 wasdescribed by Berry in 1959 [31, 32]. His writings, decades later, still provide useful

processing and property information on this ubiquitous system. The equipment,methodology, and kinetics for anodizing Al [33–35] and Ta are very similar, butthis section will concentrate on Ta since it provides a dielectric constant that is 2.7times greater.

All metals except Au form a thermodynamically stable oxide when exposed toeither oxygen or moisture and since this is an electrochemical oxidation reaction it

can be promoted by making the metal the anode in an electrochemical cell. A me-chanically stable and defect-free oxide may be formed this way if the resulting ox-ide is adhers to the underlying metal, has compressive stress, and is insoluble in theaqueous solution used in the cell. It is the same electrochemical reaction as corro-sion, except that the reaction product—metal oxide—remains on the surface insteadof dissolving or flaking off. The compressive stress serves to create crack-free filmsand is the normal result since the volume of oxide produced is nearly always greater than the volume of metal consumed. If the oxide is, instead, soluble and dissolves inthe electrolyte, the surrounding solution may become saturated, causing precipita-

tion onto the anode, resulting in a loose, porous oxide. Cadmium, zinc, and magne-sium exhibit this dissolution and precipitation behavior, and the resulting oxidecoatings are leaky and noncontinuous. Anodized Ta2O5 has been stretched by asmuch as 50% before breakage [36] . The film will continue to thicken as long as theapplied electric field is less than the breakdown field of the oxide but, once the crit-ical field is exceeded, pinholes and other defects will result. The metals capable of satisfying these conditions, listed in Table 6.2 [37], are known as “valve metals”due to the mildly rectifying properties of their oxides, as described later. The word“valve” refers to the old term for a vacuum tube, not fluid control devices. Al and

Ta have received by far the most attention over the decades as anodized dielectrics[38, 39].The procedure is quite simple. The metal to be oxidized is made the positive side

of an electrochemical cell by immersing it in a conductive solution as described be-low along with a cathode of a noble metal, such as Pt-coated mesh. The DC power supply should be capable of providing about 150 V and about 1 mA per cm2 of area

6.3 ANODIZATION 117



to be anodized. 2000 Å of film formation on Al or Ta can be accomplished in about20 minutes. The procedure is described in more detail below.

6.3.1 Benefits of Anodization for Capacitor Dielectrics

Anodized films are useful as capacitor dielectrics for several reasons. They may be

grown quite thin, a few hundred angstroms, without defects because thin spots inthe oxide have lower local resistance, which results in higher anodization currents,whereas thick spots will have higher resistance. As a result, thin spots grow faster and thick spots slower, resulting in a uniform, defect-free film. Also, the final thick-ness is mainly a function of the voltage used in the electrochemical cell, which iseasily set, and is only weakly affected by the processing time, composition of the

bath, temperature, and current. [40–44]. Anodization avoids the substrate roughness problem inherent with sputtering since a thick layer of anodizable metal can be deposited and the anodization procedure can be controlled to convert only enough

metal into dielectric as is necessary to achieve the desired specific capacitance[45–50]. Therefore, the composition or roughness of the capacitor bottom platemetal underlying the anodized metal is not an issue and this approach avoids havingto planarize and monitor the state of the bottom electrode. The apparatus is quite in-expensive, uses safe chemicals, and produces almost no toxic waste products. Also,films formed by electrochemical means are inherently stochiometric, whereas sput-tering may require careful control of the chamber gas composition and conditions to

produce balanced oxides.

6.3.2 Film Formation During Anodization

Anodized films are formed by a chemical reaction of a species already present onthe surface, the metal, and oxygen from water in the aqueous solution. The electro-chemical reaction at the anode is


Table 6.2 Anodizable valve metals with their dielectric constants

Dielectric ConstantMetal Oxide of Oxide

Aluminum Al2O3 9Zirconium ZrO2 12Bismuth Bi2O3 18Antimony Sb2O3 or Sb2O4 ~20Tantalum Ta2O5 23Titanium TiO2 40 Niobium Nb2O5 41Tungsten WO3 42Hafnium HfO2 45



2 Ta + 5 H2O Ta2O5 + 10 H+ + 10 e –

The electrons are returned to the solution at the cathode where they reduce H+ to

hydrogen gas, preventing the pH from changing appreciably. It is improper to saythat anodized films are “deposited” because only the oxide part is; they are “grown”or “formed.” Some thickness of metal is consumed in order to form a given thick-ness of metal oxide, and this ratio is important in determining how much metal must

be present initially to achieve a certain amount of oxide. At 100% current efficien-cy, Faraday’s law gives the rate of oxide growth:

=

where z ox = oxide thickness, cmt = time, seci = current density, A/cm2

n = number of electrons given off in the half reaction at the anode (6 for Al, 10 for Ta) F = Faraday’s constant (96,500 coulombs/mole of electrons) M ox = molecular weight of the oxide, gms/mole (102 for Al, 442 for Ta)

ox = density of the oxide, gms/cm3 (3.99 for Al2O3, 8.2 for Ta2O5)

Therefore, 1 mA/cm2 will give an oxide growth rate of 265 Å/min for Al and 335Å/min for Ta. Although it is possible to grow films of a given thickness by countingthe number of electrons that went into forming it, in practice it is actually easier than that because the final thickness can be set according to cell voltage, as will bedescribed later.

Taking as a basis 1 cm2 of surface area, the thickness of metal consumed to makethe oxide contains the same number of Ta atoms that end up in the resulting oxide

film thickness in the same area:

z Ta = 2 z TaO atoms of Ta/cm2

where z Ta = thickness of Ta metal consumed to make oxide, cm Ta = density of Ta metal, 16.7 gm/cm3

M Ta = molecular weight of Ta metal, 181 gm/mole2 = each molecule of tantalum oxide contains two atoms of Ta z TaO = thickness of Ta2O5 grown, cm TaO = density of Ta2O5 oxide, 8.2 gm/cm3

M TaO = molecular weight of Ta2O5 oxide, 442 gm/mole

TaO

M TaO

Ta

M Ta

M ox

ox

i

nF

dz ox

dt

6.3 ANODIZATION 119



So the ratio of Ta2O5 formed to Ta metal consumed is 2.49, which means that an-odizing one nm of Ta will produce a film 2.49 nm thick that will protrude 1.49 nmabove the original surface (Figure 6.1). A similar analysis indicates that 1 nm of Al

will form 1.28 nm of oxide, which will protrude 0.28 nm above the original surface.The mechanism of anodization is complex and not fully understood, but there is

strong evidence that the rate-controlling step is the migration of ions within the ox-ide film. The main support for this is that the amount of current induced during an-odization is linear with voltage and not exponential as would be expected from ki-netic control. Also, agitation of the fluid has no effect on the rate of anodization andthe anodizing solution also has little effect as long as it is sufficiently conductive to

place ohmic current control in the film and not in the solution and does not chemi-cally attack the film. Al anodization requires pH values between about 6 and 9 since

the metal dissolves in strong acids and strong bases, but Ta may be anodized over amuch wider range [49].

6.3.3 Ta Anodization

During anodization, hydrogen is liberated at the cathode and some bubbles will beseen near the anode, so an agitator should be used to prevent bubbles on the anodefrom hindering film formation. Films anodized from bcc Ta are soft and may crack upon anodizing; those from beta Ta are better. The bcc form is also known as the

“alpha” form, the same as bulk metal, and, like most materials, has a resistivityslightly higher than the 14 -cm bulk value at 20–40 -cm. The “beta” form iseasily formed by sputtering, especially under conditions that exclude contaminants.This is a tetragonal form with the same density as bcc but considerably higher resis-tivity and gives better anodized films. It has a much higher resistivity of 180 -cm and is unknown in bulk form [51].

The final film thickness is directly proportional to the final voltage used in thecell (Figure 6.2). Thus, the dielectric thickness can be dialed in with the electro-chemical cell’s voltage control. For Ta, the constant of proportionality is 16 Å/V

and for Al it is 3.5 Å/V so that a 2000 Å Ta2O5 film requires 2000/16 = 125 V. Themaximum thickness of anodized films is limited by voltage-induced breakdownduring anodization. A change in film color can make this apparent even during an-


Figure 6.1 Relative thickness of tantalum oxide formed by anodization and tantalum metalconsumed.



odization. Lower-conductivity solutions allow thicker films [52]. Some manufac-turers, such as AVX, use the concept of a “formation voltage,” which is set at 3.5times the required working voltage for Ta. If a working voltage of 20 V is required,

the anodization would be carried out at a final voltage of 70 V, resulting in a filmthickness of 70 × 16 = 1120 Å and a specific capacitance of about 180 nF/cm2. At-tainable film thicknesses are given in Table 6.3.

6.3.4 Dielectrics from Anodized Ta

Leakage currents and breakdown voltages for anodized Ta films are shown in Fig-ures 6.3 and 6.4.

Anodized oxides are mildly rectifying, exhibiting lower leakage currents in the

direction of the original anodization current, as shown in Figure 6.5 [54].

6.3 ANODIZATION 121

Figure 6.2 Film properties of anodized Ta2O5 as a function of final cell voltage.

Table 6.3 Metals that can be anodized to give nonporous adhesive oxides [53]

Ratio of Final Maximum FilmThickness to Thickness Attainable

Dielectric Final Voltage by AnodizationMetal Constant (Å/volt) (m)

Al 9 3.5 1.5

Ta 23 16 1.1 Nb 41 43Ti 40 15Zr 12 12–30Si 3.7 3.5 0.12




Figure 6.3 Leakage current through anodized Ta2O5 at 5V.

Figure 6.4 Breakdown voltage of anodized Ta2O5.



Nitrogen is one of the most common dopants for tantalum films and has beenwell characterized because of the wide use of TaN as a thin-film resistor material.Upon anodization, it gives an oxynitride dielectric [55–57]. The addition of nitro-

gen to the thin film makes the capacitors more stable to heat, especially in combina-tion with oxygen, but the disadvantage is loss of capacitance. Carbon doping seemsto penalize capacitance to a lesser extent, retaining between 70 and 90% of the ca-

pacitance density compared to undoped tantalum oxide.

6.3.5 Patterning Ta and Ta2O5

Ta metal and Ta2O5 are only effectively wet etched at room temperature by mixturesof hydrofluoric and nitric acid. 5% HF at room temperature etches Ta2O5 at 320 Å/hr,

increasing semilogarithmically to 1400 Å/hr at 50% [58]. Table 6.4 shows somecommon etchants for this system and some of the expected collateral rates [59].

Both Ta and Ta2O5 may be rapidly dry etched with SF6 and oxygen in an RIE atabout the same rate. Barlow has studied the conditions in a PlasmaTherm etcher andfound this optimum set:

Power = 150 watts

Pressure = 250 mTorr

Etch time = 3 min

O2 flow rate = 35 cm3(STP)/sec

SF6 flow rate = 30 cm3(STP)/sec

The resulting etch rate for both films was 970 Å/min with a uniformity of 0.03%across a 5 inch wafer. The surface roughness of partially etched Ta2O5 was less than

6.3 ANODIZATION 123

Figure 6.5 Leakage current is lower in the direction of the anodization current for 1200 Åof anodized Ta2O5.



2 Å. Thick photoresist can be used as a mask and the etch rate of this process on Alis almost zero, enabling it to be used as either a mask or an etch stop.

6.3.6 Ferroelectrics by Anodization

BaTiO3 has been made by anodization without a high-temperature anneal but, to

date, with poorer dielectric properties than sol–gel films that were subsequentlythermally cured. Also, the solution must be very alkaline—as high as pH 14 [60,61].

6.4 SOL–GEL AND HYDROTHERMAL FERROELECTRICS

Sol–gel involves the application of a thin layer of a liquid-phase metallo-organiccompound followed by thermally induced removal of the organic portion, leaving

a metal oxide behind. Sol–gel processes allow for the deposition of films witha high degree of chemical homogeneity at relatively low temperatures. The process starts with organometallic compounds such as metal alkoxides that aredissolved in alcohol to give a homogeneous solution. Various forms of titaniumalkoxides are widely used to form titanate films along with other elementalsources such as barium hydroxide for BaTiO3, lead acetate for lead zirconate ti-tanate, etc. The solution or “sol” is subsequently gelated by a hydrolysis reactionwith water or exposure to the atmosphere. The gelation forms a polymeric net-work or a colloidal network. Many factors influence the gelation: the nature

(acidic or basic) and concentration of the catalyst, the amount and composition of solvent, and the sequence of mixing. The gel is amorphous and mechanicallyweak because it has continuous pores and trapped organics, water, and hydroxylgroups. Thin-film coatings are typically obtained from polymer solution deposi-tion techniques such as dip-coating or spin-coating. Heat treatment and densifica-tion of the gel form the final film. The high surface area of the dried gels results


Table 6.4 Wet etchants for Ta and Ta2O5

Etchants Metal/Oxide Etch Rate (Å/min)

2.0% HF and 0.5% HNO3 (Ti Etch) Ti 4800Ta <3Ta2O5 8.6

4.0% HF and 0.7% HNO3 Ta 638.0% HF and 0.5% HNO3 Ta 830

Cu 480SiO2 >10,000

8.0% HG and 0.7% HNO3 (Ta Etch) Ta 8602.5% CH3COOH, 2.5% HNO3, 1.0% H2SO4, Ta <1.4

and 94.0% H2O



in very high reactivity, which in turn results in a relatively low-temperature process compared to conventional ceramic processes that involve sintering of mi-cron-sized particles. It has been demonstrated for both thin-film high-k capacitors

and low-k dielectrics.Sol–gel can be a low-cost technique yielding high dielectric constant films

compared to sputtering and CVD since it requires less equipment and no vacuumsteps. However, the temperatures required to form crystalline films to give k >1000 are typically higher than 500°C. Films formed at temperatures less than400°C may result in dielectric constants less than 100. Alternately, the films can

be formed at higher temperatures separately on a copper foil and then integratedinto the organic substrate. The “sol” can also be mixed with polymers to formnanoscaled ceramic–polymer-composite high-k films. In general, the electrical

properties of sol–gel high-k films are not yet well characterized [62]. The liquidmay be spun on or blade coated followed by a partial cure at around 300°C, whichturns the liquid into a very viscous and adherent gel. This procedure can be re-

peated to give thicker final dielectric materials and to decrease defect density.Each coating will result in only about 0.1 m; film thickness over a micron is

prone to stress cracking. After all coating steps, a final cure at 600–700°C givesthe cubic perovskite crystal structure needed for high-k materials [63–72]. Leadzirconate titanate (PZT) sol–gel technologies based on 1,3-propanediol enablethicker films, up to 1 m at a time. The resulting 0.50 micron films are 2000

nF/cm2

, twenty times that possible with anodized Ta, with a breakdown voltage of 1.3 MV/cm (65 V). These films show all the characteristics of ferroelectrics: de-crease in k with bias and frequency as well as profound temperature effects [72].These final cure temperatures are too high for organic boards, but sol–gel is worthmentioning due to the ability to achieve high capacitance at little expense. Perhapsa way can be found to either reduce the cure temperatures through rapid thermal

processing or to mount precured coupons, such as layers of copper coated with di-electric, onto organic boards.

Hydrothermal treatment involves dissolution of reactants and precipitation of

crystalline compounds in hot, pressurized water. It is a standard technique to formfine powders with superior physical and chemical properties. The raw materials aretypically similar to those used in the sol–gel process. A subsequent hydrothermaltreatment of the sol can assist in the formation of thin films at lower temperatures.Water serves as a pressure-transmitting medium and also accelerates the kinetics.More importantly, the presence of water enables reactions to take place at lower temperatures because the free energy of hydrated ions is similar to that of crys-talline BaTiO3. These unique process characteristics enable formation of crystallineceramics at temperatures <100°C. The reactions are carried out in closed vessels,

typically under strong alkaline conditions. The bath conditions such as temperature,alkalinity, etc. can be predicted from the theoretical phase-stability diagrams of therelevant systems. The phase diagrams provide a thermodynamic basis for the for-mation of films. Hydrothermal synthesis of BaTiO3 films need a bath of pH >13.The film growth is dependent on the type of substrate. Substrates with structurescloser to the films allow easier nucleation and growth of defect-free films. For the

6.4 SOL–GEL AND HYDROTHERMAL FERROELECTRICS 125



formation of BaTiO3, Ti-sputtered substrates, Ti foils or titanium-alkoxide-coatedsubstrates are treated in Ba(OH)2 solution. The temperature can be less than 80° for crystalline film formation. These films are typically porous and show microcrack-

ing, resulting in poor yield. Films formed on Ti foils at temperatures of 90°C yield-ed capacitance of 1.5 microfarad/cm2. Significant process development and filmcharacterization is needed to yield reliable BaTiO3 films from hydrothermal tech-niques [73].

6.5 THIN- AND THICK-FILM POLYMERS

Many polymer materials are available for application by spin-on or various panel-

coating methods with a subsequent cure that is easily tolerated by organic sub-strates. These materials will be suitable only for the smallest-valued capacitorssince the highest polymer dielectric constant known is only about 12. Both BCB(benzocyclobutene) and polyimide are available as spin-on or castable resins thatcan be formed as thin as a micron or layered to indefinite thicknesses. The high-est practical specific capacitances achievable are 2.4 nF/cm2 for BCB at k = 2.6and 3.3 nF/cm2 for polyimide at k = 3.7, both at 1 micron [74]. Polyester filmlaminated on FR4 gives around 0.1 nF/cm2 [75]. Avatrel dielectric polymers fromDuPont are really designed as an interlayer dielectric, and so are tailored for low

k of 2.6, low dielectric loss of 0.2%, good adhesion, low moisture absorption, andstable properties [76]. Other polymeric materials such as epoxies, thermoplastics,and fluorocarbons would all perform in a similar manner (Table 6.5). On the plusside, their dissipation factors tend to be low, much lower than high-k ferro-electrics, which makes them more suitable for small-valued RF applications thatrequire low losses. Making a pF-sized capacitor from a high-k material might re-sult in a component that is too small to achieve good tolerance. Polymer di-electrics may absorb moisture (k = 78), which typically increases both k and thedissipation factor. Breakdown voltages are the same as most metal oxides at

around 1–5 MV/cm. They may be applied in multiple thin layers to decrease thedefect density to negligible values.


Table 6.5 Dielectric properties of some thin-film polymers

Dielectric Dielectric Constant Dissipation Factor (%)

Mylar 2.0 0.02

Polystyrene 2.6 0.01BCB 2.6Parylene 2.7 0.01–0.1Polycarbonate 3.1 0.1Mylar 3.2 0.4Kapton 3.7Epoxies 4–6 0.4–0.7



6.6 THICK-FILM DIELECTRICS

The attractive feature of thick-film processing for resistors, capacitors, or intercon-

nects is that they can be printed on and cured in place with no patterning, photolith-ography, or waste. The resulting capital and operating cost should be much lessthan for subtractive processes, especially those involving vacuums.

6.6.1 Ferroelectric Powder Dispersed in Polymer

This is one of the only dielectrics developed specifically for integrated capacitors.Its development was motivated by low cost and ease of processing, but may be near its limit of specific capacitance. Almost any high-k ferroelectric material can be

produced in quantity as submicron powders. For example, BaTiO3 can be made bythe dry calcination of BaCO3 and TiO2 at >1200°C, resulting in particles well under a micron in diameter with dielectric constants in the thousands. These high-k parti-cles can be mixed with a polymer resin such as epoxy or polyimide at up to 60–80%loading by volume, then screen printed, spun-on, or stenciled onto the substrate,and the polymer phase cured at temperatures quite tolerable to organic boards. Mul-tiple printings can eliminate pinholes. The mixing rules for composites of two mate-rials with different dielectric constants are, unfortunately, such that the dielectricconstant of the final composite will be much closer to that of the low-k material,

which is generally the polymer with a k of about 3 to 5. The overall dielectric con-stant will end up being around 30–100. The result is a film as thin as 5 microns thatcan be screen printed cheaply, made pinhole-free, and delivers in the low tens of nF/cm2. Dissipation factors are more typical of the ferroelectric powder, rangingfrom 1–7% [77–87]. This method is not suitable for paraelectric powders becausethe mixture of these much-lower-k powders with polymer would have about thesame dielectric constant of the polymer alone. The advantage of this approach isthat much of the processing, and all of the high-temperature steps necessary to gethigh k from the ferroelectric phase, can be done in advance of application to the or-

ganic substrate. Application is additive and the dielectric is applied only where it iswanted so there is no patterning and little waste. No vacuum equipment is required.Because the films are thicker than sputtered, sol–gel, or CVD films, the workingvoltages are higher, on the order of hundreds of volts. However, screen printing or stenciling is not amenable to tight tolerances. Also, the highest composite dielectricconstants reported to date do not exceed 100 and films thinner than a few micronsare very difficult to produce with good tolerance, so the maximum capacitance den-sities are around 20–30 nF/cm2. Finally, once the ceramic loadings approach 85%

by volume, which amounts to about 98% by weight, adhesion to the metal elec-

trodes is very poor, resulting in air gaps and lowered capacitance [88].Figure 6.6 shows typical results of mixing lead magnesium niobate-titanate plus barium titanate (k = 17,800) with a polymer, in this case photodefinable Ultradel®

7505 from Amoco (k = 3) for 100 hrs in a ball mill, spin coating to 1.1 m, and cur-ing at 225°C. After curing and with 35% filler, 4 mil vias could still be made. Evenat 60% loading, less than 1% of the dielectric constant of the high-k phase wasachieved.

6.6 THICK-FILM DIELECTRICS 127



There are several semiempirical equations that relate the dielectric constants of the filler and binder along with the volume fraction filler to give an overall compos-ite dielectric constant [89]. The Lichtenecker logarithmic law of mixing is popular:

log k comp = (1 – n)v f log k f + (1 – v p)log k p

wherek comp = dielectric constant of the composite of materials 1 and 2v f = volume fraction of high-k filler in the compositev p

= volume fraction polymer in the compositen = a constant between 0 and 1

Most models break down at high loading, above maybe 60%, probably due to imperfect particle dispersion or voids in the matrix. With decreasing particle sizes, theinfluence of the particle/polymer interface becomes more important due to the high-er ratio of surface area to volume for the filler. Particle aggregation rather than uni-form dispersion becomes a problem due to the difference between the hydrophobic

polymer and hydrophilic ceramic particles, leading to difficulties in forming uni-form thin films. Various surfactants are under investigation to prevent this, but thesurfactants themselves may influence the dielectric constant [90]. The highest pos-sible packing density for single-diameter spheres is 74% with the hexagonal close-

pack arrangement. To see an example of this, go to the grocery store and look athow the oranges are stacked; every grocer knows how to do hexagonal close pack.The only way to get higher filler fractions than this is to use multiple-diameter


Figure 6.6 Dielectric constant and dissipation factor as a function of fraction ferroelectricfiller in a polymer matrix.



spheres so that the small ones fit in between the big ones, but this exacerbates prob-lems, with particles agglomerating into clumps. It is difficult to print films thinner than a few microns, especially when highly loaded with solids. Spin coating is pos-

sible, even at 60% by volume, to a thickness of 1–5 m. The CTE of 60 vol% of BaTiO3 in epoxy has been measured at 17 ppm/°C, a value conveniently close tothat of Cu metallization and FR4 board materials [91].

The dielectric constant of the filler is certainly high enough, so developmentstrategies for filled polymers have centered on increasing the fraction of filler in thecomposite, decreasing the cured film thickness, and increasing the dielectric con-stant of the polymer binder. In one study, 0.90 m PMT-PT (lead magnesium nio-

bate-titanate) and 0.065 m BaTiO3 was mixed in a 3:1 ratio to optimize the filler packing. This was mixed with an epoxy with k = 3 in a ball mill for four days to

achieve up to 80% by volume. Viscosity adjustment was obtained by adding sol-vents (NMP). The resulting composite had a dielectric constant of 82 at 10 kHz anda specific capacitance of 7.3 nF/cm2. Other projects have concentrated on increas-ing the dielectric constant of the polymer. 68% volume loading of PMT-PT in anepoxy of k = 3–4 gave an overall k of 74. But the addition of cobalt acetylacetonate(Co-acacs) to the epoxy raised its dielectric constant to about 6, enabling an overallk of 98 at 79% loading. This is the highest dielectric constant found in literature todate. Metal-acacs materials contain a structural group that is commonly used as acuring catalyst for epoxies. As mentioned in Chapter 4, ions that are permitted to

move some distance in the dielectric provide a very high degree of polarizability;this is the mechanism that gives ferroelectrics their very high dielectric constants.The idea here is that the metal ion would be left behind by the Co-acacs after poly-mer cure and provide some of that ionic polarization mechanism to the otherwisevery low-k epoxy material. In that study, it was added to the epoxy resin at up to 5%

by weight and 10 m layers of this material were spin-coated and cured at 100°Cfor 10 min, then up to 180°C for 1 hour for final cure. Gold top and bottom plateswere used. The resulting films were 25 nF/cm2 [92, 94].

Although the dielectric constant of the composite is much closer to epoxy than to

the ferroelectric filler, large instabilities characteristic of ferroelectric materials arestill seen from temperature, frequency and voltage excursions [94]. Figure 6.7shows the decrease in dielectric constant with frequency for a BaTiO3/epoxy com-

posite dielectric, a behavior characteristic of ferroelectrics.

6.7 INTERLAYER INSULATION

The FR4 or flex insulation material used to separate interconnect, power, andground layers has a low specific capacitance but costs very little since it is thereanyway. When placed between power and ground planes, some degree of decou-

pling can be obtained due to the large area. Two mils of FR4 at k = 4.8 would giveonly 0.085 nF/cm2 but on a 1 ft2 computer-sized board would amount to around 80nF. There is some work in progress in creating specialty layers for lamination thatmight include BaTiO3 powder, increasing k to around 25 [95].

6.7 INTERLAYER INSULATION 129



6.8 INTERDIGITATED CAPACITORS

Very small values of capacitance can be obtained by interdigitating interconnectmaterial, which will provide about 0.05–0.10 pF/mm. Figure 6.8 shows measure-ments from interdigitated 10 micron lines. Design of this approach can be com-

plicated by floating plate capacitance between these structures and metallizationon other layers. Due to the low area efficiency, this may only be useful for sub-pF


Figure 6.7 Loss of dielectric constant with frequency for a BaTiO3/epoxy composite di-electric.

Figure 6.8 Capacitance from interdigitated conductors.



values that would be difficult to achieve by patterning a dielectric to acceptabletolerance.

6.9 CAPACITOR PLATE MATERIALS

Naturally, the first choice for the capacitor plate material would be the same metalused as the interconnect, typically Cu or Al. Not only is it already present, it also haslow resistivity. If the contacts are both along the same edge, the current goes, on theaverage, one third of the way out and one third of the way back. That, plus spreadingresistance, amounts to about one square of resistance for a square integrated capaci-tor, about 10 m for 2m sputtered Cu or Al. If anodized Ta is used, it might appear advantageous to use Ta as the plate material, but the sputtered form of Ta almost al-ways obtained is the beta, or tetragonal, structure that has a high resistivity—180-cm. This gives significantly better anodized films than the more conductive bcc

bulk form. The downside is that beta Ta is 100 times less conductive than Cu or Aland is that much less suitable as a bottom plate. Therefore, it is usually necessary tohave a more conductive metal under the Ta that is anodized. No matter what metal isused as the bottom plate, it is best to deposit more Ta than will be anodized since thisremoves much of the influence of any underlying roughness. For example, 2000 Å of Ta may be deposited over Cu or Al, then anodized to an anodic potential of 63 V,which will consume 400 Å of Ta to make 1000 Å of Ta2O5, giving a dielectric with212 nF/cm2 and leaving 1600 Å of unanodized Ta to screen the roughness of the bot-tom plate. There is little reason to deposit only the required amount of Ta since thethickness of the oxide is easily controlled by the anodization voltage at 16 Å/V.Anodization of Al does not require a separate underlying bottom plate metal, of course. Another reason to have more Ta than is required for anodization is that con-tact with Al may reduce the TaO to Ta metal since the Al has a greater affinity for oxygen. This oxygen leaching can occur due to the high temperatures of subsequent

polymer cure cycles. A thin barrier of TaN in between the Al and Ta can prevent thisif it is necessary to anodize all of the Ta. W and Mo are also compatible with TaO and

may provide a diffusion barrier [96, 97]. TaN can also be anodized, making it muchless prone to oxygen loss, but at some cost of lower dielectric constant.

The choice for the bottom electrode for ferroelectrics is often restricted tononoxidizable materials such as Pt or Au, which can add complexity and expensewhen using ferroelectrics. More common metals, such as Al or Cu, can react duringthe high-temperature anneal to form their own oxides which, for thin dielectrics,will dominate the overall dielectric constant of the two layers. Pt is popular as the

base electrode because, in addition to thermodynamic stability, it has a high Schot-tky barrier and, therefore, a lower leakage for thin films [98].

6.10 TRIMMING INTEGRATED CAPACITORS

As described in Chapter 3, integrated resistors can be trimmed to higher values bycutting the resistor material with a laser. By cutting across the resistor, the current

6.10 TRIMMING INTEGRATED CAPACITORS 131



path is effectively increased and, depending on the length of the cut, the resistancecan be adjusted to any value on a continuous basis. However, capacitance is arearuled and it would require the removal or addition of top or bottom plate sections to

bring about trimming. This could be done on a continuous basis in principle but notechnologies have been demonstrated to date. A technique used for many years inhybrid microelectronics involves the removal of trim tabs, as shown in Figure 6.9,enabling the capacitance to be adjusted downward in steps.

6.11 COMMERCIALIZED INTEGRATED

CAPACITOR TECHNOLOGIES

A few integrated technologies for capacitors are either commercialized or close to it(Table 6.6) [99]. These can produce singulated capacitors for one-to-one replace-ment of discrete components or can be left as a continuous layer between power andground planes for integrated decoupling, replacing many discretes at once.

6.11.1 DuPont InterraTM

DuPont is developing a high-k integrated capacitor process called Interra™ that in-volves firing a screen printed ferroelectric paste on one side of Cu foil at 900°C,then firing a Cu-based paste over that to form a 3 m top plate, and flipping thestack onto FR4. The foil is then patterned to electrically separate the plates andform the interconnects, as shown in Figure 6.10 [100–102]. Two separate dielec-tric printings and firings are performed to eliminate pinholes, resulting in a 20–40

m total thickness. The dielectric is a formulation based on a doped barium ti-tanate plus a glass that is compatible with board-level etching processes and doesnot dissolve the barium titanate phase during firing. The resulting dielectric con-stant is in excess of 1000, yields a capacitance density up to about 44 nF/cm2 andexhibits temperature, frequency, and voltage behavior characteristic of ferroelec-


Figure 6.9 Trim tabs for adjusting capacitance.



tric materials. The dissipation factor is 1.1–1.5% at 100 kHz and the breakdownvoltage is 900–1200 V. From here, the board may be further processed to add oth-

er layers of conductor and even other layers of capacitors. Ceramics are weak intension and strong in compression, so the most important processing precaution isto avoid putting the capacitors under tension during lamination. If provided asclad copper foil, this might be processible by board shops using standard equip-ment.

6.11.2 3M C-Ply

3M’s C-Ply is a dielectric sandwiched in between two layers of Cu foil, typically

one ounce. The foil can be patterned and included in an FR4 build for decoupling or as singulated integrated capacitors. The dielectric is barium-titanate-filled epoxywith k = 15–23 and a thickness of 8–23 m to give 1.6 nF/cm2 with a 0.45% dissi-

pation factor [103]. If provided as clad copper foil, this might be processible by board shops using standard equipment.

6.11.3 DuPont HK ™

DuPont’s HK ™ laminate is a board-wide embedded planar capacitor material de-

signed for use between the power and ground planes of FR4. The HK ™

productfamily consists of unfilled and ferroelectric-filled polyimide laminated as a double-sided material with copper thicknesses from 18 m (½ oz) to 72 m (2 oz). Thick-er copper is available on special request. The dielectric constants range from 3.4 to15 and thickness from 8 to 25 m, which allows for capacitance densities ranging

6.11 COMMERCIALIZED INTEGRATED CAPACITOR TECHNOLOGIES 133

Table 6.6 Summary of integrated capacitor technologies either commercialized or under development

Supplier

Licensed fromDuPont 3M DuPont Sanmina

Trademark Interra™ C-Ply HK ™ BC2000™

Dielectric material and Fired ferroelectric Cu-clad Cu-clad Cu-clad FR4capacitor configuration paste on Cu foil BaTiO3 polyimide

in epoxy (filled or unfilled)

Specific capacitance ~44 1.6 0.12–1.6 0.07(nF/cm2)

Loss tangent (%) 1.5 0.45 Unfilled 0.3 ~1Filled 1.0

Dielectric constant 1000 15–23 3.4–15 4Thickness (m) 20 8 8–25 50



from 0.12 nF/cm2 to 1.75 nF/cm2. This range of products permits use of these lami-nates for removing decoupling capacitors, reducing impedance, and reducing EMIfor high-speed applications. Dissipation factors are approximately 0.3% at 1 MHzfor unfilled products and rises to 1% for filled organics. Breakdown voltage rangesfrom a low of 1000 V/mil for highly filled offerings to a high of >6000 V/mil for unfilled products such as Interra™ HK 042536.

Because the unfilled materials are low-k paraelectrics, their dielectric constantsare very stable with regard to temperature (<2% from –55 to +125 deg. C), frequen-cy, and voltage. They may be processed as thin flexible laminates with drop-in pro-


Figure 6.10 DuPont Interra™ prefired integrated capacitor process for FR4.



cessing conditions within typical PWB processes. Most products will permit copper removal from both sides simultaneously.

6.11.4 Motorola’s Mezzanine Capacitor

Motorola has partnered with Vantico AG to develop a polymer material filled withhigh-k ceramic particles to be used on FR4. It is called Probelec™ CFP. The dielec-tric is a positive-acting photodielectric formed by roller coating, lamination, andsolvent developing to form an embedded capacitor between the FR4 core and theHDI outer layer, which gives the concept the name “mezzanine capacitor.” Becauseof the positive-acting chemistry, the top electrode can be used as the mask, resultingin a self-aligned dielectric and top plate. The cured dielectric has a dielectric con-

stant of about 21 and a thickness of 12 m, for a capacitance density of 1.7 nF/cm2

[105]. Typical of the ferroelectric-containing polymer thick-film dielectrics de-scribed earlier in this chapter, it exhibits a dissipation factor of 2–3%, considerablyhigher than paraelectrics, and shows more dependence on frequency and voltage aswell. Measured tolerances were about 15%.

6.11.5 Sanmina BC2000™

Sanmina Corporation produces a 2 mil thick glass-reinforced epoxy called

BC2000™

for use as a board-wide decoupling capacitor with a specific capacitanceof about 0.068 nF/cm2. Research is underway to develop a 1 mil version to increasethe capacitance.

6.11.6 nChip

nChip of San Jose, California was an early pioneer of MCM-D technologies. Theydeveloped and produced MCM-D configurations of SiO2 and Al on Si substrateswith chips and some discretes mounted on the surface. They anodized the surface of

the Al power plane, and then deposited the ground plane over that to form an inte-grated decoupling layer with a specific capacitance of around 55 nF/cm2. This process was part of their nC1000 technology and was used to build several com-mercial modules [105]. nCHIP was purchased by Flextronics and no longer pro-duces MCM-D substrates.

6.12 SUMMARY

Of the large number of dielectric materials and processes that have been demon-strated for integration, a few are now coming onto the market, mainly for FR4 sincethis is the dominant board material in consumer systems. As flex and HDI increasetheir penetration into the consumer market, more of these technologies should ap-

pear, particularly those associated with thin films and requiring vacuum processes.Table 6.7 provides a comparison of the techniques described in this chapter.

6.12 SUMMARY 135



136

T a b l e 6 . 7

S u m m a r y o f i n t e g r a t e d c a p a c i t o r t e c h n o l o g i e s

M a x i m u m

S p e c i f i c

C a p a c i t a n c e

P r o c e s s

M a t e r i a l s

( n F / c m

2 )

A d v a n t a g e s

D i s a d v a n t a g e s

D e v e l o p m e n t S t a t u s

S p u t t e r e d

S i O 2 , A l 2 O 3 ,

L o w h u n d r e d s

W e l l - e s t a b l i s h e d p

r o c e s s a n d

R e q u i r e s v a c u u m p r o c e s s i n g

C o m m e r

c i a l i z e d i n

p a r a e l e c t r i c s

T a 2 O 5 , T i O 2

m a t e r i a l s , f r o m

f r o n t - e n d

V e r y s e n s i t i v e

t o u n d e r l y i n g

i n t e g r a t e d p a s s i v e

t e c h n o l o g i e s

r o u g h n e s s

a r r a y s

a n d n e t w o r k s

M a n y c o m m e r c i a l i z e d

C e r a m i c t h i n f i l m s m a y b e

D e m o n s t r a t e d o n F R 4

p r o c e s s e s

f r a g i l e o n F R 4 o r f l e x

a n d f l e x

P r o p e r t i e s s t a b l e w

i t h

t e m p e r a t u r e , f r e

q u e n c y ,

v o l t a g e , t i m e

S p u t t e r e d

B a T i O 3 , B S T ,

T h o u s a n d s


r o c e s s


A n n e a l i n

g r e q u i r e m e n t s

f e r r o e l e c t r i c s

B Z T

a n d m a t e r i a l s

R e q u i r e s h i g h

t e m p e r a t u r e

h a v e l i m i t e d i t s

H i g h s p e c i f i c c a p a c i t a n c e

a n n e a l

d e v e l o

p m e n t f o r

k

i s s e n s i t i v e t o t e m p e r a t u r e ,

e m b e d

d i n g i n

f r e q u e n c y , v

o l t a g e , t i m e

o r g a n i c b o a r d s



C V D , M O C V D ,

P a r a e l e c t r i c o r

P a r a : h u n

d r e d s


r o c e s s


P E C V D

f e r r o e l e c t r i c

F e r r o : t h o u s a n d s

a n d m a t e r i a l s

M a y r e q u i r e h i g h d e p o s i t i o n

t e m p e r a t u r e s

M O C V D r e a g e n t s a n d

e q u i p m e n t a

r e v e r y e x p e n s i v e





137

S o l – g e l

B a T i O 3 , B S T ,

T h o u s a n d s

H i g h s p e c i f i c c a p a c i t a n c e

R e a g e n t s e x p e n s i v e

I n p r o d u c t i o n a t A V X

f e r r o e l e c t r i c s

B Z T

R e q u i r e s h i g h

t e m p e r a t u r e a n n e a l

f o r i n t e g r a t e d a r r a y s

k



o l t a g e , a n d t i m e

A n o d i z e d

A l 2 O 3 , T a 2 O 5 ,

L o w h u n d r e d s

F i l m s m u c h l e s s s e n s i t i v e t o

R e q u i r e s v a c u u m p r o c e s s i n g f o r

U n i v e r s i

t y o f A r k a n s a s ,

p a r a e l e c t r i c s

r o u g h n e s s t h a n

t h o s e f r o m

s p u t t e r i n g T

a o r A l

H i D E C ,

I n t a r s i a

s p u t t e r i n g , a l l o w s t h i n n e r


n C h i p

f i l m s


B e l l L a b

s ( 1 9 5 0 ’ s )

U n f i l l e d

B C B , p o l y i m i d e , U p t o ~ 1

f o r < 5

E a s y , i n e x p e n s i v e

p r o c e s s i n g

V e r y l o w s p e c i f i c c a p a c i t a n c e

D u P o n t ( H K ™ )

o r g a n i c s

e p o x y , F R 4

m s p i n - o n

L o w d e f e c t d e n s i t y

S a n m i n a

( B C 2 0 0 0 ™

o r c a s t

L o w d i s s i p a t i o n f a c t o r

I n t a r s i a ( s p i n - o n )

U p t o 0 . 3

f o r 1 / 2

m i l l a m

i n a t e

F i l l e d o r g a n i c s

B a T i O 3 i n B C B ,

U p t o 2 3

i n

E a s y , i n e x p e n s i v e

p r o c e s s i n g

L o w s p e c i f i c c

a p a c i t a n c e

3 M ( C - P

l y )

p o l y i m i d e ,

c o m m e r c i a l i z e d

L o w d e f e c t d e n s i t y

k


D u P o n t ( H K ™ )

e p o x y , F R 4

p r o d u c

t s


o l t a g e , t i m e

G e o r g i a

T e c h

F e r r o e l e c t r i c

B a T i O 3

~ 5 0

S e p a r a t e s t h e h i g h

- t e m p e r a t u r e

k


D u P o n t ( I n t e r r a ™ )

f i r e d o n t o

f i r i n g s t e p f r o m

t h e o r g a n i c


o l t a g e , a n d t i m e

C u f o i l

b o a r d

C o n d u c t o r -

A g f l a k e i n

1 0 t o d a t e

P o t e n t i a l f o r h i g h

c a p a c i t a n c e

V e r y h i g h l o s s

t a n g e n t

G e o r g i a

T e c h

i n s u l a t o r

e p o x y

S e n s i t i v e t o m i x i n g p r o p o r t i o n s

n a n o c o m p o s i t e



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145

CHAPTER 7

DEFECTS AND YIELD ISSUES

RICHARD K. ULRICH

One of the main impediments to establishing integrated passives in mmercial processes is the potential for losing the entire board due to a defect in one single in-tegrated component. Inductors are not expected to cause much of a problem sincethey are few in number compared to resistors and capacitors and since they arenothing more than shaped interconnect metal. Resistors will be somewhat more

prone to yield losses, mainly due to being out of specification, but can be trimmedto tolerances of less than 1%. Integrated capacitors will probably be the main con-cern for board yield losses for two reasons. First, they are usually the most numer-ous passive component on the board, mainly due to their use in decoupling. Second,to have high specific capacitance, they must have thin dielectrics, which are more

prone to leakage. This chapter discusses the causes of capacitor defects, gives anexample of how defect density in integrated capacitors can be measured, and de-scribes how this number can be used to predict the yield of boards that are limited

by capacitor defects.

7.1 CAUSES OF FATAL DEFECTS IN INTEGRATED CAPACITORS

Defects in integrated capacitors are manifested by high leakage currents, sometimeswith leakage resistances under an ohm, and low breakdown voltages. As discussed inChapter 4, dielectric breakdown in thin films occurs primarily at defects, whichmakes their resistance properties significantly poorer than those of the same materi-als in bulk form [1]. Integrated capacitor dielectrics are very delicate structures. Not

only are they thin, but also their lateral dimensions may be over 10,000 times their thickness. Ceramics are much weaker in tension than in compression and, especiallyif they are on the wrong side of the neutral axis or subjected to CTE mismatch stress-es, can fail during board flexure or thermal excursions. In fact, ceramic dielectricscan rarely be made much thicker than a micron even without external stresses be-cause they may crack under their own internal stress. A thin-film ceramic dielectric



ISBN: 0-471-24431-7



might encounter a challenging environment if used in a flex substrate underneath sur-face-mount components. During FR4 lamination, movement of layers relative to oneanother can be 200–500 ppm, up to 10 mils over a 20 inch distance. This sort of dis-

tance can be hundreds of times the thickness of these dielectrics. For anodized films,Cu, Au, and other nonanodizable particles can be left over from bottom plate sput-tering, or dielectric breakdown can occur during anodization if the formation voltageis too high [2]. For sputtered films and to a lesser extent for anodized ones, rough sub-strates will always result in more defects than smooth ones, especially when theroughness is a significant fraction of the dielectric thickness [3–6].

7.2 MEASUREMENT OF DEFECT DENSITY

No comprehensive studies of integrated capacitor defect density have been found inthe literature, certainly due to the large number of processes under consideration,

but a few mentions have been made, mainly with regard to thin-film dielectrics. Pe-ters et al. measured the defect densities for anodized films at 0.02/cm2 and foundthem to be much lower than in similar sputtered films [7]. The authors of this book have studied the defect density in anodized Ta on a variety of substrate materialsusing a test structure consisting of 2300 1 × 1 mm capacitors that are processed si-multaneously [8]. After fabrication, the individual capacitors were tested for leak-

age resistance as a measure of their yield using an automated flying-probe tester.Since all the capacitors shared a common bottom plate, only one probe had to bemoved. As long as the defect density was not so large that multiple defects were oc-curring on one capacitor, an accurate measure of the number of defects per cm2

could be obtained.

146 DEFECTS AND YIELD ISSUES

Figure 7.1 Distribution of leakage defects in anodized Ta2O5 films over Kapton flex.



The upper limit of the apparatus to measure resistance was 8 M, which under 5

V would have resulted in a current density through the 1 mm2 capacitor of 62.5A/cm2. The results for 500, 1000, and 1920 Å anodized Ta2O5 films over 2 milKapton flex substrates showed that the individual capacitors were either defectivedue to being very leaky, with a leakage resistance less than a k , or were goodcomponents showing a leakage resistance over 8 M, with little distribution in be-tween, as shown in Figure 7.1. Extensive SEM examination of known bad capaci-tors did not reveal any obvious defects, even at magnifications of 1000 times over asearch area of only 1 mm2.

Based on these criteria, the defect density could be quantitatively measured,

which provided a tool for optimizing the processing and substrate conditions. Thedefect density for anodized films on flex was found to be very high—as much asone per cm2 —but this could be lowered considerably by coating the flex with BCBas a planarizing layer, leading to the conclusion that surface roughness contributesto the defect density. Defect densities measured over Si substrates, shown in Figure7.2, were much lower than those on flex.

7.3 DEFECT DENSITY AND SYSTEM YIELD

Since integrated capacitors generally cannot be tested before being added to a sub-strate, yield is a major concern in their implementation. As with the processing of any integrated structure, the fraction of working individual components (the yield)strongly affects the usable fraction of the final assemblies. For N integrated passives

7.3 DEFECT DENSITY AND SYSTEM YIELD 147

Figure 7.2 Defect density for anodized Ta2O5 dielectric films over Si substrates.



on a substrate, each with an individual yield Y i, the yield for a substrate will be of the form

Y board+passives = Y board N

i=1 Y ip,iwhereY board+passives = yield of the substrate with integrated passives in placeY board = yield of the substrate prior to the addition of integrated passivesY i,pi = yield of the individual integrated passives N = the number of integrated passives on the substrate

The effect of integrated passive yield is easier to visualize if there is only one type

on the substrate and if the substrates themselves come into integrated passive pro-cessing with 100% yield prior to the addition of integrated passives. The overallyield is then

Y board+passives = (Y ip) N

Figure 7.3 shows that, even for only a few dozen integrated passives, any significantyield reduction of the individual components results in a large loss of assembly yield.

7.3.1 Predicting Yield from Defect Density

If the same integrated component technology is used on the entire board, the densi-ty of fatal defects, D per cm2, should also be the same everywhere (Figure 7.4).That means that the number of individual passives doesn’t matter, only their total


Figure 7.3 Yield of the substrate after addition of integrated passives as a function of thenumber and yield of the individual passives.



area, A cm2. Multiplying these together gives the average number of defects per board. From there, the Murphy equation can be used to estimate the expected boardyield:

Y passives = 2

whereY passives = yield of the passive set D = fatal defect density, defects/cm2

A = total capacitor area integrated into the board, cm2

DA = average total number of defects/total capacitor area

For example, consider a board having a total integrated capacitance of 10 F using2000 Å of anodized Ta. This would give 105 nF/cm2 so the required total capacitor area is 95.2 cm2. If this dielectric had a defect density of 0.04 per cm2, then the av-erage number of fatal capacitor defects per board is 3.8, resulting in a board yield of only about 6%, which is far too low for economic manufacture. A board yield of,say, 90% requires an average defect number of 0.107 per board. A thicker dielectricwith a lower defect density would also require more area so the shape of the de-fects/cm2 versus dielectric thickness curve, such as the one in Figure 7.2, is impor-tant in evaluating the trade-off.

7.4 YIELD ENHANCEMENT TECHNIQUES FOR CAPACITORS

Flaws in thin oxide films may be made visible by placing the bottom plate and di-electric, with no top plate, in a solution of metal ions and making this stack cathod-

1 – e –D A

DA

7.4 YIELD ENHANCEMENT TECHNIQUES FOR CAPACITORS 149

Figure 7.4 Passive set yield as a function of the average total number of fatal defects.



ic. The metal ions in solution will plate over the defects since those are the onlyareas that current can pass. The amount of current gives some indication of thenumber and size of the defects [9]. This can also work if the top plate is not shorted

to the bottom plate by the defect, which can occur if high leakage current has vapor-ized a portion of the top plate around the defect.

The anodized Ta2O5 or NbOx dielectric of discrete capacitors is sometimesdipped in a solution of Mn(NO3)2 that is then pyrolytically decomposed at 250°Cinto a solid layer of semiconducting MnO2 with a resistivity of only 1–10 -cm.This treatment significantly decreases the defect density of the resulting capacitor

but at the cost of adding some series resistance. What seems to be happening is thatcurrent flowing through a defect site in the Ta2O5 dielectric locally heats MnO2. Atabout 400°C, the conductive semiconductor MnO2 is changed to Mn2O3, a material

that is much more resistive at about 10,000 -cm, which effectively plugs the de-fect [10, 11]. In addition, the oxygen liberated during the Mn oxide conversion,along with the localized heating, may reoxidize Ta back to the insulating oxide[12].

As mentioned above, when sputtered Cu bottom plates are oversputtered in thesame equipment with Ta that is subsequently anodized, residual Cu particles may

be incorporated into the Ta. Copper is not anodizable and can leave a conductive path through the resulting Ta oxide. Using an anodizable metal such as Al as the bottom plate will decrease the number of defects since any Al particles will be an-

odized, with about the same oxidation kinetics of Ta, and will not result in shorts.After anodization, Ta2O5 films can be electrochemically etched at 70% of the an-odization voltage with the same polarization used in the anodization in a solution of LiCl or 0.01% AlCl3 in methanol to remove the metal from underneath defects.Then the part is returned to the anodizing bath for another 30 minutes of anodiza-tion [13]. There are also reports of burning out defects by increasing the voltage atthe end of anodization or by reversing the voltage [14]. Breakdown itself can be lo-cally very destructive, resulting in visible holes in the overlying capacitor plates andsplashed metal. One interesting observation is that if the top electrode is thin (less

than about 1500–3000 Å), defects will vaporize a larger area of electrode than thearea of the flaw in the dielectric, with the result that the defect is isolated and non-shorting. This has been suggested as a way to actually clear out weak spots in thecapacitor [15, 16].

Thin-film polymers and sol–gel dielectric precursors are commonly applied inmultiple thin layers to add up to the desired final thickness. This strategy can great-ly decrease the number of pinholes for liquid-applied dielectrics but has not beeninvestigated in detail for gas-deposited or anodized materials.

7.5 CONCLUSION

Shortly after the invention of the integrated circuit, there were many who thoughtthat yield problems would restrict the number of devices per chip to a few dozens atmost. But advances in manufacturing technology have pushed that number into the




tens of millions. It’s not clear how far down the defect density can be pushed, espe-cially with thin-film high-specific-capacitance structures. Yield may be one of themost important considerations in reducing the vast number of possible integrated

passive materials and processes.

REFERENCES

1. C. Coombs (ed.), Printed Circuits Handbook, 5th ed., McGraw-Hill, New York, 2001.

2. L. Young, Anodic Oxide Films, Academic Press, New York, 1961.

3. S. Byeon and Y. Tzeng, “High Performance Sputtered/Anodized Tantalum Oxide Ca- pacitors,” In Proceedings of the IEDM ’88, San Francisco, CA, p. 722, 1988.

4. R. Kambe, R. Imai et al., “MCM Substrate with High Capacitance,” In Proceedings of the MCM ’94 Conference, 1994.

5. K. Chen, M. Nielsen, S. Soss, J. Rymaszewski, T. Lu, and C. Wan, “Study of TantalumOxide Thin Film Capacitors on Metallized Polymer Sheets for Advanced Packaging Ap- plications,” IEEE Transactions on Components, Packaging, and Manufacturing Tech-

nology, Part B, 20, 2, 117, 1997.

6. H. Yoshino, T. Ihara, S. Yamanaka, and T. Igarashi, “Tantalum Oxide Thin Film Capac-itors Suitable for Being Incorporated Into an Integrated Circuit Package,” In IEEE/CHMT ’89 Japan IEMT Symposium, p. 156, 1989.

7. M. Peters, M. Lee et al., “Thermally Stable Thin Film Tantalum Pentoxide Capacitor for MCM Applications,” International Journal of Microcircuits and Electronic Packaging,

19, 4, 364, 1996.

8. R. Pandey, “Defect and Failure Mode Analysis of Large Area Ta2O5 Integrated Capaci-tors,” MS thesis, Dept. of Chemical Engineering, University of Arkansas, May 2001.

9. B. Mandakis, “The Solid Tantalum Capacitor—A Solid Contributor to Reliability,” In Proceedings of the Capacitor and Resistor Technology Symposium, IEEE, p. 45, 1973.

10. T. Berry, P. Hall, and M. Harris, Thin Film Technology, Van Nostrand, New York, p.271, 1968

11. D. McLean and F. Roxztoczy, Electrochemical Technology, 4, p. 523, 1966.

12. B. Smith, “Failure Mechanisms in Passive Devices,” In M. Minges (ed.), Electronic Ma-

terials Handbook, vol. 1, Packaging, ASM International, 1989, p. 995, 1989.

13. N. Schwartz and R. Berry, In G. Hass and R. Thun (eds.) Physics of Thin Films, vol. 2, p. 398, Academic Press, New York, 1964.

14. C. Standley and L. Maissel, Journal of Applied Physics, 35, 1530, 1964.

15. N. Axelrod, Journal of the Electrochemical Society, 116, 460, 1969.


REFERENCES 151



153

CHAPTER 8

ELECTRICAL PERFORMANCE OF


RICHARD K. ULRICH AND LEONARD W. SCHAPER

A more complete and accurate model of each passive component’s electrical behav-ior leads to a better model and subsequent design of the system. For any passive, dis-crete or integrated, this model should include both the pure value of the ideal compo-

nent together with its associated parasitics in a proper arrangement. The result will bea simple circuit made up of at least one capacitor, resistor, and inductor in some combination of series and/or parallel to accurately represent the observed frequency-dependent behavior of the component. For a capacitor, that would mean taking into ac-count its resistive and inductive aspects as well. Purchased discrete passivessometimes come with a full set of electrical performance data from their suppliers,enabling designers to create models of systems that will closely match the manufac-tured article. If the inductance of a capacitor is included in the SPICE model when de-signing an LC filter, it could be interpreted that the parasitic was either taken into ac-count or that is was utilized, depending on if you are a pessimist or an optimist. Either way, it is important to know the parasitics in a passive component. In the case of anintegrated passive, that particular size, value, and configuration may never have ex-isted before it was designed into a product. In the absence of a specification sheet, itmay be necessary to understand what parastics to expect and how to measure them.

The major difference between a surface mount and an integrated capacitor is thatthe latter will almost always have much less inductance. This is a major advantageof integrated capacitors and opens the door for their use in applications such as de-coupling, in which inductance is an important issue. The inductance of the integrat-ed capacitor itself can be so small that it is insignificant compared to that of theleads to it, vias on its leads, and other nearby contributions, whereas a surface-mount capacitor nearly always has a significant inductance. Because of this, it isimportant to be aware of all of the contributions to inductance that will be seenwhen measuring or utilizing an integrated capacitor. The purpose of this chapter isto describe the useful models of integrated or discrete capacitors, to show how and



ISBN: 0-471-24431-7



why integrated capacitors differ, and to describe the best methods for measuring in-ductance in integrated capacitors.

8.1 MODELING IDEAL PASSIVES

Ideal passives can be characterized by one number: resistance, capacitance, or in-ductance. The impedance of an ideal resistor is not a function of frequency, where-as the magnitude of impedance versus frequency for ideal capacitors and inductorsare functions of opposite slope. The electrical models of ideal components areshown in Figure 8.1.

Plotted together in Figure 8.2, capacitance moves downward and inductance up-

ward with increasing frequency. Capacitors act as zero-order high-pass filters andinductors are low-pass filters. The impedance of an ideal resistor would, of course, be a flat line at an impedance equal to its resistance.

8.2 MODELING REAL CAPACITORS

Figure 8.3 shows a practical model made up of four ideal components useful for areal capacitor and its parasitics. The impedance of this arrangement is:

Z cap =1

(8.1)

+

This model works well for both discrete and integrated capacitors to match the ob-served total impedance versus frequency for a wide range of capacitor sizes, styles,and dielectric materials. The ESR is due to the finite conductance of the top plates,

the bottom plates, and the associated leads to the capacitor and represents the resis-tance seen by a AC signal passing through the component. It is ideally zero. The

1

RDC

1

R 2AC + 2 1

fC – 2 fL 2

154 ELECTRICAL PERFORMANCE OF INTEGRATED CAPACITORS

Figure 8.1 Electrical models of ideal components. Z = impedance, ; f = frequency, Hz; R= resistance, ; C = capacitance, F; L = inductance, H.



leakage resistance of the capacitor dielectric is ideally infinite and the series induc-tance, ESL, is ideally zero.

The solid line in Figure 8.4 is the impedance versus frequency for a 100 nF capacitor that exhibits only one parasitic—20 pH of inductance. The ESR is verysmall since it does not show (less than about a milli-ohm), and the leakage resis-tance is very large. The dotted lines are ideal 100 nF and 20 pH behavior.

The point in Figure 8.4 where the capacitive and inductive impedances are equal

and the slope changes is the “self-resonant frequency” of the capacitor:

f srf = (8.2)1

2 L C

8.2 MODELING REAL CAPACITORS 155

Figure 8.2 The magnitude of impedance for capacitors and inductors.

Figure 8.3 Four-parameter model for a capacitor. C = capacitance, F; R AC = parasitic ACresistance or “equivalent series resistance” (ESR),; L = parasitic inductance or “ equivalentseries inductance” (ESL), H; RDC = DC or leakage resistance of the capacitor’s dielectric,.



Above this point, the impedance begins to rise with frequency so the overall component is no longer a capacitor at all; it becomes an inductor. For this example, theresonant frequency is 113 MHz. This is also the point at which the phase passesthrough zero as it moves from –90° to +90° and is, exactly at f srf , 0°. This frequencyis important to almost all applications since it marks the end of the component’srange of acting like a capacitor.

An ESR as low as the value used in the previous example (<1 m) is rarely seenin any type of capacitor. A more realistic measured curve would look like the one inFigure 8.5. Inserting these three values into Equation 8.1 and setting RDC to infinitywould give a model fit that would match the observed impedance curve very well,indicating that this model is valid for engineering analysis and design over thisrange of frequencies:

Z cap =

R 2AC + – 2 fL 2 (8.3)

The corresponding circuit model to be used in SPICE or other simulations is shownin Figure 8.6. It would then appear that these three components in series constituteC , L, and RAC for this capacitor but what about RDC? The leakage resistance willonly become important when its value is about the same or less than the total im-

1

2 fC


Figure 8.4 Fit of individual C and L values (dotted lines) over the capacitor’s impedance

(solid lines).



pedance of the C / L/ RAC leg, which, for this example, is below 1 for almost theentire frequency range. Therefore, unless this capacitor is very leaky, it would notshow up in the model or in actual measurements. In fact, RDC would have to bearound 10 before it would show up at all in the impedance plots such as those inFigures 8.4 and 8.5 but a DC resistance 1000 times larger may still be too small for a useful capacitor, especially in filtering and A/D applications. Figure 8.7 shows the

same plot but with a leakage resistance of only 1 . The low resistance of the RDC branch pulls the total impedance down from the straight-line models of the individ-ual series components at high and low frequencies. That would generally be a far leakier capacitor than could be acceptable for almost any application.

In principle, Equation 8.1 could be used to perform a curve fit to the data in Fig-ure 8.7 to come up with all four components but, for any useful capacitor, the leak-age resistance will be so high that it will not show up in the overall impedance data

8.2 MODELING REAL CAPACITORS 157

Figure 8.5 Superimposed values of a 100 nF capacitor, a 120 m resistor, and a 20 pH in-ductor over the measured capacitor impedance.

Figure 8.6 Circuit model for a real capacitor.



except at very low frequencies. As a result, Equation 8.3, corresponding to thearrangement in Figure 8.6, is the most useful form for modeling discrete or integrat-ed capacitors. In fact, many models of electrical measurement equipment will per-form this very curve fit automatically and give numerical values of C , L, and RACdirectly.

8.3 ELECTRICAL PERFORMANCE OF DISCRETE AND


8.3.1 Inductance of the Capacitor Alone

The main difference between the electrical performance of discrete and integratedcapacitors is that the integrated capacitors typically exhibit far lower parasitic in-ductance, which is a major advantage in a wide range of applications. Figure 8.8shows measured data for a surface mount and an integrated capacitor, both with

equal values of capacitance (8.5 nF) and equal values of parasitic resistance (40m). Both curves are straight on log-log coordinates down to the lowest measuredfrequency, so DC leakage does not appear in the data. Therefore, both componentscan be accurately modeled using Equation 8.3. The parameters giving the best fitare shown in Table 8.1.


Figure 8.7 A very leaky capacitor: RDC = 1 .



The parasitic inductance of the integrated capacitor is almost two orders of mag-nitude less, giving it about an order of magnitude higher frequency range than thesurface-mount component. There are two main reasons that an integrated capacitor usually exhibits lower inductance than the typical discrete capacitor. The first has todo with the size of the current loop through the component. The discrete will have amuch larger loop because of the height of the component above its contacts to the

board, whereas the entire integrated capacitor is within a mil or two of the level of the interconnects. The other effect has to do with the reduction of the self-induc-tance of the structure by mutual inductance. In the conventional SMD on the leftside of Figure 8.9, current travels from left to right in the plates of both polarities. Inthe integrated capacitor on the right, the connections to the plates are arranged sothat current flows in opposite directions in the plates, thereby canceling some of thestructure’s self-inductance by mutual inductance.

8.3 ELECTRICAL PERFORMANCE OF DISCRETE AND INTEGRATED CAPACITORS 159

Figure 8.8 Measured electrical performance for a surface mount and an integrated capaci-tor.

Table 8.1 Best-fit parameters for the performance curves of the surface mount andintegrated capacitors

Parasitic Parasitic AC Self-ResonantCapacitance Inductance Resistance FrequencyComponent (nF) (pH) (m) (MHz)

Surface mount 8.5 340 41 94Integrated 8.5 5 38 760



Concentrating now on integrated capacitors, it can be shown that the inductanceof the structure is directly proportional to the thickness of the dielectric. This is bestexpressed in henrys/square just as resistance can be expressed in /square. For a

parallel plate integrated capacitor with the current entering and leaving the sameside and the contacts distributed over that entire side so there is not spreading in-ductance, the inductance is 0h H/square where 0 is 4 × 10 –7 H/m and h is the

plate separation. In convenient units this is:

L = 1.26h (8.4)

where L = inductance/square for an integrated capacitor, pH/squareh = plate separation, m

Therefore, the inductance of a square integrated capacitor with current flowing inand out the same edge would have an inductance on the order of only 1 pH. Thistrend can be seen in the data in Figure 8.10, which is a set of impedance scans be-tween the power and ground planes of three circuit boards with different dielectric

thicknesses [1].The capacitance can be pulled out in the linear portions at 10 MHz and, together

with the resonant frequencies, Equation 8.2 can be used to deduce the inductance of the structures as a function of dielectric thickness. The results in Table 8.2 showthat the inductance increases roughly linearly with plate separation thickness.

Figure 8.11 shows the measured curves for five different sizes of the same typeof integrated capacitor, all square in shape. Their capacitance increases linearlywith their area, which, in this case, covers a range of over four thousand. The twosmallest capacitors of the group do not reach their resistive floors, so the value of

AC resistance cannot be determined but, on the other hand, it does not affect their performance either over this frequency range. Also because of the low value of thesmallest capacitor, it does not reach resonance by the end of the scan so its ESLcannot be determined. The jog in the 0.1 nF curve at 200 MHz is a standing waveresonance probably in the cabling and is commonly seen when the wavelength of


Figure 8.9 Current flow through discrete and integrated capacitors.



the signal approaches the same order of magnitude as the linear size of the conduc-tors. They disappear as the frequency moves away from that which produces thestanding wave.

Curvefitting this data gives the results in Table 8.3. There are some trends com-mon to thin-film integrated capacitors that should be noted. Although the capacitor area and value change by two orders of magnitude, the parasitic inductance and re-sistance change very little since these are per-square quantities. If the capacitor

plates are all square and the dielectrics are all the same thickness, the inductancewill be the same. If the plates were rectangular with contacts along the long edges,

the inductance would be smaller. The larger capacitors have a lower self-resonantfrequency because, even though their inductances are all about the same, the capac-itance values are larger. The resistance changes little because all of the capacitorswere the same shape (square) and the resistance to AC current should be on the or-der of one square of plate metal since the current, on average, moves out one-half


Figure 8.10 Impedance of three circuits boards with different dielectric thicknesses.

Table 8.2 Inductance of capacitors with varying plate thicknesses

0.3 mil 1.0 mil 2.0 milZ at 107 Hz () 0.25 0.37 0.79C (nF) 630 43 20f res (MHz) 33 91 100L (pH) 37 71 130



square and back one-half square. The resistance values are rather high becausethese capacitors used bottom plates of very thin Ta, a high-resistivity metal. Resis-tance and inductance have the same geometric relationship, based on the number of squares rather than on the absolute area, and are both subject to spreading effects.

Figure 8.12 shows the performance of two surface-mount discretes—an 0603and a low-inductance capacitor array—along with a floating plate and a parallel

plate integrated capacitor made from anodized Ta. The integrated capacitors have ahigher self-resonant frequency and, hence, a larger working range than either of thediscretes, even though the integrated components have higher capacitance values.

Extracting the model parameters (Table 8.4) shows that the integrated capacitorshave orders of magnitude less parasitic inductance than the discretes. Measure-ments of discrete capacitors from three manufacturers shows that their parasitic in-


Figure 8.11 Performance curves for five different sizes of the same type of integrated capacitor.

Table 8.3 Best-fit parameters for the performance curves of the five sizes of integratedcapacitors

Parasitic Parasitic AC Self-ResonantCapacitance Inductance, ESL Resistance, ESR Frequency

(nF) (pH) (m) (MHz)

0.1 Too small to measure Too small to measure Too high to measure >18001 62 Too small to measure 6409 40 170 27070 67 120 73445 48 110 34



ductance is typically much higher than any integrated capacitor (Table 8.5). The in-ductance of the integrated capacitors is very difficult to determine, since the ex-tremely low impedance at high frequency pushes the measurement limits of the HP4291 instrument.

The main difference in the sets of values for discrete versus integrated capacitorsis the much lower parasitic inductance for integrated units. ESL values for surface-mount discretes range from the nH range down to about 50 pH, whereas integratedcapacitors are much lower, as little as a few pH. The lower ESL for integrated capac-itors is a result of their planar structure, which provides smaller current loops and isa major advantage of integrated capacitors. The measurements of inductance for the


Figure 8.12 Comparison of two surface mount and two integrated capacitors.

Table 8.4 Best-fit parameters for the performance curves of the discrete and integratedcapacitors

Parasitic Parasitic AC Self-ResonantCapacitance Inductance Resistance Frequency

Component (nF) (pH) (m) (MHz)Discrete 0603 10 1900 570 36Discrete LICA 55 30 110 120Integrated floating plate 105 ~2 24 ~400Integrated parallel plate 240 ~1 19 ~400



integrated capacitors were below the resolution of equipment used to measure them.Much of this is probably contact inductance. To put the small magnitude of these val-ues into perspective, a short loop of 1 mil bond wire is about 1000 pH, a solder bump

is 50 to 100 pH, and a single circle of metallization 1 mm in diameter is about 2500 pH. The inductances associated with integrated capacitors are often going to be muchsmaller than the methods used to contact them in an electrical system.

8.3.2 Inductance of the Capacitor’s Leads and Contacts

From Equation 8.4, it is clear that the inductance of a parallel plate capacitor, properly connected along one end of the pair of plates, can have a very small in-ductance. With a thin-film dielectric only 1000 angstroms thick, the inductance of

a square capacitor is only 0.13 pH, far too low to measure. In fact, since mea-surement probes are basically point contacts, the measured inductance is mostlydue to the connections, not to the capacitor itself [2]. Simulations based on mea-sured data, but corrected for connection inductance, confirm that the intrinsic in-ductance of thin-film capacitors is extremely low. Thus, designers must be verycareful in connecting to these capacitors in order to realize the benefit of their lowinductance properties. It is best to connect with two closely spaced rows of vias or other connections, as close to the load as possible. In other words, try to approachthe ideal of a continuous pair of line connections along one edge of the capacitor.

The goal is always to minimize the loop inductance of the connection cross sec-tion.This connection inductance problem shows up in connections to discrete and in-

tegrated capacitors not only during measurement, but also in applications. Particu-larly when trying to get the benefit of low-inductance discretes, it is essential tominimize the inductance of connections from the power/ground planes to the solder


Table 8.5 Parameter fits to several discrete capacitors from three manufacturers and fivefloating-plate integrated capacitors

Parasitic Parasitic AC Self-Resonant

Capacitance Inductance Resistance FrequencyType (nF) (pH) (m) (MHz)

Discrete 100 707 126 19Discrete 10 594 445 65Discrete 2 568 481 150Discrete 10 79 55 180Discrete 2 71 487 420Discrete 55 30 108 120Floating-plate integrated 270 < 2 19 > 220

Floating-plate integrated 106 < 2 18 > 350Floating-plate integrated 79 < 2 16 > 400Floating-plate integrated 51 < 2 15 > 500Floating-plate integrated 10 < 2 17 > 1100



pads, as shown in Figure 8.13 [3]. Depending on the geometry, there could be sev-

eral nH present in the loop [4]. Even better than the “via in pad” design shownwould be larger pads with multiple vias to the power and ground planes. Since inte-grated capacitors are in plane with the power and ground connections and do not re-quire solder pads for mounting, they also avoid these contributions to total induc-tance.

In many boards, however, the power and ground planes themselves are a prob-lem, because of their spacing; they also follow Equation 8.4 for computing per square inductance. A plane separation of several mils can seriously affect capacitor

performance, unless the capacitor is close enough to the load that only a small frac-

tion of a square of the power distribution system lies between them.

8.3.3 Equivalent Series Resistance

Since the current moves, on average, about halfway down and back the plates of anintegrated capacitor, the AC resistance values are on the order of one square of topand bottom plate material since there are no leads to the integrated capacitors. For most capacitor plates made of copper or aluminum, the ESR is of little conse-quence. However, for very thin plates or plates made of valve or refractory metals,

ESR should be considered and accounted for in power distribution system models.

8.3.4 Capacitors as Distributed Devices

A discussion of the complexity of generalized power distribution models is beyondthe scope of this book, and the topic is extremely complex. Istvan Novak and Larry


Figure 8.13 Inductance of vias and interconnects from the power and ground plane.



Smith of Sun Microsystems, George Katopis of IBM, and Peter Krusius at Cornellhave done excellent work in this area, as have others. A large, distributed capacitor with multiple source and sink locations is simply a special case of the generalized

power distribution system, and can be modeled using a “bedspring” model, which breaks a plane (or a plate) up into a matrix of individual R, L, C , and M elements.Both plates must be modeled; each element represents a given subarea. The size of each of these elements must be a small fraction of the wavelength (in the dielectric

between the plates) at the highest frequency of interest. Sources and sinks are con-nected to the bedspring at appropriate nodes. In this manner, a complete equivalentcircuit can be developed for SPICE simulation [5–7].

For an edge-connected parallel plate capacitor, a multisection transmission linemodel gives accurate results to many GHz. This model is much easier to implement

than the large bedspring if the connection points allow its use. Again, any model isvalid only over a frequency range in which a given physical element is a small frac-tion of a wavelength.

8.4 DISSIPATION FACTOR OF REAL CAPACITORS

The dissipation factor of an overall capacitor consists of contributions from the di-electric itself, resistance of the leads and plates, and leakage through the dielectric.

The total dissipation factor is

Dtot = 2 fCRAC + + Ddielec

where Dtot = total dissipation factor Ddielec = dissipation factor of the dielectric

The contribution of leakage is often negligible. Consider a 1 nF capacitor operatingat 100 MHz with an ESR of 10 m and an insulation resistance of 100 M. TheESR contribution is 0.006 and the leakage contribution is 2 × 10 –8. Referring back to Table 4.1, 0.6% is on the order of the lower dissipation dielectrics.

8.5 MEASUREMENT OF CAPACITOR PROPERTIES

Referring back to Equation 8.1, there are four parameters to be measured: capaci-tance, ESR, leakage resistance, and ESL. The capacitance is easily measured with adigital multimeter or LCR meter for almost any value required in common systems.The leakage resistance can be determined to at least a lower bound by the same typeof equipment, but may require a variable voltage source and picoameter if true leak-age curves are desired, such as the one in Figure 8.14.

1

2 fCRDC




However, the exact shape of the leakage curve is usually not important in a pro-

duction situation since it is typically required that the capacitor meet a maximumcurrent leakage specification such as 1 A/cm2 at 5 V. Most capacitor dielectricshave a leakage resistance of 1012 –1017 -cm. If this range is formed into 1000 Åfilms with an area of 1 cm2 and measured, the ohmic values would be 107 –1012 ,and would give well under 1 A/cm2 at 5 V. Therefore, the value of RDC wouldhave to be orders of magnitude lower than is generally acceptable to show up onmost digital multimeters or LCR meters. For that reason, the leakage resistance isusually relegated to being an acceptance specification and the capacitor model actu-ally used is the RCL series model of Equation 8.3. The other two parameters, ESR

and ESL, may be difficult to measure for integrated capacitors due to their low val-ues, particularly for the inductance.

8.5.1 ESR and ESL Measurement with an Impedance Analyzer

The principle behind an impedance analyzer (IA) is shown in Figure 8.15, with thecapacitor as the device under test (DUT). The voltage-source frequency is sweptfrom some low value, perhaps a few kHz, to as high as a couple of GHz. Mean-while, the magnitude and phase of the resulting current is measured and converted

into impedance and phase angle for display. This has the convenience of being aone-port measurement, but is usually limited in frequency range. Although this isusually sufficient for discrete capacitors, integrated capacitors may resonate out of this range. Impedance analyzers should always be able to provide reliable values of capacitance regardless of ESL, ESR, or leakage resistance levels because it canmake this measurement at frequencies high enough to reduce the impedance of the

8.5 MEASUREMENT OF CAPACITOR PROPERTIES 167

Figure 8.14 Leakage current through thin-film anodized Ta2O5 integrated capacitors.



capacitor well below the leakage resistance but at frequencies low enough to avoidinterference from the inductive parasitics. For leakage resistance, many IAs cannot

approach zero frequency and so can measure RDC values that are very low, muchlower than would be desired in a capacitor. As a result, the IA usually cannot beused for this and the measurements should be made with a high-range resistancemeter or, better yet, a voltage source and picoameter set up to measure leakage cur-rent curves.

ESR shows up as a floor that appears in two ways depending on whether or notthe capacitor’s parasitic inductance becomes dominant at high frequencies (Figures8.16 and 8.17).

In the first case, shown in Figure 8.16, the self-resonant peak, in theory, extends

down to zero ohms since the reactance of the capacitive and inductive aspects of thecomponent are equal in magnitude and opposite in phase. In the second case (Figure8.17), the self-resonant frequency is off the scale of the IA—1 GHz as shown in thisexample—as it often will be for integrated capacitors. In this instance, it is easy todetermine the minimum ESR that can be seen. A capacitor of value C would run off the scale of maximum frequency f max at 1/(2 f maxC). Many HP impedance analyz-


Figure 8.15 Schematic of an impedance analyzer with a capacitor as the DUT.

Figure 8.16 Resistance floor cuts off the self-resonant peak.



ers have a maximum frequency of 1.8 GHz. The impedance of a 10 pF capacitor atthat frequency would be 8.8 and, for a 10 nF capacitor, 8.8 m, and no ESR val-ues lower than this could be seen. The ESR of smaller capacitors is harder to mea-

sure because of their higher impedance but, if the resistance floor does not show upover the frequency of interest for the application, it is unimportant anyway.The resonant frequency of the capacitor must be well below the upper range of

the impedance analyzer, perhaps several hundred MHz below, or the impedancewill not change slope in time for the value of inductance to be measured. Many in-tegrated capacitors, especially those with small values, will not meet this require-ment before a couple of GHz and cannot be measured effectively with most imped-ance analyzers. Table 8.6 shows the minimum values of RAC and parasiticinductance that can be measured with an impedance analyzer with a maximum fre-

quency of 1.8 GHz.An integrated capacitor with one square of resistance in the plates and contactswould have about 10 m of ESR, so a capacitor smaller than about 10 nF would


Figure 8.17 Self-resonant frequency is off scale.

Table 8.6 Minimum values of parasitic resistance and inductance measurableon an impedance analyzer with a maximum frequency of 1.8 GHz

Capacitance Possible Measurable ESR Possible Measurable ESL

1 pF >88 >7.8 nH10 pF >8.8 >0.78 nH100 pF >0.88 >78 pH

1 nF >88 m >8 pH10 nF >8.8 m >0.8 pH

100 nF >0.8 m



run off the 1.8 GHz scale before the ESR became apparent in the data. It would also probably have an ESL no higher than about a pH and this would probably not bemeasurable on most impedance analyzers.

8.5.2 ESR and ESL Measurement with a Network Analyzer

A network analyzer (NA) utilizes a two-port measurement designed to be used withmicrowave devices that have about 50 of impedance. A typical NA can sweepinto the tens of GHz, which can push the small inductive parasitic impedance of anintegrated capacitor high enough to see it above other impedances [8]. However,many capacitors for common electrical equipment are not designed to be mi-crowave devices and may exhibit a variety of resonations and standing waves that

may interfere with the measurement. Also, proper connections must be made with probes that have very close tips—as narrow as 150 m—and not all capacitors aredesigned to accommodate this. Figure 8.18 shows a capacitor mounted in the shunt

position in a network analyzer. The NA provides a frequency-swept excitation volt-age through a 50 output impedance, shown as a resistor; the voltage is measuredat a second port, also through a 50 impedance.

Network analyzers typically give outputs in the form of S parameters, which arevarious ratios of measured to exciting voltages. Of the four S parameters availablefrom a NA, the S 21 parameter gives the most useful information about a capacitor

under test and is obtainable from the configuration shown in Figure 8.18. S 21 is theratio of the magnitude of voltage measured with the DUT present divided by thevoltage if no DUT is present. If the DUT has no gain, like all passive components,then S 21 is a number less than or equal to one. If no DUT is present, then the mea-sured voltage is one-half the source voltage since the source voltage is dropped over two identical resistors. So the definition of S 21 is

S 21 = (8.5)V meas

(1 – 2V source

)


Figure 8.18 Schematic of a network analyzer with a capacitor as the DUT in shunt config-uration.





As before, the three-parameter model from Equation 8.3 can be plotted versusfrequency and curve fit, assuming that the leakage resistance has been tested with aresistance meter and is larger than about 100 :

Z = R 2AC + – 2 fL 2 (8.3)

As an example, Figure 8.20 shows the S 21 readout from a NA for an integrated capacitor, which comes off the HP 8510 as dB with a linear frequency axis. This datacan be turned into an impedance versus frequency diagram using Equation 8.9. The

black dots in Figure 8.20 were converted from the S 21 data and plotted on a log-logscale in Figure 8.21. The solid line is the three-parameter fit with C = 0.93 nF, ESR

= 18 m and ESL = 3.0 pH. Again, the quality of the fit of this approach to mea-sured data indicates that the model and parameter values are accurate over this fre-quency range.

To summarize the utility of network analyzers for measuring the characteristicsof integrated capacitors, the capacitance value can be measured at the low end of the frequency scale. As with LCR meters and impedance analyzers, the leakage re-sistance can only be measured quantitatively for values that are so low that the ca-

pacitor would certainly be considered leaky for almost any application. However, itcould be used to see if the component meets a specification of minimum leakage re-

sistance. ESR and ESL should be measurable, at least in principle, due to the much

1

2 fC


Figure 8.20 S 21 parameter data from the network analyzer for an integrated capacitor.



higher upper limit of frequency compared to LCR and impedance analyzers. Inter-ference from reflections and standing waves may become significant as the fre-quency increases into the microwave region.

The wavelength of an electromagnetic signal passing through a conductor that issurrounded by a dielectric is

= (8.10)

where = wavelength, cmc = speed of light in a vacuum, 3 × 1010 cm/sec f = frequency, Hzk = dielectric constant of the surrounding

As an example, a signal passing through an integrated capacitor with a dielectric

made from Al2O3 (k = 9) would have a wavelength of 10 cm at 1 GHz and 1 cm at10 GHz. Once these wavelengths approach the same order of magnitude as the di-mensions of the capacitor in the signal’s direction, standing waves and reflectionscan show up as anomalous peaks, valleys, and slopes in the measured S parametersand impedance values. These can make the determination of the component’s CRL

parameters difficult and uncertain.

c

f k


Figure 8.21 Curve fit of impedance versus frequency for an integrated capacitor.



8.6 SUMMARY

The main difference between a discrete and an integrated capacitor is that the lat-

ter has much less parasitic inductance, so low that it may be difficult to measure.As a result, the resonant frequency of an integrated capacitor will be higher for thesame value, giving it a wider range of applicability. The reasons for this are thatthe integrated capacitor moves current in opposite directions internally, providinga canceling effect on the resulting magnetic fields, and also because the plates arevery close together, providing a small current loop. Additionally, the inductanceof the conductors between the interconnects and the capacitor is lower for the in-tegrated model because the capacitor is planar and in plane, also providing asmaller loop. Discrete capacitors normally require a via to the surface and back.

Finally, integrated capacitors do not require solder connections. In electronic sys-tems, the inductance of vias and interconnects may exceed that of an integratedcapacitor to the point that the capacitor’s contribution to the total parasitics is neg-ligible.

Another difference is that both the inductance and the resistance of integratedcapacitors is a per-square quantity rather than a per-area one. This refers to the ca-

pacitor itself if the current comes in distributed evenly over one edge so there isnot spreading inductance or resistance, which would itself be a constant quantitywith capacitor size above a small lower limit. With discrete capacitors, the unit’s

inductance tends to follow the case size since this creates a larger current loop.Figure 8.22 shows the effect of increasing value on both types. In each case, in-creasing capacitance causes the self-resonant frequency to move down, but less soin the case of the integrated capacitor because its inductance curve does notchange.

This figure also shows why it is easier to measure the inductance on larger values of both types of capacitors; the self-resonant frequency for smaller unitsmay be off the frequency scale, particularly for integrated capacitors that havevery small ESLs. Of course, if the inductive effects do not show up over the fre-

quency range of interest, they are unimportant anyway. Table 8.7 outlines the best


Figure 8.22 Effect of value change for discrete and integrated capacitors.



equipment to use for measuring the four components of a standard lumped capac-itor model.

REFERENCES

1. “Impedance and EMC Characterization Data of Embedded Capacitance Materials,” In Proceedings of APEX2001, San Diego, CA, January 16–18, 2001.

2. K. Chen, W. Brown et al., “A Study of the High Frequency Performance of Thin Film Ca- pacitors for Electronic Packaging,” IEEE Transactions on Advanced Packaging, 23, 2,293, 2000.

3. T. Roy and L. Smith, “ESR and ESL of Ceramic Capacitor Applied to Decoupling Appli-cations,” In IEEE Topical Meeting on Electrical Performance of Electrical Packaging,

West Point, NY, p. 213, Oct. 1998.

4. J. Cain, “Interconnect Schemes for Low Inductance Ceramic Capacitors,” AVX Corpora-

tion, avx.com.5. G. Carchon, S. Brebels, et al., “Accurate Measurements and Characterization up to 50

GHz of CPW-based Integrated Passives in Microwave MCM-D,” In Proceedings of the

2000 Electronics Components and Technology Conference, IEEE Press, New York, p.459, 2000.

6. E. Diaz-Alvarez and J. Krusius, “Modeling and Simulation of Integrated Capacitors for

REFERENCES 175

Table 8.7 Summary of measurement methods for integrated capacitors

LCR or DigitalMulti-Meter Impedance Analyzer Network Analyzer

Capacitance Excellent Excellent Excellent

Leakage Good. Can at least May be used for May be used forResistance determine if the value specification testing, specification testing,

is high enough for the but some models but most modelscap to not be leaky. cannot operate at zero cannot operate at zero

frequency to give an frequency to give anexact value. exact value.

ESR Some LCR meters can Good Good

do this, but integratedcapacitors may be toolow to measure accurately.

ESL Integrated capacitors Only useful if the Can give good valuesusually too low to resonant frequency is by finding themeasure this way. lower than the resonant frequency

instrument’s upper if there is norange. interference from

microwave frequencystanding waves.



High Frequency Chip Power Decoupling,” IEEE Transactions on Components and Pack-

aging Technologies, 23, 4, 611, 2000.

7. K. Lim Choi and M. Swaminathan, “Synthesis of Equivalent Circuits For Two-Port Inte-

gral Passive Components,” In Proceedings 1999 International Conference on High Den- sity Packaging and MCMs, p. 316, 1999.

8. I. Novak, “Measuring Milliohms and PicoHenrys in Power Distribution Networks,” In Proceedings of DesignCon2000, Santa Clara, CA, February 1–4, 2000.




177

CHAPTER 9

DECOUPLING

LEONARD W. SCHAPER

9.1 POWER DISTRIBUTION

Power distribution is one of the principal functions of electronic packaging, and de-coupling is one of the principal aspects of power distribution. Simply stated, therole of power distribution is to supply stable, noise-free power, at a constant, specif-

ic voltage, to integrated circuits (ICs) and other components that comprise an elec-tronic system. The trends in electronic systems are for the supply voltages to de-crease, required currents to increase, and clock speeds to increase, making it moredifficult to distribute noise-free power to all parts of the system. Decoupling capac-itors are necessary to achieve this, but the use of discrete capacitors in decoupling is

becoming less effective due to their parasitic inductance. This opens the door to theuse of integrated capacitors, with far less parasitic inductance, for this application.

The ideal power distribution system would look like a battery of constant volt-age, regardless of the current draw, connected to the IC by a zero-impedance line,

as shown in Figure 9.1. From the viewpoint of the IC, it would see constant voltageno matter how much power it drew or how its current requirements changed withtime over the space of a single clock cycle.

In reality, of course, this is not the case. In most systems, one power supply dis-tributes power for the entire system through a combination of wires, connectors,distribution planes within circuit boards, etc. All of these conductive paths have

parasitic inductance, which has no effect on DC, but has a significant effect at thehigh frequencies typical of IC operation. They also have parasitic resistance, whichaffects both DC and AC current. The problem, particularly in digital systems, is that

as ICs switch many devices between high and low logic levels at each clock cycle,their current demands change rapidly with time. Thus, the power supply is not justsupplying a constant current at a particular voltage, but is being asked to supply ahighly variable amount of current over a fraction of the clock cycle, which meansthat the current waveform has many components across a wide range of frequen-cies, from DC to several GHz. Any impedance present in the real power distribution



ISBN: 0-471-24431-7



system will produce a voltage drop as shown in Figure 9.2. Individual ICs will notsee the purely constant voltage they need for proper operation. Noise in the voltagesupply can cause false logic triggering or insufficient potential to drive signals on or off the chip. The current changes demanded by the IC will not be supplied becauseof the series inductance.

The solution to this problem is to put capacitors, called decoupling or bypass capacitors, across the power and ground distribution conductors, physically close tothe ICs that are demanding the varying current. These capacitors act as short-term,low-impedance reservoirs of charge, and supply current that cannot otherwise besupplied by the power supply because of the low-pass filtering action of the para-sitic inductances. They are referred to as “decoupling” because they decouple the

power distribution system from the current surges of the IC, or as “bypass” becausethey bypass whatever noise is on the power supply conductors to ground. This isshown in basic form in Figure 9.3. Viewed as decoupling capacitors, they act as bat-teries to run the IC for one clock cycle. In between periods of high current demand,the power supply acts as a battery charger to recharge the capacitor. Viewed as by-

pass capacitors, they are high-pass filters that short high-frequency noise generated by the IC and prevent it from getting back into the power distribution system.

178 DECOUPLING

Figure 9.1 An ideal power supply and power distribution system.

Figure 9.2 A real power supply and power distribution system without decoupling capaci-tors.



Considered still another way, the job of the decoupling capacitor is to make the power distribution system have zero AC impedance when viewed from the IC.Since the parasitic series inductances are relatively small, the IC can “see” all theway to the power supply at low frequencies. That is, low frequency components of varying current can be supplied directly from the power supply and its output ca-

pacitors. At high frequencies, it is the decoupling capacitor that must provide near-zero impedance. The capacitor should be sized to make its impedance sufficiently

low (ideally zero) over the frequency range of interest to satisfy the voltage stabili-ty requirements of the IC. The decoupling capacitor in Figure 9.3 is shown as a purecomponent with no parasitics of its own but, as described in Chapter 8, it wouldhave a small amount of ESR and ESL of its own along with some in the leads andvias between it and the IC.

The issue can also be examined in the time domain. The IC tries to draw a spe-cific amount of charge from the power distribution system in a certain amount of time. Because of the parasitic inductance, the power supply itself is unable to deliv-er that charge; it all must come from the decoupling capacitor. The capacitor obeysthe equation

I × t = C

× V

. That is, pulling a current I

out of a capacitor for atime t will reduce the voltage on that capacitor by V . The bigger the capacitor,the more charge it can store, and the less voltage drop will be produced by a givencurrent drain. The chain of decoupling capacitors must be able to keep the supplyvoltage within the tolerance of the IC throughout the period when the IC is drawingcurrent. This establishes the lower limit on capacitor values [1].

In normal operation, the power supply must be able to recharge the capacitor upto the full power supply voltage during one clock cycle, even though the IC is draw-ing large amounts of current during part of the cycle. If the intervening inductanceis too large, this will not be possible. This gives rise to the idea of a hierarchy of de-coupling in which each stage closer to the load is able to respond to higher frequen-cy components of the load current than the stage before. This is shown in Figure9.5. The capacitor closest to the power supply (furthest from the IC) supplies thelowest frequency components of the load’s varying current, the middle one suppliesmid-frequency components, and the capacitor closest to the load, with very little in-

9.1 POWER DISTRIBUTION 179

Figure 9.3 A real power supply and power distribution system with a decoupling capacitor.



tervening inductance, supplies the highest frequency currents. The power supplysimply delivers the average current needed by the whole system. The values of theindividual capacitors are a complex function of how the current requirement’s fre-

quency components are distributed through the system, which is in turn a functionof the IC’s demands as well as the value and location of the distributed parasitics onthe board and in the capacitors.

The picture is further complicated because there are many ICs and many decoupling capacitors in the system, but the principle is the same. The low-frequency en-ergy is typically supplied by large electrolytic capacitors, perhaps one on each

board; the mid-frequency energy by large ceramic SMDs, with several on each board; and the high-frequency energy by smaller ceramic SMDs placed close to theICs they decouple. Because the low-frequency capacitors are not as affected by the

series inductances of the power distribution system, they can be anywhere on the board. Capacitors for higher frequencies have to be located closer to the loads theyserve in order to minimize the inductance between them and the ICs they serve. Itshould be noted that the high frequencies and large current demands of the latest

180 DECOUPLING

Figure 9.5 Hierarchy of decoupling capacitors.

Figure 9.4 Impedance-frequency behavior of ideal and real decoupling capacitors.





real discrete capacitors, corresponding parasitics run approximately in proportion todiscrete component value or case size. In this example, the ESLs range from 500 to

100 pH, and ESRs from 80 to 20 m. Both the individual capacitor impedances aswell as the impedance of the parallel combination are shown. Note that parallelingcapacitors of different values rather than all the same value significantly broadensthe range of frequencies with low impedance. However, decoupling at frequencies>100 MHz is still difficult because of the intrinsic inductance of standard surface-

182 DECOUPLING

Figure 9.7 Comparison of one and five different decoupling capacitors in parallel.

Figure 9.6 Comparison of one and five identical decoupling capacitors in parallel.



mount devices. This has led to the development of low-inductance capacitors (~60 pH), such as the AVX LICA (low inductance capacitor array). Multiple devicesmust still be used in parallel to achieve a power distribution system impedance be-

low 0.1 ohm at frequencies in the GHz range [8].

9.3 DECOUPLING WITH INTEGRATED CAPACITORS

As described in Chapter 8, integrated capacitors have much less parasitic induc-tance than surface-mount discretes for three reasons. First, the current flows in op-

posite directions in the plates, which results in fields that tend to cancel each other out, lowering the inductance. Second, the plates tend to be flat and parallel in a sin-

gle plane, which decreases the current loop size relative to folded capacitors in asurface-mount case. Third, the integrated capacitor is in plane with the intercon-nects, further reducing the current-loop area and eliminating vias that contribute toinductance. The result is that the total inductance of an integrated capacitor, includ-ing lead and spreading inductance, can easily be less than a few pH. For example,using anodized tantalum, dielectrics of 1000 Å can be produced with good yields,leading to a per-square inductance, as measured, of ~4 pH, and about one square of resistance (about 10 m using 2 m sputtered Cu as the plates). Figure 9.8 shows acomparison of the 100 nF discrete from Figure 9.6 and a 100 nF integrated capaci-

tor, which would have an area of about 0.5 cm2 or 7 mm on a side. Even without thelower ESR, the improved ESL performance of the integrated capacitor would giveit superior decoupling performance [9].

In fact, the high frequency performance of this integrated capacitor would beeven better than pictured. The as-measured inductance reflects the problem of prob-

9.3 DECOUPLING WITH INTEGRATED CAPACITORS 183

Figure 9.8 Comparison of 100 nF discrete and integrated decoupling capacitors.



ing a device with a microwave probe, which is a two-point connection. In actuality,multiple connections could be made to the integrated capacitor. If they are made as

power/ground pairs to minimize loop inductance, these numerous connections par-

allel the inductance of many two-point connections. Simulations have shown thatwith line connections instead of point connections into a one-square capacitor, the

performance at 10 GHz would be at least five times better than a two-point connec-tion would indicate. This is shown in Figure 9.9, which shows a capacitor of only500 pF and very thin (resistive) plates. But the important feature is the difference inthe two simulations at >3 GHz. The line contact has a significant beneficial effecton high-frequency performance [10].

Figure 9.10 shows an array of 25 nF Ta2O5 capacitors on flex that have distrib-uted contacts along one half of their long side. Of course, the transition has to be

made somewhere from narrow interconnect or solder ball to the wide connection, but careful design using integrated capacitors can lower the overall inductance be-low anything achievable with surface mounts.

Since the inductance and the resistance of integrated capacitors, apart from leadsand contacts, is constant per square of area rather than per area itself, a 1 mm2 inte-grated capacitor would have the same inductance and resistance as a 1 cm2 device.The fact that parasitic inductance and resistance do not scale with size but capaci-tance values do provides another important advantage for decoupling. A single inte-grated capacitor can replace the multiple discrete capacitors mounted in parallel; a

certain total area is required for the integrated solution and it does not much matter how it is arranged, as long as the total number of squares is low.In order to determine the effectiveness of any decoupling scheme in today’s

high-frequency digital systems, it is necessary to model the power distribution sys-tem with a high level of detail. The power and ground planes are generally repre-sented by a “bedspring” model with per-area values of self-inductance, resistance,

184 DECOUPLING

Figure 9.9 The advantage of line contact over a point contact to an integrated capacitor.



and capacitance. The mutual inductance between the power and ground planes mustalso be considered. The models of the planes alone can have hundreds of nodes andcomponents. Then the models for decoupling capacitors and time-varying loads areconnected at appropriate locations, and a detailed simulation can be run [11, 12].The details of this level of modeling are, of course, well beyond the scope of this

book. Accurate prediction of the performance of a power distribution system, in-cluding the effects of all decoupling capacitors, requires an extremely elaboratemodel that takes into account capacitor placement, the incremental inductance of

portions of power distribution planes, and an accurate prediction of the time-variantcurrent loads of all ICs in the system. Needless to say, most systems are never mod-eled to this level of detail.

It has become clear from some modeling and measurement efforts that power distribution plane resonances can create problems when capacitors with very lowESR are used for decoupling. Lossy dielectrics, either for discrete or integrated ca-

pacitors, may be needed to quiet these effects [13].

9.4 DIELECTRICS AND CONFIGURATIONS FOR

INTEGRATED DECOUPLING

An extremely simple approach to integrated decoupling is to just reduce the thick-ness of the insulator between the power and ground planes, thereby forming a paral-

9.4 DIELECTRICS AND CONFIGURATIONS FOR INTEGRATED DECOUPLING 185

Figure 9.10 25 nF integrated capacitors with distributed contacts.



lel plate capacitor the size of the board. The Zycon “buried capacitance” material isa 2 mil layer of FR–4 that can be used between power and ground planes. This pro-vides a capacitance of 0.078 nF/cm2, which is a very small value. Some materials

that have been proposed for integrated decoupling in printed wiring boards consistof fine particles of high dielectric constant material mixed into an epoxy or other or-ganic that can be applied to copper foil in a thin layer. Even with very fine particlesof barium titanate or other ferroelectric materials, there is a limit on the density of

particles that can be mixed with an organic binder and still have the resulting mate-rial be processable. The resulting dielectric constant of many of these compositematerials is around 40–60. The inability to make extremely thin layers (<10 mi-crons or so) means that the capacitance is, at most, around 20 nF/cm2. Their perfor-mance at the highest frequencies may be limited by inductance caused by the

spacing between the plates or power distribution planes compared to thin-film inte-grated capacitors.If the specific capacitance is low and a large area of the board is used to boost the

total available capacitance to the required value, care must be taken in the design toensure that the entire board-sized capacitor can be seen by the ICs it serves. At veryhigh clock rates, the time of flight may be too short for the highest-frequency com-

ponents to reach very far from the chip. For a given design, say that the highest fre-quency to be considered is six times the clock frequency of 1 GHz. The distance of flight through the board at 6 GHZ is only about two inches, so whatever capacitance

is intended to decouple these frequencies must be well under that distance from theIC. It may be necessary to utilize an integrated dielectric with a higher specific capacitance to put the decoupling within reach.

Thin-film dielectrics are currently the only way to obtain over 100 nF/cm2. Tan-talum, for example, can be sputtered on copper foil and anodized, or Ta2O5 can besputtered directly to give up to 200 nF/cm2, with excellent high-frequency charac-teristics, as discussed in a previous chapter [14]. The same might be possible withTi or Nb. These represent the high end of the paraelectrics. Ferroelectrics are evenmore suitable for decoupling since they provide very high specific capacitances,

perhaps 1000s of nF/cm2

, and since their frequency- and temperature-dependent behavior is not a problem for energy storage as long as they meet the minimum val-ues. The problem with utilizing them in organic boards, as has been mentioned fre-quently before, is that they generally require a high-temperature anneal to achievehigh dielectric constants. To circumvent this problem, integrated capacitors basedon ferroelectrics can be formed on metal coupons separately from the organic boardand laminated in later, as in the DuPont process [15, 16].

It was pointed out earlier that integrated capacitors are starting to be seen on-chip, utilizing gate oxide over otherwise unused areas of the IC [17]. Gate oxide

can provide up to several hundred nF/cm2

with the lowest possible parasitic in-ductance, but the areas are limited. It probably would never be economical to in-crease chip size solely for providing on-chip decoupling. Some preliminary work has been done on fabricating capacitors directly on top of the passivation layer of the IC, as shown Figure 9.11 [18] but this process would have to be very highyield to be feasible.

186 DECOUPLING



9.5 INTEGRATED DECOUPLING AS AN ENTRY APPLICATION

Decoupling is an ideal candidate for an entry application for integrated passives.There are no critical tolerance issues; any amount of capacitance is a help. Althoughhuge amounts of capacitance would be useful at the board level, it is not anticipatedthat integrated decoupling will replace the low-frequency bulk decoupling supplied

by electrolytic capacitors, or even all of the mid-frequency decoupling required byrapid power fluctuations controlled by power management techniques. But integrat-ed decoupling will replace a great many discrete ceramic chip capacitors that cur-

rently crowd around high-powered microprocessors, and will eliminate the boardarea and dozens of solder joints needed to mount them. [19] Surface space near these chips would be better utilized for memory access or on-board communicationfunctions. With the proper low-inductance IC packaging, the integrated capacitor will be useful up to several gigahertz. Integrated decoupling requires no modifica-tions to the CAD system to be useful. It must be accounted for in the design

process, of course, and proper design rules for clearances must be implemented, butthe integrated decap does not need the design system to understand that componentscan be located within a PWB, not just on the top and bottom.

One of the most important unknowns in replacing discrete decoupling with inte-grated decoupling is determining how much capacitance is really needed. In dis-crete decoupling, much of the capacitance is present only because more capacitorswere put in parallel in order to reduce the total inductance. When evaluating inte-grated decoupling, this thinking results in a desire to put in large amounts of capac-itance, much more than is needed to run the IC for one clock cycle. However, due to

9.5 INTEGRATED DECOUPOING AS AN ENTRY APPLICATION 187

Figure 9.11 Decoupling capacitor fabricated on the passivation layer of an IC.



the inherently low inductance of integrated capacitors, the amount required should be evaluated on its own merits. The complexity of determining this, particularlywith all of the various board, power supply, and IC configurations, probably means

that some combination of modeling and experimentation is necessary [20].As an example of how direct measurements of decoupling performance can be

done, Figure 9.12 shows a side-by-side test structure used to measure decoupling performance, designed by Pat Parkerson at the University of Arkansas. Two iden-tical high-current chips were mounted in a single enclosure, the one of the rightwith a 22 nF surface mount decoupling capacitor and the one of the left with a 22nF integrated decoupling capacitor made of anodized Ta2O5 with the same value.The 4 × 4 mm integrated capacitor is beneath the two broad power-ground padsand cannot be seen. Figure 9.13 shows the measurements of power-to-ground

noise for the two cases with the test ICs running at 6.7 MHz. The peak-to-peak waveform using the integrated capacitor was considerably less due to its reducedinductance.

Decoupling is a function presently required by every electronic system and iscurrently satisfied using discrete capacitors only. However, integrated capacitorsare very attractive for this application due to their low inductance, savings of sur-face area, and lack of solder joints. Decoupling is one of the few applications inwhich a single integrated component can replace multiple surface mounts, againdue to the very low inductance of the integrated units. In the near future, high-

speed systems will require considerably more current fed to them at higher fre-quencies and will require lower voltage noise levels. Integrated capacitors may bethe only way to decouple some of these systems. The potential volume of PWBswith integrated decoupling will drive technology development and bring costsdown. Since yield will be critical, introduction will probably be first implementedon small substrates, such as individual IC packages or small few-chip modules,

188 DECOUPLING

Figure 9.12 Side-by-side test structure for measuring the relative performance of integrat-ed and surface-mount decoupling.



rather than on large motherboards. As yields and economics allow, the integrateddecoupling solution will move to larger and larger boards, until it is regarded as

standard practice.

REFERENCES

1. L. Schaper and D. Amey, “Improved Electrical Performance Required for Future MOSPackaging,” IEEE Transactions on Components, Hybrids, and Manufacturing Technolo-

gy, 283–289, September, 1983.

2. L. Smith, “Packaging and Power Distribution Design Considerations for a Sun Mi-

crosystems Desktop Workstation,” In Electrical Performance of Electrical PackagesConference, Oct, 1997.

3. L. Smith, “Decoupling Capacitor Calculations for CMOS Circuits,” In Electrical Perfor-

mance of Electrical Packages Conference, Nov, 1994.

4. W. Becker et al., “Modeling, Simulation and Measurement of Mid-Frequency Simulta-neous Switch Noise in Computer Systems,” IEEE Transactions on Components, Pack-

aging and Manufacturing Technology, Part B, 21, 2, 1998.

5. L. Schaper and G. Morcan, “High Frequency Characteristics of MCM Decoupling Ca- pacitors,” In Proceedings of the 46th ECTC, pp. 358–364, 1996.

6. A. Murphy and F. Young, “High Frequency Performance of Multilayer Capacitors,” IEEE Transactions on Microwave Theory and Techniques, 43, 2007–2015, 1995.

7. A. Murphy and F. Young, “High Frequency Design and Performance of Tubular Capac-itors,” IEEE Transactions on Components, Hybrids, Manufacturing Technology, 16, 2,228, 1993.

8. L. Smith et al., “Power Distribution System Design Methodology and Capacitor Selec-

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Figure 9.13 Comparison of power-ground voltage to an IC with integrated and discrete de-coupling.



tion for Modern CMOS Technology,” IEEE Transactions on Advanced Packaging, 22,

3, 284, 1999.

9. L. Schaper, R. Ulrich, D. Nelms, E. Porter, T. Lenihan, and C. Wan, “The “Stealth” De-

coupling Capacitor,” In Proceedings of the 47th ECTC, pp. 724–729, 1997.10. K. Chen, W. D. Brown, L. Schaper, S. S. Ang, and H. Naseem, “A Study of the High

Frequency Performance of Thin Film Capacitors for Electronic Packaging,” IEEE

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11. W. Becker et al., “Modeling, Simulation, and Measurement of Mid-Frequency Simulta-neous Switching Noise in Computer Systems,” IEEE Transactions on Components,

Packaging, and Manufacturing Technology, Part B: Advanced Packaging, 21, 2, 1998.

12. S. Chun, M. Swaminathan, L. D. Smith, J. Srinivasan, Z. Jin, and M. K. Iyer, “Modelingof Simultaneous Switching Noise in High Speed Systems,” IEEE Transactions on Ad-

vanced Packaging, 24, 2, 132, 2001.

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14. Y. Imanaka, T. Shioga, and J. Baniecki, “Decoupling Capacitor with Low Inductance for High Frequency Digital Applications,” Fujitsu Science and Technology Journal, 38, 1,22, 2002.

15. R. Ulrich and L. Schaper, “Materials Options for Dielectrics in Integrated Capacitors,”In Proceedings of the International Symposium on Advanced Packaging Materials,

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190 DECOUPLING



191

CHAPTER 10

INTEGRATED INDUCTORS

GEERT J. CARCHON AND WALTER DE RAEDT

10.1 INTRODUCTION

Inductors integrated in today’s typical silicon processes cannot meet the high per-

formance specifications required for future RF ICs [1] as they typically use an

Al/Cu metallization to pattern the spiral and underpass. This metal is inherently

fairly resistive and, as the integration level increases, the metal thickness is typical-ly thinned to decrease the achievable line pitch. As will be shown in Section 10.2,

this thinning of metal layers and their associated interlayer dielectrics, creates a fun-

damental problem when trying to realize high-quality inductors on a Si chip as

process technologies advance.

There are basically two options to realize the high-quality inductors required for

future high performance applications:

1. In the system in a package (SiP) approach, high-quality inductors and other

passive components are realized off-chip using a passive integration technol-ogy such as LTCC or MCM-D [2–13]. In this case, a full codesign between

the active and passive components is required. The SiP approach results in

higher performance inductors as compared to on-chip Si-solutions as low-

loss dielectrics and thick Cu layers can be readily used. In addition, due to the

lower cost per-unit area, size constraints for the off-chip passive components

are not as severe as for an on-chip solution, thereby further increasing the

performance that may be achieved.

2. Another approach is to further increase the performance of on-chip inductors.

This may be done by replacing the conventional Al/SiO2 technology withlow-k materials and thick Cu metallization [1, 14–18]. However, thick Cu is

not a standard back-end process and the dielectric in between the spiral and

the lossy silicon substrate is still relatively thin.

1. An alternative is the use of micromachining techniques to remove the



ISBN: 0-471-24431-7



lossy substrate underneath the spiral inductor in a postprocessing step. This

may be done from the top [19, 20] or the backside [21] of the Si wafer. Other

possibilities are the creation of an air gap in between the spiral inductor and

the substrate using air bridge technology [22] or the realization of spiral in-ductors using wafer-level packaging techniques [23–27]. In the latter process,

thick Cu layers with high accuracy and small dimensions may be realized

above the passivation, on top of standard silicon wafers. Due to the availabil-

ity of relatively thick dielectrics, the distance between the spiral and the lossy

silicon substrate can be increased, thereby improving the high frequency per-

formance of the inductors.

Whichever of the two options described above, on- or off-chip, is selected for the

integration of the inductors, the layout of the integrated spiral inductor is basicallythe same and governed by the same factors: material properties and inductor operat-

ing principles.

The goal of this chapter is to study the performance of spiral inductors for RF ap-

plications and to see how their performance is related to material parameters (the

conductivity of the used metals, the resistivity/loss tangent of the used dielectrics,

their respective thicknesses, etc.) and to design parameters (inductor type and lay-

out parameters). First we will describe several inductor layouts and briefly discuss

the operating principle as this will help in understanding the limiting factors of per-

formance. Then, the equivalent circuit model of a spiral inductor will be explained.The inductor’s quality factor, Q L, will be presented and the relation between the

quality factor and the equivalent circuit parameters will be outlined and illustrated.

This will be used to explain how the performance of spiral inductors may be im-

proved by technological, design, and layout changes.

Several approaches to predict the performance of integrated inductors will be de-

scribed and several examples of inductors integrated in various technologies (Si,

GaAs MMICs, MCM-D, and LTCC) will be given. Finally, we will discuss some

circuit applications to show how the overall circuit performance may be determined

by the performance of the inductors.

10.2 INDUCTOR BEHAVIOR AND PERFORMANCE PARAMETERS

10.2.1 Inductor Layouts and Values

Some layouts of integrated inductors are shown in Figure 10.1. The transmission

line inductor uses a single metal strip, whereas the loop inductor is more compact

and has a shape. Repeats of these layouts may be cascaded, thereby resulting in a

meander inductor. Due to the enhanced inductive coupling between neighboring

turns, spiral inductors (Figure 10.1d) allow a larger inductance/unit area, resulting

in increased performance through reduced parasitic effects compared to single-layer

configurations (layouts a, b, and c). Solenoid inductors (layout e) may also be inte-

grated, although the three-dimensional (3-D) structure is difficult to realize using

conventional planar technology.

192 INTEGRATED INDUCTORS



Spiral inductors require a multilayer process for the realization of the over- or

underpasses to connect the inner part of the spiral inductor to the outside. In the fol-

lowing, we will mainly focus on transmission line inductors and spiral inductors.

The loop inductor can be considered as a special case of the spiral inductor with less

than 1 turn. The solenoid inductor will also be briefly discussed.

Typical inductance values for RF applications in the 1 to 5 GHz range cover the

range of 500 pH up to 5 nH, although values up to 10 nH may also be used. The

maximum frequency at which an inductor may be used is its resonance frequency

10.2 INDUCTOR BEHAVIOR AND PERFORMANCE PARAMETERS 193

(a) (b)

(c)

(d) (e)

Figure 10.1 Layout examples of integrated inductor (a), transmission line inductor, (b)

loop inductor, (c) meander inductor, (d) circular spiral inductor (the layout parameters are

also indicated), and (e) solenoid inductor.



which is, in turn, determined by material and layout parameters. When the inductor

is used as an RF biasing choke, it is used at the resonance frequency. In most other

applications, such as filters, matching networks, resonators, etc., the inductor is

used below its resonant frequency. In resonator applications, a variable capacitanceis usually placed in parallel/series with the inductor.

10.2.2 Inductor Operating Principles

An inductor is a passive electronic component that stores energy in the form of a

magnetic field. It is of primary concern for time-varying problems. To understand

the inductor’s operating principle, one may first consider the simple case of a trans-

mission line inductor (Figure 10.2a): when the conductor is carrying a current I

flowing in the direction into the page, indicated by the symbol , a magnetic field H is created as illustrated in Figure 10.2a. The magnetic field vector H

is related to

the magnetic flux density vector

B by

B = H

. Here, the permeability is a proper-

ty of the medium. The inductance L is defined in terms of flux linkage [28] by

L = S

B · d

S (10.1)

where the surface S must be specified. Consider, for example, the loop of wire

shown in Figure 10.2b. The current I produces a magnetic flux in the hatched area S bounded by the loop. Some of the flux produced by the current I is also inside the

wire itself. It is convenient to separate the inductances related to these two compo-

nents of flux and call them, respectively, external inductance and internal induc-

tance. The self-inductance of a wire is the sum of the external and internal induc-

tance. For high frequencies, there is not much penetration of the fields into the

conductors, hence, the external inductance is the main contribution to the self-in-

ductance.

The mutual inductance M is defined as the inductance arising from the induced

voltage in one circuit due to the current flowing in another circuit [28]. The mutual

1

I


(a) (b)

Figure 10.2 (a) Relation between a current in a conductor and the resulting magnetic field

vector H

. (b) Loop of wire; hatching shows the surface used for calculation of the external in-

ductance.



inductance may be calculated by finding the magnetic flux 12 linking one circuit

related to the current in the other circuit. Thus, for two circuits 1 and 2, we obtain

M 12 = = (10.2)

where

B2 is the magnetic flux arising from current I 2 and integration is over the sur-

face of circuit 1. By reciprocity, M 21 = M 12 for isotropic magnetic materials, so the

calculation may be made with the inducing current in either circuit.

A vertical cross section of a spiral inductor is given in Figure 10.3a: the currents

on the right-hand side flow into the page, the currents on the left hand side flow out

the page, as indicated by the symbol. In a first approximation, the magnetic fieldsassociated with the current in each of these conductors add constructively, thereby

resulting in a large inductance per unit area. The inductance further increases by the

inductive coupling between the different coils (mutual inductance) (see also Section

10.3.2.3).

By applying the same principle to the meander inductor shown in Figure 10.1c,

one can understand that the overall inductance/area ratio for this type is lower than

for the spiral inductor because the magnetic fields in between two closely spaced

lines do not add constructively. Hence, the mutual inductance between two closely

spaced lines is not constructive.Magnetic fields also interact with conductive materials, such as conductors or

low-resistivity dielectrics, hereby giving rise to eddy currents. This effect needs to

be understood since it limits the performance of spiral inductors. Assume that con-

ductor 1 in Figure 10.3b is carrying a current I 1 flowing in the indicated direction.

On the left-hand side of the conductor, this current has an associated magnetic field

density B1, oriented perpendicular to the page, in the direction coming out of the

page. The field B1 also crosses conductor 2. According to the law of Faraday–Lenz,

an electrical field is magnetically induced in conductor 2, thereby generating circu-

lar eddy currents I eddy. The direction of these eddy currents is such that they oppose

12

I 2

S 1

B2d

S 1

I 2


(a) (b)

Figure 10.3 (a) Cross section of a spiral inductor indicating the direction of the current and

the resulting magnetic field. (b) Creation of eddy currents in conductors due to the presence

of a varying magnetic field.



the original change in magnetic field. So the magnetic field density Beddy, resulting

from the eddy currents, has a direction flowing into the page.

Eddy currents manifest themselves as skin and proximity effects [29]:

In the case of the skin effect, the time-varying magnetic field due to the cur-

rent flow inside the conductor induces eddy currents in the conductor itself.

The proximity effect takes place when the conductor is under the influence of

a time-varying magnetic field produced by a nearby conductor carrying a

time-varying current, as shown in Figure 10.3b. In this case, eddy currents are

induced in the first conductor, whether or not it carries current itself.

It can be easily understood that eddy currents flowing in a material with finite con-

ductivity will result in an increase of the AC resistance. The distribution of the eddycurrents depends on the geometry of the conductor and its orientation with respect

to impinging time-varying magnetic fields. The most critical parameter pertaining

to eddy current effects is the skin depth , defined in Equation 10.3, where and

are the permeability and conductivity of the used material and f is the frequency.

= (10.3)

The skin depth expresses the “depth of penetration” by the electric current and mag-netic flux into the surface of a conductor at high frequencies. Hence, at high fre-

quencies, the current can be regarded as flowing only at the surface of the conductor

(rather than a homogenous distribution) up to a depth . The severity of the eddy

current effect is determined by the ratio of the skin depth to the conductor thick-

ness: the eddy current effect is negligible only if the skin depth is much greater than

the conductor thickness.

When referring to Figure 10.3a, one can understand that eddy currents are gener-

ated in every turn of the spiral inductor as every conductor shown in Figure 10.3a is

under the influence of the magnetic field created by itself as well as the neighboringturns. The nature of eddy currents, explained above, also clearly illustrates the in-

fluence of a conductive material (e.g. a solid metal plane or conductive dielectric)

present directly underneath the inductor. This will be discussed in more detail in

Section 10.2.7.4.

10.2.3 Equivalent Circuit

The equivalent circuit of a spiral inductor, valid for an inductor on a low-resistivity

substrate (e.g., lightly doped silicon) is given in Figure 10.4a [15, 29–34]. One mayobserve that, besides the primary inductance LS , several other components are pres-

ent that are considered parasitic elements. They occur due to the nonideal behavior of

the inductor: nonzero length, conductive and dielectric losses, etc. The location of

these parasitic elements for a microstrip-based circular spiral inductor with the coils

separated from the lossy Si by a thin low-loss dielectric is shown in Figure 10.5.

1

f




For high-resistivity substrates, such as alumina, glass, or quartz, R gL is very large

and may be neglected. The capacitances C L1, C L2, and C L3 may then be replaced by

a single capacitance C GL (similar for C GR and RGR). The resulting model is given in

Figure 10.4 (b).

When the substrate has a very low resistivity, eddy currents are induced in the sub-

strate due to the penetration of the inductor’s magnetic field, as outlined in Section

10.2.2 [35]. The direction of this induced current is such that it opposes the original

change in magnetic field. So the eddy currents flow in a direction opposite to the cur-

rent in the conductor, thereby increasing the losses and decreasing the overall induc-tance. The substrate currents may be considered to flow in an imaginary coil in the

substrate underneath the inductor. To account for this, an inductance coupled to the

primary inductance LS and resistance can be added to the model to describe the addi-

tional losses and the loss in series inductance [36]. More information on the effect of

substrate resistivity on the inductor performance may be found in [37].


(a)

(b)

Figure 10.4 Lumped element spiral inductor model for (a) low-resistivity substrates, (b)

high-resistivity substrates.



A number of variations on the model shown in Figure 10.4a exist: inductances

may be added at the input and output to represent the feeding lines, the feedback ca-

pacitance is omitted [38], capacitances C L1 and C R1 may be omitted if there is noground plane in the plane of the spirals above the lossy substrate [29, 31–33], ca-

pacitances C L3 and C R3 are sometimes omitted [15], and a resistance is also some-

times put in between C L2 and C R2 [39].

10.2.4 Extraction of the Equivalent Circuit Parameters

For a high-resistivity substrate, one can easily extract the equivalent circuit parame-

ters from the component’s Y parameters as shown in Equation 10.4:

RS = –Re ; LS = –Im ;

C GL = ; C GR = ; = 2 f (10.4)Im(Y 21 + Y 22)

Im(Y 11 + Y 12)

1

Y 21

1

Y 21


Figure 10.5 Cross section of a circular spiral inductor on a low resistivity substrate, illus-

trating the location and nature of the parasitic elements. RS represents the series metal losses

in the spiral coils. C fb represents the capacitive coupling in between the turns and the cou-

pling between coils and over/underpass. R gL and R gR represent substrate losses, stemming

from the penetration of the inductor’s electric field into the substrate. C L and C R represent thecapacitances to ground: for an inductor on a low resistivity substrate, C L2 is the oxide capaci-

tance (separating the spiral inductor and the low resistivity substrate), whereas C L3 is the sili-

con substrate capacitance.

Low-K

dielectric

Substrate

Ground



The information in Y 21 does not allow a unique determination of RS , LS , and C f b be-

cause there are three unknowns with only two equations. Extracting the inductance

value from measurements at the lowest frequencies, where the influence of C f b is

negligible, may solve this. The feedback capacitance C f b can then be determined ei-ther from the resonance behavior of Y 21 or by an optimization procedure. As report-

ed in [40], the feedback capacitance can become negative when an optimization

procedure is used due to the distributed nature of the spiral inductor; however, the

capacitance of the lead-out bridge is usually dominant such that positive values are

obtained. The relation between the feedback capacitance and the resonance fre-

quency of the component is given in Equation 10.5. Here f res1 and f res2 are the reso-

nance frequencies of the inductor with port 2 and port 1, respectively, connected to

ground.

f res1 = ; f res2 = (10.5)

The result of the above extraction, for a MCM-D spiral inductor (the technology

is described in section 10.4.3) with layout parameters (see Figure 10.1d) N = 2.5,

W coil = 30 m, S coil = 20 m, Rin = 100 m, and Dout = 200 m is shown in

Figure 10.6a.

At low frequencies, one may note that the extracted series inductance slightly

decreases as the conductors reach the skin-effect range. At high frequencies, the ex-tracted inductance increases due to the parallel resonance with C f b. After the reso-

nance of Y 21, the extracted value becomes negative. For the ground capacitances

C GL and C GR, a frequency range is found at which constant values can be extracted.

The extracted resistance increases with increasing frequency from its DC value due

to eddy currents and usually has a ripple at higher frequencies. The short-to-open

resonance frequency of the above described spiral inductor is located at 13 GHz.

Above this frequency, the input impedance of the spiral inductor becomes capaci-

tive, which limits the use of the inductor in most applications. Due to the asymme-

try of the spiral, the outer ground capacitance C GL, associated with the outer turns,is larger than the inner ground capacitance C GR, associated with the inner turns,

causing a difference in the parallel resonance frequencies.

Although the spiral itself shows multiple resonances, the lumped equivalent cir-

cuit has only one resonance, causing a deviation between the measurements and the

simulation at higher frequencies. Additionally, at the highest frequencies, the di-

mensions of the spiral become comparable to the wavelength such that a distributed

approach has to be used in order to correctly model the behavior. The agreement be-

tween the measured and simulated performance, using the model in Figure 10.4b, of

the above spiral inductor is given in Figure 10.6b. A good agreement up to the reso-nance frequency (13 GHz) may be observed. When the inductor is to be modeled

above the short-to-open resonance frequency, a cascaded version, using two or

more stages, of the model shown in Figure 10.4b may be used [41–44] to increase

the accuracy of the model at higher frequencies.

1

2 L (C G R + C fb )

1

2 L (C G L + C fb )




10.2.5 Figure of Merits: Q L, Q LC, FOML

The performance of inductors is usually expressed by a quality factor, Q. A thor-ough understanding of this quality factor is, hence, mandatory. First we will de-

scribe the difference between the quality factor Q, used to describe the performance

of a resonator, and the quality factor Q L, commonly used to describe the perfor-

mance of inductors.


(a)

(b)

Figure 10.6 (a) Extracted equivalent circuit parameters as a function of frequency. — = Ls,

= C GR, = C GL. (b) Agreement between measured (—) and simulated (, ) S parame-

ters using the lumped element model in Figure 10.4b.



10.2.5.1 Quality Factor. An important parameter in the discussion of the per-

formance of spiral inductors is the quality factor, Q [32, 43, 45–47], defined as

Q = 2 (10.6)

Equation 10.6 also defines the Q of an LC tank. The definition is fundamental in the

sense that it does not specify what stores or dissipates energy. The distinction be-

tween an inductor Q L and LC tank Q LC lies in the intended form of energy storage.

For an inductor, only the energy stored in the magnetic field is of interest. Any en-

ergy stored in the inductor’s electrical field as parasitic capacitances is counterpro-

ductive. Hence, Q L is proportional to the net magnetic energy stored. An inductor is

at self-resonance when the peak magnetic and electric energies are equal. There-fore, Q L vanishes to zero at the self-resonant frequency and becomes negative

above the resonance frequency. Q L can hence be expressed as

Q L = 2 (10.7)

and may be obtained from the measurements as

Q L = (10.8)

where Z in is the input impedance of the inductor when one side is connected to

ground. It should be noted that Equation 10.8 only gives a good approximation of

Equation 10.6 at the lowest frequencies, as long as the energy stored in the parasitic

capacitances is negligible compared to the energy stored in the inductor.

In contrast, for an LC tank, the energy stored is the sum of the average magnetic

and electric energies. The Q-factor of an LC -tank at resonance may also be deter-

mined as the ratio of the resonant frequency to the –3 dB bandwidth of the resonator [28, 45]. The above described difference in Q-factor is quite often overlooked in the

design/optimization of spiral inductors. As we will see in Section 10.5, the Q-factor

of the LC -tank is very often important for the performance of the circuit (e.g., nar-

rowband bandpass filters, VCOs, etc.), however, in most publications on spiral in-

ductors, only the Q L factor is considered. The two definitions are however different:

Equation 10.7 may become negative, whereas equation 10.6 does not.

10.2.5.2 Mathematical Treatment of the Q-factor QL . To discuss the Q L

factor of a spiral inductor, it is more convenient to reorganize the circuit shown inFigure 10.4a to the form of Figure 10.7a, as the frequency-dependant parameters

C LP , C RP , R LP , and R RP can be directly extracted from the Y parameters of the com-

ponent. The relation between C LP , R LP , and C L1, C L2, C L3, and RGL (Figure 10.4a) is

given in Equations 10.9 and 10.10.

Im(Z in)

Re(Z in)

peak magnetic energy – peak electric energy

energy loss in one cycle

energy stored

energy loss in one cycle




R LP = + (10.9)

C LP = C L1 + C L2 (10.10)

The Q L factor is calculated with one port shorted to ground. When port 2 is shorted

to ground, the model shown in Figure 10.7a reduces to the one shown in Figure

10.7b. It can be shown [32] that the Q L factor of the inductor can now be written as

Q L = 1 – – 2 LS (C f b + C P ) (10.11)

Q L = (substrate loss factor)(self-resonance factor)

where LS / RS accounts for the magnetic energy stored in the inductance and the

ohmic loss in the series resistance. The second term in Equation 10.11 is a substrate

loss factor representing energy dissipated in the lossy substrate. The last term is the

self-resonance factor describing the reduction in Q L due to the increase in the peak

electric energy with frequency and the vanishing of Q L at the self-resonant frequen-

cy.

The different contributions in Q L factor are shown in Figures 10.8 and 10.9 for an

inductor realized on a 10 -cm silicon substrate using data from [14]. One may ob-

serve that Q L is well described by the ratio LS / RS at low frequencies when both

degradation factors have values close to unity. As frequency increases, the degrada-tion factors decrease from unity, hereby reducing the Q L factor of the spiral inductor.

For this specific inductor realized on a 10-cm Si substrate, the substrate loss factor

is dominant up to about 20 GHz. For inductors realized on high-resistivity substrates,

the self-resonance factor is dominant as the substrate loss can often be neglected.

LS

RS

R S 2(C f b + C LP )

LS

R LP

R LP + [( LS / RS )2 + 1] RS

LS

RS

1 + 2(C L2 + C L3)C L3 R2GL

1 + 2(C L2 + C L3)2 R2GL

RGL(C L2 + C L3)2

C 2 L2

1

2C 2 L2 RGL


(a) (b)

Figure 10.7 (a) Reorganized lumped-element spiral inductor model of Figure 10.4a. (b)

Equivalent circuit if one port of the model shown in Figure 10.7a is connected to ground.




Figure 10.8 Q L-limiting factors for an inductor realized on a 10 -cm Si substrate with pa-

rameters LS = 1.95 nH, C L2 = C R2 = 180 fF, C f b = 30 fF, RS = 3.2 , C L1 = C L3 = C R1 = C R3 =

0, and RG = 800 (data from [14]).

Figure 10.9 Q L contributions for an inductor realized on a 10 -cm Si substrate with para-meters LS = 1.95 nH, C L2 = C R2 = 180 fF, C f b = 30 fF, RS = 3.2 , C L1 = C L3 = C R1 = C R3 = 0,

and RG = 800 (data from [14]).



In the special case of high-resistivity substrates (where R LP in Figure 10.7 is in-

finity), the Q L factor of the inductor may be written as

Q L = 1 – – 2 LS (C fb + C P ) (10.12)

When the series resistance RS is assumed to be frequency independent, one can

show that the Q L factor reaches its maximum at a frequency f Qmax, given by

f Qmax = – (10.13)

The Q L factor becomes zero at a frequency f Q=0 given by

f Q=0 = – (10.14)

which implies the following relation between f Qmax and f Q=0:

f Qmax =

f Q=0 (10.15)

10.2.5.3 Graphical Interpretation of QL . In the following discussion, the

parameters of a MCM-D spiral inductor (the technology is described in Section

10.4.3) with layout parameters N = 2.5, W coil = 30 m, S coil = 20 m, Rin = 100 m,

and Dout = 200 m are used as a benchmark. The equivalent circuit parameters are

LS = 3.4 nH, C GL = C GR = 40 fF, C fb = 4 fF, and RS = 0.84 .

The variation of Q L as a function of RS is shown in Figure 10.10 with RS being

frequency independent. It can be seen that RS directly influences the low-frequencyslope of Q L and the maximum Q L factor.

The variation of Q L for various capacitances to ground is shown in Figure 10.11.

One may observe that C G does not influence the low frequency slope of Q L because

the self-resonance factor is 1. The influence on the inductor’s Q L-factor at the

lower microwave frequencies is also limited. The capacitances to ground primarily

limit the high-frequency performance, given by the resonance frequency and, ac-

cordingly, the maximum Q L-factor. It should be noted that increasing C f b has the

same effect on Q L as an increased capacitance to ground.

The variation of Q L for various RG is shown in Figure 10.12 for an inductor real-ized on a 10 -cm Si substrate (data from [14]; the nominal values are LS = 1.95

nH, C L2 = C R2 = 180 fF, C fb = 30 fF, RS = 3.2 , C L1 = C L3 = C R1 = C R3 = 0, and RG

= 800 ). One may observe that RG does not influence the low-frequency slope of

Q L (the substrate loss factor 1).

1

3

RS 2

LS 2

1

LS (C G + C f b)

1

2

RS 2

LS 2

1

LS (C G + C f b)

1

3

1

2

RS 2(C fb + C P )

LS

LS

RS





Figure 10.11 Variation of the inductor Q-factor Q L for various C G . Example for an

inductor on a high-resistivity glass substrate with parameters LS = 3.4 nH, C GL = C GR =

28/40/52 fF, C f b = 4 fF, and RS = 0.84 .

Figure 10.10 Variation of the inductor Q-factor Q L for various RS . Example for an inductor

on a high-resistivity glass substrate with parameters LS = 3.4 nH, C GL = C GR = 40 fF, C f b =

4 fF, and RS = 0.68/0.84/1.0 .



It can be noted that decreasing RG lowers the resonant frequency of the spiral.

One may also note that the maximum Q L factor for RG = 8 is higher than for RG =

80 – 800 .

10.2.5.4 FOML . As will be shown in section 10.5.5, the quality factor Q of a

spiral inductor directly influences the performance of narrowband bandpass filters

and voltage-controlled oscillators and is hence a good comparison criterion to com-

pare the performance of several technologies for these applications. The previously

discussed quality factors, however, do not take the consumed area into account. For

this purpose, one may use another figure of merit, FOM L, [11] given by

FOM L = (10.16)

The FOM L will be expressed here in nH/mm2. This figure of merit is, however, less

frequently used than the Q and Q L-factor to compare the performance of integrated

inductors. It generally gives a relatively high priority to the ratio inductance/unit

area, thereby giving high values for inductors realized with a large number of turns

or with very narrow strips and spaces.

10.2.6 Spiral Inductor Layouts

Spiral inductors may be realized in various ways; however, the circular (Figure

10.1d), octagonal (Figure 10.13a), and rectangular (Figure 10.13b) realizations are

Q L L s

Area


Figure 10.12 Variation of the inductor Q-factor Q L for various RG . Example for an induc-

tor on a 10 -cm Si substrate with parameters LS = 1.95 nH, C L2 = C R2 = 180 fF, C f b = 30 fF,

RS = 3.2 , C L1 = C L3 = C R1 = C R3 = 0, RG = 8 , 80 , 400 , 800 , 4000 , and 8000 .



the most common ones. For mask-making purposes, the octagonal and rectangular

realizations are preferred as they only require a limited number of points. For pro-

cessing reasons, on the other hand, rounded shapes are preferred since sharp angles

and corners create stresses in thin films.

The influence of the inductor layout on the Q-factor was experimentally studied

in [48]. It was found that the resistance of circular and octagonal-shaped inductors

is about 10% smaller than that of a square-shaped inductor with the same induc-

tance value. On the other hand, for the same inductance value, a rectangular realiza-

tion has a smaller distance between the input and output ports and may, therefore,

result in a more area effective solution for some applications. These inductors also

have a lower layout complexity. In the paper [48], however, the area consumption is

not taken into account. In [49], circular and rectangular inductor layouts, realized

using multilayer thin-film MCM-D technology, described in Section 10.4.3, are

compared based on the following comparison criteria:

Equal area consumption (equal cost): the circular/rectangular cut out from the

ground plane is used (Figure 10.14).

Equal strip width and slot.

Equal DC resistance: this implies that the circular and rectangular coil realiza-

tions have an equal total length.

Pictures of a circular and rectangular inductor (layouts based on the above de-

scribed comparison criterion) are shown in Figure 10.14 (equal scale).

The layout parameters of some investigated spiral inductor geometries are given

in Table 10.1, the explanation of the symbols can be found in Figure 10.1d. Only

the layout parameters of the circular realization are given, as the parameters of the


(a) (b)

Figure 10.13 Some layout alternatives to the circular spiral inductor: (a) Octagonal spiral

inductor, and (b) rectangular spiral inductor (the layout parameters are also indicated) exam-

ples of a CPW-based GaAs MMIC technology.



rectangular realization can be determined using the above-mentioned comparison

criterion. The measured performance of the corresponding circular and rectangular

inductors is given in Table 10.2.

It can be noted that for an equal area and DC resistance, a circular layout consis-

tently results in a higher inductance/unit area, a higher maximum Q L-value and a

higher FOM L; however, the distance between the input and output ports is larger for

the circular realization. In some cases, this may also be used as the size-determiningfact.

10.2.7 Improving Q L by Technology and Layout Parameters

As has been explained in Section 10.2.5, the performance of an inductor with a giv-

en LS may be improved by modifying RS , RG , or C G . This may be done by changes

in the technology as well as by layout optimization. In the following, we will first

concentrate on technological improvements. The influence of the layout parameters

will be discussed afterwards.

10.2.7.1 Improving QL by Reducing the Series Resistance. From a

technological point of view, the most straightforward way to decrease the series re-


(a) (b)

Figure 10.14 Picture of an equivalent circular (a) and rectangular (b) MCM-D spiral induc-

tor (on equal scale).

Table 10.1 Layout parameters of the circular MCM-D spiral inductor realizations

# N W coil (m) S coil (m) Rin (m) Dout (m) Area (mm2)

C L1 2.5 20 10 100 50 0.19

C L2 3.5 10 10 50 50 0.10

C L3 1.5 20 10 100 50 0.15

C L4 2.5 10 10 50 50 0.08

C L5 4.5 20 10 100 50 0.29



sistance is to use a metal with a high conductivity and a sufficient thickness. This is

demonstrated in the following situations:

Si technologies in which thin Al layers are replaced by Cu layers [1, 14–18].

The fact that LTCC has an advantage over HTCC as high-conductivity metals

such as silver and gold can be used [50] since the melting point is well above

the temperature at which the LTCC stack is fired.

MCM-D (Section 10.4.3), in which thick Cu layers are preferred for the inte-

gration of the spiral inductors.

When the thickness of the metal layer is increased above a certain threshold, how-

ever, a point of diminishing returns will be reached due to the skin effect. Increas-

ing the metal thickness above this value will still result in a decreasing series resis-

tance due to current-crowding effects in adjacent spiral turns which cause part of

the current to flow along the edge of the spiral. This may be noted in Figure 10.15,

where the simulated Q L-factor is given for different Cu thicknesses. The simula-

tions have been performed for an inductor realized on a 20 -cm Si substrate (tech-

nology cross section given in Figure 10.30b) using wafer-level packaging tech-

niques (Section 10.4.5). In these simulations, S coil is equal to the thickness of the Cu

(aspect ratio of 1); the pitch in between the turns is kept constant. In this way, the

resulting spiral inductors have roughly the same inductance and consume the same

area. It can be observed that for the given frequency and layout, increasing the Cu

thickness above 10 m only results in minor increases in Q L-factor.

Experimental results may be found in [17]. Here a spiral inductor with a Cu

thickness of 4 m up to 33 m has been realized. Although the skin depth at 2 GHz

is only 1.5 m, increasing the Cu thickness from 4 m to 8 m, 16 m, and 22 m

increases the maximum Q L from 27 to 29, 33, and 35, respectively.

When a single thick metal layer is not available, one may improve the perfor-

mance of the spiral by shunting several metal layers [14]. Naturally, a point of di-


Table 10.2 Measured performance of the circular and rectangular MCM-D spiral inductor

realizations

# L s (nH) F res (GHz) Q L @ 5 GHz Qmax FQmax (GHz) FOM L (nH/mm2)

C L1 2.6 16 36 56 10 778

R L1 2.3 17 30.6 44 10 537

C L2 2.6 18 26 50 13 1293

R L2 2.3 20 21 38 13 853

C L3 1.1 28 29 77 16 580

R L3 1.0 30 26 60 18 411

C L4 1.4 29 22 67 18 1187

R L4 1.2 31 19 50 18 774

C L5 8.0 7.8 40 40 5 1097

R L5 6.8 8.5 34 34 5 792



minishing returns will also be encountered here. A drawback to shunting several

metal layers occurs when low-resistivity substrates are used. When lower-level

metals are shunted to the top metal level, the distance between the spiral inductor

and the lossy substrate decreases, thereby resulting in increased substrate losses and

parasitic capacitances. This limits the high-frequency performance of the inductor,

as has been shown in Section 10.2.5. A last remark, which should be made, is that

surface roughness also has an effect on the series resistance: the rougher the con-

ductor surface, the higher the losses [51].

10.2.7.2 Improving QL by Reducing Substrate Losses. For inductors

realized on high-resistivity substrates, conductive losses are dominant and substrate

losses can often be neglected. For inductors realized on low-resistivity substrates,

substrate-induced losses become important, as was illustrated in Figure 10.9. Sever-

al ways exist to decrease these substrate-induced losses.

A first possibility locally replaces the lossy silicon with a higher-quality dielec-

tric such that the electric and magnetic fields do not penetrate as far into the lossy

substrate. One option to obtain this is to increase the thickness of the low-loss di-

electric layer in between the spiral inductor and the lossy substrate [1, 14, 16, 23,

52–54]. This may be observed in Figure 10.16a where the extracted G LP (= 1/ R LP )

for two inductors (technology given in Figure 10.30b) are given. Increasing the

thickness of the low-k dielectric layer underneath the spiral from 5 m to 16 m

significantly increases R LP , thereby reducing the substrate losses.


Figure 10.15 Simulated Q L-factor (Ansoft HFSS) as a function of frequency for different

Cu thicknesses t = 3 m (), t = 5 m (), t = 10 m (), t = 15 m (), and t = 20 m

(). The relation between width and thickness is t + W coil = 35 m (S coil = t ), t BCB –1 = 20 m.

Other inductor layout parameters are N = 2.5 and Rin = 75 m.



Another option is to etch away the silicon underneath the inductor, as shown in

Figure 10.17a. This may be done in a postprocessing step from the top [19, 20] or

the back [21] of the Si wafer. Other possibilities are the creation of an air gap in be-

tween the spiral inductor and the substrate by using airbridge technology [22] (Fig-

ure 10.17b). A nonexhaustive overview of MEMS-based techniques, which may be

used to improve the performance of spiral inductors, may be found in [55]. Finally,

one may also realize the spiral inductors using wafer-level packaging techniques

[23, 24, 27].

Another way to reduce the substrate-induced losses is the use of metal or re-

sistive ground shields underneath the spiral inductor to terminate the electric field

before it reaches the lossy substrate. However, when a full metal shield is put di-

rectly below the inductor, one should be careful that it is at a sufficient distance

as the inductance decreases significantly due to the negative mutual coupling be-


(a)

(b)

Figure 10.16 Extracted G LP (a) and C LP (b) for a 2.8 nH inductor realized on a 20 -cm Si

substrate (technology described in Figure 10.30b): one with 5 m BCB in between the spiral

and the substrate, the other with 16 m BCB.

16 m

16 m



tween the spiral and the image currents in the solid ground shield (see also Figure

10.20). Hence, it is better to use a patterned ground shield when only a limited

distance can be supplied. The slots in the patterned ground shields should be or-

thogonal to the direction of the current flow in the spiral to prevent the build-up

of image currents. This technique is, for instance, used to improve the perfor-

mance of spiral inductors integrated on standard Si [32, 56, 57]. A drawback to

the use of shields is that they also increase the parasitic capacitances to ground,

thereby lowering the resonance frequency of the inductor. This is not a problem as

long as the resonance frequency is considerably higher than the maximum fre-quency of interest.

Another technique [58] reduces the eddy currents in the substrate by inserting

narrow strips of n+ regions perpendicular to the current flow. Another technique

places a substrate contact almost completely around the spiral inductor [59]. This

technique aims at reducing RG to zero, thereby making the substrate loss factor

equal to 1 as shown in Figure 10.12.

10.2.7.3 Improving QL by Lowering the Parasitic Capacitances to

Ground. For nonmagnetic substrates (with r = 1), changing the dielectric con-stant of the substrate does not influence the series inductance. Lowering the dielec-

tric constant, however, reduces the parasitic capacitances to ground, thereby yield-

ing higher maximum Q L-factors as demonstrated previously (Figure 10.11).

The limitation introduced by parasitic capacitances to ground is especially large

for inductors integrated on low-resistivity substrates, as can be seen in Figure

10.16b where the extracted parasitic capacitance to ground (C LP in Figure 10.7b) is

given for an inductor realized on a 20 -cm Si substrate, as described in Section

10.4.5; increasing the thickness of the low-k dielectric separating the spiral and sub-

strate from 5 m to 16 m, decreases the extracted C LP , thereby increasing the res-onance frequency and the maximum Q L factor.

Methods to decrease the parasitic capacitance have been discussed in the previ-

ous section. They basically replace the lossy silicon with a higher-quality, low-k di-

electric. This can be done by removing the lossy substrate underneath the spiral in-

ductor in a postprocessing step [19–21], by creating an air gap in between the spiral


(a) (b)

Figure 10.17 (a) Schematic cross section of an inductor suspended on a thin membrane;

the Si underneath the inductor is etched away. (b) Schematic view of a suspended inductor

using airbridge technology; regularly spaced studs are used to support the spiral.



inductor and the substrate using airbridge technology [22], or by realizing the spiral

inductors using wafer-level packaging techniques [23–25] that increase the thick-

ness of the dielectric underneath the spiral inductor.

Recently, solenoid on-chip inductors such as in Figure 10.1e have been proposed as an alternative solution to minimize both parasitic capacitive coupling to the sub-

strate and inductor area [60–62]. However, the 3-D structure of the solenoid induc-

tor is difficult to realize using conventional IC technology as a sufficient distance

between the top and bottom turns are required. In addition, it is difficult to combine

this with a narrow distance in between the different turns, which requires small

vias. The latter results in a decreasing mutual coupling between the turns. Hence, a

linear dependence of inductance on the number of turns may be found in practical

realizations.

10.2.7.4 Influence of Layout Parameters. In the previous paragraphs, we

have primarily discussed the influence of several processing-related parameters on

the spiral inductor’s performance. This section will discuss the influence of the in-

ductor’s layout parameters. We will primarily focus on a circular layout, although

similar conclusions are valid for the rectangular and octagonal layouts.

The main layout parameters of a circular spiral inductor are:

The number of turns N

The width of the coils W coil

The spacing in-between the coils S coil

The inner radius of the spiral Rin

The distance between the spiral inductor and the ground plane ( Dout for a

CPW-based approach)

As may be expected, the inductance of the spiral inductor increases if one of the

parameters N , W coil, S coil, Rin, or Dout is increased while keeping all others fixed.

However, not all parameters have a large influence on the series inductance. In-creasing N or Rin is most suited to increasing the inductance value. In this respect, it

should be noted that the inner turns of the spiral inductor only make a limited con-

tribution to the series inductance; however, they do contribute significantly to the

losses [23, 35, 63] due to eddy currents generated in the inner coils. Hence, a higher

Q L can be achieved by leaving a hole in the center of the inductor. This implies that

Rin should not be made too small.

The above situation is illustrated in Figure 10.18a, where the measured Q L for

two realizations of a 2.5 nH inductor are given. It can be noticed that the 2.5 turn re-

alization with a larger Rin has a higher Q L-factor compared to the 3.5 turn realiza-tion. This is due to the fact that the center of the 3.5 turn realization is very small

and almost completely covered with metal.

It should also be mentioned that increasing Rin, while keeping all other parame-

ters constant, results in a more or less linear increase of the series inductance, as

shown in Figure 10.18b [23, 64].




Changing either W coil or S coil results in a weak change in series inductance, es-

pecially when the pitch remains constant [29]. Widening W coil may be used to in-

crease Q L; however, a point of diminishing returns will be reached due to eddy

currents generated in the coils, and due to the fact that most of the current is lo-cated at the edges of the strips [35, 48]. The losses related to eddy currents in the

strips may be reduced by making the inner turns slightly narrower than the outer

turns: narrow strips optimize the losses in the inner turns, where the magnetic

field reaches its maximum, whereas wide strips optimize the outer turns, where


(a)

(b)

Figure 10.18 (a) Measured Q L-factor for two realizations of a 2.5 nH inductor, ( N = 3.5/ Rin= 25 m; N = 2.5/ Rin = 75 m) realized on a 20 -cm silicon substrate. (b) Variation of LS as

a function of N and Rin. (– –) N = 1.5, W coil = 30 m; (– –) N = 2.5, W coil = 5 m; (– –) N

= 2.5, W coil = 30 m; (–+–) N = 3.5, W coil = 30 m.



ohmic losses are predominant [21, 65]. Another possibility is to split the strip into

several parallel traces or to change the location of the different traces as was sug-

gested and done in [35, 66].

The distance to the ground plane also has an influence on the spirals perfor-mance. When discussing the influence of Dout, it is important to distinguish between

a microstrip and coplanar waveguide (CPW) design approach (Figure 10.19). In a

microstrip approach, the spiral inductor is realized on the top of the wafer, whereas

the ground plane is located below the spirals (usually at the back side of the wafer).

Hence, the distance between spiral inductor and ground plane is usually not a de-

sign parameter. In a CPW approach, the ground plane is realized in the same plane

as the spiral inductor.

The influence of the distance to the ground plane for a microstrip- and CPW-

based spiral inductor is illustrated in Figure 10.20. It can be noted that as the dis-tance to the solid ground plane decreases, the series inductance decreases while the

parasitic capacitances to ground increase. The Q L-factor of the spiral, hence, de-

creases due to a decreasing LS , an increasing C G , and an increasing RS due to the

generation of eddy currents in the ground plane. This is also shown in [50] for an

LTCC-based spiral inductor.

From the above observations, one may conclude that one should not put the

ground plane too close to the spiral inductor. Hence, when one is only interested in

the inductor performance, it is safe to say that inductors need a sufficient volume of

space to allow the magnetic field to be unimpeded by other structures. On the other hand, the distance between the spiral inductor and the ground plane may not be too

large for reasons of compactness and cost. Once Dout is larger than a certain thresh-

old (depending on the spiral’s geometry), increasing it further will not have a dras-

tic influence on the series inductance and Q L-factor.

When a small area is required, one can reduce Doutwhile simultaneously increas-

ing N to obtain the same inductance value, thereby introducing additional losses.

This implies a trade-off between cost, due to area, and performance. Many variables

may, therefore, be optimized in the design of spiral inductors. Different solutions


(a) (b)

Figure 10.19 Difference between (a) a coplanar waveguide (CPW) approach, in which the

coils and ground plane are realized on the same metal layer, and (b) a microstrip approach, in

which the ground plane is located at the bottom of the wafer.



will be found when the inductors are optimized for cost, small area, or performance

(higher Q and larger area). How to predict the performance of a spiral inductor will

be discussed in the next section.

10.3 INDUCTOR PERFORMANCE PREDICTION

Predicting the performance of spiral inductors is an area of vast research. A detailed

discussion of all modeling approaches is beyond the scope of this work. Hence, we

will primarily concentrate on a discussion of the different methods to give some in-

sight into the possibilities and limitations of the different approaches.


(a)

(b)

Figure 10.20 Influence of the distance to the ground plane for a spiral with N = 2.5, W coil= 30 m, S coil = 20 m, and Rin = 100 m. (a) Microstrip configuration (– –) C G , (– –)

LS . (b) CPW configuration (– –) C G , (– –) LS . Simulations performed using Agilent

Momentum.



10.3.1 Transmission Line Inductor

The strip-type inductor (Figure 10.1a) can be regarded as a transmission line and

can be very easily and accurately modeled accordingly. For short lengths (l < g /4),

the inductance LS and shunt capacitance to ground C G , such as in the model shown

in Figure 10.4b, are given by Equation 10.17, where Z c and g are the characteristic

impedance and wavelength of the transmission line, respectively, f is the frequency

at interest and l is the physical length of the strip. It may be noted that a high char-

acteristic impedance is required to realize an inductance with small parasitic ele-

ments. This usually transfers into a larger separation from the ground plane.

LS = sin and C G = tan (10.17)

To predict the transmission line properties, several approaches may be followed

ranging from quasistatic approximations, to 2.5-D method of moment and full 3-D

simulations. The performance of CPW and microstrip technologies using a single

dielectric can be easily simulated using most commercial design simulators [67].

For multilayer substrates, fast and good results may be obtained using the quasistat-

ic approximation from [68, 69].

10.3.2 Spiral Inductors

Predicting the performance of spiral inductors is more complicated and may be

done in several ways:

Using closed-form formulas derived using a large number of measurements

or simulations.

Approximating the performance of the spiral by decomposing the spiral in-

ductor into its constituent elements and calculating the inductance using the

Greenhouse algorithm (See section 10.3.2.3). Solving Maxwell’s equations using 2.5-D or 3-D simulators. The method of

moments and the finite element method will be discussed in this respect.

Choosing an experimental method by fabricating/measuring a large number

of spiral inductors.

Which method is preferred depends on the required accuracy, the flexibility of the

modeling method, the time required to do a simulation, and the specific use that is

being made from the spiral inductor simulation:

From a circuit designer point of view, an optimal model should offer high ac-

curacy and a continuous spectrum of inductances, require limited storage ca-

pacity, and give insight into the physical behavior of the component; optimiz-

ing the inductor in a design should be fast and easy.

l

g

1

2 fZ c

2 l

g

Z c

2 f

10.3 INDUCTOR PERFORMANCE PREDICTION 217



From a technology and component designer point of view, a good model

should deliver a priori knowledge of the component’s behavior, thereby al-

lowing the designer to optimize the technology toward achieving the required

performance with regard to quality factor and taking area consumption intoaccount.

Closed-form formulas can be readily implemented in commercial simulators, how-

ever, they are usually only available for the inductance, usually with limited accura-

cy, not for the parasitic elements. The Greenhouse method predicts the inductance

with reasonable accuracy; however, the parasitic elements have to be estimated by

different means.

2.5-D and 3-D simulators are very convenient as they give rise to an unlimited

range of inductors. The influence of a technological change on the performance of the spirals, inductors, and parasitic elements can also be easily simulated with good

accuracy. A specific drawback is that these methods are relatively time consuming

and, hence, less suited for the development of a large range of spiral inductors. Op-

timizing the layout of the spirals in a design is also difficult, if at all possible.

The main advantage of closed-form expressions or expressions based on the

Greenhouse method, is that these methods allow one to study the influence of the

spiral’s geometry on its performance, as simulating the spiral only takes a limited

amount of time. Naturally, this requires expressions/approximations for all ele-

ments of the equivalent circuit. If these are available, one may construct an inductor design space showing the influence of, for example, W coil and S coil on Qmax and LS .

One can also easily optimize the performance of the inductor for a given inductance

value, frequency, and area. The accuracy of the simulation may not be sufficient for

all applications, for example, when narrowband filters are being designed and trim-

ming after fabrication is not available.

10.3.2.1 Measurement-Based Methods. From a design point of view,

measurement-based methods are very attractive as they offer very high accuracy.

They are usually the only way to take into account surface roughness effects, uncer-tainties in material parameters, planarization effects, etc. However, simply measur-

ing a large range of inductors is relatively time consuming and only offers a limited

set of inductors. An additional drawback is that the method does not provide any

performance prediction before the component is made.

The measured S -parameters are usually fitted to a lumped-element equivalent

model, such as the one shown in Figure 10.4. A continuous range of inductances

may be obtained by consistently varying one parameter of the spiral inductor such

as the inner radius Rin in Figure 10.1d. The equivalent elements of the lumped ele-

ment model are subsequently expressed as a function of the series inductance. Theresulting model can then be easily incorporated into commercial design-software.

This approach has been followed in [64], where the equivalent elements of the

lumped element model are expressed as a function of the inner diameter of the rec-

tangular CPW-based GaAs MMIC spiral inductors.

The above-described procedure gives the designers access to a large range of in-




ductance values, and the accuracy of the model is excellent. The major drawback is

that the inductors themselves are not necessarily optimized for the frequency at in-

terest. One also has to redo this step each time the technology is changed.

10.3.2.2 Closed-Form Inductance Formulas. An accurate model of a spi-

ral inductor requires that the primary inductance, as well as the parasitic elements,

are known. Exact closed-form formulas for spiral inductors do not exist as the com-

ponent layout is far too complex. Closed-form formulas for some simplified struc-

tures, however, do exist, for example, the static self-inductance for a microstrip line

with rectangular cross section given by [70]

L =

ln – 1

(10.18)

ln = ln(2c) – – 2 ln 1 + 2 + 2 ln 1 + 2 (10.19)

+ arctan + arctan

c = (10.20)

where w is the width, t the thickness, and l the length of the microstrip line section.

The formulas given above do not consider the inhomogeneous and frequency-

dependant current density over the cross-section of the conductor as predicted by

skin-effect theory.

For two coupled straight thin films of width w, length l , and zero metallization

thickness, the mutual inductance for a certain spacing s between the lines can be an-

alytically expressed as [70]

M = 2[ F ( s/l ) + F ((2w + s)/l ) – 2 · F ((w + s)/l )] (10.21)

F (q) = q2 · ar sinh + q · ar sinh(q) + – (1 + q2)3/2 (10.22)

The above formulas may be used to calculate the inductance of a rectangular spiral

inductor using the Greenhouse method, discussed in the next section.Recently, several closed-form formulas have been presented (primarily targeted

on Si-based technologies) that may be used to predict the performance of spiral in-

ductors [29, 33, 34, 39, 70–75]. Some methods rely on closed-form expressions for

the inductance, whereas others use the Greenhouse method (explained in the next

section) [29, 70, 73] to estimate the value of the inductance. Only a limited number

1

3

q33

1

q

l

w

l

4

w 2 + t 2

2

w

t

t

w

t

w

w

t

2

3

w

t

t

w

t

w

w

t

1

6

25

12

2l

0l

2




of models give closed-form expressions for all parasitic elements. Most do not

specify the parasitic elements, or use a number of measurement-based terms to ob-

tain good accuracy. It should be noted that most expressions primarily target rectan-

gular spiral inductors realized in planar technologies. Closed-form expressions for inductors realized in three dimensions are not available.

10.3.2.3 Greenhouse Method. The foundation for computing the induc-

tance is built on the concepts of the self-inductance of a wire and the mutual in-

ductance between a pair of wires. The method of Greenhouse [76] computes the

inductance of planar rectangular spirals by summing the self-inductance ( Li) of

each wire and the positive and negative mutual inductance ( M ij ) between all pos-

sible wire segment pairs. The mutual inductance between two wires depends on

their angle of interconnection, length, and separation. The current flow directionsin the wires determine the sign of coupling: positive if the currents in the two

wires are in the same direction, and negative for opposite currents. In this way, we

obtain

L = N

i=1

Li + N –1

i=1 N

j=i+1

2 M ij (10.23)

Hence, circular and rectangular spiral inductors are modeled by breaking up the in-

ductor into segments, which are straight lines in the case of the rectangular spiral in-ductor (Figure 10.21a) and circular one-turn elements [73, 77–81] in the case of the

circular spiral inductor (Figure 10.21b). For the circular case, it is assumed that the

width W coil and spacing S coil of the concentric ring model are identical to those of

the spiral inductor. The overall dimension of the concentric ring model may be de-

fined by two criteria [73]:


(a) (b)

Figure 10.21 Greenhouse method. (a) Decomposition of a square spiral inductor into inter-

acting parallel segments. (b) Approximation of a circular spiral inductor into a 2-D axisym-

metric model.



1. The perimeter of every circular loop must equal the perimeter of every turn of

the spiral.

2. The area of every loop must be the same as the average area of every spiral turn.

Choosing one or the other depends on the geometry, basically on the value of the

pitch. For instance, for small pitches the first criterion would give a better descrip-

tion, whereas for large pitches it is better to use the second one.

In addition to the modeling method described above, the inductance of the rec-

tangular spiral inductor has also been modeled by treating the spiral as a network of

single and coupled transmission lines [82, 83].

10.3.2.4 Solving Maxwell’s Equations: Method of Moments. Momen-

tum is an example of a commercial solver based on the method of moments [84,85], able to compute the S -parameters of arbitrary shapes in multilayered circuits by

solving mixed potential integral equations in the spatial domain. To simulate a

structure, one first defines the dielectric layer build-up; all specified dielectrics are

assumed to be infinite in the XY-plane. Metal planes can be drawn in between these

dielectrics in strip or slot form. In the first case, metal is only present when drawn;

in the second case, metal is assumed to be everywhere in between the two di-

electrics except in the slots. The different metal planes can be connected to one an-

other using vias. Only vertical currents can be accounted for in the vias, thereby

giving rise to the name 2.5-D simulator: the simulator can account for XY-oriented currents in the metal planes and for Z-currents in the vias.

Once the substrate is defined, the Green’s functions of the substrate, which can

consist of an arbitrary number of signal and connecting vias layer, are calculated.

To solve the structure, a planar mesh consisting of both rectangular and triangular

cells is generated. The calculation time mainly depends on the complexity of the

structure and substrate and the density of the mesh. An example of a substrate and

mesh definition is shown in Figure 10.22.

A variety of components can be simulated: simple structures such as transmis-

sion lines, BCB capacitors, and spiral inductors, and more complex structures suchas bandpass filters, matching networks, and Lange couplers. One of the main limita-

tions of this method is that the conductor thickness is not accurately accounted for.

Metal losses are calculated when drawn in strip form, however, it is assumed that

the metal thickness is sufficiently larger than the skin depth. For the slot mode, con-

ductive losses are neglected.

The accuracy of CPW-based simulations is generally very good, as can be noted

in Table 10.3, where the measured and simulated equivalent circuit parameters for

circular spiral inductors, realized in a multilayer MCM-D technology (technology

described in Section 10.4.3) are given. It can be seen that very good accuracy can beobtained. As the technology is CPW-based, a slot-based simulation approach has

been used.

10.3.2.5 Solving Maxwell’s Equations: Finite Element Method. An ex-

ample of a commercial 3-D simulator is Ansoft HFSS. It is based on the finite ele-





(a)

(b)

Figure 10.22 (a) Layer definition example for a technology using two metal layers (one

strip-based, one slot-based). (b) Layout and mesh example of a circular spiral inductor: the

inductor is drawn in slot form, whereas the vias and overpass are drawn in strip form.

Table 10.3 Comparison between equivalent circuit parameters that are measured and

simulated in momentum for circular spiral inductors realized in a multilayer, CPW-based

MCM-D technology

Geometry Measurements Momentum _____________________________ _____________________ ___________________

W coil S coil Rin Dout L s C gL C gR L s C gL C gR N (m) (m) (m) (m) (nH) (fF) (fF) (nH) (fF) (fF)

0.5 30 20 100 200 0.65 22.1 21.4 0.67 22.8 22.8

1 30 20 100 200 1.12 27.6 28.1 1.12 31.6 30.0

1.5 30 20 100 200 1.55 31.2 31.1 1.58 34.3 34.8

2.5 30 20 100 200 3.36 42.3 37.5 3.33 45.5 40.5

4.5 30 20 100 200 10.08 64.9 49.9 10.42 71.8 51.7

1.5 20 20 100 50 1.18 28 25.5 1.21 27.3 26.1



ment method [86, 87]. It uses volume meshing and is appropriate for truly 3-D prob-

lems. In contrast to 2.5-D simulators, it can accurately account for vertical currents

that occur when large vias and thick metal layers are used. The dielectric layers can

also be drawn with finite dimensions. 3-D simulations are generally slower than sim-ulators based on the method of moments and are hence more suited for structures

with small complexity. The calculation time depends mainly on the overall size of the

structure and the density of the mesh that is required to obtain accurate results; how-

ever, 3-D simulations may be used to predict the performance of spiral inductors

[88]. A typical layout of a circular spiral inductor is shown in Figure 10.23a, in which


(a)

(b)

Figure 10.23 (a) Layout of a circular spiral inductor in Ansoft HFSS; a full 3-D layout of

the structure is drawn. (b) Simulated (—) versus measured S 11 () and S 21 () of a circular

spiral inductor realized on a 20 -cm Si substrate using wafer-level packaging techniques.



a fully 3-D structure is drawn. The obtained agreement between measured and simu-

lated S -parameters for a 2.5 turn circular spiral inductor realized on a 20-cm Si sub-

strate (technology cross section given in Figure 10.30b) is shown in Figure 10.23b. A

good agreement can be observed. The Q-factor can also be very well predicted.

10.4 INTEGRATED INDUCTOR EXAMPLES

In the following, several approaches for integrating spiral inductors are discussed.

Examples of on-wafer Si, GaAs MMIC, as well as system-in-package solutions

based on MCM-D or LTCC will be described. Some information on inductors inte-

grated on-chip using postprocessing techniques will be also given.

10.4.1 Inductors Integrated on 10–20 -cm Si Substrates

Inductors integrated in today’s typical silicon processes suffer from low Q-values

as they typically use an Al/Cu metallization to pattern the spiral and underpass, and

the lossy substrate also significantly reduces the high-frequency performance.

Hence, a lot of work is being done to improve the performance of on-chip Si-spiral

inductors. Techniques to achieve this have been discussed at length in Section 10.2

and include, among others, replacing Al by Cu, increasing the thickness of the met-

al, interconnecting several metal layers, increasing the thickness of the dielectricunderneath the spiral inductors, and use of resistive and conductive ground shields.

Typical inductors are realized using relatively narrow strips and slots (especially

when compared to off-chip realizations) as cost-per-unit area is relatively high. A

cross section of a silicon technology [16] is given in Figure 10.24. Three Al metal

layers are used. The top is a 4 m thick Cu layer separated from the standard back-

end layers using a 2 m intermetal dielectric (SiLK ™ from DOW Chemical). The

measured performance of the spiral inductors is given in Figure 10.25 [44].

When the 3 nH inductor is realized on the thin Al layers, a low Q L value of 5 is

obtained. Realizing the inductor on the 2 m Cu layer increases Q L,max to 17,whereas the 4 m Cu layer increases the maximum Q L-factor to 24. The inductor

has a total length of 2900 m, W coil = 18 m, S coil = 2 m, and an inner diameter of

83 m.

10.4.2 GaAs MMIC Inductors

In MMIC design, cost-per-unit area is high, hence, the inductors are optimized pri-

marily for cost, so the inductors are realized using relatively narrow strips and slots,

especially when compared to off-chip solutions. An example of a technology crosssection used for CPW-based GaAs and InP MMICs is shown in Figure 10.26a. Next

to the spiral inductors, other passive components such as resistors and capacitors

are also integrated. In a CPW-based MMIC technology, airbridges are often avail-

able. In this case, it is possible to suspend the spiral inductor on airbridges, thereby

reducing the parasitic capacitances to ground. An example is shown in Figure




10.4 INTEGRATED INDUCTOR EXAMPLES 225

(a) (b)

Figure 10.25 Measured performance of inductors realized on a 20 -cm Si BiCMOS tech-

nology [44]. (a) Increase of the Q L factor as the Cu thickness is increased from 2 m to 4

m. (b) Increase of the Q L factor obtained by replacing the thin Al layers (standard TLM) by

4 m Cu.

Figure 10.24 Cross section of a three-metal level Al back-end layer. The top layer is a 4

m Cu layer.



10.26b. The measured performance of a number of CPW-based rectangular spiralinductors is given in Table 10.4. For the measurements, the metallization was

2.1 m Au. An underpass is used to connect the inner part of the spiral to the out-

side. As this layer is very thin, the underpass makes a relatively high contribution to

the overall series resistance of the spiral inductor.

The Q L-factors given above may be improved by increasing the thickness of the

metal, e.g., in [48] a 7.4 m thick metal layer is being used, whereas in [89], multi-

ple metal layers are connected in 3-D MMIC technology to decrease the series re-

sistance. One may also vary W coil as a function of the number of turns to improve

the performance, as was done in [65].

10.4.3 MCM-D Inductors

In this section, we describe the measured performance of spiral inductors integrated

in a multilayer MCM-D technology on glass. A cross section of the technology is


(a)

Figure 10.26 Spiral inductors integrated in a CPW-based MMIC technology. (a) Technol-

ogy cross section. (b) Picture of a suspended inductor using airbridge technology.

(b)



given in Figure 10.27. For the realization of the spiral inductors, three different met-

al levels are available. The middle one, metal–2, is used for the realization of the

spiral inductors as this layer has the highest conductivity. Overpasses on metal–3

are used to connect the inner part of the spiral to the outer part. The spiral inductors

are only one passive component that may be integrated, along with TaN resistors

(25 /) and capacitors (interdigital, BCB and Ta2O5). A low-loss glass substrateis used—AF45 from Schott, with r = 6.2 and tan = 8.10 –4. The metal layers are

separated by two 5 m thick BCB layers (Cyclotene™ from DOW Chemical), with

r = 2.65 and tan = 5.10 –4. More detailed information on the technology and over-

all design philosophy may be found in [4, 90–92].

A CPW-based technology is being used, as this prevents the need for substrate

vias and backside metallization. Thin-film microstrip, in which a ground plane is

realized on the top of the wafer, on metal-1, is also quite often used in thin-film

technologies [93], however, for the realization of the spiral inductors, this ground

plane has to be opened underneath the spiral inductors; the presence of a ground plane directly underneath the spiral inductors would result in the creation of large

eddy currents in the ground plane, thereby reducing the series inductance and in-

creasing the series resistance (see Figure 10.20). Hence, from the inductor design


Table 10.4 Performance of CPW-based rectangular spiral inductors integrated on a GaAs

MMIC substrate

LS Freq w s Gap S 0 Area

(nH) Q L,max (GHz) N (m) (m) (m) (m) (mm2)

0.50 24.4 19.7 1.5 8 6 30 120 0.035

0.50 28.2 20.3 1 10 10 30 160 0.053

0.95 28 12.6 1.5 10 10 50 200 0.096

1.36 9.2 7.9 2.5 10 10 10 200 0.053

1.54 13.9 7.9 2.5 10 10 30 200 0.073

1.63 18.3 7.9 2.5 10 10 50 200 0.096

2.03 12.3 5.9 2.5 10 10 30 240 0.096

2.96 11 5 3.5 10 10 30 240 0.096

Note. Freq is the frequency at which Q L reaches its maximum value Q L,max. The layout parameters areexplained in Figure 10.13b.

Figure 10.27 Cross section of IMEC’s MCM-D technology.



point of view, a CPW-based technology and a thin-film microstrip based technolo-

gy are more or less the same.

For flexible circuit design, layouts optimized for either low cost or high perfor-

mance have been developed. For the first case, minimal strip and slot dimensions (5to 20 m) are used, whereas for the second, wider strips and slots, with values up to

100 m, have been supplied. The high-performance inductors also have a larger

Dout. Integrated MCM-D spiral inductors are shown in Figure 10.28. The measured

performance of the MCM-D inductors is illustrated in Table 10.5. It can be seen

that the quality factors Q L may go above 100 at 10 GHz for inductances less than


(a)

Figure 10.28 A spiral inductor realized in MCM-D. (a) The layout parameters and inductor

reference planes. (b) An inductor with 5 m wide slots.

(b)



1.8 nH. Naturally, for inductors with larger values, the quality factor drops due tothe increased losses and capacitive coupling between the turns but a good perfor-

mance is still achieved; for example, an inductor of 18 nH still has a Q L of 38 at 2

GHz, an inductor of 40 nH still has a Q L of 29 at 1 GHz. The Q L-values are, there-

fore, significantly higher than those reported on silicon or GaAs. It should be noted

that the technology described here uses a 3 m thick Cu layer, however, Cu thick-

nesses of 5 m with critical dimensions of 5 m have also been demonstrated [23,

49]. This further increases the maximum Q L-factor, especially for applications in

the lower GHz range.

The high quality factors obtained in the MCM-D technology may be attributed toseveral factors:

In the MCM-D technology, high-conductivity Cu metallizations are used to-

gether with high-quality dielectrics.

The lower dielectric constant of the glass and BCB as compared to GaAs- and

Si-based solutions also help to increase the maximum Q L-factor by reducing

the parasitic capacitances to ground.

The available area (cost) also determines the achievable performance of the in-

ductors as a larger area allows one to decrease the number of turns to realize aspecific inductance. It is also possible to increase W coil and S coil. In this respect,

MCM-D has a considerable advantage over GaAs- and Si-based inductors.

MCM-D inductors may also be integrated on a variety of substrates such as low-

[88, 94, 95] and high-resistivity [11, 96] silicon, alumina [97], etc. For the first, a 10


Table 10.5 Measured performance of the integrated MCM-D spiral inductors

W coil S coil Rin Dout L s Freq @ Qmax F res Area

N (m) (m) (m) (m) (nH) Qmax (GHz) (GHz) (mm2)

0.5 30 20 100 200 0.65 >200 18.9 46.3 0.395

1.5 30 20 100 200 1.55 110 13.0 22.5 0.515

2.5 30 20 100 200 3.36 61 6.3 13.0 0.650

3.5 30 20 100 200 6.15 48 4.4 7.8 0.801

4.5 30 20 100 200 10.08 40 2.8 5.3 0.967

5.5 30 20 100 200 14.77 37 2.0 4.0 1.149

1.5 30 40 100 200 1.72 93 12.0 21.3 0.594

1.5 30 60 100 200 1.84 100 10.0 19.8 0.679

1.5 50 20 100 200 1.62 130 10.0 19.8 0.6501.5 77 20 100 200 1.72 90 8.5 16.3 0.857

1.5 100 20 100 200 1.8 90 6.8 14.5 1.056

0.5 20 20 100 50 0.35 >200 37 (64) 0.113

1.5 20 10 100 50 1.13 120 18 29 0.145

Note: F res is the resonance frequency. The area of the circular cutout from the ground plane is also given.

The other geometrical parameters are outlined in Figure 10.1d.



m thick Cu layer is combined with a 25 m thick oxidized porous silicon [98] lay-

er, thereby resulting in high Q-factors on a low-resistivity substrate.

10.4.4 LTCC

In LTCC, multiple dielectric and metal layers can be used, thereby allowing the in-

tegration of spiral inductors. High quality factors may be obtained [5, 50, 99–101],

however, primarily at low RF frequencies. This is mainly due to the quality of the

materials, the large tolerances on dimensions of the screen-printed conductors, the

minimum dimensions, and the vertical shrinkage during firing. Unlike HTCC,

LTCC processes allow the use of high-conductivity metals such as silver and gold

since the melting point of these metals is well above the temperature at which the

LTCC stack is fired [50]. As discussed previously, this improves the performanceof the integrated inductors.

Miniaturization may be achieved by exploiting the three-dimensional capabili-

ties of the technology, as illustrated in Figure 10.29. However, this 3-D configura-

tion causes large modeling difficulties, hereby severely complicating the use of

LTCC in practical circuit design. Photolithographic techniques may be used to re-

duce the accuracy problems [102]; however, this reduces the cost benefits over

competing technologies.

In [5, 50], results on integrated spiral inductors in multilayer LTCC are reported.

A 20 layer LTCC process using 90 m thick Dupont 951AT tapes has been used with dielectric constant 7.8. Typical metallizations are either 5 m electroplated

gold (surface and back side) and 6 m silver or silver–palladium alloy. Convention-

al designs require a minimum of 100 m line widths and slots, although 25 m is

possible utilizing a photoimageable process. The reported spiral inductor perfor-

mance is given in Table 10.6. In [50], it has been mentioned that increasing the

height above the ground plane may increase the Q L-factor further. This, however,

will result in larger coupling in between circuits. It can be noted that the inductors

in the 1–4 nH range are realized using a 2-D planar approach, hence, in this case,

the 3-D possibilities of the technology do not aid in reducing the size of the inte-grated spirals. As the minimum dimensions are in the order of 100 m, the overall


Figure 10.29 Schematic diagram of a 3-D helical inductor structure: technology cross sec-

tion and 3-D view.



size of the spiral inductors is considerably larger as compared to the MCM-D-based

implementations described in the previous section.

10.4.5 Integration of On-Chip Si Inductors Using Wafer-Level

Packaging Techniques

Another approach to realize high-performance spiral inductors on a Si chip is to

perform postprocessing steps on Si wafers [23, 24, 26, 27, 52–54]. One possibility

is to integrate the spiral inductors in the redistribution layers. This concept is illus-

trated in Figure 10.30a, where two low-k and low-loss benzocyclobutene dielectric

layers with r = 2.65 and tan = 5.10 –4, and a thick Cu interconnect layer are

formed on top of the passivation. The thick Cu layer can then be used for integrat-

ing the spiral inductors as well as for flip-chip redistribution. An additional advan-

tage is that this method allows one to use contact masks for the realization of the in-

ductors, as opposed to the more expensive Si reticules, thereby reducing costs.

Patterned ground shields or substrate contacts to improve the performance of the in-

ductors, as mentioned previously, may be realized in the silicon back-end layers.

To characterize the above concept, the layer buildup shown in Figure 10.30b has

been realized; substrate contacts and shields have not been used in this case. The

measured Q L-factor for a 2.5 nH inductor for different Cu and BCB layer thickness-

es, separating the spiral and the lossy Si substrate, is given in Figure 10.31. The lay-

out parameters of the inductor are also given there. Split 1 (3 m Cu, 5m BCB)

results in a maximum Q L-factor of 16 at 1.9 GHz. Increasing the Cu and BCB thick-

ness to 5 m and 16 m (split 3), respectively, increases the Q L-factor to 23 at 1.9

GHz, with a maximum Q L-factor of 26 at 2.8 GHz. A 5 m thick Cu layer with 8

m BCB (split 2) results in a maximum Q L-factor of 23 at 2 GHz. Using MCM-D-

based postprocessing, minimum feature sizes of 5 m are possible for a Cu thick-ness of 5 m.

Increasing the Cu thickness results in a higher slope of the Q L-factor at lower fre-

quencies, determined by LS / RS . The small difference in slope between the inductor

on splits 2 and 3 can be explained by small differences in the actual Cu thickness.


Table 10.6 Measured performance of LTCC-based inductors

Type N Height (m) W coil LS (nH) Q L,max F res (GHz)

2-D 2 180 4.8 37 @ 1.3 GHz 2.92-D 2 360 6.1 47 @ 1.3 GHz 3.2

2-D 2 540 6.7 52 @ 1.3 GHz 3.25

3-D 2 180 7.6 36 @ 1 GHz 2.1

2-D 3/4 180 500 1.2 100 7.2

2-D 1/2 180 250 1.4 88 8

2-D 3/4 180 250 2.5 70 4.5

2-D 3/4 180 250 3.8 78 4.7

Note: According to [5, 50], height is the distance above the ground plane.



Increasing the BCB thickness allows one to reduce the parasitic capacitances to

ground, thereby shifting the resonance frequency from 12.5 GHz (split 1) to 15

GHz (split 3). At the same time, the substrate losses are reduced. The maximum

FOM L for the above mentioned inductors is 210/340 (split 1/split 3). Pictures of spi-

ral inductors realized on top of a five-metal layer Cu back-end (Figure 10.30a) real-

ized at IMEC are shown in Figure 10.32. Substrate contacts are present at the probe

tips.

10.5 USE OF INDUCTORS IN CIRCUITS: EXAMPLES

In the following, we will describe a number of applications in which inductors are

being used. A more detailed discussion of the applications of integrated passives

can be found elsewhere.


(a)

Figure 10.30 (a) Schematic cross section of the “inductor above passivation” concept; the

MCM-D layers are postprocessed on top of passivation. (b) Layer buildup used to character-

ize the performance of the postprocessed spiral inductors.

(b)



10.5.1 Filters

The first application in which a high Q-factor is important is integrated filters, es-

pecially narrowband bandpass filters. A 5.2 GHz bandpass filter, realized in the

MCM-D technology described in Section 10.4.3, and the equivalent circuit are

given in Figure 10.33. At the 5.2 GHz design frequency, the two 0.625 nH MCM-

D inductors have a Q L of 127. In the same figure, a comparison between mea-

10.5 USE OF INDUCTORS IN CIRCUITS: EXAMPLES 233

Figure 10.31 Q L-factor as a function of frequency for a 2.5 nH inductor with N = 2.5, W coil= 20 m, S coil = 10 m, and Rin = 100 m (area = 0.19 mm2) for different Cu and BCB thick-

nesses. Split 1: t Cu = 3m, t BCB = 5m. Split 2: t Cu = 5m, t BCB = 8m. Split 3: t Cu = 5m,

t BCB = 16 m.

(a) (b)

Figure 10.32 Spiral inductors postprocessed on a five-metal layer Cu back end. (a) With

postprocessed overpass. (b) Underpass on fifth Cu back end layer.



surements and simulations of the complete filter are shown. In addition, the graph

shows simulation results indicating the influence of a decreasing inductor quality

factor. With the high-Q L inductor, the insertion loss in the passband is –3 dB at5.16 GHz. When the Q L drops to 35 or 24 at 5.2 GHz (due to an increase in se-

ries resistance), the insertion loss of the filter increases to –4.9 dB or –6.2 dB, re-

spectively. It should be noted that the insertion loss of bandpass filters is primari-

ly determined by the Q-factor of the used LC resonators, however, the inductor is


(a)

Figure 10.33 (a) Photograph of a 5.2 GHz MCM-D bandpass filter (3 × 1.5 mm2) using

high-Q spiral inductors. The equivalent circuit is also shown. (b) Comparison of measure-

ments (dotted lines) and simulation results (solid lines) of the bandpass filter indicate the in-

fluence of reduced Q values on the insertion loss.

(b)



usually the performance-limiting factor. The Q-factor of a parallel resonator may

be obtained by [45]

= + (10.24)

Note that the Q-factor of the inductor is used in this definition, not the Q L-factor.

10.5.2 Voltage-Controlled Oscillators

The phase noise of a voltage-controlled oscillator (VCO) is also highly determined

by the Q-factor of the used LC tank. In Equation 10.25, it can be seen that the phase

noise is inversely proportional to the square of the quality factor Q of the LC tank

and the square of the power [103]. Again, it should be noted that the Q-factor is

used, not the Q L-factor.

S 2 (10.25)

From this, one may conclude that the capacitive limitation, which lowers Q L, is not

necessarily a problem for a VCO: a capacitor is put in parallel with the inductor. If

the inductor has a slightly higher capacitance to ground, which results in a lower

Q L, one only has to put a smaller capacitor to ground in parallel with the inductor.This illustrates that one should be careful when Q L is used as a criterion to optimize

the performance of the spiral inductors.

10.5.3 Size Reduction Techniques

A quarter-wavelength transmission line is a key element in many microwave cir-

cuits; however, a straightforward realization requires a large amount of chip area,

especially at the lower microwave frequencies. Different size reduction techniques

are available to reduce the length of a transmission line with characteristic imped-ance Z c and electrical length 1 (Figure 10.34).

In the lumped/distributed technique, a shorter transmission line is used. This re-

sults in a loss in distributed series inductance and shunt capacitance, which is com-

pensated for by using a higher characteristic impedance (to compensate the induc-

tance loss) and adding lumped capacitors to ground (to compensate the capacitance

loss) at the edges of the line (Figure 10.34b) [104]. The maximum Z c value that can

be obtained therefore determines the achievable size reduction.

In the lumped element technique, the transmission line is replaced by the combi-

nation of lumped inductors and capacitors. A -equivalent (Figure 10.34 (d)) or T-equivalent circuit can be used.

It should be mentioned that the structures are only equivalent at one fixed fre-

quency; hence, reduced-size circuits usually have a more narrow frequency band

than the distributed designs.

1

P 2Q22k T · F

P S

f osc

f m

1

Q2

1

Qinductor 1

Qcapacitor 1Q

10.5 USE OF INDUCTORS IN CIRCUITS: EXAMPLES 235



An example of the above-described approach can be found in [105], where dis-

tributed as well as lumped approaches have been implemented. The realized

Wilkinson power dividers are shown in Figure 10.35, whereas the measured perfor-

mance is summarized in Table 10.7.

It can be seen that the use of miniature spiral inductors allows one to drastically

reduce the size of the circuit (the lumped-element circuit only consumes about 30%

of the size of the distributed approach), however, this does not have a significantimpact on the circuit’s performance. So, although the Q-factor of the miniature spi-

ral inductors is lower, the overall circuit performance is more or less the same, and

the area is significantly reduced.


(a)

Figure 10.34 Example of some size-reduction techniques used to reduce the length of a

transmission line section. (a) With characteristic impedance Z c and electrical length . (b)

Lumped/distributed technique using shunt capacitors. (c) -equivalent lumped-element cir-

cuit.

(b) (c)

(a)

Figure 10.35 Different Wilkinson power divider architectures. (a) Distributed design using

capacitively loaded high-impedance lines. (b) Lumped realization. (c) Lumped, very com-

pact realization.

(b) (c)



10.5.4 Coupled Spiral Inductors

Coupled spiral inductors employ the mutual inductance in between two neighboring

spiral inductors. To increase the mutual coupling, the two spirals may be realized

on top of one another (which results in fairly large capacitive coupling) or with al-

ternating coils. Coupled spiral inductors may be used in the realization of baluns.

An example of a balun using two coupled spiral inductors is given in Figure 10.36.

10.6 CONCLUSIONS

In this chapter, the performance of spiral inductors for RF applications has been dis-

cussed. First, the layout and operating principle of inductors has been briefly re-

viewed. Then the inductors equivalent circuit has been presented, followed by a de-

tailed discussion of the Q-factor, a commonly used figure of merit to describe the

inductor’s performance. We have shown how the performance of the spiral inductor

is related to material parameters such as the conductivity of the metals used, the re-

sistivity/loss tangent of the dielectrics used, their respective thicknesses, etc., and

design parameters such as inductor type and influence of layout parameters. Ways

to improve the performance have also been discussed. Several approaches to pre-

dicting the performance of integrated inductors have been described, including

10.6 CONCLUSIONS 237

Table 10.7 Measured performance of the Wilkinson power dividers depicted in Figure

10.35

Figure 10.35 Part

(a) (b) (c)

Area 5.52 mm2 3.82 mm2 1.70 mm2

Insertion loss –3.42 dB –3.44 dB –3.45 dB

–25 dB isolation 6.4–7.6 GHz 6.6–7.8 GHz 6.8–7.8 GHz

–17 dB return loss 6.3–7.5 GHz 6.2–7.6 GHz 6.7–7.8 GHz

Figure 10.36 Picture of a 5.2 GHz balun using two coupled spiral inductors.



closed-form formulas, the Greenhouse method, and 2.5-D and 3-D simulations.

Next, several examples of inductors integrated in planar technologies such as on-

chip realizations (Si, postprocessed Si, and GaAs MMICs) as well as system in a

package solutions (MCM-D and LTCC) have been given. Finally, we have brieflydiscussed the use of inductors in circuits.

ACKNOWLEDGMENTS

The authors acknowledge the support of E. Beyne, K. Vaesen, S. Brebels, X. Sun,

P. Pieters, Y. Baeyens, S. Jenei, and the MCM-D processing team.

REFERENCES

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MOS Process Utilizing a Thick Metal Process Add-On Module,” In IEEE BCTM, Min-

neapolis, MN, pp. 149–152, Sept, 26–28, 1999.

2. G. Carchon, W. De Raedt, and B. Nauwelaers, “Integration of CPW Quadrature Cou-

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247

CHAPTER 11

MODELING OF INTEGRATEDINDUCTORS AND RESISTORS FORMICROWAVE APPLICATIONS

ZHENWEN WANG, M. JAMAL DEEN, AND A. H. RAHAL

11.1 INTRODUCTION

The expanding wireless communications market is one of the driving factors for the

increased use of microwave integrated circuits (MICs). With MICs, the size of

lumped elements (R, L, C) can be reduced to values much smaller than the signal

wavelength so that good performance is obtained at microwave frequencies. In ad-

dition, more circuits per unit area can be realized for lower-cost, high-volume inte-

grated microwave systems.

Precise modeling of lumped elements is very important for microwave circuit

design. Modeling even simple passive elements is complicated at high frequencies

because many parasitics contribute to the HF characteristics. The full-wave elec-

tromagnetic (EM) analysis techniques can be used to model the lumped elements,

with very high accuracy; however, these techniques requires a large amount of

computing time. Furthermore, it usually does not provide a clear analysis review

of the relation of geometrical dimensions to circuit performance. Although circuit

simulators are very fast, the circuit element models utilized in computer-aided-de-

sign tools are often inaccurate. Artificial neural network (ANN) based modeling

techniques have recently been used to generate parameterized models. ANN can

provide highly accurate models, and the size of the model does not grow expo-

nentially with the number of input parameters. However, the training needed to

use the model can be very long and it is not always easy to find a good topology

because of the number of hidden layers and nodes. Because of this, we explore a

different approach using semidistributed equivalent circuit models to represent the

passive components. The elements in the equivalent circuit model are physics-

based.



ISBN: 0-471-24431-7



11.1.1 Miniature Hybrid Microwave Integrated Circuit (MHMIC)

In many microwave technology companies, miniature hybrid microwave integrated

circuits (MHMICs) are realized by combining MICs with passive elements. This

technique improves manufacturing efficiency, reproducibility, and reliability com-

pared to the traditional method of manufacturing microwave hybrid circuity, since

all passive components are constructed during the photolithography process. Mono-

lithic microwave integrated circuits (MMICs) have the advantages of small size,

low cost, and high integration, and require very little labor for implementation.

However, MMICs are only economical when large production runs are required.

Therefore, there remains a large arena of applications in which MMICs are not used

because of the price and performance trade-offs [1]. The advantage of the MHMIC

approach is its flexibility and its cost advantage for small to mid-sized production

runs. The advantages and disadvantages of MHMICs, when compared with

MMICs, are listed in Table 11.1 [2].

Passive lumped elements, such as resistors, capacitors, and inductors, are exten-

sively used in MHMICs for impedance matching, DC biasing, load, and many other

functions. Figure 11.1 shows typical MHMICs. In addition, vias are extensively

used to make good high-frequency connections to the ground plane.

11.1.2 Goals of this Chapter

The purpose of this chapter is to present highly accurate models for spiral inductors,

thin-film resistors, and interdigital capacitors in MHMIC technology. It will be

demonstrated that a semiempirical approach can be implemented to model spiral in-

ductors and thin-film resistors. This approach is based on the characteristics of mi-

crostrip line and microwave theory. For completeness, a short overview of the char-

248 MODELING OF INTEGRATED INDUCTORS AND RESISTORS

Table 11.1 Advantages and disadvantages of MHMICs

MHMICs MMICsSimple circuits can be cheaper; automatic Cheap in large quantities; especially

assembly is possible economically efficient for complex

circuits

Poor reproducibility due to device placement Very good reproducibility

and bond wires

Hybrids are mostly “glued” together, so Highest possible reliability

reliability suffers

Substrate is cheap, which allows microstrip Substrate is expensiveand lumped elements to be used abundantly

A vast selection of devices and components Very limited choice of components

is available

Very little capital equipment is required Very expensive to start up



acteristics of microstrip lines is presented in the Appendix. This is required because

analytic expressions for the microstrip line are used either directly or as a starting point for modeling resistors and inductors, the main components discussed here.

11.2 MODELING OF SPIRAL INDUCTORS

The spiral inductor is implemented on-chip using microstrip lines. When a small

section ( l < 1) of a microstrip line is terminated in a short circuit, the input imped-

ance may be written as

Z in = Z L l = ( R + j L)l (11.1)

where Z L is the characteristic impedance of the microstrip line, is the propaga-

tion constant for a microstrip line of length l , and R, and L are the resistance and

inductance per unit length, respectively. Since the sheet resistance of the metal mi-

crostrip line is very low, then the input impedance is predominantly inductive. A

narrow microstrip has a higher characteristic impedance, so narrow microstrips are

used to spiral inwards to realize a high inductance in an economical amount of

area.

In this first section, we will consider several aspects of spiral inductor model-

ing such as inductance calculation, ground plane effects, series resistance, para-

sitic capacitance, and quality factors. We will also discuss inductor synthesis, de-

emdbedding and measurement techniques, and model verification using a

low-pass filter circuit. Finally, in this section, we will also consider inductors fab-

ricated on silicon substrates because of their immense technological importance at

present.

11.2.1 Geometry of the Spiral Inductor

An example of a rectangular planar spiral inductor is shown in Figure 11.2. The key

device geometry parameters are also indicated in the figure. L1 is the length of first

segment, L2 is the length of second segment, L3 is the length of third segment, Ln is

11.2 MODELING OF SPIRAL INDUCTORS 249

Spiral Inductor

Resistor Network

Via Hole

Figure 11.1 Typical MHMICs.



length of last segment, W is conductor width, and S is the spacing between the con-

ductors.

In designing the layout of a spiral inductor, the objective is to obtain the desired

value of inductance in the smallest area, while keeping the parasitic capacitance low

to ensure that the self-resonance frequency of the element is outside of the designed frequency band. The Q-factor is a very important parameter in the design of the in-

ductor, and it is a function of frequency and geometrical parameters. By changing

the geometry, the inductor’s Q-factor can be optimized to the highest value for the

frequency range at which the inductor will operate.

11.2.2 Inductor Circuit Model

Generally, the spiral inductor is a distributed structure. There are capacitive and in-

ductive couplings between each of the microstrip lines and the series resistance isdistributed over the entire microstrip structure. These complicated effects can be ig-

nored up to the inductor’s first self-resonance frequency. The distributed model of

the spiral inductor can be reduced to a lumped one. A basic lumped-element repre-

sentation of the spiral inductor is shown in Figure 11.3.

In this model, L s represents the series inductance of the structure, R s represents

the series resistance of the metallization, C i models the interturn capacitance be-

tween the metal traces, and C sub1 and C sub2 represent the capacitance from the metal

layer to the ground plane. Because alumina is a low-loss dielectric, the substrate

conductance is neglected in this model.

11.2.3 Calculation of Inductance

The inductance of a spiral inductor is a complex function of its geometry.

Generally, designers use the Greenhouse method [5] to compute the inductance.


Figure 11.2 Example of microstrip rectangular inductor (1½-turn).



The flexibility and computational efficiency afforded by this approach have been

adopted for the scalable inductor model. In Greenhouse’s method, the inductance

of each segment of the spiral inductor is computed, and the total inductance is

equal to the sum of inductance from every segment. The calculation of each seg-

ment of a spiral inductor includes self-inductance and mutual inductance, which

means that the magnetic coupling between parallel conducting microstrips is tak-

en into account. However, Greenhouse only calculated the inductance for the ide-

al case of an inductor in free space without a ground plane. The ground plane ef-

fect should be included because the inductance is typically lower by 20% when

the spiral diameter is large compared to the ground plane distance [6]. In order to

reduce the model complexity, the weak coupling between orthogonal strips is ne-

glected [7].

11.2.3.1 Self-Inductance. The exact self-inductance Lself for a straight con-

ductor is calculated from Grover’s formulation [8]. For a single rectangular conduc-

tor, the inductance is given by [5]

Lself = 2 × 10 –7 l ln + 0.50049 + (11.2)

where t is the thickness of the metal.

11.2.3.2 Mutual Inductance. The mutual inductance among the segments of

a spiral plays an important role in computing the total inductance. The mutual in-

ductance M between two parallel conductors of equal length l and the geometric

mean distance GMD between them is given by [5]

M = 2 × 10 –7 l ln + 1 + 2

– 1 + 2

+ (11.3)

where M is in henrys, l is in meters, and GMD is calculated by [5]

GMD

l

GMD

l

l

GMD

l

GMD

W + t

3l

2l

W + t


C i

Ls Rs

C sub2

Port 1 Port 2

C sub1

Figure 11.3 Equivalent circuit of a spiral inductor on alumina substrate.




GMD = expln( D) – + + + (11.4)

with D being the center-to-center distance of the two conductors in meters.

The generic mutual inductance model for all possible relative-position cases be-

tween two segments requires two configurations of two parallel segments, as shown

in Figures 11.4a and b. In Figure 11.4a, the mutual inductance can be given by [9]

M j,m = 0.5[( M m+j+d + M d ) – ( M j+d + M m+d )] (11.5)

where d is positive for nonoverlapping segments and negative for overlapping ones.

The individual M terms are calculated using Equation (11.3) and the lengths corre-sponding to the subscripts.

In Figure 11.4b, the mutual inductance is given by

M j,m = 0.5[( M m+p + M m+q) – ( M p + M q)] (11.6)

11.2.4 Ground Plane Effect on Inductance

The ground plane reflection can be treated as an image spiral located at a distance

of twice the substrate’s thickness, as shown in Figure 11.5. It contributes a net neg-

ative mutual inductance M m because the current flow is in the opposite direction in

the return path. M m can be calculated by using Equation 11.3.

The inductance of a segment of spiral inductor is

L j = Lself, j + N s

n=1,n j

(–1)| j–n|/2 M j,n + N s

n=1

(–1)| j–n|/2+1 M m j,n (11.7)

Here, Lself, j is the self inductance value of segment j , M j,n is the mutual inductance

value of segments j and n, M m j,n is the mutual inductance value of actual inductor segment j and image inductor segment n, and N s is the number of segments.

1

360W

D8

1

168W

D6

1

60W

D4

1

12W

D2

GMD

j

pm

q

GMD

d m

(a) (b)

j

Figure 11.4 Two parallel filament geometry.



The total inductance L s of the spiral inductor is the sum of inductance of all the

segments, that is

L s = N s

j =1

L j (11.8)

11.2.5 Series Resistance

For substrates such as alumina, the substrate loss is very small compared to the con-

ductor loss; therefore, it is neglected and the series resistor models the losses in the in-

ductor structure. For a multiturn spiral inductor operating at high frequencies, the con-

ductor loss is known to increase dramatically above its DC value. This phenomenon is

due to the skin effect and the current crowding effect. The skin effect resistance will

be discussed in the Appendix in section, and it is determined using Equation A.23.

The basic mechanism behind current crowding typically cited in the literature isillustrated in Figure 11.6. As the magnetic field of adjacent turns in the inductor

penetrates a metal trace normal to its surface, eddy currents are produced within the

trace edge and substrate from the excitation current on the outside edge. This con-

stricts the current, increasing the effective resistance above the value that would ex-

ist for a uniform flow throughout the trace width.

According to [10], the resistance caused by the current crowding effect is given by

Rcrowd

= 0.1 × Rdc

2

(11.9)

with

f crit = W –0.65 S 0.28 (11.10) Dout – Din + 2W

l

310

0t

f

f crit


I

I

Mirror Inductor

Ground Plane

Figure 11.5 Spirals produce a reflected image in the ground plane [6].



Here l is the length of conductor, Dout = L 2 L 3 , Din = L Ns L Ns –1 , W is the conduc-

tor width normalized to 1 mil and S is the conductor spacing normalized to 1 mil.

(Note that 1 mil = 25.4 m.)

The series resistance R s can now be given as the sum of the skin effect resis-

tance, the ground resistance, and the current crowding effect resistance:

R s = Rskin + Rcrowd + R g (11.11)

Here, Rskin and R g are given by Equations A.23 and A.25, respectively.

11.2.6 Parasitic Capacitance

Semiempirical design equations for the even- and odd-mode characteristics of cou-

pled microstrip lines are used to calculate capacitance C i, C sub1, and C sub2 in the

model in Figure 11.3. In [11], a very simple formula to calculate the capacitance of

coupled microstrip lines is provided. Here, the line capacitance is divided into sev-

eral capacitances, as shown in Figure 11.7. In the even mode, the capacitance is de-


Magnetic Field

Excitation Current

Eddy “loops”

Spiral Trace

Figure 11.6 Illustration of current crowding [10].

h

(a)

W

h

(b)

W W S S

C f C m C f ’ C f C mC f ’ C f C m C m

C f

C ge

C ga

W

Figure 11.7 Fringing capacitance of coupled microstrip lines excited in (a) the even mode

and (b) the odd mode.



composed into C f , C m, and C f . In the odd mode, the capacitance is decomposed into

C f , C m, C ga, and C ge.

The total even- and odd-mode capacitances can be written as

C e = C m + C f + C f (11.12)

C o = C m + C f + 2(C ga + C gd ) (11.13)

where C m is the main capacitance of a microstrip line of width W on a substrate of

thickness h and with a relative dielectric constant r , and C m is

C m = (11.14)

C f , C f , C ga, and C ge represent various fringing capacitances. Capacitance C f can be

calculated using

C f = – C m (11.15)

where c0 is the velocity of light in free space, Z L is the characteristic impedance of a

microstrip line of width W given by Equation A.19, and eff is the effective dielec-

tric constant of the microstrip line given by Equation A.13.The even-mode fringing capacitance C f is obtained empirically [11]:

C f = (11.16)

where A = exp[–0.1 exp(2.33 – 2.53 W /h)] and S is the spacing between two mi-

crostrips.

C ga represents the capacitance in odd mode for the fringing field across the gap,

in the air region:

C ga = (11.17)

where K (k ) is the complete elliptical integral, K (k ) is its complement, k = S /h(S /h +

2W /h), and k = 1 – k 2 . K (k ) is given by [11]

K (k ) = /20

d (11.18)

C ge represents the capacitance in odd mode for the fringing field across the gap,

in the dielectric region [11]:

C ge = lncoth + 0.325C f r + 1 – r –2 (11.19)

0.02h

S

S

4 H

0 r

2

1

1 – k 2 si n 2

K (k )

K (k )

0

2

C f

1 + A(h/S )tan h(8S /h)

ef f

c0Z L

1

2

0 r W

h




Interturn Capacitance. The capacitive coupling between the turns, modeled by

C i in, is determined by the odd-mode coupling. Its value is obtained by multiplying the

capacitance per unit length by l t , which is the perimeter of the center spiral turn [12].

Capacitance to Ground and Line-Segment Model. Capacitance to ground

calculations were accomplished using the method discussed in [13]. Due to the com-

plicated capacitive and inductive coupling between turns, the voltage phase differ-

ence between the turns is very small, so the microstrip capacitance coupling is dom-

inated by even-mode coupling. The capacitance of each segment can be given by

C sj = (C f L + C m + C f R)l sj (11.20)

where l s is the length of segment, and C f L and C f R represent the left-side and right-side fringing capacitance of the segment. If there is an adjacent strip at the strip left

side, the C fL value is given by Equation 11.16, otherwise it is given by Equation

11.15. C fR is obtained in a similar way as C fL.

The inductance, capacitance, and resistance of each segment j of the spiral in-

ductor can be determined using the expressions given above. For example, for a line

of length l divided into segments of length l j , the resistance of each segment is R sj =

( R s · l j )/l . L j is from Equation 11.7 and C sj is from Equation 11.20. An equivalent

circuit shown in Figure 11.8 can be found for each line segment of the spiral induc-

tor. The ABCD matrix of this equivalent circuit is

1 + j

2

C sj ( j L sj + R sj ) j L sj + R sj

j = (11.21)

j C sj + j 2C sj 2

( j L sj + R sj ) 1 + j

2

C sj ( j L sj + R sj )

Because of the asymmetrical geometry of the spiral inductor structure, capaci-

tances of C sub1 and C sub2 are not equal. A slightly higher capacitance value is ob-tained for the outside end of the spirals due to a broader extension of the electrical

field. The inside of the spiral is associated with a more confined field, shielded by

the outside turns.

B s

D s

A s

C s


Lsj Rsj

C sj / 2

Port 1 Port 2

C sj / 2

Figure 11.8 Equivalent circuit of a line segment.



By cascading all the equivalent circuits of the line segments and connecting an

interturn capacitor between the two ports, the Y parameter of the inductor model can

be found from classical circuit theory. The capacitance of C sub1 and C sub2 can be ob-

tained from

C sub1 = (11.22)

C sub2 = (11.23)

11.2.7 Summary of Spiral Inductor Model

Table 11.2 shows the methods and equations for the model parameters shown in

Figure 11.3.

11.2.8 Quality Factor of a Spiral Inductor

Below the first resonance frequency, the quality factor of the inductor is defined by

Q = – = –

R s +

(C sub1 + C i) (11.24)

Conductor Factor Substrate Factor

where L s, R s, C sub1, and C i are the lumped elements shown in Figure 11.3.

At low frequencies, the Q-factor increases with the frequency because the con-

ductor factor is dominant and is approximately equal to L s/ R s. However, as the

frequency increases, the effect of substrate parasitic capacitance, C sub1, comes into

play, and then the Q-factor will decrease with increasing frequency. Because the

curve of Q-factor versus frequency is convex below the first resonant frequency, the

frequency f Q at which the Q-factor is maximum may be found by setting dQ/df = 0,

and f Q is approximately given by

f Q = = f res (11.25)1

3

1

2 L s( C su b1 + C i)

1

3

2 L s2

R s

L s

R s

Im(Y 11)

Re(Y 11)

Im(Y 22 + Y 21)

Im(Y 11 + Y 12)


Table 11.2 Equations for the model parameters

L s from Eq. (11.8) Components of L s —Eqs. (11.2), (11.5)/(11.6), and (11.7)

R s from Eq. (11.1) Components of R s —Eqs. (A.23), (A.25), and (11.9)

C i Determined from Eqs. (11.17) + (11.18)*l t

C sub1 and C sub1 Eqs. (11.22), (11.23)



where f res is the first self-resonance frequency. However, in practice, the series re-

sistance R s is a function of frequency and the maximum Q-factor point frequency f Qis approximately equal to f res/2.

11.2.9 Inductor Synthesis

Using Greenhouse’s method, the inductance error can be constrained to 5%, al-

though it is very hard to derive the geometrical parameters from the value of induc-

tance, quality factor, and first self-resonance frequency.

However, a fairly accurate expression for the inductance is given in [14]:

L s = a0T 2 De[b(T –1)(W+S )/ D]

c

(11.26)

where D = L 2 L 3 , T is the number of turns; 0 is the permeability in vacuum; and

a, b, and c are fitting parameters that depend on the fabrication technology and sub-

strate parameters. For a 25 mil alumina substrate, the values of a, b, and c are given

in Table 11.3.

To design an inductor with minimal area, the inductor is optimized to be a square

shape. From this point of view, we can let the geometrical parameters be as simple

as shown in Table 11.4.

In Table 11.4, T is the number of turns, which is equal to (i + 0.5), and i is an in-teger. For example, in one technology, S is equal to 1 mil, because the minimal

spacing of the technology is 1 mil and the minimal spacing is used to increase the

inductive coupling.

Increasing W results in a higher quality factor. However, the area of the inductor

becomes larger. This results in higher parasitic capacitances, which lowers the in-

ductor’s self-resonance frequency. Magnetic flux must be allowed to pass through

the center of the spiral. This ensures that negative mutual coupling between oppo-

site sides of the inductor does not significantly affect the inductance and the Q-fac-

tor. Thus, the four groups of coupled lines that form the sides of the inductor must

be spaced sufficiently far apart. A spacing greater than five conductor widths is rec-

ommended [7]. Therefore, Ln must be greater than 2.5 times the conductor width.

Once the Q-factor and inductance values are known, the conductor width can be

chosen according to the design rules of a certain technology. Ln is initially as 2.5

times the conductor width. From Table 11.4, L1, L2, and L3 can be represented by Ln

and T . In Equation 11.26, T is the only unknown value. Using “solve function” in

Matlab, T can be solved. If i + 0.5 T < i 1.5, T is set to be i + 0.5, where i is inte-

ger. Now T = i + 0.5 can be put back into Equation 11.26 to solve for Ln.

D

W


Table 11.3 Parameters in Equation 11.26

a b c

0.96 4 0.26



11.2.10 Design and De-Embedding of Inductor Test Structure

To experimentally investigate the accuracy of the model expressions developed, 20

rectangular spiral inductors designed on a test chip are used. They are different in

the number of segments, the conductor width, the conductor spacing, and the length

of the last conductor segments. The number of turns can be derived from N s, L1, and

Ln. The inductance of these 20 inductors ranges from 1 nH to 15.53 nH, and the first

self-resonance frequency is from 3.2GHz to 25GHz. All the geometrical parameters

are given in Table 11.5.

To measure the spiral inductor scattering parameters, the ground–signal–ground

(GSG) structure was used in an on-wafer microwave measurement system. The

layout of the test structure is shown in Figure 11.9. Two groups of ground–

signal–ground pads are used in the two-port measurement. The ground pads are

connected by four through-substrate vias to the ground plane contact. In order to


Table 11.4 Geometrical parameters represented by the number of

turns T and the length of last segment Ln

N s L1 L2 L3 W S

4T + 1 Ln + (T – 0.5)(W + S ) 2 L1 L2 – W W S

Table 11.5 Parameters of 20 inductors’ test structures

# of turns Width Spacing L1 L2 L3 Ln

Cell name (T ) N s (mil) (mil) (mil) (mil) (mil) (mil)

Ind1 1.5 7 1 1 6.0 12.0 11.0 3.5

Ind2 2.5 11 1 1 8.0 16.0 15.0 3.5

Ind3 3.5 15 1 1 10.0 20.0 19.0 3.5

Ind4 4.5 19 1 1 12.0 24.0 23.0 3.5

Ind5 1.5 7 2 1 7.0 14.0 12.0 3.0

Ind6 2.5 11 2 1 10.0 20.0 18.0 3.0

Ind7 3.5 15 2 1 13.0 26.0 24.0 3.0

Ind8 4.5 19 2 1 16.0 32.0 30.0 3.0

Ind9 1.5 7 1 1 8.0 16.0 15.0 5.5

Ind10 2.5 11 1 1 10.0 20.0 19.0 5.5

Ind11 3.5 15 1 1 12.0 24.0 23.0 5.5

Ind12 4.5 19 1 1 14.0 28.0 27.0 5.5

Ind13 1.5 7 2 1 9.0 18.0 16.0 5.0

Ind14 2.5 11 2 1 12.0 24.0 22.0 5.0

Ind15 3.5 15 2 1 15.0 30.0 28.0 5.0Ind16 4.5 19 2 1 18.0 36.0 34.0 5.0

Ind17 1.5 7 2 2 10.0 20.0 18.0 5.0

Ind18 2.5 11 2 2 14.0 28.0 26.0 5.0

Ind19 3.5 15 2 2 18.0 36.0 34.0 5.0

Ind20 4.5 19 2 2 22.0 44.0 42.0 5.0



minimize the effect of ground pads, the spacing of DUT (device under test) to

ground pad is more than five times the conductor width of the spiral inductor.

To de-embed the feeding microstrip at the right side and bond wire with a feed-

ing microstrip at the left side, the two other dummy structures were designed asshown in Figures 11.10a and b.

The de-embedding procedure developed in [15] is used to de-embed the mea-

sured DUT data. This de-embedding technique is based on the cascade configura-

tions without the requirement of any equivalent circuit models for the probe pads or

the interconnections.


Ground

Ground

Ground

Ground

Signal Signal

Figure 11.9 A typical Inductor test structure (3.5-turn inductor) in a ground–signal–ground

configuration. The ground vias are labeled in the figure.

(a) (b)

Figure 11.10 (a) Test structure for de-embedding the bond wire with a microstrip feed line

at the left side in Figure 11.9. (b) Test structure for de-embedding the microstrip at the right

side in Figure 11.9.



11.2.11 Measurement Setup and Calibration Specifications

The S -parameter measurement system is shown in Figure 11.11. The system con-

sists of a HP 8510 vector network analyzer system, a microwave probe station, and

a computer. The network analyzer and microwave probes are connected by high-

frequency cables. The measurement data are transferred from the network analyzer

to a computer via the HP-IB bus.

In our measurements, we used 150 m pitch GSG microwave probes, made by

GGB Industries Inc. The probe tips have three in-line contacts, spaced 150 m

apart. The two outside contacts provide ground connections and the center contact

provides the signal connection. CS–5 calibration substrate in the calibration kits is

used for calibration. The calibration method used in our system calibration is SOLT

(short, open, load, through). The accuracy of the system calibration is mainly limit-

ed by the accuracy of the impedance standards and the accuracy of the probe place-

ment. When the open measurement is performed, the probes contact open pad struc-

tures because the electrical fields at the probe tips are very similar to those of the

matched load and the through structures.

11.2.12 Experimental Verification

The spiral inductor test structures and dummy structures were measured by the

measurement set up shown in Figure 11.11. The intrinsic S -parameters are extracted

by using the de-embedding procedure which was developed in [15]. Figure 11.12shows S -parameters of Ind5 to Ind8, whose geometrical parameters are given in

Table 11.5. The agreement of measurement data and model simulation is quite

good.


Probe Station

P R O

BE

G

SG

P R

O B E

HP 8510B Network Analyzer

ComputerHighFrequencyCable

HB-IB

Figure 11.11 S -parameter measurement setup.




0 4 8 12 16 20

0.0

0.2

0.4

0.6

0.8

1.0

Ind8

Ind6

Ind7

Ind5

Measurement

Model

S 2 2

M a g n i t u d e

Frequency (GHz)

0 4 8 12 16 20-20

0

20

40

60

80

Ind5

Ind6Ind7Ind8

S 2 2

P h a s e ( D e g r e e )

Frequency (GHz)

Measurement

Model

Figure 11.12 S -parameters comparison of Ind5, Ind6, Ind7, and Ind8 (measurement and

model simulation).

0 4 8 12 16 200.0

0.2

0.4

0.6

0.8

1.0Ind8

Ind6

Ind7

Ind5

Measurement

Model

S 1 1

M a g n i t u d e

Frequency (GHz)

0 4 8 12 16 20

0

20

40

60

80

Ind5

Ind6Ind7

Ind8

S 1 1

P h a s e ( D e g r e

e )

Frequency (GHz)

Measurement

Model

0 4 8 12 16 20

0.4

0.6

0.8

1.0

Ind5

Ind7

Ind8

Ind6

Measurement

Model

S 1 2

M a g n i t u d e

Frequency (GHz)

0 4 8 12 16 20-100

-80

-60

-40

-20

0

Ind8Ind7

Ind6

Ind5

S

1 2


Frequency (GHz)

Measurement

Model



In order to see the performance of the inductors from the measured S -parame-

ters, S -parameters are converted to Y -parameters. Therefore, the Q-factor and in-

ductance of spiral inductor are extracted by using Equations 11.24 and 11.27:

L = (11.27)

Figure 11.13 shows the Q-factor of Ind5 to Ind8. The Q-factor of Ind5 is higher

than other inductors because it has only 1.5 turns and suffers less ground capaci-

tance and current crowding effects. With increasing number of inductor turns, the

parasitic capacitance from metal layer to ground plane increases, so that the first

self-resonance frequency decreases. The first self-resonance frequency is located at

the frequency where the Q-factor is zero.Figure 11.14 shows the inductance of Ind5 to Ind8. It is obvious that the induc-

tance increases with the number of turns. The inductance increases very sharply

near the first self-resonance frequency because of the resonance effect. Similar

good agreement between model predictions and experiments were obtained for the

other 16 test inductors, verifying the model expressions developed and discussed

here.

11.2.13 Low-Pass Filter

From an engineering perspective, the inductor model will be verified using a simple

circuit. This is done using the inductors in a third-order, low-pass filter circuit,

Im(1/Y 11)


0 4 8 12 16 20-10

0

10

20

30

40

50

Q

Frequency (GHz)

Ind6Ind7Ind8

Ind5

Measurement

Model

Number of turns

Figure 11.13 Q-factor of spiral inductor.



shown schematically in Figure 11.15. The inductance of L1 and L2 is 1.5 nH and the

capacitance is 0.5 pF. Figure 11.16 shows the layout of the low-pass filter. The in-ductor is implemented with a 1.5-turn spiral inductor and the capacitor is imple-

mented with an interdigital capacitor.

11.2.13.1 Interdigital Capacitor. The model of interdigital capacitor which

is used in the low-pass filter is shown in Figure 11.17. The model is a two-port T -

network. C is the most important element and it represents the capacitance of the in-

terdigital capacitor. L1 and L2 represent the series inductances. R1 and R2 represent

series resistances, which are frequency-dependent. C i1 and C i2 are the distributed

capacitances. The parameters in the model are derived by fitting the model-simulat-ed S -parameters to experimental S -parameters. The parameters’ values are shown in

Table 11.11. R1DC and R2DC are the DC values of resistances R1 and R2.

Figure 11.18 shows the S -parameters comparison of interdigital capacitance in

which good agreement between measurement and model simulation is obtained.


L1

Port 1 Port 2

C 1

L2

Figure 11.15 Schematic diagram of a third-order low-pass filter.

0 5 10 15 20

0

10

20

30

40

50

60

Ind6

Ind7Ind8

Ind5

I n d u c t a n c e ( n H )

Frequency (GHz)

Measurement

Model

Number of turns

Figure 11.14 Inductance of spiral inductors (Ind5–Ind8).



By applying the models of the spiral inductors and the interdigital capacitor in

Figure 11.15, the S -parameters of model simulation can be obtained from the ADS

circuit simulator. Good agreement of model simulation and measurement is ob-

tained as shown in Figure 11.19 for the third-order, low-pass filter.

11.2.14 Extension of the Model to Spiral Inductors on Silicon

Substrates

Today, due to the demand for system-on-chip solutions, inductors need to be de-

signed on a silicon wafer. During the past few years, much effort has been focused

on the modeling and design of integrated inductors for silicon RF ICs [6,7,16]. The

most challenging part of the inductor modeling on a silicon substrate is to exactly

model the substrate loss. This is because the substrate loss is very significant com-

pared to the conductor loss and the mechanism of the loss is not easily represented

by analytical expressions. In some publications, the inductor models are expressed

in terms of physics-based parameters [6,7,16]. However the errors of these models

are quiet large because it is very difficult to get a good ground reference point due


Figure 11.16 Test structure of the low-pass filter.

L1 L2 R1

C i1

R2

C

C i2

Figure 11.17 Equivalent circuit model of an interdigital capacitor.



to the lossy silicon substrate. In some of the reported works, curve fitting tech-

niques are used to get the model parameters from either measurements or EM simu-

lations. In most publications, the model is given as a lumped-element equivalent

circuit shown in Figure 11.20. In this model, the substrate network is more complex

than that of an alumina substrate because of the metal–insulator–silicon (MIS)structure. Here, C ox1 and C ox2 represent the capacitance of the inductor metal layer

to substrate, C sub1 and C sub2 represent the capacitance of the silicon substrate, and

Rsub1 and Rsub2 represent the resistance of lossy silicon substrate.

Once the circuit model is developed, parameters for the circuit elements must be

obtained. Here, a general technique was developed to extract lumped-element para-


0 4 8 12 16 20

-180

-120

-60

0

60

120

180

S11

S21

P h a s e ( D e

g r e e )

Frequency (GHz)

Measurement

Model

0 4 8 12 16 20

0.0

0.2

0.4

0.6

0.8

1.0

S11

S21

M a g n i t u d e

Frequency (GHz)

Measurement

Model

Figure 11.18 S -parameter comparison of an interdigital capacitor (measurement and model

simulation).




0 4 8 12 16 20

-180

-135

-90

-45

0

45

90

135

180

S11

S21

P h

a s e ( D e g r e e )

Frequency (GHz)

Measurement

Model

Momentum

Figure 11.19 S -parameter comparison of a third-order low-pass filter (measurement, mo-

mentum simulation, and model simulation).

Ls

C ox 1

C i

Rs

Rsub1 Rsub2

C ox 2

C sub1 C sub2

Port 1 Port 2

Figure 11.20 Equivalent circuit of a spiral inductor on a silicon substrate.

0 5 10 15 20

-30

-20

-10

0

S11

S21

M a g n i t u d e ( d B )

Frequency (GHz)

Measurement

Model

Momentum



meters of the model from measured S -parameters. The extraction procedure is de-

scribed in the following 3 steps.

1. The experimental S -parameters are transformed into Y -parameters using the

expressions

Y 11 = Y 0

Y 12 = Y 0

(11.28)

Y 21 = Y 0

Y 22 = Y 0

where Y 0 = 1/(50)

2. Y 1, Y 2, and Y 3 in the two-port -network can be represented by Y -parameters

as

Y 1 = Y 11 + Y 12

Y 2 = – Y 12 (11.29)

Y 3 = Y 22 + Y 21

Figure 11.21 shows the structure of two-port -network.

Y m1, Y m2 and Y m3 are two-port -network parameters of the inductor model given

as

Y m1

=

Y m2 = (11.30)

Y m3 = j C i +1

j L s + R s

j C ox2(1/ Rsub2 + j C sub2)

1/ Rsub2 + j (C ox2 + C sub2)

j C ox1(1/ Rsub1 + j C sub1)

1/ Rsub1 + j (C ox1 + C sub1)

(1 + S 11)(1 – S 22) + S 12S 21

(1 + S 11)(1 + S 22) – S 12S 21

– S 21

(1 + S 11)(1 + S 22) – S 12S 21

– S 12

(1 + S 11)(1 + S 22) – S 12S 21

(1 – S 11)(1 + S 22) + S 12S 21

(1 + S 11)(1 + S 22) – S 12S 21


Y 1

Y 3Y 2

Port1 Port2

Figure 11.21 Two-port -network.



3. The parameters of the lumped-element inductor model are obtained from an

optimization program for the fitting of the model’s Y m1, Y m2, and Y m3 to Y 1, Y 2, and

Y 3, respectively that are derived from experimental S -parameters. The optimization

employed a least-mean-square algorithm, which is built in the Matlab software. For

the optimization, the convergence is very important and it depends on the starting

values of parameters and the numbers of parameters. The starting values are derived based on the physical dimension of the spiral inductor and electrical parameters of

the substrate. Table 11.7 lists the equations for the starting values. In the table, l is

the length of inductor, hox is the thickness of the insulator layer, hsub is the thickness

of the substrate, h56 is the distance between metal 5 to metal 6, C ox is the starting

value of C ox1 and C ox2, C sub is the starting value of C sub1 and C sub2, and Rsub is the

starting value of Rsub1 and Rsub2.

A 2.5-turn square spiral inductor is designed in 0.18 m CMOS technology. The

test structure layout of the inductor is shown in Figure 11.22. Similar to the spiral

inductors on alumina substrate, the ground–signal–ground design is used for on-wafer probe measurement for this spiral inductor. The geometrical parameters of

this inductor are shown in Table 11.8.

The extracted model parameters are given in Table 11.9. Figure 11.23 shows that

good agreement is obtained between the measured and modeled S -parameters of the

inductor. Figure 11.24 also shows the good agreement between the measured and mod-

eled quality factor and inductance obtained using expressions discussed above. The

equivalent-circuit model parameters used in the simulations are shown in Table 11.9.


Table 11.6 Parameter for circuit elements of interdigital

capacitor model

C L1, L2 R1DC, R2DC C i1, C i2

0.48 pF 0.376 nH 0.29 74 fF

Figure 11.22 Test structure layout of a 2.5-turn spiral inductor on a silicon substrate.




Table 11.7 Equations for the model parameters used as initial values in optimization

program

L s =

N s

j =1 Lself, j +

L s

n=1, n j (–1) M j,n +

N s

n=1(–1)

+1

M m j,n

(11.31)

R s = , eff = (1 – e –t /2 ) (11.32)

C i = 0 r ,ox (11.33)

C ox = 0 r ,ox (11.34)

C sub = 0 r,si , W = W , C m = , C f = – C m(11.35)

Rsub = sub (11.36)hsub

( L2 + W )( L3 + W )

1

2

ef f

c0Z L

1

2

0 r,siW

hsub

C f

C m

( L2 + W )( L3 + W )

hsub

1

2

Wl

hox

1

2

NW 2

h56

l

2W · · eff

| j–n|

2

| j–n|

2

Table 11.8 Geometrical parameters of spiral inductor on silicon substrate

# of turns Width Spacing L1 L2 L3 Ln

(T ) N s (m) (m) (m) (m) (m) (m)

2.5 11 30 1.5 180 360 330 102

0 1 2 3 4 50.0

0.2

0.4

0.6

0.8

1.0

M a g n i t u d e

Frequency (GHz)

Mag. S11

Mag. S12

-60

-40

-20

0

20

40

60

Phase S11

Phase S12


Figure 11.23 Comparison between measured and model-simulated S -parameters of a 2.5-

turn silicon spiral inductor.



11.3 MODELING OF THIN-FILM RESISTORS

Thin-film resistors (TFRs) are used in microwave circuits to implement compo-

nents such as passive attenuators and terminal loads. To date, the TFR model con-

siders the parasitic series inductance and shunt capacitance to be the same as thoseof a lossless microstrip line [17]. However, this model does not provide good re-

sults when the width of resistor is much smaller than the substrate thickness. In ad-

dition, the self-capacitance has to be taken into account to improve the model accu-

racy. The self-capacitance of planar resistors was introduced in [18]. If a voltage is

applied at the terminals of a resistor, a potential difference will exist across two ar-

bitrary points A and B in the resistor. Therefore, a parasitic capacitance exists be-

tween A and B [27].

In microwave integrated circuit (MIC) technology, a thin-film resistor is realized

as a thin strip of a lossy conductor on top of a dielectric substrate. The resistive lay-er can be a self-passivating tantalum nitride (TaN) compound. The sheet resistivity

of the process is adjusted by controlling the thickness of the resistive layer. In most

processes, a sheet resistivity of 50 per square is selected due to the convenience

that it provides to circuit designers. A small area of highly conducting metal is de-

posited at the ends of the element as contacts to the resistor. The exposed resistive

area defines the resistance of the structure. The fabrication design rules generally

require that the resistive layer be narrower than the width of the conducting contact

by some minimum distance. This requirement arises due to the need to have a good

contact between the resistive layer and the conducting layer to take into account the process alignment tolerances.

Figure 11.25 shows the layout cross section of a thin-film resistor. The mea-

surement reference planes at the ends of the conductor contacts are shown in

Figure 11.25a, so that the conductor contact is removed from the measurement.

However, the electrical effect of the step discontinuity will not be removed from

11.3 MODELING OF THIN-FILM RESISTORS 271

0 1 2 3 4 50

2

4

6

8

Q

Frequency (GHz)

Measurement

Model

0

1

2

3

4

5

L ( n H )

Figure 11.24 Comparison between measured and model simulated Q-factor and induc-

tance of a 2.5-turn silicon spiral inductor on a silicon substrate.



the measurement. As a result, the thin-film resistor model should be divided into

three sections, as shown in Figure 11.26. The middle section is the intrinsic thin-

film resistor, which is modeled as a lossy microstrip transmission line. The other

two sections model the step discontinuities at both sides of the intrinsic thin-film

resistor.

In this section, various aspects of thin-film resistors important for developing an

accurate equivalent-circuit model will be discussed. Step-discontinuity, sheet resis-

tance, and design of test structures for experiments and model verification will bediscussed. In addition, the S -parameters measurement system, measurement cali-

bration, and comparison between measurements and model will be presented and

discussed.


Figure 11.25 (a) Overhead and (b) side views of a thin-film resistor.

Lossy Microstrip LineStep Step

Port 1 Ref. Plane Port 2 Ref. Plane

Port 1 Ref. Plane Port 2 Ref. Plane

Figure 11.26 Equivalent circuit of a thin-film resistor.



11.3.1 Step Discontinuity in Microstrip Width

Since the width of the thin-film resistor must be narrower than that of the contacting

conductor layer, a step discontinuity exits at both ends of the resistor. The electro-

magnetic field is discontinuous at the steps because the current density increases

from the wider to the narrower conductor and scattered electric fields exist on the

front edge of the wider conductor, as shown in Figure 11.27a. Figure 11.27b shows

the equivalent circuit of the step in conductor width. L s represents the current com-

pression and C p represents the electrical scattering fields.

An approximate expression C p [21] is given by

C p = C f 1(W 1 – W 2) (11.37)

Here, C f 1 is the fringing capacitance per unit length of the wider microstrip [21]:

C f 1 = – 0 r W 1/h[ F /m] (11.38)

where c0 is the speed of light in free space, and Z L1 and eff1 are the characteristic

impedance and effective dielectric constant of the wider microstrip, respectively.

In some cases, TFRs may have very small lengths, and the two step discontinu-

ities can be very close to each other. In this case, capacitance C p at one end of resis-tor will decrease because the electrical scattering field is constrained by the step at

the other end of the resistor. To calculate C p under this condition, the method that

derives the even-mode fringing capacitance C f 1 of two parallel microstrip lines is

employed, and it can be expressed as [11]

C f 1 = [ F /m] (11.39)C f 1

1 + A(h/l )tan h(8l /h)

ef f1

c0Z L1

1

2


(a) (b)T

W 1

Current Lines

W 2

Electrical scattering fields

Ls

C p

TT

Figure 11.27 Step in microstrip. (a) Width construction. (b) Lumped-element equivalent

circuit [21].



where A = exp[–0.1 exp(2.33 – 2.53 W 1/h)] and l is the length of the resistor. By

putting Equations 11.38 and 11.39 into 11.37, C p can be obtained as

C p = (11.40)

The closed-form expression for inductance L s has been derived by curve fitting

the numerical results, and L s [21] is

L s = [a( – 1) – b log(() + c( – 1)2)]h [nH] (11.41)

where a = 40.5, b = 75, c = 0.2, and = W 1/W 2.

11.3.2 High Sheet Resistance Microstrip Model

As a two-port network, a high sheet resistance microstrip line can be represented by

an ABCD matrix [19]:

cosh( l ) Z L sinh( l )

=

(11.42)

sin

Z

h

L

( l )

cosh( l )]

where Z L is the characteristic impedance and is the propagation constant. It is well

known that Z L and can be given by the series impedance per unit length Z and the

shunt admittance per unit length Y of the microstrip line:

Z L = (11.43)

= Z · Y (11.44)

Due to the low value of the losses in the alumina substrate, the shunt conductance

per unit length is neglected. Therefore, Y can be given by the shunt capacitance per

unit length C as

Y = j C (11.45)

For a low-loss microstrip line, Z can be given by the sum of the per-unit length re-

sistance R and the per unit length inductance L:

Z = R + j L (11.46)

However, for a high sheet resistance microstrip line, the self-capacitance must be

taken into account. In [18], the self-capacitance was derived by numerical calcula-

Z

Y

B

D

A

C

12 c0

Z e

0

f 1

f1

–

0 hr W 1(W 1 – W 2)

1 + A(h/l )tan h(8l /h)




tion. Here, however, the self-capacitance was derived by using a commercially

available full-wave electromagnetic simulator (HP-Momentum).

Two sets of microstrip lines were simulated by HP-Momentum. One set consist-

ed of microstrip lines with high sheet resistance of 50 per square; the other setconsisted of lossless microstrip lines. Electromagnetic simulations were performed

from 1 GHz to 40 GHz in 4 GHz steps. The dimensions of the microstrip lines are

shown in Table 11.9.

The series resistance, inductance, and shunt capacitance per unit microstrip

length were extracted from the simulated S -parameters. The four-step extraction

procedure is now described.

1. Convert S -parameters into ABCD parameters using the standard expression.

A =

B = Z 0

(11.47)

C =

D =

where Z 0 = 50.

2. Determine the propagation constant as = acosh( A)/l and the characteristic

impedance as Z L = B/sinh[achosh( A)].

3. Determine the series impedance per unit length Z and the shunt admittance

per unit length Y of the microstrip line from Z = Z L · and Y = /Z L, respectively.

4. Obtain the series resistance per unit length as equal to the real part of Z , series

inductance per unit length as L = Im(Z )/ , and shunt capacitance per unit length as

C = Im(Y )/ .Figure 11.28 shows the capacitance per unit length versus frequency and mi-

crostrip width. The capacitance increases as the microstrip width increases. The

values of the capacitance are nearly identical in Figures 11.28a and b, which veri-

fies that the shunt capacitance per unit length of a high sheet resistance microstrip

line can be simply derived from the lossless line case.

Figure 11.29 shows that the series resistance per unit length of high sheet resis-

tance line decreases with the frequency because of the self-capacitance effect.

(1 – S 11)(1 + S 22) + S 12S 21

2S 21

(1 – S 11)(1 – S 22) – S 12S 21

2S 21

1Z 0

(1 + S 11)(1 + S 22) – S 12S 21

2S 21

(1 + S 11)(1 – S 22) – S 12S 21

2S 21


Table 11.9 Extracted model parameters

L s R sDC C i C ox1 C ox2 C sub1 C sub2 Rsub1 Rsub2

(nH) () (fF) (fF) (fF) (fF) (fF) () ()

3.56 4.396 2.17 188 192 145 161 225 213



Clear differences can be seen between Figures 11.30a and b. This means that the

series inductance per unit length of a high sheet resistance microstrip line cannot be

simply obtained from the case of a lossless line. Further, we find that the series im-

pedance per unit length cannot be represented by just a resistor in series with an in-

ductor. An appropriate first-order model for the series impedance Z is shown in Fig-

ure 11.31 and is given by Equation 11.48.

Z = R1 – + j L – (11.48)

In Equation 11.48 L is equal to the series inductance per unit length in the case of a

lossless line, R is the series resistance per unit length at DC, and C s represents the

self-capacitance, which has been derived by curve fitting of the numerical Momen-

tum simulation results:

R2C s/4

1 + ( RC s/2)2( RC s/2)2

1 + ( RC s/2)2


0 10

20 30

40

0.10.2

0.4

0.6

50

100

150

200

250

Frequency (GHz)Width (mm)

C a p a c i t a n c e ( p F )

0 10

20 30

40

0.10.2

0.4

0.6

50

100

150

200

250


C a p a c i t a n c e ( p F )

(a) (b)

Figure 11.28 Shunt capacitance per unit length of (a) resistive line (50/) and (b) loss-

less line.

0 10

20 30 40

0.10.2

0.4

0.60.8

0.85

0.9

0.95

1


o r m a

z e

r e s s a n c e

Figure 11.29 Frequency dependent series resistance per unit length normalized to DC se-

ries resistance per unit length of resistive line (50/).



C s = 1.58 × 10 –18 + 1.26 (11.49)

where W is the width of resistor and h is the substrate height, which is 15 mil for

these samples.

In the model given by Equation 11.48, the real part of Z is the series resistance per unit length, which decreases with frequency, in agreement with the trend in .

The equivalent inductance per unit length is a function of the DC resistance per unit

length R, self-capacitance C s, and series inductance per unit length L in the case of

lossless line, and it is smaller than that of the lossless line case.

The series inductance per unit length L and shunt capacitance per unit length C

of a lossless line can be directly calculated from the empirical formula for Z L and

eff of a lossless transmission line, which are given by Equations A.19 and A.11.

The resistance per unit length R is determined by the technology. C s is given by

Equation 11.48. Thus, the impedance per unit length Z and the admittance per unitlength Y of a high sheet resistance microstrip line can be calculated from L, R, C s,

and C . By using Equations 11.43 and 11.44, the characteristic impedance Z L and

propagation constant can be calculated. Finally, the model can be implemented in

matrix form by using the ABCD matrix shown in Equation 11.42.

W

h


0 10

20 30

40

0.2

0.40.6

250

300

350

400

450

500


I n d u c t a n c e

( n H )

0 10

20 30

40

0.2

0.40.6

300

400

500

600

700

800


I n d u c t a n c e

( n H )

(a) (b)

Figure 11.30 Series inductance per unit length of (a) resistive line (50/) and (b) losslessline.

L R/2 R/2

C s

Figure 11.31 Equivalent circuit of per unit length series impedance.



11.3.3 Experimental Verification

Nine thin-film resistors (TFRs) were fabricated and measured. They had different

widths and lengths. The height of the substrate is 15 mil. The planar physical di-

mensions of the TFR test structures were measured using a microscope. The DC re-

sistance of the TFRs were measured using a digital multimeter. Based on the mea-

sured resistance and the physical dimensions of a resistor, the sheet resistance of the

resistive layer was determined. The physical parameters of thin-film resistors are

presented in Table 11.10.

The layout of resistors 3 and 9 are shown in Figure 11.32. The microstrip feed

lines are 5080 m long and 361 m wide. Although the width of resistor 9 is larger

than the width of microstrip feed line, a short length (100 m) of wider conductor

had to be added between the end of the microstrip feed line and the resistor. Since

the measurement reference planes are at the ends of the microstrip feed lines, the ef-

fect of the short length of wide conductor was included in the measurements. There-

fore, this short length of wide conductor has to be included in the resistor model,

which is shown in Figure 11.33.

The model of wider resistors, such as resistors 7 to 9, is divided into seven sections

as shown in Figure 11.33. The middle three sections are the same as the model shown

in Figure 11.26. A low-loss microstrip transmission line is used to model the short

length of wide conductor. A step in microstrip width exists at the connection of the

microstrip feed line and wide microstrip, so a step model is used to model this effect.

11.3.4 S-parameter Measurement Setup

The block diagram of a measurement setup is shown in Figure 11.34. The measure-

ment setup consisted of a Wiltron 37396A vector network analyzer (VNA), two

high-frequency cables, and a universal test fixture (UTF). The Wiltron 37396A

VNA was used to make the S -parameter measurements of the thin-film resistors.

The coaxial cables from the VNA are attached to the two connector blocks of the

UTF. The connector of UTF provides a coaxial–microstrip transition. S -parameters

were measured over a frequency range of 1 to 40GHz.

11.3.5 Measurement Calibration

At microwave frequencies, a proper calibration is critical for high measurement ac-

curacy. The goal of calibration is to remove the influences of elements other than the


Table 11.10 Parameters of simulated microstrips

Input Parameter Minimum Value Maximum Value

Frequency (GHz) 1 40

Width (m) 100 500

Length (m) 200 500




(a)

(b)

Microstrip Feed Lines Resistor Layer

Figure 11.32 Layout of resistor test structure. (a) Resistor 3. (b) Resistor 9.

Table 11.11 Measured physical parameters of thin-film resistor test structures

Resistor Width (m) Length (m) DC Resistance () Sheet Resistance (/)

1 145 70 27.1 56 ± 22 140 140 52.8 52 ± 1

3 140 280 104.3 52 ± 1

4 265 130 26.2 53 ± 1

5 270 265 52.4 51.2 ± 0.8

6 270 530 103.4 52.7 ± 0.8

7 510 260 26.1 51.2 ± 0.8

8 510 510 51.1 51.1 ± 0.8

9 510 1020 104.2 52.1 ± 0.8

Lossy Microstrip LineStep Step

Port 1 Reference Plane Port 2 Reference Plane

Step Step

Resistor Layer

Low-Loss Microstrip Line

Microstrip Feed line Microstrip Feed line

Port 1 Reference Plane Port 2 Reference Plane

Figure 11.33 Equivalent circuit for wider resistor.




High Frequency Cables

Universal Test Fixture

Vector Network Analyzer

Figure 11.34 Block diagram of measurement setup.

0 10 20 30 400.4

0.5

0.6

0.7

0.8

0 10 20 30 40

-60

-40

-20

0

103.4Ω

52.4Ω

Measurement

Model

S 1 2

M a g n i t u d e

Frequency (GHz)

103.4Ω

52.4Ω

S 1 2


Frequency (GHz)

Measurement

Model

Figure 11.35 Comparison between measured and simulated S -parameters for two TFRs

[Cell 5 (52.4) and Cell 6 (103.4)].

0 10 20 30 400.2

0.3

0.4

0.5

0.6

0 10 20 30 40-60

-45

-30

-15

0

103.4Ω

52.4Ω

Measurement

Model

S 1 1

M a g n i t u d e

Frequency (GHz)

103.4Ω

52.4Ω

S 1 1

P h a s e ( D

e g r e e )

Frequency (GHz)

Measurement

Model



device under test (DUT). All cables, transitions, and feed lines connecting the DUT to

the VNA influence the S -parameter measurements. Therefore, the effects of the trans-

mission medium must be removed through measurement calibration. Calibration in-

volves the measurement of a series of standards relative to the measurement reference planes. The reference planes are generally placed at the ports of the DUT. After cali-

bration, the effect of all influences behind the reference planes are mathematically re-

moved from measurements. In the measurement of TFRs, the reference planes are

placed at the end of microstrip feed lines, as shown in Figures 11.26 and 11.33.

The TRL (Thru reflect line) calibration method was used for the measurement

calibration. This calibration method avoids the difficulty of producing precision im-

pedance structures. In the TRL calibration procedure, the Thru standard is mea-

sured with two ports connected with a 10.16 mm 50 microstrip line, and the mea-

surement reference planes are placed in the middle of the line. The reflect standard is realized as an open-end 5.08 mm 50 microstrip line.

The S -parameters of two TFRs (resistors 5 and 6), whose widths are smaller than

microstrip feed line, are shown in Figure 11.35. As is shown, good agreement be-

tween model simulations and measurements has been obtained. The S -parameters of

two TFRs (resistors 8 and 9), whose widths are larger than the microstrip feed line,

are shown in Figure 11.36. As before, good agreement between model simulations


0 8 16 24 32 40

0.2

0.3

0.4

0.5

0 8 16 24 32 40-150

-120

-90

-60

-30

0

0 8 16 24 32 40

0.4

0.5

0.6

0 8 16 24 32 40

-180

-135

-90

-45

0

Measurement

Model

S 1 1

M a g n i t u d e

Frequency (GHz)

S 1 1


Frequency (GHz)

Measurement

Model

Measurement

Model

S 1 2

M a g n i t u d e

Frequency (GHz)

S 1 2


Frequency (GHz)

MeasurementModel

51.1Ω51.1Ω

51.1Ω 51.1Ω

104.2Ω

104.2Ω

104.2Ω

104.2Ω

Figure 11.36 Comparison between measured and simulated S -parameters for two TFRs

[Cell 8 (51.1) and Cell 9 (104.2)].



and measurements was obtained. Similar good agreement between experiments and

simulations for the other five resistors listed in in Table 11.11 were obtained.

11.4 CONCLUSIONS

In this chapter, equivalent circuit models for spiral inductors, interdigital capacitors,

and thin-film resistors were proposed. Twenty test structures of spiral inductors

were designed and tested to verify the scalable inductor model. A low-pass filter

was designed to verify the spiral inductor model for circuit applications. Good

agreement has been found between measurement and model simulation. The induc-

tor model was extended to the silicon substrate. Due to the complex substrate effect

in silicon substrates, the model is not scalable, but a technique to extract the model parameters was presented.

An accurate scalable model for thin-film resistors has been represented in ABCD

matrix form. Details of the inductive and capacitive parasitics in the TFR have been

discussed. A self-capacitance is used to get better fitting of the model. Good agree-

ment between simulations with the proposed model and measurements has been ob-

tained up to 40GHz.

REFERENCES

1 C. J. Mattei, “Advanced Alumina: A Manufacturing Medium for Microwave Oscillators

and Amplifiers,” Microwave Journal, 36, 2, 64–74, 1993.

2. I. D. Robertson and S. Lucyszyn, RFIC and MMIC Design and Technology, The Institu-

tion of Electical Engineers, London, 2001.

3. www. nanowavetech. com.

4. Advanced Design System 1.3—Momentum Menu, Agilent Technologies, November

1999.

5. H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,” IEEE Transactions on Parts, Hybrids, and Packaging, PHP-10, 2, 101–109, 1974.

6. M. Parisot, Y. Archambault, D. Pavlidis, and J. Magarshack, “Highly Accurate Design

of Spiral Inductors for MMIC’s with Small Size And High Cut-off Frequency Character-

istics,” In IEEE MTT-S Digest, 1984.

7. J. R. Long and M. A. Copeland, “The Modeling, Characterization, and Design of Mono-

lithic Inductors for Silicon RF ICs”, IEEE Journal of Solid-State Circuits, 32, 3,

357–369, 1997.

8. F. Grover, Inductance Calculations, Working Formulas and Tables, New York: Dover

Publications, 1962.

9. Y. K. Koutsoyannopoulos and Y. Papananos, “Systematic Analysis and Modeling of In-

tegrated Inductors and Transformers in RF IC Design,” IEEE Transactions on Circuits

and Systems-II: Analog and Digital Signal Processing, 47, 8, 699–713, 2000.

10. W. B. Kuhn and N. M. Ibrahim, “Analysis of Currnet Crowding Effects in Mutiturn Spi-

ral Inductors,” IEEE Microwave Theory and Techniques, 49, 1, 31–39, 2001.




11. R. Garg and I. H. Bahl, “Characteristics of coupled microstriplines,” IEEE Transactions

on Microwave Theory and Techology, 27, 700–705, 1988.

12. P. Pieters, K. Vaesen, S. Brebels, S. F. Mahmoud, W. D. Raedt, and R. P. Mertens, “Ac-

curate Modeling of High-Q Spiral Inductors in Thin-Film Multilayer Technology for Wireless Telecommunication Applications,” IEEE Transactions on Microwave Theory

and Technology, 49, 4, 589–599, 2001.

13. E. Pettenpaul, H. Kapusta, A. Weisgerber, H. Mampe, J. Luginsland, and I. Wolff,

“CAD Models of Lumped Elements on GaAs up 18 GHz,” IEEE Transactions on Mi-

crowave Theory and Technology, 36, 2, 294–304, 1988.

14. H. Ronkainen, H. Kattelus, E. Tarvainen, T. Riihisaari, M. Andersson and P. Kuiv-

alainen, “IC Compatible Planar Inductors on Silicon,” IEEE Proceedings on Circuits,

Devices, and Systems, 144, 1, 1997.

15. C. H. Chen and M. J. Deen, “A General Noise and S -Parameter De-Embedding Proce-

dure for on-Wafer High Frequency Noise Measurements of MOSFETs,” IEEE Transac-

tions on Microwave Theory and Techniques, Electronics Letters, 49, 5, 1004–1005,

2001.

16. A. M. Niknejad and R. G. Meyer, “Analysis, Design and Optimization of Spiral Induc-

tors and Transformers for Si RF IC’s.” IEEE J. Solid-State Circuits, 33, 1470–1481,

1998.

17. G. Carchon, S. Brebels, W. De Raedt, and B. Nauwelaers, “Accurate Measurement and

Characterization up to 50 GHz of CPW-based Integrated Passives in Microwave MCM-

D,” In 2000 Electronic Components and Technology Conference, pp. 459–464, 2002.

18. S. N. Demurie and G. De Mey, “Parasitic Capacitance Effects of Planar Resistors,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 12, 3,

348–351, 1989.

19. H. Patterson, “Modeling Lossy Transmission Lines from S -Parameter Data,” Microwave

Journal, 36, 11, 96–104, 1993.

20. M. J. Deen and M. Urteaga, Modeling of Passive Microwave Circuit Elements, Techni-

cal Report to Nanowave Technology, Etobicoke, Ontario, 140 pages (May 1999).

21. R. K. Hoffmann, Handbook of Microwave Integrated Circuits, Artech House, Norwood,

MA.

22. E. Hammerstad and O. Jensen, “Accurate Models for Microstrip Computer-aided De-sign,” In IEEE MTT-S International Microwave Symposium Digest, pp. 407–409, 1980.

23. E. Yamashita, K. Atsuki, and T. Ueda, “An Approximate Dispersion Formula of Mi-

crostrip Lines for Computer-Aided-Design of Microwave Integrated Circuits,” IEEE

Transactions on Microwave Theory and Technology, MTT-27, 12, 1036–1038, 1979.

24. M., Kirschning, and R. H. Jansen, “Accurate Model for Effective Dielectric Constant of

Microstrip with Validity up to Millimetre Wave Frequencies,” Electronics Letters, 18, 6,

272–273, 1982.

25. D. M. Pozar, Microwave Engineering, 2nd ed., Wiley, New York, 1998.

26. R. Faraji-Dana and Y. L. Chow, “The Current Distribution and AC Resistance of a Mi-crostrip Structure,” IEEE Transactions on Microwave Theory and Techniques, Electron-

ics Letters, 38 9, 1268 –1277, 1990.

27. Z. Wang, M. J. Deen, and A. Rahal, Accurate Modelling of Thin-Film Resistor up to 40

GHz, In 32nd European Solid-State Device Research Conference (ESSDERC 2002),

Firenze, Italy, pp. 307–310, 24–26 September, 2002.

REFERENCES 283



APPENDIX: CHARACTERISTICS OF MICROSTRIP LINES

The microstrip line has been used extensively in microwave circuits as a transmis-

sion line for a wide range of applications because it is easily made using standard photolithographic fabrication technology. The characteristics of microstrip lines are

the basis for modeling thin-film resistors (TFRs), spiral inductors, and through-sub-

strate vias. There are numerous publications dealing with the analysis, design, and

applications of microstrip lines [21,22]. The resistor layer of a TFR can be assumed

to be a lossy microstrip line; the spiral inductor can be decomposed into a few seg-

ments of microstrip line and the via pad can be treated as a short piece of microstrip

line. The properties of microstrips are determined by the characteristic impedance

Z L, the effective dielectric constant eff , and the attenuation factor c [21].

A MHMIC microstrip line is shown in Figure A.1. It consists of a thin strip of conductor separated from a ground plane by a dielectric substrate. The conductor

strip is defined by its width W and thickness t . The ground plane is completely met-

alized to a thickness t . The substrate is described by its thickness h, relative permit-

tivity r , and dielectric loss factor tan For MHMIC, the substrates are typically

made of alumina (Al2O3) with thickness h of 0.254 mm (10 mil), 0.381 mm (15

mil), or 0.635 mm (25 mil). Metal film of t = 5m is used for the microstrip and

ground plane. r is 9.9 and tan is 0.0001.

A.1 Characteristic Impedance Z L and Effective Dielectric Constant eff under Static TEM Approximation

Because a microstrip line is surrounded by an inhomogeneous dielectric (Al2O3 and

air), it is incapable of supporting a pure transverse electromagnetic mode (TEM)

wave. The fundamental mode of a wave propagating in a microstrip is hybrid. How-

ever, the longitudinal electric E L and magnetic H L fields are small compared to

transversal electrical E T and magnetic H T fields at low microwave frequencies.


Figure A.1 Microstrip configuration [21].



Therefore, the microstrip line can be analyzed under static TEM approximation at

low microwave frequencies. The upper frequency at which static approximation can

be used in practical circuit designs is given empirically by [21]

f stat = [GHz] (A.1)

where W and h are in mm.

Approximate formulas for the circuit parameters of a microstrip can be derived

by various methods [21,22]. Among these approaches, Hammerstad and Jensen

produced highly accurate equations for Z L0 and eff of microstrips by functional ap-

proximations of analytical equations. Z L0 is defined as the characteristic impedance

of a microstrip without substrate ( r = 1) for zero conductor thickness and is given by

Z L0 = ln + 1 + ( 2 h /W )2 (A.2)

with

F 1 = 6 + (2 – 6)e –(30.666h/W )0.7528 (A.3)

The effective eff of microstrip without substrate ( r = 1) for zero conductor

thickness was derived by functional approximations of numerically calculated val-

ues from the static Green’s function method [21]:

eff = + 1 + – ab (A.4)

with

a = 1 + ln + ln1 + 3 (A.5)

and

b = 0.564 0.053

(A.6)

Due to the effect of the finite conductor thickness of the microstrip, a concept of

equivalent width W eff0 was used [22]:

W eff0 = W + ln1 + (A.7)4e

t/h coth2( 6 .5 1 7 W /h )

t

r – 0.9

r + 3

W

18.1h

1

18.7

(W /h)4 + 5W

2h

2

(W /h)4 + 0.432

149

10h

W

r – 1

2

r + 1

2

F 1h

W

0

2

21.3

(W + h) r + 1

APPENDIX: CHARACTERISTICS OF MICROSTRIP LINES 285



For a microstrip with substrate ( r > 1), the equivalent width is given as [22]

W eff = W + ln

1 +

1 +

(A.8)

Finally, the characteristic impedance and effective dielectric constant for finite con-

ductor thickness are given as [21]

Z L , , r = Z L , t = 0, r = (A.9)

eff (W

h, , r ) =

2

(A.10)

= eff

W

h

eff

, t = 0, r

2

A.2 Dispersion Models of Effective Dielectric Constant eff and

Characteristic Impedance Z L

Because the wave propagating in a microstrip is intrinsically dispersive, the charac-

teristic impedance Z L and effective dielectric constant eff are frequency dependent.

Therefore, the dynamic analysis method is required for the calculation Z L and eff above the upper static approximation frequency f stat. Approximate formulas for the

circuit parameters for microstrip can be derived by various methods [21,23,24].

Among these approaches, Yamashita et al. published a dispersion model that de-

scribes the frequency dependence of eff [23]:

eff ( f ) = + ef f ( 0 ) 2

(A.11)

with

F = 0.5 + 1 + 2 log101 + 2 (A.12)

where 0 is the wavelength in free space, eff (0) is the static effective dielectric con-

stant given by Equation A.4.

W

h

4h r – 1

0

r – ef f ( 0 )

1 + 4 F –1.5

Z L0W

h

eff0, t = 0

Z LW

h

eff , t = 0

Z L0W

h

e

,

ff0 t = 0

Z LW

h

eff , t = 0, r

t

h

Z L0W

h

eff , t = 0

ef f W

h

e

ff

, t = 0 , r

W eff

h

t

h

W

h

1

cosh r – 1

1

2

4e

t/h coth2( 6 .5 1 7 W /h )

t




More accurate dispersion equations for effective dielectric constant are given by

Kirschning and Jansen [24]:

re( f ) = r – (A.13)

P = P 1 P 2[(0.1844 + P 3 P 4)10 fh]1.5763 (A.14)

P 1 = 0.27488 + [0.6315 + ] – 0.065683e –8.7513(W/h) (A.15)

P 2 = 0.33622(1 – e –0.03442 r ) (A.16)

P 3 = 0.0363e –4.6(W/h)[1 – e –( fh/3.87)4.97] (A.17)

P 4 = 1 + 2.751[1 – e –( r /15.916)8] (A.18)

where h is in cm and f is in GHz. The accuracy of this expression is better than 0.6%

in the range 0.1 W/h 100, with 0 h/ 0 0.13 and 1 r 10.

The closed-form expression describing the effect of frequency on the character-

istic impedance Z L is given by [21]

Z L( f ) = Z L0 (A.19)

The frequency dependence of effective dielectric constant and characteristic im-

pedance are shown in Figure A.2. In this figure, the effective dielectric constant in-

creases with frequency.

eff (0)

eff ( f ) eff ( f ) – 1 eff (0) – 1

0.525

(1 + 0.157 · fh)20

W

h

r – eff (0)

1 + P


1E9 1E10 1E11 1E1245

50

55

60

65

70

75

80

C

h a r a c t e r i s t i c I m p e d a n c e ( Ω )

Frequency (Hz)

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.09.5

10.0

E f f e c t i v e D i e l e c t r i c C o n s t a n t , ε

e f f

Figure A.2 The frequency-dependent effective dielectric constant and characteristic im-

pedance for a microstrip with W = 361 m, h = 381 m, and r = 9.9 (alumina).



A.3 Lumped-Element Model of a Microstrip Line

A short piece of microstrip line of length z can be modelled as a lumped-element

circuit, as shown in Figure A.3. Here, R is the series resistance per unit length in

/m and it represents the losses of the conductor, L is the series inductance per unit

length in H/m, G is the shunt conductance per unit length in S /m and it represents

the losses of the substrate, and C is the shunt capacitance per unit length, in C /m

[25]. If the length of microstrip line is of the same order as the wavelength or larger,

a large chain of the circuit blocks in Figure A.3 are cascaded together to model the

microstrip line. Usually, 100 circuit blocks are good enough to represent a one-

wavelength microstrip line.

According to the transmission line theory, L and C of a low-loss microstrip line

can be calculated from characteristic impedance Z L and effective dielectric constant

eff :

L = (A.20)

C = (A.21)

A.4 Microstrip Losses

There are four kinds of microstrip losses: conductor losses, dielectric losses, radi-

ation losses, and leakage losses . Since the models discussed here are for applica-

tions below 40 GHz, the leakage losses and radiation losses can be neglected in

alumina substrates. Therefore, only conductor losses and dielectric losses are dis-

cussed.

Conductor Losses. The total conductor loss in a microstrip line is composed of two parts: the loss in the rectangular strip and the ground plane loss.

ef f

cZ L

ef f Z L

c


C ∆l

R∆ z

G∆l

L∆l

Figure A.3 Lumped-element circuit model for a short piece of microstrip line of length

l .



The DC resistance of a conductor is calculated from

RDC = (A.22)

where is metal conductivity, and l , W , and t are its length, width, and thickness,

respectively.

At high frequencies, the skin effect due to magnetic fields causes nonuniform

current flow in the conductor, causing most of the current to flow near the surface

of the metal traces, as shown in Figure A.4. The resistance can be calculated

from

Rskin = = (A.23)

where is the skin depth of the metal given by

= (A.24)

eff is the effective skin depth. The derivation of eff is illustrated in Figure A.5, inwhich the area under solid line is the same as the area under the dashed line. The

solid line represents the current density inside the conductor. It is well known that

the current density decreases exponentially inside the metal. At DC and low fre-

quencies, is much larger than conductor thickness t , so that eff is approximately

equal to t /2, and Rskin is equal to the DC resistance. At high frequencies, is much

smaller than conductor thickness t , thus eff is approximately equal to . Therefore,

by introducing eff , Equation A.23 can model the resistance of the conductor from

DC to microwave frequencies.

2

l

2W (1 – e –t /2 )

l

2W eff

l

Wt


δeff

E

δeff

Figure A.4 Skin effect in a microstrip.



The distribution of current density in microstrip structure is shown in Figure A.6.The exact analytical expression for the distribution is very difficult to determine.

Therefore, curve fitting techniques are typically used to determine this distribution.

A curve-fitted approximation formula for ground plane AC resistance is given by

[26]

R g = 0.55 RDC (1 – e –W /1.2 h) (A.25)t


J ( x )

Ground plane

top of strip

bottom of strip

-W /2 W /2 x

Figure A.6 Microstrip surface current density distribution [26].

t /2

J 0

0

J

δ e

Metal

Thickness

J 0e t δ ⁄ –

x

δef f e x δ ⁄ –

x d 0

t 2 ⁄

δ 1 e t 2 δ ⁄ –

–( )⋅= =

Figure A.5 Illustration of the effective skin depth.





293

CHAPTER 12

OTHER APPLICATIONS ANDINTEGRATION TECHNOLOGIES

ELIZABETH LOGAN, GEERT J. CARCHON, WALTER DE RAEDT,

RICHARD K. ULRICH, AND LEONARD W. SCHAPER

The use of integrated passives offers wide capability for the realization of a varietyof highly compact, lightweight, and high-performance devices. In this section, a

number of examples of both demonstrators and commercial products will be dis-cussed, which will clearly show the potential of the integrated passives approach ina broad range of applications. Indeed, as some of these examples will show, the pas-sive components can be successfully used in devices from portable phone and Blue-tooth™ applications (in the 1–2 GHz frequency range) up to Ka-band satellite appli-cations (30 GHz and higher), as well as for simpler filtering and termination.

The main driving forces for integration are primarily those of reduced system cost,smaller form factor and mass, improved reliability, and increased design flexibility.Passive integration, in and of itself, brings little to the table in the way of new andnovel circuit configurations and so replacement of surface-mount with integratedcomponents often tends to be close to a one-to-one trade. The main exception to thisrule is decoupling (see Chapter 9), in which the close proximity of the capacitors tothe circuitry and active elements can lead to greatly reduced series inductance andimproved electrical performance. At higher frequencies, where it is often not possi-

ble to use surface-mount components, integrated passive components can also pro-vide unique solutions. In general, however, typical devices made from integrated

passives will have a similar schematic and number of components to the equivalentdevice made from discretes. An examination of the commercialized surface-mountintegrated passive arrays and networks described in this chapter supports this; it is ex-

pected to also be true once integrated passives migrate into the main boards.Although surface-mount discretes are available in a greater range of values and

tolerances, the advantages of integration often outweigh any compromises a design-er may make in forgoing the convenience of an extensive discrete product catalog.Moreover, when a suitable design library with high-frequency models is available,



ISBN: 0-471-24431-7



the device design cycle becomes fast and reliable, leading to efficient solutions for avariety of analog applications within the component values and tolerances availablefrom the integrated passive technology. When devices are designed in this way, it is

often found to be possible to avoid the use of expensive, tightly toleranced compo-nents in order to meet the performance specification. From a manufacturing per-spective, the simplification of the circuit assembly and reduced conversion costsmay also favor the use of smaller numbers of integrated devices rather than the cor-responding discretes. These devices can be custom sized and, therefore, have the

potential to replace groups of discretes that have been arranged in series or parallelto achieve a specific component value, or to provide multiple terminations or filters.

To date, integrated passives have found commercial application in the form of surface-mounted modules or devices containing multiple passives of the same kind

(integrated passive arrays) or of different kinds (integrated passive networks) thatare installed as a unit on the surface of the primary interconnect board. However,very few main boards manufactured today utilize integrated passives, which reflectsan early stage in the progression of a technology seeking to enter a well-establishedindustry. It is hoped that, ultimately, increasing numbers of potential board-levelapplications will be realized by matching them to some of the R, C, and L compo-nent technologies described earlier in this book.

A survey of the integrated passive literature shows that most papers in the jour-nal and proceedings literature are concerned with materials and processing and uti-

lize multicomponent devices only for the purpose of demonstrating the fabricationtechnologies. Although demonstration circuits may be complex, the commercial-ized components, with a few exceptions, usually involve simple RC filters, termina-tors, or voltage dividers. This chapter is divided into two parts, starting with anoverview of some of the devices that have been demonstrated in the literature andconcluding with a description of some of the types of devices and technologies cur-rently available from vendors.

12.1 DEMONSTRATION DEVICES FABRICATED WITH

INTEGRATED PASSIVES

12.1.1 RC Terminators

Signal line terminators are used in large numbers on high-speed digital and analogcircuit boards. For instance, a 32-wide parallel port may require 32 terminators,each consisting of a resistor and a capacitor in a small area of the board. RC termi-nators are, therefore, very attractive candidates for passive integration. In a circuit,if the rise/fall time of the signal is faster than twice the time of flight along the

transmission line, then reflections and other signal distortions can occur that mayresult in errant switching. A termination resistor with a value matching the line, typ-ically 50 , will decrease or totally prevent these reflections [1]. AC terminationconsists of a capacitor in series with the termination resistor to form the configura-tion shown in Figure 12.1. The advantage of this over simple resistive termination(DC termination) is that there is no loss of direct current to ground.

294 OTHER APPLICATIONS AND INTEGRATION TECHNOLOGIES



The value and tolerance of the passives are not critical but must meet some gen-eral criteria. Effective termination is assured if their time constant is much larger than time of flight down the transmission line [2]:

C T RT > 25 t f

whereC T = terminating capacitance, F RT = terminating resistance, t f = time of signal flight down the transmission line, sec

Increasing the capacitor value increases the undesired power dissipation, where-as decreasing it can lower the RC time constant and make the termination less ef-fective. 50 pF and 50 are commonly used, for an RC of 2.5 ns, which is the timeof flight through about 15 inches of interconnect line.

Integrated 100 pF plus 50 RC terminators have been fabricated using only twodeposited metals: Ta and Cu [3, 4]. The Ta may be used as the capacitor bottom

plates, the resistor, and as the source of Ta2O5 dielectric for the capacitor. Cu isused as the top plates for the capacitors, and also serves as the contacts. Utilizingone material for multiple purposes reduces the required number of masking steps toonly two. Forty of these terminators are shown in Figure 12.2 along with a schemat-ic of the layout and circuit. In order to form a 100 pF capacitor in series with a 50 resistor, two 200 pF capacitors were fabricated at either end of the structure so thattheir top plates can serve as terminal pads. These terminators were fabricated with

dimensions of 34 by 18 mils, placing them inside the footprint of an 0402.In order to achieve the required capacitor value in this area, a capacitance den-

sity of 140 nF/cm2 was required, which was produced by a film of tantalum oxide1520 Å thick. The 50 resistor was made from an extension of the sputtered Tametal that makes up the bottom plates of the capacitors, which serves to connectthe two bottom plates to put the capacitors in series. A large range of sheet resis-

12.1 DEMONSTRATION DEVICES FABRICATED WITH INTEGRATED PASSIVES 295

Figure 12.1 Resistor and capacitor termination of a transmission line to prevent signal re-

flection.



tance may be exhibited from sputtered Ta thin films depending on the crystalstructure. The common phase of Ta in bulk form is bcc, with a resistivity of 13-cm, but thin-film bcc Ta has a resistivity as high as 65 -cm. Thin-film Tacan also be found in a beta phase that is tetragonal in structure with a resistivityof 180 -cm. This phase is not stable in bulk form but is commonly found asthe product of sputtering [5, 6]. In order to achieve 50 at a sheet resistance of

0.83 /square, 60 squares were required. At 180 -cm, this would require a Tafilm 2.16 m thick. To produce a Ta2O5 dielectric layer 1520 Å thick, 610 Å of Ta metal is consumed. The bottom plate of the capacitor therefore ended up being21,600 – 610 = 20,990 Å = 2.10 m thick. Glass or other highly insulating sub-strates are preferred for this application over silicon because of the possibility of capacitive coupling to the conductive Si. The cross section of this structure isshown in Figure 12.3.


Figure 12.2 Forty integrated RC terminators in a 20 mm2 area.

Figure 12.3 Cross section of an integrated RC terminator.



The magnitude of impedance versus frequency is shown in Figure 12.4. The de-

vice exhibits series R/C behavior as desired.Figure 12.5 shows two RC terminators fabricated by Integral Wave Technolo-

gies for NASA’s Langley Research Center with the same resistor material but twodifferent capacitor dielectrics. The high-k material allows for a smaller footprint,

but probably at higher cost since low-k interlevel dielectrics are usually already present in the board.

12.1.2 Voltage Dividers

Integrated voltage dividers can be made in compact footprints by using combina-tions of the same resistor material in series and in parallel. Figure 12.6 shows some


Figure 12.4 Impedance analyzer scan of an integrated RC terminator.

Figure 12.5 Integrated RC terminators with low- and high-k dielectric capacitors.



low-ratio dividers that consist of two CrSi resistors with a tap in between them. Fig-ure 12.7 shows a 10/1 divider and a portion of a nearby 100/1 divider that can beseen at the right. V in would be across the top and bottom pads and V out would befrom the middle and bottom pads. The division ratio for this sort of layout is

=

where N p = number of resistors in parallel N s = number of resistors in series

The ohms/square of the resistor material is irrelevant, but it must be the same for all parts of the divider to deliver accurate division ratios. Of course, for a givengeometry, higher resistivities will result in less current draw over the V in terminals.

12.1.3 Reliability Test Structures

Thin-film dielectrics are capable of much higher specific capacitances than thick films but will be more prone to mechanical damage. The highest-valued thick-filmmaterials in use today consist of ferroelectric particles, such as barium titanate, dis-

persed in a polymer matrix and applied to a minimum of a little less than a milthick. These can provide maximum values of around 30 nF/cm2, which is enough toreplace only the smallest capacitors on a typical board and provide some decou-

pling. Thin-film paraelectrics can deliver about an order of magnitude more capaci-tance, but are typically less than a micron thick and are composed of various metaloxides, which are relatively brittle. Because they are thinner and more brittle than

1

1 + N p N s

V out

V in


Figure 12.6 Low-ratio voltage dividers.



polymers, there is a potential problem with the yield and reliability of these struc-tures during board fabrication and use. A 100 nF capacitor made from anodized

Ta2O5, sputtered Al2O3, or PECVD Si oxide or nitride might require around a cm2

of area but would only be 1000 Å thick, an aspect ratio of 100,000. Something thisthin would have no appreciable strength compared to the forces of board lamina-tion, flexure, and CTE mismatch so it is not certain that these materials could beused in laminated polymer boards or even as build-up structures on more forgivingsubstrates such a glass or Si.

Figure 12.8 shows a schematic of a test structure for evaluating the reliability of stacked thin-film capacitors and resistors built up over a Si substrate. The bottomlayer consists of alternating 0.25 × 0.25 cm capacitors made from 2000 Å of Ta2O5

and 4 m BCB along with sputtered CrSi resistors. The second layer provides thesame types of structures positioned to overlap the bottom layer devices in variouscombinations, and the top layer consists of Cu pads for placing an underfilled flipchip over these. This project was commissioned by Erik Brandon of NASA’s JetPropulsion Laboratory; the structure was designed by Richard Ulrich and fabricated

by Matt Leftwich of Integral Wave Technologies. The finished product is shown inFigure 12.9, magnified to emphasize the overlap of the various capacitors, resistors,and the chip. The structure will be subjected to temperature shock (85/85), high-temperature storage, and other standard reliability tests in order to evaluate the via-

bility of stacked large area, thin-film devices.

12.1.4 Filters and RF Devices

Filters are by far the most widely used demonstration vehicle for integrated passivetechnologies in the literature and many examples are available for those wishing to


Figure 12.7 A 10/1 integrated voltage divider.




Figure 12.8 Schematic of a three-layer reliability test structure.

Figure 12.9 The fabricated test structure before the flip chip was mounted.



implement them. [7–13]. Filters and signal conditioners, as discussed later in thischapter, make up a large fraction of commercial integrated passive network sales,which are in the form of surface-mounted modules. Figure 12.10 shows a typical ex-

ample—a low-pass filter designed by one of the editors of this book (Ulrich) andmade by Integral Wave Technologies for NASA’s Langley Research Center, demon-strating the advantage of being able to fabricate components with exact values.

A thin-film technology with integrated passive components can be used in manyapplications. For most RF applications, narrowband bandpass filters (BPF) areneeded. The following examples show bandpass filters operating in three differentfrequency bands: 2.45 GHz (ISM band), 15 GHz (Ku band), and 30 GHz (Ka band).Most of the filters are based on a two-coupled resonator topology, such as that inFigures 12.11 and 12.12. For the 30 GHz filter, a topology based on coupled trans-

mission line sections is also discussed. The filters described below also provide in-sight into the different design approaches/constraints applicable for the differentfrequency bands.


Figure 12.10 Low-pass integrated filter.



The MCM-D technology used for the fabrication of the following devices has been described in Section 10.4.3. More information on the technology may befound in the references [14, 15].

12.1.4.1 Bandpass Filters. As illustrated in Chapter 10, the realization of low-loss filters requires the availability of high-quality (Q-factor) passive compo-nents, especially high-quality inductors, as these are quite often the performance-limiting devices. In the following examples, some typical bandpass filters (BPFs)are designed and implemented at various frequencies. [16, 17].

A schematic of a 2.45 GHz BPF is shown in Figure 12.11 and the fabricated de-

vice in Figure 12.12. The circuit is based on the two-coupled resonator topologyconsisting of two parallel resonator circuits (L1, C1 and L2, C2) that are capacitive-ly coupled by capacitor C3.

This bandpass filter makes use of two 3.9 nH spiral inductors that have a maxi-mum Q-value of 74 at 6 GHz; at the filter design frequency of 2.45 GHz, the Q-value is about 45. The high Q-values of the spiral inductors make it possible toachieve narrowband, low insertion loss filters. The measurements of the perfor-mance of such a filter are shown in Figure 12.13. For a bandwidth of 100 MHz, at acenter frequency of 2.45 GHz, an insertion loss below –2.5 dB was obtained. The

return loss at both ports is better than –20 dB. The performance of this filter may be


Figure 12.11 Schematic representation of the two-coupled resonator bandpass filter topol-ogy. (Courtesy of IMEC.)

Figure 12.12 2.45 GHz bandpass filter, based on the two-coupled resonator topology.(Courtesy of IMEC.)



further improved by increasing the thickness of the Cu used to form the spiral in-ductors.

15 GHz and 30 GHz band pass filters, based on the two-coupled resonator topol-ogy, are shown in Figure 12.14. For both implementations, the inductances L1 andL2, like those in Figure 12.11, are formed by the shunt-shorted transmission lines,whereas the capacitances to ground (C1 and C2) are realized by a combination of

BCB capacitors and the parasitic capacitances of the T junctions. For the 30 GHzfilter, only the parasitic capacitance of the T junction is used to resonate with theshunt stubs. The measured and simulated performance of the filters are shown inFigure 12.15. Very good agreement is observed over a wide frequency band and alow insertion loss of –1.75 ± 0.25 dB was obtained over the 14.3–16.3 GHz band,whereas –2.3 ± 0.2 dB was obtained over the 29.6–33.1 GHz band.


Figure 12.13 Measured insertion loss [S21 (top)] and return loss [S11(bottom)] of the 2.45GHz filter. For a 100 MHz at 2.45 GHz, the insertion loss is better than –2.5 dB. (Courtesy of IMEC.)

d B f r o m S

2

1



Other topologies may also be used for the realization of bandpass filters. For ex-ample, the 30 GHz filter shown in Figure 12.16 is based on multiple coupled trans-mission line sections using interdigitated capacitors, which are very well suited for the implementation of small capacitance values. Moreover, their values are very in-

sensitive to BCB thickness variations, in contrast to parallel plate capacitors, inwhich the capacitance is a strong function of dielectric thickness. In an interdigitat-ed capacitor, the capacitance value is mainly determined by the lateral dimensions,especially the gap between the fingers, which may be very accurately controlled bythe Cu electroplating process. For narrow gaps, the thickness of the Cu also be-comes important; however, this factor may be very accurately defined. This filter has a measured insertion loss of –3 dB over the 28.6–30.6 GHz frequency band, anda return loss better than –15 dB, both at input and output.

12.1.4.2 Broadband Couplers. The versatility of the technology is further il-lustrated by a high-performance broadband coupler, such as that shown in Figure12.17. Over a band of 700 MHz centered at 1 GHz, an insertion loss better than –3dB was achieved together with a phase error smaller than 3 degrees and aninput/output return loss below –14 dB.


Figure 12.14 A 15 GHz (a) and a 30 GHz (b) bandpass filter. The location of the compo-nents from the schematic, depicted in Figure 12.11, are also indicated. (Courtesy of IMEC.)

(b)

(a)



This broadband performance was achieved due to the successful use of coupledspiral inductors. Other examples of integrated couplers at 14 GHz and 30 GHz can

be found in the literature [18–20].

12.1.5 Functional Modules and Subsystems

It is clear from a preliminary analysis of the requirements of RF and wireless appli-cations that integrated passive technology can have a significant impact on the im-

plementation of more complex wireless systems. The combination of the large pas-sive-to-active ratios and large overall numbers of passive circuit elements, asoutlined in Chapter 1, combined with the lower ranges of component values, make


Figure 12.15 Measured return loss (— —) and insertion loss (— —), together with sim-ulated return loss (— —) and insertion loss (— —), of the 15 GHz (a) and 30 GHz (b)

bandpass filter. (Courtesy of IMEC.)

(b)

(a)



wireless applications an appealing market for many integrated passives technolo-gies. The fact that most of these applications are under severe size and weight con-straints also helps to drive the systems manufacturers to seek ever better ways to in-clude greater functionality in a smaller volume. This combination of factors

resulted in many of the early demonstrations of passive integration being focusedon the fabrication of wireless functional modules and subsystems.

12.1.5.1 Bluetooth™ Wireless Systems Implementations. Many manu-facturers and researchers have turned to the emerging Bluetooth market for their first demonstrations of the capabilities of integrated passives. Teams from a number of research centers and industry have published accounts of the fabrication of Blue-


Figure 12.17 1 GHz broadband (0.7 GHz) 90 degree combiner (3 × 2 mm2). (Courtesy of IMEC.)

Figure 12.16 A 30 GHz (Ka band) bandpass filter realized using multiple capacitively coupled transmission lines. Interdigital capacitors are used to realize the coupling. (Courtesy of IMEC.)

Interdigital capacitors



tooth modules using integrated passives technology. Examples include both low-temperature cofired ceramic (LTCC) and thin-film build-up structures.

The LTCC approach has been taken by a number of groups [22, 23] and is a log-ical extension of the technology used by Ericsson to demonstrate the first commer-

cially available Bluetooth module [24]. The LTCC substrate includes a number of integrated passive components, which make up sections of the Bluetooth circuitsuch as the balun, output matching circuit, and filters. The active components, suchas the transceiver chips, are mounted onto the LTCC. In many cases, additional pas-sive devices, which for reasons of tight tolerance or large value could not be em-

bedded within the LTCC layers, are mounted onto the LTCC substrate in order tocomplete the circuit. The PRC group at Georgia Institute of Technology alsodemonstrated that a 3-D loop antenna could be added to the module. Companiessuch as National Semiconductor Corp. and Murata Manufacturing Co. Ltd., have

since commercialized Bluetooth modules based on LTCC technology, and a brief description is included in the section on commercialized products.

A different approach was taken by Intarsia Corporation which, in collaborationwith Ericsson Mobile Communications (now Ericsson Mobile Platforms), demon-strated a thin-film build-up version of a Bluetooth module. The module incorporat-ed a Bluetooth single chip transceiver and wire-bonded active components for theVCO circuit, all mounted onto an integrated passive substrate. The integrated pas-sive substrate was used to implement a receive matching balun for the on-chipLNA, a transmit matching balun for the on-chip PA, a resonant tank circuit for the

2.4GHz VCO, and a VCO loop filter. A wire-bonded version of the module, at-tached to a board for initial testing, is shown in Figure 12.18 [24]. This module,when tested for the first time, showed oscillation in the Bluetooth band and wasmeasured with an output power that was close to specification, the slight shortfall

being attributed to the initial design having been performed without accurate S -pa-rameter measurements of the output flip chip.


Figure 12.18 Prototype thin-film-on-glass integrated passive Bluetooth module. (Courtesyof Intarsia Corp. and Ericsson Mobile Platforms.)



In a later iteration, the RF filter and Tx/Rx switch were also added and the mod-ule was configured to be attached to the board using a solder ball or direct moduleattach (DMA) approach, further reducing the final module size. The DMA technol-

ogy is analogous to direct chip attach, in which the device is mounted directly ontothe circuit board by means of solder balls. In this case, the device itself forms the

package, thus eliminating the additional costs and area of an extra level of packag-ing [25, 26]. The DMA version of the Bluetooth module is shown in Figure 12.19.

Other demonstrations of integrated passive functional modules have been made bya number of organizations, using both LTCC and thin-film build-up technologies.One of the research groups active in this field is IMEC, based in Leuven, Belgium.They use passive components as a means to codesign active circuits together withthin-film passives in order to achieve more optimal (performance, cost, etc.) mi-

crowave integrated modules. Their technology is discussed in Chapter 10 and has been used to demonstrate numerous filter functions, as described earlier in this chap-ter. IMEC has demonstrated not only these simple filters but also more complex func-tional blocks, including a DECT VCO and a 5.2GHz wireless LAN LNA. [27, 28].

12.1.5.2 WLAN Receiver Function. Figure 12.20 shows a low-noise amplifi-er (LNA) section for a 5.2 GHz wireless LAN. All passive components for match-ing and biasing are integrated into the MCM-D substrate. Bandpass filters are alsoincluded before and after the amplifier stage, for use in a superheterodyne architec-

ture, making 23 integrated passives in total.The active device is a commercial GaAs pHEMT, flip-chip mounted on theMCM using gold stud bumps. The LNA was optimized for high gain performance:

NF below 2.4 dB, gain of 12.9 dB, –1 dB compression point of –5 dBm at the input,and power consumption = 28 mW (14mA @ 2V).


Figure 12.19 Direct module attach version of the integrated passive Bluetooth module.(Courtesy of Intarsia Corp. and Ericsson Mobile Platforms.)



Measurements of the module, including the bandpass filters, are also shown inFigure 12.20. The noise figure for the combined circuit now becomes 5.4 dB, withgain of 6.8 dB, input matching less than –9 dB, and output matching less than –15dB. This performance is better than that which can be achieved with similar inte-grated solutions in silicon, including integrated bandpass filters.

One can go a step further by codesigning the passive components of a function


Figure 12.20 (a) Photograph and (b) simulated and measured performance of a 5.2 GHzwireless LAN LNA with integrated bandpass filters, realized in thin-film MCM-D. The mod-ule measures 7.0 × 5.1 mm2. (Courtesy of IMEC.)

(b)

(a)

Frequency (GHz)



together with the active silicon chip. A trade-off between on-chip passives andhigh-Q passives on the embedded passive substrate can be easily made. Since thedesign of the whole module is done in the same design environment, with perfor-

mance and cost optimization based on area, it can be done in a straightforward way.The result of such an optimization cycle is illustrated by the WLAN receiver func-tion developed at IMEC and depicted in Figure 12.21. Filters, bias and matchingnetworks, and the required high-Q inductors of the VCO tank are built on the thin-film passives substrate, whereas the active BiCMOS die, which is flip-chip mount-ed, contains the LNA, the VCO, and the downconvertor mixer functions [29].

12.1.5.3 Ku Band Subharmonic QPSK Modulator. The integration of thin-film passive components becomes even more attractive at microwave frequen-

cies and the availability of a microwave model library [30] associated with thistechnology allows a MMIC (monolithic microwave integrated circuit) style designfor more complex microwave circuits up to mm-wave frequencies. These powerfulcapabilities are illustrated by the design of the subharmonic QPSK modulator,shown in Figure 12.22 [31].

This I/Q linear vector modulator has been developed for VSAT (very small aper-ture terminals) applications with an RF output frequency of 14–14.5 GHz. A sub-harmonic configuration has been used, which means that the I and Q baseband sig-nals are mixed with the second harmonic of the LO frequency (LO = 7–7.25 GHz).

The design band of the modulator was taken in the range 13.6–14.9 GHz.The architecture of the QPSK modulator and subharmonic mixer is shown inFigure 12.23. A 3 dB power splitter (Wilkinson power divider) delivers the LO in-

put power to two identical subharmonic mixers (BPSK modulators), which multi-


Figure 12.21 Receiver section of a WLAN front-end consisting of a 0.8 m BiCMOS chip(LNA, mixer, VCO) with a size of 2 × 1.7 mm2, mounted on a thin-film passives substratewith high-Q passive functions (inductor for the VCO’s LC tank, bandpass filters, and match-ing and bias networks). (Courtesy of IMEC.)




Figure 12.22 17 mm by 7 mm, 14 GHz subharmonic QPSK modulator. (Courtesy of IMEC.)

(b)

(a)

Figure 12.23 (a) Top-level architecture of a subharmonic linear vector modulator. (b) Sub-harmonic mixer architecture. (Courtesy of IMEC.)



ply the I and Q of the IF input signal with the second harmonic of the LO signal.The resulting RF signal is combined at the output with a 90° phase shift betweenthe two branches. For the latter, a quadrature Lange coupler has been selected due

to its good isolation, amplitude, and phase balance. Moreover, the structure is not prone to BCB-thickness variations as compared to other quadrature coupler real-izations [19]. Each subharmonic mixer consists of a beam-lead antiparallel diode

pair (HSCH–9251) and four filters: LO filter, RF filter, IF filter, and LO block fil-ter.

The resulting chip, shown in Figure 12.22, contains more than 160 standard pas-sive library components such as transmission lines, resistors, capacitors, inductors,and discontinuities. The measured characteristics are summarized in Table 12.1, to-gether with the initial specifications put forward in the design phase. From this

table, it can be concluded that all the important specifications are met, in a frequen-cy band that is wider than specified. Only the return loss at the LO port was slightlyabove the specification, due to some BCB thickness variation, however, this para-meter is only of minor importance for the specific design.

It should be noted that these results were obtained from a first design and fabri-cation cycle and it is clear that there is tremendous potential for realizing high-

performance, ultrasmall subsystems and modules by means of these technologies,together with their associated component design libraries. Although most of thesemore complex implementations remain in the realm of the demonstrator module,

many less complex integrated passive functions have made the leap from demon-


Table 12.1 List of the QPSK modulator specifications versus measured characteristics

Specification atParameter 7–7.25 GHz Measured Result

Vector phase error < 2° < 2° over 6.7–7.6 GHz OK Vector magnitude error < 0.2 dB < 0.2 dB over 6.7–7.6 GHz OK Image rejection > 25 dB > 25 dB over 6.7–7.6 GHz OK

> 32 dB in the VSAT bandOutput level –10 dBm –10 dBm OK Harmonics 40 dB 34 dBa at max output power OK (1)

Carrier rejection (2 LO) 25 dB 43 dB OK Modulation bandwidth 8 Mbps > 100 Mbpsb OK (2)

RF return loss 18 dB 18 dB OK LO return loss 15 dB 13 dBc (OK)(3)

Conversion flatness 0.2 dB 0.2 for BPSK, 0.25 QPSK OK Input power variation ± 1.5 dB image > 25 dB image > 25 dB OK Output level variation < 3 dBpp 1 dB OK

Source: Courtesy of IMEC.aThe harmonic specification can be met by slightly lowering the output power. This specification is notheavily related to design, but more to the specified diodes.bThe 3 dB bandwidth of the QPSK output power is 2.4 GHz.c20 dB was simulated in the original design. This dropped, in simulation, to 14 dB due to the increasedBCB thickness on the specific run.





blessing for designers who are aiming for small form factor and for manufacturerswho want to produce more powerful systems without expanding their operation.The word “continuum” is applicable here since surface-mounted devices are avail-

able with almost any number and configuration of integrated passives and, with ac-tive devices thrown in, can be almost complete systems unto themselves.

Since the majority of the cost for installed discrete passives is from conversion,the savings from even simple arraying can be significant. A four-unit capacitor or resistor array requires one-fourth the conversion cost of four individual devices.The conversion cost for arrays with internal connections is about the same as if theywere all terminated to the outside, but is still lower than mounting the componentsindividually, and there are fewer solder joints to fail.

Many resistor and capacitor arrays are made the same way as individual units,

with fired oxide resistors and electrolytically processed Ta and Al or ferroelectricdielectrics. However, capacitor arrays that are optimized for low inductance mayhave unique internal structures that guide the current in such a way as to cancel outinternal inductance. On the higher end, integrated passive devices (IPDs) and func-tional modules are commonly fabricated on Si substrates using either sputteredTiNx or CrSi resistors along with SiOx or SiNx capacitors. The advantages of fabri-cating on Si include:

The manufacturing infrastructure is in place since it uses, essentially, 30-year-old technology and geometries. In most cases, cast-off front end equipmentwill suffice.

The substrates are plentiful. If there are no diodes or transistors, then the puri-ty and doping of the substrate may be unimportant, particularly if a field ox-ide is grown first. Glass panels may also be used, especially if the substrateneeds to be fully insulating.

Si is very smooth so the passive component yields are high and tolerance isnot degraded. It can withstand high-temperature processing.

The tolerances of thin-film processes are usually much better than for thick

film. Schottky, zener, and varactor diodes can be added to the systems for rectifica-

tion, filtering, and ESD protection.

The ability to add transistors creates the possibility of the devices being self-contained functional modules.

If Si is used as the substrate for integrated passives, it should be remembered that it isa conductive material so there exists the potential for capacitive coupling betweencomponents and also for interference with magnetic fields of integrated inductors,

which can lower their performance. Using glass substrates avoids these problems.

12.2.1 Capacitor Arrays

Arrays of two and four capacitors per package with the same or different values arewidely available and in common use in packages as small as 0402. Each individual






Figure 12.25. It consists of an interdigitated capacitor in which the electrodes aremade of resistive RuO2 and function simultaneously as a distributed resistor at the100 level. This oxide is used because it has a combination of high conductivity

and stability and a proven track record in ceramic substrates. The dielectric is composed of a glass-loaded ceramic material, so the mechanical and thermal propertiesof the resistor and capacitor elements are well matched, leading to good reliability.[33, 34] This has the advantage of small size and parallel integration, but may takesome design iteration to get the resistance right since current is not the samethrough all parts of the electrodes. The actual performance is close to ideal RC se-ries behavior, but the resistive floor falls off slightly, 3–5% per decade, due to thedistributed nature of the resistors. This is predictable and can be modeled.

12.2.3 Intarsia

Perhaps the most far-reaching production technology for integrated passive net-works came from Intarsia, during the period between their establishment as a jointeffort between Dow Chemical and Flextronics in 1997 and their closing in 2001. In-tarsia manufactured a variety of filters, terminators, amplifiers, and other integrated

passive modules on 350 × 400 mm glass panels using Al and Cu interconnects and photo-BCB insulator. The resistors were reactively sputtered TaNx, deposited togive either 10 or 100 /square films, depending upon the application. Three differ-

ent capacitor materials were used in the technology. The larger-value capacitorswere formed from anodized Al, about 1500 Å thick, to give a capacitance density of 50 nF/cm2. A Si3 N4 film technology was also added, giving a capacitance density of 10 nF/ cm2, which enabled tighter tolerance capacitors to be added at the lower ca-

pacitor values. It was also possible to utilize the BCB already present as the dielec-tric to form small-value capacitors at 0.5 nF /cm2. The inductors were thin-filmmetal spirals with inductances in the range of 1–100 nH and typical line widths andspaces of around 30 m and 10 m [35, 36].

In addition to this basic technology, Intarsia also developed and implemented a

design kit, named PassPort™

[37]. Recognized by Electronic Products magazine,which awarded it its 25th Annual Product of the Year Award, the PassPort™ design


Figure 12.25 Integrated RC terminator employing resistive capacitor plates.



palette enabled Intarsia to quickly design, simulate and layout single- and multifunc-tion modules that integrated numerous individual passive and semiconductor devicesinto a single thin-film-on-glass microcircuit. Such design tools are a key factor in in-

suring design success with integrated passive components and a similar approachwas followed by other integrated passive groups, notably IMEC [30, 39]. Althoughused by some of the thin film build-up technology manufacturers, the concept of anavailable design kit appears to be less prevalent among the LTCC manufacturers,most of whose design activities are still retained in-house due to the complexity of designing embedded passives in the LTCC substrate. Although multiple layers areavailable to build complex microwave components, full 3-D simulations are usuallyneeded in order to take into account all the coupling effects in these layers. Thismakes it much more difficult to develop a library-kit-based design style.

Although Intarsia demonstrated many different levels of integration, from thecomplex Bluetooth and similar modules discussed earlier in this chapter to simplefilter devices [39], the main thrust of the product strategy was to incorporate the in-tegrated passive components into functional blocks. These blocks would replace

predetermined sections of the RF circuitry, such as low-noise amplifiers or power amplifiers, primarily in telecommunications applications. To this end, Intarsia de-veloped a range of LNA and PA products using not only its own Direct Module At-tach packaging technology but also the more conventional SOIC and PLCC plastic

packages. Clearly, further integration would allow the incorporation of additional

functions such as the Tx/Rx switching filters and matching networks and, ultimate-ly, integration of the complete transceiver. A picture of some of the Intarsia inte-grated passive networks and a DMA version of the LNA are shown in Figure 12.26.

The initial products were aimed at a range of wireless applications, from broadband wireless access to WLAN, point-to point radio, and cellular. For example, theLNA-015-01-S08, a low-noise amplifier with a low noise figure of 0.65dB mini-mum, operated in the range 1.5–2.7GHz and satisfied requirements for cellular base

12.2 COMMERCIALIZED THIN-FILM BUILD-UP INTEGRATED PASSIVES 317

Figure 12.26 Three integrated passive devices including a Direct Module Attach (DMA)version of the low-noise amplifier. (Courtesy of Intarsia Corp.)



station, Bluetooth wireless systems, broadband wireless access, and MMDS appli-cations. Other products in the initial offering covered the frequency range from 800MHz to 6 GHz.

The products were packaged using conventional SOIC overmolded packages asshown in the diagram in Figure 12.27, and thus were compatible with standard

board-assembly techniques.Intarsia also developed a range of power amplifiers incorporating matching net-

works, which were packaged into molded leadless chip carriers as shown in theschematic cross section in Figure 12.28. An example of one of the products is the1.75–1.91GHz three-stage amplifier, designed for U.S. and Korean PCS bands. The

performance characteristics of this particular power amplifier are shown in Table12.2.

Unfortunately, Intarsia Corporation ceased operation in June 2001 and so these particular products are no longer available. It is clear, however, that they played animportant role in raising the awareness of the capabilities of an integrated passiveapproach to wireless solutions.

12.2.4 SyChip

Founded as a spin-off of Lucent (Bell Laboratories) in 2000, SyChip focuses on thedesign and marketing of modules for wireless applications, based on the Micro Sys-

tem Integration Technology developed at Bell Labs during the 1980s and 1990s.[40] The technology uses a low-loss silicon substrate for fabrication of a high-Q

passive component structure, with Al metallization and polyimide for the interlayer dielectric. Two metal layers are used, one to form the component contacts and theupper capacitor plates, the other to form the contact pads. Inductors are patterned asspirals in the Al layer and Q-values as high as 50 to 80 can be obtained. TaSi film isused as the resistor layer, which also forms the bottom contact of the capacitor


Figure 12.27 Cross-sectional representation of Intarsia low noise amplifier module. (Cour-tesy of Intarsia Corp.)





small form factor. Although SyChip’s current product offerings do not include inte-grated passive components, the capability forms part of a wide portfolio of tech-nologies available for future performance enhancement and size reduction. SyChip

anticipates that the integrated passive technology will be utilized in next-generation product implementations, such as the next version of their WLAN 802.11b module,or in combo modules, which require the integration and isolation of multiple cir-cuits operating at different frequencies.

12.2.5 Telephus

A recent entrant to the thin-film build-up integrated passives community is Tele- phus, a Korean company whose integrated passives business forms part of a larger

silicon fabrication and packaging materials portfolio. Telephus’ technology uses asilicon substrate but, unlike other manufacturers that use silicon to provide diodefunctions or control dopant levels to give a higher resistivity and improved RF per-formance, Telephus uses an ultrathick oxide layer, grown on the wafer surface, toimprove RF characteristics. This oxide layer is used to improve the isolation of the

passive circuitry from the effects of the silicon substrate. The thick oxide is grownusing an electrochemical process to give an oxidized porous silicon surface withfilms of the order of 35 m in thickness. These films do not have the high stressesassociated with conventionally deposited films so greater thicknesses can be

achieved. In addition, the processing time is relatively short.The thin-film passive layers are built up on top of the thick oxide. Copper is usedas the main metallization and for the interconnections, inductors, and capacitor

plates. Three metal layers are used, two of Ti/Cu and one of thick plated Cu for thetop pads, allowing crossovers and, hence, routing to the center of the inductor. Thedielectric is photoimageable BCB. Resistors are fabricated using a thin Ni–Cr layer,whereas the capacitors use a Si3 N4 film [42]. The RF properties of the thick oxidesubstrate mean that products built using this technology can readily operate at fre-quencies above 10 GHz so they can be applied to a wide range of wireless applica-

tions. The current thrust of the product offerings, however, is in the cellphone andWLAN arena, with low-pass filters, baluns, diplexers, and power dividers availablein flip-chip and wire-bond format. Passive arrays and a foundry service are alsoavailable. A typical product is a flip-chip, 900MHz, low-loss, low-pass filter withinsertion loss of 0.35dB and attenuation at two and three times the operating fre-quency of 15dB (min.) and 22dB (min.), respectively. Applications would be in an-tenna switch modules, RF front ends, and other RF/microwave modules.

12.3 OTHER INTEGRATED PASSIVE TECHNOLOGIES

It is fair to say that the companies and technologies mentioned in the preceding sec-tions of this chapter represent only a selection of those involved in the field of inte-grated passives and is by no means an exhaustive list. A brief scan of the recent lit-erature and company publications indicate that many other organizations have an




interest in, or are actively working on, integrated passive technologies, althoughonly a few are, as yet, making these technologies available in the form of products.Although this book has concentrated on the available thin-film build-up technolo-

gies, no review of the commercially available integrated passive devices would becomplete without mention of ceramic-based technologies. It is wise to remember that integrated passives have formed a part of ceramic technology from the days of the early hybrids. Today, both high-temperature cofired ceramic (HTCC) and low-temperature cofired ceramic (LTCC) capabilities include the incorporation of

buried and surface-layer integrated passive devices. A comparison of the technolo-gies can be long and complex as both the ceramic and the thin-film build-up tech-niques have different capabilities and, hence, different advantages. Whereas thethin-film approach allows for tighter control of passive tolerances during fabrica-

tion and finer geometries, the ceramic technology allows multiple buried layers andtight control of surface-layer printed components by means of laser trimming. Ce-ramic modules often include a number of surface-mounted discrete passives for high-tolerance, high-Q-value components, whereas thin-film technologies seek toinclude most of these components within the substrate. Both have successfullydemonstrated functional modules.

In the United States, one of the main proponents of the integrated passive LTCCapproach is National Semiconductor, and an extensive range of information and

product data is available on their website. Kyocera, traditionally associated with the

HTCC package market, has also demonstrated a number of integrated passive ce-ramic technologies in LTCC. Both Murata and National Semiconductor have suc-cessfully used LTCC to fabricate passive substrates for Bluetooth modules, and al-though a large number of the passive devices were incorporated as surface-mounteddiscretes in the earlier versions, the numbers of components integrated into the sub-strate are rising. Murata, announcing the world’s smallest Bluetooth module in May2001, claimed to have embedded the bandpass filter, balun, and other passives with-in the substrate. Their recently announced Blue Module™, shown in Figure 12.29, is

12.3 OTHER INTEGRATED PASSIVE TECHNOLOGIES 321

Figure 12.29 Blue Module™, an ultra-compact HCI module for Bluetooth. (Courtesy Mu-rata Manufacturing Co., Ltd.)



a host-controller interface (HCI) module that incorporates RF circuitry, basebandsignal processing circuitry, flash memory, and other Bluetooth circuit components.The passive components are embedded within the multilayer, LTCC substrate.

National Semiconductor’s Bluetooth module, the LMX9814 wireless personalarea network (WPAN) shown in Figure 12.30, also incorporates multiple features,including USB and UART host-control interfaces together with flash memory, re-ceive/transmit switching, front-end filtering, and localized supply voltage decou-

pling. The adoption of advanced integration allows this to be included in a modulethat measures 10.1 × 14 × 1.9 mm.

In order to advance the ceramic interconnect industry, many of the ceramic man-ufacturers have joined a collaborative effort aimed at bringing together suppliersand manufacturers of ceramic circuits. This collaboration, the Ceramic InterconnectInitiative, a part of IMAPS, is actively participating in the development and intro-duction of new ceramic-based technologies and provides a useful source of infor-mation on ceramic-based passive integration capabilities.

12.4 SUMMARY

The adoption of integrated passive technology is rapidly becoming more wide-spread. Although mainly focused on the telecommunications and computing sec-tors, the number of potential and current applications is considerable and new ap-

proaches and implementations are arising all the time. Within these pages it is

clearly not possible to feature every available technology, demonstration, and prod-uct. It is hoped, however, that the examples chosen will give the reader an apprecia-tion for the types of offerings currently available and provide a foundation fromwhich it will be possible to gain a better understanding of the capabilities and op-

portunities that integrated passives have to offer.


Figure 12.30 National Semiconductor’s LMX9814 WPAN Bluetooth module. (Courtesyof National Semiconductor.)



ACKNOWLEDGMENTS

The authors would like to acknowledge the support of E. Beyne, S. Brebels, Wim

Diels, S. Donnay, P. Pieters, and K. Vaesen from IMEC, and of P. Garrou and J.Plonka (The Dow Chemical Company), C. von Scheele (Ericsson Mobile Plat-forms), Naoko Igarashi (Murata Manufacturing Co., Ltd.), M. Brozda (NationalSemiconductor Corp.), N. Miglani (SyChip, Inc.) and Inho Jeong (Telephus Inc.)who helped make this chapter possible. The authors would also like to acknowledgethe contributions of the former Intarsia team and to thank D. Pedder and J. Youngfor their reviews of the Intarsia material.

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327

CHAPTER 13

THE ECONOMICS OF

EMBEDDED PASSIVES

PETER A. SANDBORN

13.1 INTRODUCTION

In the past, engineers involved in the design of electronic systems did not concern

themselves with the cost-effectiveness of their design decisions; that was someoneelse’s job. Today, the world is different. Every engineer in the design process for an

electronic product is also tasked with understanding the economic trade-offs associ-

ated with their decisions. Nowhere is the need for economic analysis more critical

than when emerging technologies, materials, and processes are involved, for it is

the decisions of if, when, and where to insert new technologies that often separate

the winners from the losers in high-tech products.

Economics encompasses an assessment of the total life cycle cost of a design de-

cision, where the life cycle includes the design, manufacturing, testing, marketing,

sustainment, and end of life of the product. The decision to convert discrete passives

to embedded passives is much more far-reaching than simply reducing the cost of

part procurement and paying more for the board. There are a host of other cost and

benefit issues to be considered that translate into life cycle economics at some level.

In this chapter, we attempt to touch on the economic attributes of a system’s design,

production, and support that impact the decision to use embedded passives.

Embedded passives are fabricated within substrates, and although embedded

passives will never replace all passive components, they provide potential advan-

tages for many applications. The generally expected advantages include:

Increased circuit density through saving substrate area

Decreased product weight

Improved electrical properties through additional termination and filtering

opportunities, and shortening electrical connections

Cost reduction through increasing manufacturing automation



ISBN: 0-471-24431-7



Increased product quality through the elimination of incorrectly attached de-

vices

Improved reliability through the elimination of solder joints

Potentially the biggest single question about embedded passives is their cost—“. . .

of all the inhibitors to achieving an acceptable market for integral substrates, the

demonstration of cost savings is paramount” [1]. There is considerable controversy,

however, as to whether applications fabricated using embedded passives will be

able to compete economically with discrete passive technology. On the bright side,

the use of embedded passives reduces assembly costs, shrinks the required board

size, and negates the cost of purchasing and handling discrete passive components.

However, these economic advantages must be traded off against the higher cost per

unit area of boards fabricated with embedded passives, a situation that will not dis-appear over time, and possible decreases in throughput of the board fabrication

process.

Several different cost estimates for embedded passives have been presented.

These estimates range from embedding resistors in a digital application, resulting in

a 73% savings [2]; embedding inductors and capacitors in a RF application, result-

ing in a 27% savings [2]; the cost per square inch of embedded resistor ranging

from $0.15 to $0.30 on 6 × 6 inch to 24 × 24 inch substrates [3]; and combined 80%

improvement in cost/size figures of merit for MCM-D/embedded passives over a

surface mount on PCB solution for a GPS receiver front end [4]. All these esti-mates, though not necessarily inaccurate, are also obviously application-specific

and of limited use in decision making for an unrelated application. Understanding

the true economic impact of introducing embedded passives cannot be captured in a

single simple number, and trade-off decisions should not be made based on such

simplified metrics.

The application-specific costs depend on many effects when embedded passives

are present in a board:

Decreased board area due to a reduction in the number of discrete passivecomponents

Decreased wiring density requirements due to the integration of resistors and

decoupling capacitors into the board

Increased wiring density requirements due to the decreased size of the board

Increased number of boards fabricated on a panel due to the decreased board

size

Increased board cost per unit area

Decreased board yield Decreased board fabrication throughput

Decreased assembly costs

Increased overall assembly yield

Decreased assembly-level rework

328 THE ECONOMICS OF EMBEDDED PASSIVES



Several other recurring system costs may also be affected by the use of embedded

passives; for example, the need to electromagnetically shield the board may be re-

duced or eliminated when certain passives are embedded, saving on expensive ma-

terials and their assembly, and the costs associated with thermal management of the board may be affected.

Due to the opposing nature of many of the effects listed above, the overall eco-

nomic impact of replacing discrete passives with embedded passives is not trivial to

determine and, in general, yields application-specific guidelines instead of general

rules of thumb. In fact, the very nature of trade-off analysis is one in which the

greater the detail necessary to accurately model a system, the less general and

more application-specific the result.

13.2 MODELING EMBEDDED PASSIVE ECONOMICS

Several authors have addressed cost analysis for embedded passives and thus provide

varying degrees of insight into the economic impact of embedded passives. The tar-

get of all these economic analyses is to determine the effective cost of converting se-

lected discrete passive components to embedded components. The most common ap-

proach to economic analysis of embedded passives consists of three steps:

1. Reduce the system cost by the purchase price and conversion costs associated with the replaced discrete passives, including the costs of handling, storage,

and assembly associated with a discrete component.

2. Reduce the board size by the sum of the layout areas associated with the re-

placed discrete passives and determine the new number of boards on the pan-

el.

3. Determine the new board cost based on a higher per unit area cost for the em-

bedded passive panel fabrication and the new number of boards on a panel

computed in step 2.

The results of these three steps determine the new system cost. The effects in-

cluded in this first-order approach are critical; however, the approach ignores sev-

eral additional elements, most notably: decreased throughput for embedded pas-

sive board fabrication means that board fabricators will have to apply higher profit

margins for embedded passive boards to justify their production on lines that

could otherwise be producing conventional boards; routing analysis of the board

to determine not only what layers may be omitted, but what layers may have to be

added to maintain sufficient wiring capacity as passives are integrated and the

board is allowed to shrink; yield of both discrete passive components and the vari-ation in board yield due to embedding passives; and potential reductions in rework

costs due to both assembly defects and intrinsic functional defects associated with

discrete passives.

Brown [2] presents an outline of all the potential contributions to the life cycle

13.2 MODELING EMBEDDED PASSIVE ECONOMICS 329



cost of embedded passives. Rector [1] provided the economic analysis that ap-

peared in the 1998 NEMI Passive Component Technology roadmap [5], using the

first-order approach outlined above. Rector concluded that embedded passives can

be economically feasible, but only if one considers more than the effects in the first-order model outlined above. Ohmega Technologies Inc. has also generated a cost

model for assessing cost trade-offs associated with its Ohmega-Ply® embedded re-

sistor material, [6]. The Ohmega cost model follows the first-order approach de-

scribed above and includes yield and rework effects. Ohmega concludes that 2–4

embeddable resistors per square inch are required to make the use of the Ohmega-

Ply material economically practical.

Realff and Power developed a technical cost model for board fabrication and as-

sembly [7]. The model includes tests for board assembly, yield, and rework. The fo-

cus of the model is on the equipment requirements. Under the assumption that embedded resistors are fabricated using a dedicated resistor layer, they conclude that

for embedded resistors to have a significant impact on the cost of a system, their use

must allow the removal of equipment or in some other way fundamentally change

the assembly process such as changing from double- to single-sided assembly.

Power et al. [8] extend the model in [7] to embedded capacitors and cast it in the

form of an optimization problem targeted at choosing which discrete passives to in-

tegrate based on an assumption of assembly and substrate-manufacturing process

details, and material properties.

Another analysis that recently appeared, focused on design trade-offs for a GPSfront end [4]. This analysis includes detailed cost modeling of thin-film embedded

resistors and capacitors performed using the Modular Optimization Environment

software tool from ETH [9].

A recent manufacturing cost model from Sandborn et al. [10] incorporates quan-

titative routing estimation and assesses board fabrication throughput impacts for

setting profit margins on board fabrication, effects that have not been included in

previous models. This model is outlined in Figure 13.1.

Qualitatively the model in Figure 13.1 works in the following way:

1. Accumulate the area of the footprints of discrete passives to be embedded.

2. Reduce board area by the accumulated discrete passive area from step 1,

maintaining the aspect ratio of the original board. This step is optional, i.e.,

the board area may be fixed.

3. For plated or printed resistors, determine the area occupied by each plated or

printed embedded resistor on wiring layers. Perform routing analysis, remov-

ing nets and vias associated with resistors that are embedded and accounting

for area blocked by embedded resistors on wiring layers. Routing is assumed

to be unaffected by discrete resistors embedded using Ohmega-Ply® or simi-lar dedicated layer addition approaches. For decoupling capacitors, if distrib-

uted, all nets and vias associated with embedded decoupling capacitors are

removed from the routing problem. For singulated capacitors, assume that

there is approximately no affect on the routing analysis. Using these assump-




tions, determine the relative change in routing resources due to embedding

selected passives.

4. Using the layer requirements, the relative routing requirements for the em-

bedded substrate, and either a fixed measure of the routing efficiency associ-

ated with the conventional board or a range of possible efficiencies deter-

mined under the assumption that the conventional version of the board did

not include any more layer pairs than it needed to route the problem, compute

the number of required layer pairs for the embedded passive implementation.

5. Determine the yield of layer pairs that include embedded passives.6. Determine the trimming cost for embedded resistors. The necessity of trim-

ming is determined by the resistor’s tolerance. The application-specific cost

per trim is determined by modeling the throughput of a laser trimming process.

7. Compute the number of boards per panel from the board size (number-up)

and the effective panel fabrication costs from the layer and material require-

ments, yields, and resistor trimming costs.

8. Determine the relative board fabrication profit margin from layer pair

throughput modeling (see discussion in Section 13.3.3).

9. Accumulate assembly cost, test, rework, and board fabrication costs and in-clude profit margin to obtain total relative cost.

The analysis in Figure 13.1 focuses on differences in system cost between embed-

ded passive and discrete passive solutions, therefore, all cost elements that are ap-

13.2 MODELING EMBEDDED PASSIVE ECONOMICS 331

Figure 13.1 Embedded passive board cost trade-off model [10].

7) BoardFabrication Cost

9) Assembly/Test/

Rework Cost

4) LayerCalculation

4) LayerCalculation

3) Routing

Analysis

3) Routing

Analysis

2) Board Size

Analysis

2) Board Size

Analysis

ComponentDescriptions

8) ThroughputModel

8) ThroughputModel

Total Cost

Application-Specific Wiring

Details

1) ComponentSize Analysis1) ComponentSize Analysis

Board Size

Layer Count

6) TrimmingTime and Cost

6) TrimmingTime and Cost

5) Layer PairYield Analysis5) Layer PairYield Analysis

ConventionalBoard Size and

Shape

Discrete Pass ives

E m b e d d e d P

a s s i v e s



proximately equivalent for the embedded and conventional system are igonored;

e.g., all functional testing of the system and procurrement and assembly costs asso-

ciated with nonembeddable parts.

13.3 KEY ASPECTS OF MODELING EMBEDDED PASSIVE COSTS

In this section, several of the key aspects that are necessary for the assessment of

embedded passive costs are discussed in detail by providing trade-off level analy-

ses. Note that the following focuses on embedded resistors and capacitors; howev-

er, the concepts are generally applicable to inductors as well.

13.3.1 Board Size and Routing Calculations

Board size is critical to the cost analysis because it determines the number of boards

that can be fabricated on a panel (number-up) and is a key input to the determina-

tion of the number of required layers for wiring. As discrete passive components are

converted to embedded passives, the physical size of the board can either remain

fixed or be allowed to decrease by the layout area associated with the discrete pas-

sives given by

Anew = Aconv – N

i=1

(l i + S )(wi + S ) (13.1)

where

Aconv = the conventional board area

S = the minimum assembly spacing

l i and wi = the length and width of the ith discrete passive

N = the total number of discrete passives that are converted to embedded passives

If the board is double-sided, the calculation in Equation 13.1 can be performed independently for each side of the board; the larger of the two sides determines the

new board size.

The area consumed by the embedded passives fabricated directly on internal

wiring layers impacts the trade-off analysis by decreasing the wiring available on

internal layers. Embedded resistors that are fabricated using a dedicated layer pair,

e.g., Omega-Ply® and Gould TCR ™, do not have a first-order effect on the wiring

availability to the application. The area occupied by an embedded resistor on a

board inner layer is given by

0

R

.8

s

R m2 for 0.8 R > R s

A R = (13.2)

0

R

.8

s

R m2 for 0.8 R R s




where

R = the value of the resistor,

R s = the sheet resistivity of the resistor material, /square

m = the minimum feature size for embedded resistor fabrication

Since embedded resistors are designed and fabricated to smaller resistance values

than required and then trimmed, a factor of 0.8 is included in Equation 13.2. The

factor of 0.8 can be derived assuming a symmetric distribution of fabricated resistor

values, where the lowest trimmable resistor is 55% of the application target value,

and a 5% design tolerance on the resistors, and then maximizing the number of re-

sistors between the high-specification limit and the lowest trimmable resistor (see

Figure 13.3 in Section 13.3.4).

There are two types of capacitors that must be considered—decoupling capaci-tors and singulated or nondecoupling capacitors. It is assumed that decoupling ca-

pacitors can be absorbed into dedicated decoupling layer pairs through the use of

planar distributed capacitance layers and the nondecoupling capacitors must be fab-

ricated individually on a dedicated capacitor layer pair if they are to be embedded.

The area occupied by an individual nondecoupling embedded capacitor on a capac-

itor layer pair is

Ac = (13.3)

where

C = the value of the capacitor

c = the capacitance per unit area of the capacitor layer pair.

Assuming square capacitors, the number of embedded capacitor layer pairs for non-

decoupling capacitors required in the board is given by

N integral cap layers = (13.4)

where

N C = the total number of nondecoupling capacitors that are converted from discrete

to individual embedded capacitors

S c = the effective spacing between individual embedded capacitors on the embed-

ded capacitor layer pair

S c is usually set larger than the minimum spacing possible to allow for perforation

of the embedded capacitor layer by vias and through holes, and to allow area for in-

terconnection.

Instead of decreasing the board area as passives are embedded, decreases in the

required board surface area could be used to convert a double-sided board applica-

N c

j =1( A c j + S c)2

Anew

C

c

13.3 KEY ASPECTS OF MODELING EMBEDDED PASSIVE COSTS 333



tion to a single-sided board, as discussed in [1]. This conversion would decrease as-

sembly costs by increasing the throughput and yield of the assembly process.

Whether it is realistic or even economically wise to convert a double-sided board to

a single sided one depends on whether there is an advantage in allowing the board to shrink. A smaller area board only saves money if it results in the ability to fabri-

cate a greater number of boards per panel. It should be noted that there may be oth-

er performance or application-specific benefits to a smaller board size as well.

Besides estimating the physical size of the board after embedding of selected

discrete passive components, we also need to consider the routing requirements.

The following first-order routing assumptions can be made with respect to embed-

ded passives:

The IO (effectively the nets and vias) associated with discrete resistors thatare replaced by embedded resistors that are directly fabricated on existing

board inner layers are effectively removed from the routing problem, i.e., the

embedded resistors are fabricated in series with the nets they are attached to

on the wiring layers; however, the area occupied by the embedded resistors

blocks routing and is accounted for (see Equation 13.6).

Singulated nondecoupling discrete capacitors converted to embedded capaci-

tors and embedded resistors fabricated using dedicated layer pairs have no ef-

fect on the routing problem.

The IO associated with discrete decoupling capacitors converted to embedded capacitors are effectively removed from the routing problem.

With these assumptions and the routing information from the conventional imple-

mentation, the routing requirements, and thereby the number of layers required, for

an implementation that includes embedded passives can be determined. An estima-

tion of the minimum number of layers required to route the application proceeds as

follows:

N layersnew = (13.5)

where

U limit = the maximum fraction of the theoretically available wiring in the board that

can be used for routing

U conv = the fraction of that wiring that is actually used to route the conventional ap-

plication

The ratio of U conv to U limit measures the routing efficiency of the conventional implementation. When the ratio is large (close to unity), the implementation has effec-

tively used all the wiring that is available and any additional wiring would require

the addition of another layer pair or an increase in board area. At some smaller val-

ue, any decrease in wiring would allow the omission of a layer pair.

The wiring blocked (W blocked ) by embedded resistors (the length of wiring that

U conv

U limit

W used new + W blocked

W layer new




cannot be used) is given by

W blocked =

W layer conv (13.6)

where

N R = the number of embedded resistors

Anew is give by Equation 13.1

A R is given by Equation 13.2

The second multiplier is the wiring per layer in the embedded passive board with no

embedded resistors included (W layer new). The total length of wiring used for the newimplementation is given by,

W used new= f (W used conv

) (13.7)

where f is the the fractional change in required total wiring length.

The wiring used in the conventional implementation is found from

W used conv= W availconv

(13.8)

where W availconv is the the total length of wiring theoretically available in the conven-

tional board, which is equal to W layer conv multiplied by the number of layers in the

conventional board minus layers on which wiring is not done, e.g., reference planes.

Assuming that the total wiring length required is proportional to the total number

of system IOs that require routing, a fundamental assumption in routing estimation

approaches that compare requirements and resources, [11], f is found from

f = (13.9)

where

N IOnew= N IOconv – 2 N R – 2 N DC , the total number of system IOs in the new imple-

mentation assuming two IOs per resistor and capacitor, assuming resistors are print-

ed or plated directly onto wiring layers

N R = number of embedded resistors

N DC = number of decoupling capacitors absorbed into a decoupling capacitance lay-

er pairs

N IOconv = total number of system IOs in the conventional implementation

Note that N in Equation (13.1) is N R + N C + N DC , where N C is the number of nonde-

coupling capacitors that are integrated into the board. The number of IOs in the

conventional implementation is given by,

N IOnew

N IOconv

Anew

Aconv

N R

i=1

A Ri

Anew




N IOconv= N netsconv

(fanout + 1) (13.10)

where

fanout = average number of IOs that a net attaches together minus one, assumed to be the same for the conventional and embedded passives implementations

N netsconv= number of nets in the conventional implementation

Since layers occur in pairs in printed circuit board manufacturing, the result given

by Equation 13.5 is rounded up to the nearest multiple of two for use in the model.

Note that the final value of N layersconvgiven by Equation 13.5 will be independent of

W layer conv.

13.3.2 Recurring Cost Analysis

Using the size and routing relationships developed in the last section, we can pre-

dict the board fabrication costs. The price per conventional board is given by

P conv = (1 + M conv) (13.11)

where M = profit margin (see Section 13.3.3)

C layer pair = cost per unit area per layer pair

N upconv = number-up (number of boards that can be fabricated on a panel)

N layersconv = total number of layers (wiring and reference) in the conventional imple-

mentation of the board

The N upconvis computed from the board length and width, panel length and width,

minimum spacing between boards, and the edge scrap allowance, using the model

in [12]. The price per embedded passives board is similar to Equation 13.11, withthe addition of the capacitor layer costs if embedded decoupling or nondecoupling

capacitors are present:

P new = [C layer pair newAreanew N layersnew

+ N bypass cap layersC bypass cap layer

+ N integral cap layersC integral cap layer ] (13.12)

where N layersnew = minimum number of layers required to route the application given by

Equation 13.5

N intregral cap layers = number of embedded capacitor layers given by Equation 13.4

N decoupling cap layers = number of decoupling capacitor layers

(1 + M new)

N upnew

C layer pair Aconv N layersconv

N upconv




The new layer pair cost in Equation 13.12 is given by

C layer pair new

= C layer pair + (C resistor material)( N upnew

)

N R

i=1

Area Ri

+ N RC trim N upnew

+ C print

(13.13)

where the sum in Equation 13.13 is taken over all embedded resistors in the particu-

lar layer pair of interest ( N R), and

C resistor material = cost per unit area of the resistive material printed on the wiring lay-

ers to create embedded resistors

C trim = the average cost of trimming one resistor

C print = the average cost of printing or plating all embedded resistors onto one layer pair

The board price is combined with component-specific assembly, test, and rework

costs to determine the system cost. The average effective cost associated with a sin-

gle instance of a discrete passive is computed as follows:

C discrete = P discrete + C handling + C assembly + C AOI

+ (1 – Y assembly

)(C assembly rework

+ P discrete

+ C handling

) (13.14)

+ (1 – Y functional)(C functional rework + P discrete + C handling)

where

P discrete = purchase price of a discrete passive component

C handling = storage and handling costs associated with a discrete passive component

C assembly = the cost of assembly of a discrete passive component per site

C AOI = cost of inspecting a discrete passive component per site

Y assembly = assembly yield for discrete passive components

Y functional = functional yield of discrete passive componentsC assembly rework = cost of reworking an assembly fault per site

C functional rework = cost of diagnosing and reworking a functional fault

The (1 – Y assembly) term in Equation 13.14 represents the fraction of discrete pas-

sives requiring rework, which includes replacment due to assembly faults, and the

(1 – Y functional) term in Equation 13.14 represents the fraction of discrete passives re-

quiring rework due to functional faults. Equation 13.14 assumes that all assembly

and functional faults associated with discrete passives are diagnosable and rework-

able.The total system cost for relative comparison purposes only is given by

C system = N discrete

i=1

C discretei+ P board (13.15)




where

C discretei = the cost associated with the ith discrete passive component from Equation

13.14

P board = the board price from Equation 13.11 or Equation 13.12 N discrete = number of discrete passive components assembled on the board

Note that the following costs are not included in the formulation because they are

assumed to be the same whether or not the system contains embedded passives: all

functional testing costs are ignored, all costs associated with other nonembeddable

system components are ignored.

13.3.3 Throughput

A fundamental issue that has to be addressed for embedded passives is the through-

put of the process that is used to manufacture the boards. Throughput is a measure

of the number of products that can be produced in a given period of time, and is the

inverse of the interdeparture time, the time elapsed between completed products.

Throughput is key to understanding the profit margin that will be required to justify

manufacturing embedded passive boards. The objective of this portion of the analy-

sis is the computation of application-specific relative profit margin values for con-

ventional and embedded passive versions of a board.

The situation faced by the board manufacturer may be the following. Assumethat there are two types of boards that could be fabricated on a process line. One is a

conventional board with a known profit margin and the other is an embedded pas-

sive board. To simplify the problem, assume that the number of boards to be manu-

factured will be the same for both types of board. The manufacturing cost of the

embedded passive board will be larger. Assuming that the interdeparture time of the

embedded passive process will be longer than that for conventional boards, the

manufacturer must decide what profit margin to use for the embedded passive

board so that the total profit per unit time made by selling embedded passive boards

equals or exceeds what can be made by selling the conventional boards. This is nec-essary to justify the use of a line to fabricate embedded passive boards when it

could otherwise be producing conventional boards.

To explore throughput effects and determine the relative profit margins of the

printed circuit boards, a model has been developed that is similar to cost of owner-

ship models for capital equipment [13]. The model captures the costs due to mainte-

nance (scheduled and unscheduled), yield loss, interdeparture time variations, and

changeovers.

The labor costs associated with scheduled and unscheduled maintenance and

changeovers are given by Equation 13.16:

Scheduled maintenance: Lsm = N smT sm R L (13.16a)

Unscheduled maintenance: Lusm = (T total) R L (13.16b)MTTR

MTBF




Changeovers: Lco = N coT co R L (13.16c)

where

N sm = number of scheduled maintenance activities in a given period of timeT sm = average labor time or “touch time” associated with a scheduled maintenance

activity

N co = number of changeovers in a given period of time

T co = average labor time associated with a change over

R L = labor rate

MTTR = mean labor time to repair for an unscheduled maintenance event

MTBF = mean time between failures requiring unscheduled maintenance

T total = total time in the period of interest

We must now evaluate the throughput impacts of various critical manufacturing

events. Computing throughput loss is basically determining lost opportunity costs;

i.e., how much good product does not get manufactured because the process has

been slowed or stopped, or because defective product is produced instead. We as-

sume that scheduled maintenance does not affect the throughput; i.e., it is per-

formed during periods when the process would not be operational. Therefore, only

the cost of performing the scheduled maintenance is important for our trade-off.

Also, we assume that the scheduled maintenance periods for lines producing con-

ventional and embedded passive boards are of the same length and occur at thesame frequency. Note that if there is no effective off-shift (no time when mainte-

nance can be performed that does not effect the throughput), then N sm is set to zero

and all maintenance is treated as unscheduled maintenance.

The throughput impact of process yield can be computed from the number of

multilayer panels lost in a fixed time period due to process yield losses:

Lostyield = (1 – Y ilp) (13.17)

where

Y ilp = yield of the panel inner layer process

N inner layers = number of panel inner layers produced in a fixed time period

N inner layers per board = number of inner layer pairs in a single board

Unscheduled maintenance, assuming it is performed during time when the process

line would otherwise be producing good product, contributes the following lost time:

Lostusm = (MTTR + 2T c/s) (13.18)

where T c/s is the cool down/startup time associated with the line being stopped for

the unscheduled maintenance activity. Similarly, the changeovers result in lost op-

portunity to produce products:

T total

MTBF

N inner layers

N inner layers per board




Lostco = N co(T co + 2T c/s) (13.19)

Knowing the interdeparture time, the average number of multilayer boards that can

be obtained from the process line during the time period defined by T total is given by

N boards = 1 – – Lostyield N boards per panel

(13.20)

where

T inter = interdeparture time of the inner layer process (time/inner layer pair)

N boards per panel = number-up; i.e., the number of boards that can be fabricated on a

panel

The parameter that needs to be evaluated for comparison purposes is the total profit

in a fixed period of time from fabricating a specific board type. Note that the profit

per board is not a good comparison metric because it does not account for the num-

ber of boards that are produced. The average profit in the time period associated

with the constituent variables is computed from

Average Profit = N boardsV – ( Lsm + Lusm + Lco) (13.21)

where the value of a board, V , is given by

V = (1 + M )C board (13.22)

where

M = profit margin

C board = manufacturing cost per board

The example results shown in Figure 13.2 were generated using the model described

by Equations 13.16–13.22. If interdeparture times of inner layer production for con-

ventional and embedded passive layers and the average profit margin for conven-

tional boards are known, then the minimum required profit margin for embedded pas-

sive board fabrication can be determined. Note that this cost model must be repeated

for each board manufacturing scenario since the number of layers in the multilayer

board and the dimensions of the individual board are application-specific.

The example shown in Figure 13.2 indicates that if conventional boards have a

15.7% profit margin and 15 second interdeparture time per layer pair, then 30 sec-

ond per layer pair embedded passive board production is only feasible for profit

margins of 26% or more. The most important property obtained from this analysis

is the difference between the profit margins; the trade-off analysis results are much

less dependent on the absolute values of the profit margins. We consistently ob-

serve profit margin differences of ~10%. The analyses presented in Section 13.4 as-

Lostusm + Lostco

T total

T total

T inter N inner layers per board




sume profit margins that make the average profit per hour of each type of board fab-

rication equal. Additional throughput and manufacturing modeling impacts such as

manufacturing cycle time and capacity analysis for embedded passive board manu-

facturing appear in [14].

13.3.4 Trimming Embedded Resistors

Laser trimming of film resistors has been performed for many years. For many ap-

plications, depending on design tolerances, embedded resistors will need to be

trimmed. Resistors are trimmed by machining a trough in the resistive element, the

length and path shape of which determine the resistance change obtained (see

Chapter 2).

It is also possible to consider reworking embedded resistors prior to completion

of the board fabrication process, as discussed in Chapter 3. Resistors may be re-

worked to higher values by laser trimming or to lower values by printing conduc-

tive ink on the surface of an embedded resistor, thus adding a lower-value parallel

resistor [15].

A cost of ownership model for a laser trimming process has been developed

by ESI [16]. The ESI model allows the amount of time to trim a layer pair to be


Conventional

Board

Integral

Passives Board

Profit

Margin:

0

200

400

600

800

1000

1200

1400

1600

1800

2000

5 10 15 20 25 30 35 40

Inter-Departure Time (sec/layer pair)

P r o f i t ( $ / h o u r )

30%

26%

20%

30%

20%

15.7%

Conventional

Board

Integral

Passives Board

Profit

Margin:

Conventional

Board

Integral

Passives Board

Profit

Margin:

0

200

400

600

800

1000

1200

1400

1600

1800

2000

5 10 15 20 25 30 35 40

Inter Departure Time (sec/layer pair)

P r o f i t ( $ / h o u r )

30%

26%

20%

30%

20%

15.7%

Conventional

Board

Integral

Passives Board

Profit

Margin:

Figure 13.2 The relationship between profit margin and production interdeparture time for conventional and embedded passive board fabrication.

Interdeparture Time (sec/layer pair)



computed as a function of the number of resistors to be trimmed per layer pair and

the size of the panel, allowing the laser trimming throughput to be calculated. A

version of the ESI model is used in the analysis process shown in Figure 13.1

(Step 6).Unfortunately, trimming and rework equipment is expensive and both processes

potentially represent bottlenecks in the board fabrication process. Therefore, the

question that naturally arises is, under what conditions pertaining to application

properties and resistor fabrication processes is it economically feasible to perform

trimming and possibly rework versus disposal of layer pairs or boards that do not

meet design specifications?

When resistors are fabricated, the resulting values form a distribution as shown

in Figure 13.3. If the resistors are to be trimmed, the fabrication target resistance is

below the application target resistance so that the greatest number of fabricated re-sistors can be trimmed to values in the specified range. The high-specification limit

(HSL) and the low-specification limit (LSL) are determined from the design toler-

ance associated with the resistor. The area under the curve between the HSL and the

LSL represents the yield of the untrimmed resistor. There is a lower limit to the

ability to successfully trim a resistor that is approximately 55% of the application


Resistance Value

F r e q u e n c y

H S L

L S L

A p pl i c a t i onT ar g e t

F a b r i c a t i onT ar g e t

L ow e s t T r i mm a b l eR e s i s t or

Figure 13.3 Distribution of fabricated resistor values.



target. The area between the lower trimming limit and the HSL represents the yield

of trimmed resistors assuming no trimming defects. Resistors in the distribution that

have values below the lower trimming limit or above the HSL would generally be

considered yield loss because they are both unusable and untrimmable. Rework al-lows resistors above the HSL to be recovered and used. In cases where no trimming

is planned, the process would be centered so that the fabrication target and the ap-

plication target are the same.

Figure 13.4 shows the result using the model developed in [17] for three differ-

ent applications. The three regions identified in Figure 13.4 provide the conditions

under which it is most economical to trim, trim and rework, and simply scrap non-

conforming inner layer pairs. This example result assumes no resistor thickness

variation. See [17] for additional assumptions and modeling parameters associated

with this result.

13.3.5 Yield and Test

The discussion in Section 13.3.2 considers the assembly and functional yield of dis-

crete passives, e.g., Equation 13.14. The critical yield parameter not explicitly con-

sidered is the board yield (see Chapter 7). The foregoing discussion effectively as-

sumes that the layer pair cost with embedded passives, C layer pair new, computed in

Equation 13.13 is a yielded cost, i.e., the cost per good layer pair [18]. This quanti-

ty can be interpreted as yielded cost only if we assume that all the defective embed-ded passive layer pairs can be identified and removed from the production process

before they are incorporated into multilayer boards.


0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0.1 1 10 100

Design Tolerance (%)

O n e P r i n t i n g / P l a t i n g S t a

n d a r d

D e v i a t i o n ( m i l s )

N o t r i m m i n g , n o r e w o r

k

( c e n t e r e d p r o c e s s )

Trimming, no rework

Trimming + rework

20%

High density picocellHigh density picocell

Fiber channel cardFiber channel card

Picocell boardPicocell board

2.17 x 2.17 in

60 boards/panel

4410 resistors/panel15.6 embedded res/in2

2.27 x 6.87 in

18 boards/panel

1260 resistors/panel

4.5 embedded res/in2

12 x 18 in

1 boards/panel

610 resistors/panel

2.8 embedded res/in2

Figure 13.4 Application-specific economical regions of trimming and reworking embed-

ded resistors.



If the yield of the embedded passive layer pairs going into board layup and lami-

nation is not 100%, then we assume that some fraction of the defects will be detect-

ed at some later point during the board fabrication, system assembly, or final test.

Obviously, the cost impact of undetected defective embedded passive layer pairs isgreater the later in the process they are discovered. The following simple exercise

demonstrates this. Consider the outgoing cost per assembled board from the final

in-circuit test step that discovers a defect caused by an embedded passive layer pair:

C out = (13.23)

where

C in = the total investment in the board and assembly prior to the testC test = the cost of performing the in-circuit test

Y in = the yield of the board coming into the test

f c = the fault coverage of the test

As an extreme case, assume that C in = C board + C assmbly & components = $100 + $50 =

$150 has been invested in a board and assembly, the test costs C test = $7.50 to per-

form per assembly, the yield of the assemblies is Y in = 0.8 or 20 out of every 100 as-

semblies are defective (assuming all the defects are the result of defective embed-

ded passive layer pair and assume further, for simplicity, that we are fabricatingonly one board per panel), and f c = 0.9, such that 90% of the defects are successful-

ly detected by the in-circuit test. Then the outgoing cost per good board is effective-

ly C out = $192.53. This result assumes that all the defective assemblies are scrapped

and none can be reworked. Note that the yield of assemblies that pass the test is giv-

en by

Y out = Y in1– f c (13.24)

So for our example case, the yield out of the test activity is Y out = 97.79% (2.21%test escapes), and the final yielded cost of the assemblies is C out/Y out = $196.88. If,

on the other hand, the defective embedded passive layer pair had been detected

prior to its lamination into the multilayer board, applying Equation 13.23 during

the board fabrication (assuming that $20 was spent on the embedded passive lay-

er pairs that have a 80% yield and we have a 90% fault coverage test, assuming

the test costs $2/layer pair) the effective embedded layer pair cost would be

$26.89. The total board cost would now increase to $106.89, but the yield also in-

creases to 97.79%. Now, applying Equations 13.23 and 13.24 with an incoming

yield of 97.79% instead of 80% at assembly gives us C out = $160.08, Y out =99.78%, and C out/Y out = $160.43, much less than the original case that did not de-

tect the defective board until assembly began. Although this is obviously a very

oversimplified case, the point is that layer pair yield will have a different effect on

the system manufacturing cost depending on where in the process you are able to

detect the problem.

C in + C test

Y f cin




In general, embedded passives represent increased complexity and possibly an

increased layer count in the board, which translates into a greater probability of test

escapes at the bare board level, leading to more scrapping at the assembly level. To

summarize, the economic viability of using embedded passives in some applica-tions may lie in how accurately defects can be detected at the layer pair level prior

to completion of the board and assembly.

13.3.6 Life Cycle Costs

Thus far, we have only considered system manufacturing and size issues. This only

represents a portion of the economic impacts of converting discretes to embedded

passives. Life cycle effects, which for many applications will dominate manufactur-

ing costs, include all other activities associated with the product. Generally speak-ing, life cycle effects are more difficult to quantify into costs than manufacturing

activities. Life cycle activities include:

Design Costs —Costs of engineering and other technical personnel to design

boards that include embedded passives. If designers require specialized train-

ing or new CAD and/or other specialized design tools to successfully perform

embedded passive board design, then the costs of these activities must be con-

sidered. A summary of the design tool requirements for embedded passives is

included in the NEMI 2002 Industry Roadmap [19]. One must also consider

costs associated with effort and tools for design verification and functional

test development. Extra design costs may also include libraries of models for

embedded passives, ranging from symbol libraries to high-performance RF

models for use in electrical simulation. The inclusion of embedded passives

may also affect the degree to which a design can be reused and upgraded.

Also included in the design costs are prototyping costs. Are embedded pas-

sive applications going to require additional prototype boards?

Nonrecurring Costs —To what extent will embedded passives require board

fabricators to invest in new equipment [7]? Equipment is not the only nonre-curring cost that may be associated with embedded passives. There will be

additional tooling and artwork for layer pair production, additional chemistry

to be managed in the board fabrication process, and licensing fees and royal-

ties to be paid for the use of technology, material, and/or processes.

Time-to-Market —Does the design, verification, and prototyping of embedded

passive boards require more calendar time than that for conventional sys-

tems? Delays in time-to-market of weeks or months for a new product can

cost substantial money and in some cases mean missing the market for the

product completely. See [20] for a typical time-to-market cost model thatforecasts revenue as a function of delays in time-to-market and the length of

the market window.

Performance Value —Embedded passives may result in size or performance

improvements in a system that enable increases in market share for the manu-

facturer. It may be the case that for some quantifiable increase in system cost,




a manufacturer can differentiate itself from its competition by providing a

product that is lighter, smaller, faster, more reliable, or more functional than

its competition, and the customer is willing to pay extra for one or more of

these improvements. This type of value increase can be mapped to a life cyclecost; however, it requires a business-oriented financial modeling capability.

Qualification and Certification —The introduction of new materials and

processes into board fabrication requires material providers and board fabri-

cators to assess and possibly update safety certifications, such as for UL certi-

fication. Although the cost of this type of certification is not directly borne by

the users of embedded passives, it will be reflected in the board costs. On the

other hand, there will be a reduction in the costs associated with qualifying

discrete component manufactures.

Liability —Embedded passives, or any new technology, material, or process,may carry with it unforeseen financial liabilities. The liabilities may be in the

form of causing injury to customers, employees of the manufacturer, or the

environment. Long-term studies of the effects of the materials and the

processes used to incorporate them into boards may be necessary to prove or

disprove liability claims.

Sustainment —Sustainment is a collection of many activities, all of which have

an economic impact. In general, sustainment is all the activities necessary to:

Keep an existing system operational, that is, able to successfully complete

the purpose it is intended for Continue to manufacture and field versions of the system that satisfy the

original requirements

Manufacture and field new versions of the system that satisfy evolving re-

quirements.

The foremost concern with embedded passives is reliability. Conventional

wisdom is that system reliability will improve because of the reduction in the

number of solder joints; however, this will only be realized if the reliability

does not commensurately decrease due to other embedded-passive-specific

effects. Reliability questions arise from two origins. First, are the specific embedded structures as reliable or more reliable than the rest of the components

and packaging? Second, are there embedded-passive-specific processing con-

ditions during board fabrication that reduce the life of other conventional

board structures? Changes in system reliability appear either as warranty

costs requiring replacement or as maintenance costs requiring repair. General

warranty cost models appear in [21].

For systems that are subject to repair, embedded passives may change the

ease with which problems in the system can be diagnosed, physically re-

paired, and retested. In turn, if the faulty board is to simply be replaced, its re-liability impacts the number of “spare” boards that must be manufactured to

fulfill expected replacement commitments.

Sustainment, however, goes further than reliability-driven replacement

and repair. Sustainment also means that the system should remain manufac-




turable through the end of its support life to fulfill additional requirements for

new products and spare replenishment. This is not generally difficult for man-

ufacturers of laptop computers and other short-life consumer products, but is

a huge concern and cost issue for long-life products such as avionics for air-craft. The biggest component-related problem that long-field-life systems see

is obsolescence [22]. Most electronic parts have short lifetimes, from an

availability perspective, relative to even the design cycle of an aircraft, let

alone an aircraft’s support life. For systems like aircraft, qualification and

certification requirements may make simple substitution for obsolete parts

with newer parts prohibitively expensive. Embedded passives will mitigate

some obsolescence problems by replacing discrete parts that would become

obsolete. On the other hand, if the materials used to manufacture the embed-

ded passives within the boards become obsolete and are replaced by newer materials, the overall obsolescence problem may well become much worse.

Models for the application-specific economic impact of part obsolescence ap-

pear in [23].

Environmental and End of Life —The fabrication of passives within boards

obviously increases the volume of waste produced during the board fabrica-

tion process. Disposition of board fabrication waste is a significant contribu-

tor to the price of boards. If any of the embedded-passive-specific contribu-

tions to the waste steam are considered hazardous, then the waste disposition

costs could increase significantly. Waste disposition is also a factor at the oth-er end of the life cycle, i.e., at end of life. Depending on the type of product

that the embedded passive board is being used in and the location in the world

where the product is being sold, the manufacturer may bear some or all of the

cost of disposing of the product when the consumer has finished with it, as is

the case of television sets in Germany.

Financial —Several costs associated with creating and holding inventory—such

as handling, storage, and procurement—associated with discrete passives are

potentially avoided; this includes the cost of money that is invested in stored

passives as opposed to invested elsewhere.

13.4 EXAMPLE CASE STUDIES

In this section, we present the results of size/cost trade-off analyses performed on

several different single-board applications, including a picocell board, the NEMI

hand-held emulator, and a fiber-channel card. It is not the intent of these analyses to

prove that embedded passives lead to less expensive systems; rather, we wish to un-

derstand the economic realities should we decide to use embedded passives. Thefollowing case studies only include manufacturing costs; no life cycle effects are in-

cluded.

The relevant characteristics of the applications are given in Table 13.1 and the

common data assumptions for all the applications are shown in Table 13.2.

13.4 EXAMPLE CASE STUDIES 347



13.4.1 Picocell Board Application

Figure 13.5 shows analysis results for the picocell board when discrete resistors, butnot capacitors, are replaced by embedded components. Each data point represents

the embedded passive solution for a specific routing resource assumption, the ratio

of resources actually used to route the conventional implementation of the board,

and the theoretical maximum amount of resources that could be used; the gray band

represents all possible embedded passive solutions for this application; and the sol-

id horizontal line is the system cost of conventional implementations. Only resistors

10 k were considered embeddable. Relative system cost is plotted in Figure

13.5 and throughout this section (the system cost less the cost of all the nonembed-

dable components and functional testing). The specific solution, shown by points inFigure 13.5, indicates that the embedded passive board becomes economical when

approximately 10% of the embeddable discrete resistors are embedded. The relative

system cost (the system cost less the cost of all the nonembeddable components and

functional test) resistors considered in this study are considerably more economical

than embedded resistors in previous studies due to the assumption of fabrication of

the embedded resistors directly on wiring layers as opposed to a dedicated embed-


Table 13.1 Picocell board, hand-held emulator, and fiber-channel card application

characteristics

Picocell Board Hand-Held [19] Fiber-Channel Card

Number of 27 (< 100) 40 (< 100) 210 (< 100)

embeddable discrete 19 (100–1000) 134 (0.1–1 k) 181 (100–1000)

resistors 22 (1 – 10 k) 150 (1 – 10k)

1 (10 – 100 k) 63 (10 – 100 k)

1 (> 100 k) 6 (> 100 k)

Size of embeddable 69 0805 (80 × 50 mils) 0402 (40 × 20 mils) 561 0603 (60 × 30 mils)

discrete resistors 1 1201 (120 × 100 mils) 10 0805 (80 × 50 mils)

31 120 × 60 mils

8 250 × 120 mils

Number of 1 (< 100 pF) 69 (< 100 pF) 88 (0.001 F)

embeddable discrete 29 (100 – 1000 pF) 40 (100 – 1000 pF) 38 (0.01 F)

capacitors 13 (1 – 10 nF) 116 (0.1 F)

Size of embeddable 0805 (80 × 50 mils) 0402 (40 × 20 mils) 159 0603 (60 × 30 mils)

discrete capacitors 82 0805 (80 × 50 mils)

Discrete passive cost $0.0045 per part $0.0045 per part $0.0045 per part

Conversion cost $0.015 per part $0.015 per part $0.015 per part

(excluding assembly)

Board size 2.27 × 6.87 inches 30 cm2 (square 12 × 18 inches

board assumed)

Number of board 10 6 12

layers



ded resistor layer. The data point at $18.30, when no resistors are embedded, repre-

sents the board price increase due only to the need for a higher profit margin to jus-

tify embedded passive board fabrication (see Section 13.3.3). The next point on the

vertical axis (~$19.00) is the relative cost of the system when the first resistor is

embedded.

The resistor results appear as a gray band in Figure 13.5 due to the range of

values that U conv/U limit can take in Equation 13.5. The upper edge of the band, theclosed data points in Figure 13.5, represents the assumption that the conventional

board used all available routing resources efficiently; i.e., U conv/U limit is close to

1.0. The lower edge of the band, the open data points in Figure 13.5, represents

the assumption that the conventional board made poor use of the available routing

resources; i.e., U conv/U limit is smaller. The minimum value is determined by find-

ing the smallest value of U conv/U limit that predicts the correct number of layers in


Table 13.2 Data assumptions used in the modeling

Panel Fabrication

Panel size = 18 × 24 inches (except where otherwise noted)

Edge scrap = 0.75 inchesMinimum spacing between boards = 0.15 inches

Cost per layer pair = $12.50/ft2

Assembly

Min. Assembly Spacing = 20 mils

Yield = 0.992/discrete passive [6]

Cost = $0.0045/discrete passive

AOI = $0.0001/discrete passive

Assembly Rework = $4/site [6]

Functional Rework = $4/site [6]

Throughput Analysis

Change overs = 4/week

Change over time = 15 minutes

Cool down and start up = 30 minutes

MTBF of the process = 200 hours (conventional)

MTBF of the process = 150 hours (embedded passive)

MTTR of the process = 1 hour

Labor rate (repair) = $25/hour

Production hours = 5000/year

Routing Analysis

Average fanout = 2.1

Embedded Passives

Capacitance layer: 10 nF/cm2

Resistive material 200 ohms/square

Minimum feature size for embedded components = 15 mils

C resistor material = $0.08/in2

C in = $0.002/embedded resistor

C out = $7.43/layer pair

Cost of capacitor layer material = $14.40/ft2 (> 10 nF/in2)

Spacing between nonbypass embedded capacitors (S c) = 50 mils



the conventional solution. Practically speaking, all solutions start at the top edge

of the band (10 layers for the picocell board) and may step down to the lower

edge of the band (8 layers for the picocell board) at some point, depending on the

actual value of U conv/U limit for the application. Another type of step discontinuity

can also appear in the results if the board shrinks in size enough so that more

boards can be fabricated on a panel. In the picocell board case, the board size nev-

er decreases sufficiently to allow more boards to be fabricated on an 18 × 24 inch

panel, however, potential board size decreases may still be important to the cus-tomer using this board and Figure 13.6 shows the board area change as the frac-

tion of embedded resistors is varied.

Next, consider the integration of capacitors. Figure 13.7 shows the relative sys-

tem costs as the embeddable capacitors, but no resistors, are integrated. Only capac-

itors 100 nF were considered embeddable. Since embedding of decoupling ca-

pacitors requires material replacement and nondecoupling capacitors require the

addition of an extra layer pair for the technologies we assumed, the very first de-

coupling capacitor embedded increases the cost of the board dramatically, but as

more capacitors are embedded, the added cost of the replacement material layer is

gradually offset by the avoidance of discrete capacitor part and assembly costs. The

driver that determines whether capacitor embedding is economical or not is the den-

sity of embeddable discrete capacitors on the board. Figure 13.8 shows that if addi-

tional embeddable capacitors were added to the picocell board application, thus in-

creasing the capacitor density, decoupling embedded capacitors would become

economically viable at approximately 6.9 capacitors/square inch, whereas the actu-


Figure 13.5 The economics of embedded resistors for the picocell board application.




15

15.1

15.2

15.3

15.4

15.5

15.6

15.7

0 10 20 30 40 50 60 70 80 90 100

% of Embeddable Resistors Embedded

B o a r d A r e a ( s q u a r e i n c h e s )

Figure 13.6 Board size decrease with resistor embedding for the picocell board applica-

tion.

10

12

14

16

18

20

22

24

26

0 10 20 30 40 50 60 70 80 90 100

Conventional Board

% of Embeddable Capacitors Embedded

R e l a t i v e S y s t e m C

o s

t ( $ )

Figure 13.7 Capacitor embedding for the picocell board application.



al picocell board application has only 2.76 capacitors/square inch. When the densi-

ty of embeddable decoupling capacitors is increased, the number-up first decreases

due to the decreased board size if the size is allowed to change, and later, as density

increases, a layer pair addition is required to support routing requirements of the ap-

plication with the smaller board size.

13.4.2 NEMI Hand-Held Product Sector Emulator

Analyses similar to those performed for the picocell board have been applied to the

NEMI hand-held emulator described in Table 13.1. Figure 13.9 indicates that the

embedded passive board becomes economical when approximately 3% of the em-

beddable discrete resistors are embedded. A discontinuity in the embedded passive

board data is labeled on the plot. The discontinuity appears when enough resistors

have been embedded to sufficiently reduce the board size so that additional boards

can be manufactured on the panel or, in other words, the number-up increases. In

the hand-held emulator case, the boards are small so that the number-up on the pan-

el is large and the overall price of the boards is low, under about $2/board; there-

fore, increasing the number-up has a minimal effect on the system cost.

Figure 13.10 shows the relative system costs as the embeddable capacitors, but

no resistors, are embedded. When decoupling capacitors are embedded, the cost ini-

tially increases by the material replacement cost. We have assumed that when a de-

coupling capacitance layer pair is added, less total decoupling capacitance will be

necessary (see Chapter 9). Note that a much better economic case can be made for


-8

-6

-4

-2

0

2

4

6

0 2 4 6 8 10 12 14 16

-8

-6

-4

-2

0

2

4

6

0 2 4 6 8 10 12 14 16

Embedded Capacitor Density (capacitors/square inch)

C o s t D i f f e r e n c e B e t w e e n C o n v

e n t i o n a l

a n d I n t e g r a l P a s s i v e s S o l u t i o n ( $ )

Actual Picocell Board capaci tor density

Breakeven

No Shrink Allow Shrink

Number-up = 18

Number of layers = 10

Number-up = 21


Number-up = 21


Figure 13.8 The impact of embeddable capacitor density on system cost for the picocell

board application.



353

6

8

10

12

14

16

18

20

0 10 20 30 40 50 60 70 80 90 100

6 layers

R e l a t i v e S y s t e m C

o s

t ( $ )

6

8

10

12

14

16

18

20

0 10 20 30 40 50 60 70 80 90 100

Conventional Board

63 boards/panel

6 layers


R e l a t i v e S y s

t e m C

o s t ( $ )

70 boards/panel

8 layers

Figure 13.10 Capacitor embedding for the 5.5 × 5.5 cm NEMI hand-held product sector

emulator. No embedded resistors are fabricated in this example. The baseline for this plot

(the horizontal line) is the board with none of the embeddable capacitors embedded.

Figure 13.9 The economics of embedded resistors for the NEMI hand-held product sector

emulator (5.5 × 5.5 cm board fabricated on an 18 × 24 inch panel). The data points represent

specific embedded passive solutions; the solid horizontal line is the relative system cost of

the conventional implementation.



embedded decoupling capacitors in the hand-held emulator than for the picocell

board due to the larger embeddable decoupling capacitor density—23.44 capaci-

tors/square inch. Similar to the embedded resistor characteristics, eventually

enough decoupling capacitors are embedded to reduce the size sufficiently to allowa number-up increase. Note that there are fewer embeddable capacitors than resis-

tors, so this discontinuity occurs later in the embedding process than for resistors.

Also note that a second discontinuity appears in Figure 13.10—a layer change. As

board area decreased, so did the available wiring resources. Eventually, an addition-

al layer pair had to be added to interconnect the system components.

13.4.3 Fiber Channel Card

Figures 13.11 and 13.12 show the results of embedding resistors and decoupling capacitors into the fiber-channel card described in Table 13.1. In this case, the board

is large and only one can be fabricated per panel. The results for two different panel

sizes are considered in these figures. Because all the cost associated with fabricat-

ing embedded resistors on a panel has to be borne by a single board, 25–35% of the

610 embeddable resistors need to be embedded to realize a cost savings. Figure

13.11 also shows that when there is less panel waste when the board is fabricated on

a smaller panel, embedded resistors become economical more quickly. Figure 13.12


Figure 13.11 The economics of embedded resistors for the fiber channel card. The data

points represent embedded passive solutions; the solid horizontal lines are relative system

costs of conventional implementations.



shows the effect of integrating decoupling capacitors for the fiber-channel card. For

this example there are only 242 embeddable capacitors on a 12 × 18 inch board,

which gives 1.12 embeddable capacitors per square inch. As indicated in the hand-

held and picocell examples, with such a low embeddable capacitor density it is not

likely to be economical to embed the capacitors.

The economics of embedded decoupling capacitors can be generalized by ob-

serving the application-specific embeddable capacitor density necessary to break even on costs, i.e., by plotting the embeddable capacitor densities where the cost

difference between the conventional and embedded passive implementations is

zero. For the picocell board application with a constant board area assumed, this

point is 6.9 embeddable decoupling capacitors per square inch (Figure 13.8). Figure

13.13 shows the general result for the three applications considered in this chapter.

The critical assumptions for this plot are that the board size and the number of lay-

ers required for routing are not allowed to change. The primary differentiator be-

tween the applications as far as this plot is concerned is in the panelization efficien-

cy—the total board area on the panel divided by the panel area. The dielectrics used to produce embedded capacitor layers are relatively expensive and would be pur-

chased and used at the panel size. Therefore, a low panelization efficiency indicates

that the application is wasting a lot of the expensive material, and a larger paneliza-

tion efficiency indicates less waste so that lower breakeven capacitor densities are

possible.


160

200

240

280

320

360

400

440

0 10 20 30 40 50 60 70 80 90 100

160

200

240

280

320

360

400

440

0 10 20 30 40 50 60 70 80 90 100

Conventional Board (16 x 20 inch panel)

Conventional Board (18 x 24 inch panel)

18 x 24 inch panel

16 x 20 inch panel


R e l a

t i v e S y s t e m C

o s t ( $ )

Figure 13.12 Capacitor embedding for the fiber-channel card. Note that in this case there

are no embeddable discrete nondecoupling capacitors.



13.5 SUMMARY

In this chapter, we have presented the results of an application-specific economic

analysis of the conversion of discrete resistors and capacitors to embedded passives

that are embedded within a printed circuit board. The model has been demonstrated

on a picocell board, the NEMI hand-held emulator, and a fiber-channel board. Inthese cases, we found embedded resistors to be generally cost-effective, with the

most significant economic impact resulting from either number-up increases due to

board size reductions or layer count decreases due to reductions in routing require-

ments. Because we considered embedded resistors fabricated directly on wiring lay-

ers as opposed to dedicated embedded resistor layers assumed in previous studies

[6, 7], we can not generalize to components per unit area because the results are

driven by the board fabrication profit margin. The profit margin is a fractional in-

crease in board cost and thus much smaller in absolute terms for high number-up,

whereas cost reduction is achieved through omission of discrete part costs. As ex-

pected, when a technology that adds resistors directly to the wiring layers is used,

embedded resistors become economically viable when considerably fewer are inte-

grated than for layer addition technologies.

For the applications considered, embedded decoupling capacitors become eco-

nomical when the capacitor density reaches 7–8.5 capacitors/square inch or greater


2

4

6

8

10

12

0.03 0.05 0.07 0.09 0.11 0.13 C a p a c i t o r B r e a k e v e n D e n s i t y ( e m b e d

d a b l e

c

a p a c i t o r s / s q u a r e i n c h )

~500 pF/in2

10 nF/in2

2

4

6

8

10

12

0.03 0.05 0.07 0.09 0.11 0.13

Material Cost ($/square inch)

C a p a c i t o r B r e a k e v e n D e n s i t y ( e m b e d d a b l e

c a p a c i t o r s / s q u a r e i n c h )

~500 pF/in2

10 nF/in2

Fiber Channel Board (18 x 24 inch panel)

Hand-Held Emulator


Hand-Held Emulator


Picocell Board

Figure 13.13 Decoupling capacitor breakeven densities as a function of dielectric material

replacement costs. Only single-layer substitution is considered in this plot. The actual capac-

itor densities are: fiber-channel board = 1.12 caps/in2, picocell board = 2.76 caps/in2, NEMI

hand-held emulator = 23.44 caps/in2.



for reasonable panelization efficiencies in which dielectric replacement material

with a cost of $0.10/square inch is assumed. These densities decrease if less expen-

sive dielectrics can be used.

It must be reiterated that due to the opposing nature of many of the effects out-lined in this chapter, the overall economic impact of replacing discrete passives

with embedded passives, in general, yields application-specific results instead of

general rules of thumb. We also need to point out several factors that should be kept

in mind when interpreting the results in this chapter:

1. Several system implementation details are not addressed in this analysis in-

cluding:

a. Waste disposition in board fabrication—we only account for additional

waste disposition costs associated with the fabrication of embedded pas-sive boards in the profit margin differential.

b. Nonhomogeneous panelization—some panel fabrication technologies and

materials allow boards to be laid out on the panel with 90 degree relative

rotations, resulting in the potential for more boards on a panel. We have

assumed homogeneous panelization in this analysis.

c. We have not considered the possibility that the conversion of discrete to

embedded passives may allow some double-sided assemblies to become

single-sided, thus saving significant assembly costs.

2. With any trade-off analysis, the results are only as good as the input data; i.e.,

inaccuracies in the input data will change the results of the analysis.

ACKNOWLEDGMENTS

The author wishes to acknowledge the members of the Advanced Embedded Pas-

sives Technology (AEPT) Consortium—NCMS, ITRI, 3M, Compaq Computer,

Delphi Delco Electronics, DuPont Photopolymer and Electronic Materials, DuPontHigh Performance Films, ESI, Foresight Systems, MacDermid, Merix Corporation,

MicroFab, Nortel Networks, ORMET Corporation, and Sanmina—and the mem-

bers of the NEMI Passive Components Technology Working Group.

REFERENCES

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the Electronic Components and Technology Conference, Seattle, WA, pp. 218–224, May1998.

2. D. Brown, “The Economics of Integrated Passive Component Technologies—An Ongo-

ing Exploration of a Life Cycle Cost Analysis,” Advancing Microelectronics, 25, 3,

55–58, 1998.

3. R. Tummala, G. E. White, V. Sundaram, and S. Bhattacharyam, “SOP: The Microelec-

REFERENCES 357



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Cost-Effectiveness of Integrated Passives,” Microelectronics International, 17, 3,11–15, 2000.

5. Passive Components Technology Roadmap, National Electronics Manufacturing Tech-

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6. “Ohmega-Ply® Cost Analysis,” white paper available from Ohmega Technologies, Inc.,

Culver City, CA, www.ohmega.com.

7. M. Realff and C. Power, “Technical Cost Modeling for Decisions in Integrated vs. Sur-

face Mount Passives,” In Proceedings of IMAPS 3rd Advanced Technology Workshop

on Integrated Passives Technology, Denver, CO, April 1998.

8. C. Power, M. Realff, and S. Battacharya, “A Decision Tool for Design of ManufacturingSystems for Integrated Passive Substrates,” In Proceedings of IMAPS IMAPS 4th Ad-

vanced Technology Workshop on Integrated Passives Technology, Denver, CO, April

1999.

9. M. Scheffler, D. Ammann, A. Thiel, C. Habiger, and G. Tröster, “Modeling and Opti-

mizing the Costs of Electronic Systems,” IEEE Design & Test of Computers, 15, 3,

20–26, 1998.

10. P. A. Sandborn, B. Etienne, and G. Subramanian, “Application-Specific Economic

Analysis of Integral Passives,” IEEE Transactions on Electronics Packaging Manufac-

turing, 24, 3, 203–213, 2001.

11. P. Sandborn and P. Spletter, “A Comparison of Routing Estimation Methods for Micro-electronic Modules,” Microelectronics International, 17, 1, 36–41, 1999.

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of PWB Fabrication and Waste Disposal,” In Proceedings of IPC Printed Circuits Expo,

San Jose, CA, pp. S10-4-4–S10-4-12, 1997.

13. D. Dance, T. DiFloria, and D. W. Jimenez, “Modeling the Cost of Ownership of Assem-

bly and Inspection,” IEEE Transactions on Components, Packaging, and Manufacturing

Technology—Part C, 19, 1, 57–60, 1996.

14. M. M. Chincholkar and J. W. Herrmann, “Modeling the Impact of Embedding Passives

on Manufacturing System Performance,” In Proceedings of ASME Design for Manufac-turing Conference, September–October, 2002.

15. V. G. Shah and D. J. Hayes, “Trimming and Printing of Embedded Resistors Using De-

mand-Mode Ink-Jet Technology and Conductor Polymer,” In Proceedings of the Techni-

cal Conference IPC Printed Circuits Expo, pp. S14-4-1–S14-4-5, March 2002.

16. K. Fjeldsted and S. L. Chase, “Trimming Embedded Passives: Cost of Ownership,” Cir-

cuiTree, September 2002.

17. P. A. Sandborn, “An Assessment of the Applicability of Embedded Resistor Trimming

and Rework,” to be published.

18. D. Becker and P. Sandborn, “On the Use of Yielded Cost in Modeling Electronic As-sembly Processes,” IEEE Transactions on Electronics Packaging Manufacturing, 24, 3,

195–202, 2001.

19. Passive Components Technology Roadmap, National Electronics Manufacturing Tech-

nology Roadmaps, NEMI, Inc., 2002.

20. J. Debardelaben, V. K., Madisetti, and A. J. Gadient, “Incorporating Cost Modeling in




Embedded-System Design,” IEEE Design & Test of Computers, 14, 3, 24–35, 1997.

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22. R. C. Stogdill, “Dealing with Obsolete Parts,” IEEE Design & Test of Computers, 16, 2,17–25, 1999.

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REFERENCES 359



361

CHAPTER 14

THE FUTURE OF

INTEGRATED PASSIVES

RICHARD K. ULRICH

This book started out with an introduction to integrated passives that covered their

definitions, various configurations, and the motivations and problems associated

with their implementation. The next twelve chapters provided an analysis of the ex-

tensive and diverse state of the art for the various aspects of the technology. This fi-

nal chapter will seek to pull together some of this large amount of information in or-der to predict the future of integrated passives.

14.1 STATUS OF PASSIVE INTEGRATION

Embedded passives in primary interconnect boards are not a new idea; they have

been used in ceramic substrates for decades. Favored materials and processes for re-

sistors, capacitors, and inductors in LTCC are well characterized with regard to

manufacturing requirements, performance, and economics, and there is a large in-frastructure supporting them. The main technical drawback with embedded pas-

sives in between ceramic layers is that tolerance is rarely better than around 10%

due to variations in printing, firing, shrinkage, and the inability to trim component

values. If passives are formed on the surface of the ceramic substrate (hybrids), they

can be trimmed after firing. Ceramic substrates, though growing in use with the rest

of the industry, will never approach organic boards in sales volume and, therefore,

will continue to host only a small fraction of the overall passives produced, discrete

or integrated.

Integrated passives are also widely available as arrays or networks, usually fabri-cated on IC-sized Si using basic front-end technologies, that can be surface mount-

ed onto ceramic or organic boards using the same sort of infrastructure used to in-

stall discretes. This technology is rapidly gaining market share due to the obvious

economic advantages with a minimum of changes in board design or on the factory

floor for implementation.



ISBN: 0-471-24431-7



To date, integrated passives have not been utilized as embedded structures in or-

ganic substrates to a significant degree, particularly with FR4, which makes up the

vast majority of boards sold today. This potentially very large market is the driving

force for R&D in the area. The problems with this implementation are well under-stood; both academia and industry are doing their parts in their own ways to solve

these issues. Literature, conferences, and workshops for integrated passives on or-

ganic substrates began to appear in the mid 1990s and the typical journal article or

conference presentation since then is a demonstration of a material or a process to

make resistor, capacitor, or inductor test structures, or else to make a simple multi-

component device such as a filter or terminator. The striking characteristic about

the technical literature is the vast array of materials and processes that have been in-

vestigated for integrated resistors and for capacitor dielectrics. The list is very long

and diverse, including metals, ceramics, and polymers as well as nano- and micro-composites of these materials that can be formed and patterned through many dif-

ferent processes. Methodology from the ceramic side is difficult to use with organ-

ics because these processes typically require much higher processing temperatures

than can be tolerated by organic board materials and can only be applied if

processed separately and laminated onto the board afterwards. A more manageable

number of candidate processes, together with design software, costing models, and

supply infrastructure, must be developed before embedded passives can move into

organic boards.

14.2 ISSUES FOR IMPLEMENTATION ON ORGANIC SUBSTRATES

A comprehensive evaluation of using an integrated passive technology versus a dis-

crete passive technology must take into account the following factors:

1. Electrical Design Issues—schematic differences due to differences in compo-

nent characteristics

2. Board Design Issues—footprint, routing, number of layers3. Fabrication Issues—materials, processes, tolerances, yield

4. Manufacturing Issues—implementation and scale-up of fabrication technolo-

gy to produce a volume process

5. Added Value to the Product—increased customer appeal resulting from

smaller form factor, mass, performance

The following is a summary of the status of these first four issues based on the ear-

lier chapters and a brief description of the remaining challenges.

14.2.1 Electrical Design Issues

The impact of passive integration on the electrical schematic of a system will be

considerable for decoupling but fairly minimal for other applications. A single inte-

362 THE FUTURE OF INTEGRATED PASSIVES



grated capacitor has such a low parasitic inductance that it can replace dozens of

discrete capacitors that have been wired in parallel for the purpose of decreasing

their overall inductance. But for other uses of passives, the replacement of discretes

will be much closer to one-to-one. In some cases it might be possible for a single in-tegrated component to replace multiple discretes if the integrated version can be

custom sized to replace more than one of the off-the-shelf discretes that are wired in

series or in parallel to give a specific overall value but, for most filters, terminators,

A/D converters, etc, the schematic will be the same.

14.2.2 Board Design Issues

The impact of passive integration on board design will be profound. The main ef-

fect will be to increase the number of layers since some considerable area must now be created to accommodate the planar integrated components. This is based on the

assumption that most integrated components will require more area per component

than the discretes they replace, and this will be true for the most part. A secondary

effect is the change in routing requirements since not all passives must be connect-

ed at the surface.

The size gap is largest for capacitors. At the time of this writing, an 0402 can be

purchased with 2.2 F, which, even with keep-away distance figured in, amounts to

230,000 nF/cm2. The highest values from the various processes becoming available

for commercialization are much lower: up to about 1 nF/cm2

for unfilled polymers,maybe 30 for ferroelectric-filled polymers, 50 for fired ferroelectric-coated foils for

lamination, and the low hundreds for sputtered or anodized paraelectrics. Ferroelec-

tric thin films cured in place might reach over 1000 nF/cm2, but that technology

seems the farthest away. Only the smallest-valued capacitors can be replaced on a

size-competitive basis with embedded components. Somewhere above that range,

the remaining driving forces include economy of manufacture, replacement of sol-

der joints, and very low inductance for decoupling. It will rarely make sense to at-

tempt to integrate the largest capacitors on the board, those over about a microfarad

that are generally used for energy storage. Larger capacitor areas not only occupymore layer space, but also pose a higher reliability risk.

Since a range of six decades or more of capacitance is required for many com-

mon systems, no one dielectric could provide the entire range with reasonable foot-

prints regardless of its specific capacitance. Even if the lowest-valued capacitors

can be fabricated, say, 10 mils across with acceptable tolerance, the highest-valued

would then be unacceptably large at 10 inches. For this reason, it might be useful to

employ the board’s interlayer dielectric for the low-valued components and a more

exotic high-k material for the large values. The low-valued capacitors generally re-

quire paraelectric-type performance, matching most common board dielectrics. Theother technology should have as high a specific capacitance as possible in order to

embed the most components.

The size of integrated resistors is ruled by the number of squares and only indi-

rectly by the specific resistance of the material. The lower limit of resistor linewidth

is set by either thermal or tolerance issues. A large number of squares is to be avoid-

14.2 ISSUES FOR IMPLEMENTATION ON ORGANIC SUBSTRATES 363



ed due to capacitive coupling between the meanders resulting in a decrease in im-

pedance at high frequencies. Resistor materials need to span between about 100 and

10,000 /square to cover the entire range of values normally required in electronic

systems. The available thin-film processes such as TaNx, CrSi, and NiP are limited to only a few hundred /square at most. There is some promise of achieving 10,000

/square with metal-deficient compounds or sputtered cermets, but more develop-

ment is needed. Fired thick-film materials on foil, borrowed from LTCC technolo-

gy, and polymer thick films can cover the entire range with no more than a few

squares. If the fundamental problems of reliability and value drift can be solved,

PTF will be hard to beat as a flexible, economical process.

Integrated inductors can be designed as square or circular spirals, and can be on

a single layer or distributed over multiple layers. Normal circuit board copper is

used for the metal. Numerous programs exist that calculate the inductance and qual-ity factor of these structures. The difficulty lies in keeping metal on other layers

away from the inductor region, and in defining a keepout region around the induc-

tor. For that reason, it is good practice to include a surrounding ground around the

inductor, including an appropriate keepout, and to compute the inductance includ-

ing this bounding structure. Then the entire structure is used as a keepout for layers

above and below the inductor. Metal on other layers outside the keepout will not

impact the inductor, since it is already bounded by ground metal on its own layer(s).

The z-axis routing will be diminished by embedding since there is no need to

route all passive connections to the surface. This would serve to reduce the number of vias and catch pads that have a limiting effect on wiring density. This beneficial

consequence would probably never offset the increased layer requirements due to

the area mismatch between discrete and embedded, so the number of layers would

probably increase with passive integration.

The number of extra board layers required for an embedded passive approach

can be estimated. The total area requirements of proposed integrated passives from

a schematic can be calculated for given set of integratable R, C, and L technologies.

This can greatly exceed the interconnect area on the board in some applications. Di-

viding the total required area by the desired circuit board footprint will give a good estimate of the number of layers needed. Layout optimization may alter this number

a bit, but this alone may indicate the worth of embedding for a specific application.

14.2.3 Fabrication and Manufacturing Issues

This topic makes up most of the book due to the large number of candidate tech-

nologies reported in the literature. The materials and their processes are inextricably

connected such that choosing one usually restricts options for the other. For in-

stance, if Al2O3 is desired as the capacitor material, about the only way to deposit itis by sputtering or anodizing. It is possible to categorize these groups as follows:

Processes Requiring Vacuum —Sputtering and CVD are necessary for most

thin-film processes. These tend to be subtractive techniques requiring pho-

tolithography and are capable of excellent tolerance. An extensive range of




component values are enabled by this, particularly with thin-film dielectrics

that make possible specific capacitances over the limit of about 30 nF/cm2

that is available with thick-film methods. Many tried-and-true materials are

possible for resistors, but most are under a couple of hundred /square; con-siderable work remains to be done to achieve values over 1000 /square that

are needed for the high end of resistor values. Inductor materials up to a few

microns can be deposited in this way, but they may be too thin to achieve

high Q at high inductance values, although at high frequencies the skin effect

comes into play and thin inductors perform almost as well as thick ones.

Complete integrated and interconnected R, C, and L systems have been

demonstrated using thin-film methods and they are well suited to HDI and

build-up technologies. However, vacuum processes are relatively expensive

and it may not make economic sense to include them solely for the purpose of creating integrated passives on low-cost commodity boards. Old front-end

lines work well for vacuum processing, using substrates of Si or glass.

Polymer Thick Film —These are additive processes using screen-printed prefor-

mulated inks. For capacitors, the maximum may be in the low tens of nF/cm2

with ferroelectric characteristics using high-k powders dispersed in curable

polymers. This may not be high enough to replace the larger capacitors on the

board or to provide sufficient decoupling in high-performance applications.

For resistors, a very wide range of /square is available, enabling almost any

practical resistor value to be fabricated with no more than 10 squares.Tolerances as printed are no better than about 10% and resistor inks tend to

have unstable values with regard to humidity, temperature and time; extensive

research is under way to improve this. The attractive feature of PTF is the low

cost of capital equipment, inks, and processing. If value drift problems of PTF

resistors can be solved, they will find widespread use for integration on almost

any platform. Trimming has already been demonstrated to improve precision.

Integrated Passives Formed Before Inclusion in the Board —Separating the

processing of capacitor dielectrics and resistor materials from the board en-

ables the use of a host of materials that have been long used on ceramic sub-strates, such as BaTiO3 dielectrics and RuO2 and LaB6 resistors. Commercial-

ized processes are soon to be released from DuPont that involve printing

resistors and capacitors that are fired onto Cu foil and provided for lamination

into FR4 or flex stacks. The metal is then photodefined to create the separated

passive components. Ohmega-Ply® has for some years provided plated NiP

resistors on Cu foil that is postprocessed in much the same way. Costs are

probably intermediate between PTF and vacuum processes.

14.3 PROGRESS ON BOARD-LEVEL IMPLEMENTATION

For implementation into the primary interconnect board, the issues listed above are

particularly suitable to be addressed by consortia since the subjects cover such a

wide range of interrelated issues.

14.3 PROGRESS ON BOARD-LEVEL IMPLEMENTATION 365



14.3.1 Advanced Embedded Passives Technology

Consortium (AEPT)

In October 1998, the National Center for Manufacturing Sciences (NCMS), the Na-

tional Electronics Manufacturing Initiative (NEMI), the Interconnect Technology

Research Institute (ITRI), and a dozen industry partners won a four year NIST Ad-

vanced Technology Program award for the purpose of developing the materials, de-

sign, and processing technology for embedding passive devices into circuit board

substrates. The program ran through the end of January 2003. The team included a

mix of OEMs, board fabricators, materials suppliers, and design tool developers in

order to solve the simultaneous problems of implementation. The goal was to come

up with marketable integrated passive technologies that include validated method-

ologies for design, materials, fabrication, trimming, reliability assessment, and eco-

nomic evaluation. Manufacturing processes for large-format boards were targeted

to improve the economics and the 1–10 GHz range was emphasized to accommo-

date future system requirements. The AEPT consortium developed a number of test

structures and product emulators to be used in evaluating the entire spectrum of is-

sues from design to reliability.

14.3.2 National Electronics Manufacturing Initiative (NEMI)

NEMI is a consortium of 400 engineers and scientists from over 190 different orga-

nizations, including industry, academia, and national labs, with the mission of help-

ing secure and maintain leadership of North American electronics manufacturing.

They have published technology roadmaps every two years since 1994, concentrat-

ing on board and system issues and coordinating with SIA and other organizations

that produce chip-level roadmaps. The reports utilize product emulators in five prod-

uct sectors, along with predictions of technological and manufacturing progress, to

identify upcoming gaps between technologies and needs. This roadmap series covers

both the various forms of interconnect substrates and passives, both discrete and in-

tegrated. They concentrate more on performance trends, in terms of upcoming spe-

cific capacitance or sheet resistance, for example, and less on the technical details onhow this might be achieved, making them complimentary to this book. Considerable

effort is given to economic analysis for the product emulators (Table 14.1).


Table 14.1 Product sectors of the NEMI roadmaps

Product Sector Characteristics

Low cost, high volume Consumer products for which cost is the primary driver

Hand-held Hand-held, battery-powered products driven by size and weightreduction

Cost/performance Products that seek maximum performance within a few

thousand dollar cost limit

High performance High-end products for which performance is the primary driver

Harsh environment Products that must operate in extreme environments



The 2000 NEMI Roadmap should be read not only for its predictions, but also to

identify the important issues. A few of its more important points are summarized

here. As mentioned earlier, lack of infrastructure is a major problem in the imple-

mentation of integrated passives, and this problem exists throughout the supplychain, from design, to materials and suppliers, to process technology. Yield and the

lack of industry standards is also a major concern. Integrated passives are being

driven more by the high-performance sector rather than the hand-held sector, be-

cause it requires better decoupling and EMI suppression, both due to the constant

push for higher clock speeds. The roadmap also predicts the continued increase in

surface-mount integrated arrays and networks. NEMI believes that the development

and implementation of microvia HDI technology is essential for the implementation

of integrated passives since they are both essential to high-speed design. Table 14.2

is taken, for the most part, from p. 6 of the Passives chapter of the 2000 NEMIRoadmap, with some updates by the authors of this book.

14.3.3 The Embedded Capacitance Project

The National Center for Manufacturing Sciences (NCMS) organized more than a

dozen partners consisting of materials suppliers, designers, board fabricators, and

academia into a collaborative effort to advance the use of distributed embedded ca-

pacitance technology for power supply decoupling. The aim was primarily at FR4

circuit boards requiring a minimum of new process technology for implementation.Test vehicles were developed for electrical characterization, reliability assessment,

and as proof-of-concept platforms for design software. High-speed measurements

of power to ground voltage ripple were used to determine the effectiveness of vari-

ous decoupling materials and configurations. The final report was issued in early

2000. Material from this project has been included in this book, as appropriate.

14.4 THREE WAYS IN FOR ORGANIC BOARDS

If the high volume of organic board production is a target for passive integration,

the entry strategies must be chosen for maximum effect. The following subsections

describe three ways that this penetration can be brought about.

14.4.1 Decoupling

As decoupling requirements become more stringent, surface-mount discretes will

have an increasingly difficult time providing low-inductance capacitance. Embed-

ded capacitance will always have less inductance than surface-mount units becausethey are planar and in-plane with the power and ground layers. Additionally, this

will free valuable area on the surface near the chip being decoupled for use by other

components such as memory.

Specific capacitance levels of at least hundreds of nF/cm2 may be required, and

this cannot be met with polymer-based films. Either thin paraelectrics or ferro-

14.4 THREE WAYS IN FOR ORGANIC BOARDS 367




Table 14.2 Implementation issues for integrated passives

Integrated Arrays

Discretes and Networks Embedded Passives

Cost Good—the Better when local Better when the average

benchmark for all densities have 4–8 component density is above

other technologies devices close 3/cm2, cost is panel-size

together dependent, number of layers is

increased by integration.

Pb-free technology.

Size Good—board area Better—50% and Best—No surface board area

required for each greater board area required since the devices are

and every device savings over buried, but more total area

discretes required

Frequency Good—but Better—higher Best—very high self-resonant

range self-resonates at self-resonant frequencies due mainly to

low frequencies frequency decreased lead length and

avoidance of inductive current

loops

Reliability Good—heavy use Better—reduces the Best—eliminates solder joints

of solder joints number of solder

joints

Flexibility Best—most flexible Better than integrated, Good, but requires modeling

for both design and not quite as good as and simulation up front, cannot

manufacturing discretes be reworked

Time to Best—flexibility Better—simple Fair—most board shops

market allows quick turns networks and arrays require 5–7 days to build an

can be quickly integrated passive board

designed and

manufactured

Availability Best—highly Better—standard Fair—only a few suppliers, butavailable from parts from multiple more coming on board

reliable sources suppliers

Value range Best—all values Good—more work Good—more work needed on

available at needed on high sheet high sheet resistance and high

commodity prices resistance and high specific capacitance processes

specific capacitance

processes

Tolerances Best—tight Better—can be Good—10% achievable as

tolerances available presorted like formed, and trimming possibleat commodity prices discretes, with slightly

more loss of parts



electrics formed at temperatures low enough for organic boards will be required.

The limit for paraelectrics is probably around 500–1000 nF/cm2 before leakage and

breakdown become a problem in the low hundreds of angstroms. Lower operating

voltages help this issue. Ferroelectrics are capable of much higher capacitances, depending on what can be achieved with tolerable processing temperatures. Rapid

thermal annealing or firing before lamination may be effective approaches.

The optimization of integrated decoupling with regard to the amount and distrib-

ution of the capacitance on the board is an important task yet to be completed and

could easily be a book unto itself. This will require a concerted effort between mod-

eling and measurement, taking into consideration the large number of possible per-

mutations of current draw characteristics and distributions of the chips, as well as

the materials and layout of the boards.

14.4.2 Component Replacement on FR4

Low-cost, everyday products require low-cost, everyday processing. To make head-

way in the massive FR4 board market in general, passive integration technologies

must be inexpensive, robust, and capable of being dropped into existing board

processes. The circuit board industry in the United States is largely outsourced and

somewhat conservative compared to those of Asia and may require more incentive

to change. PTF resistor materials are ideal for this, if some fundamental problems

can be solved. PTF capacitors will be able to replace only the lowest-valued compo-nents, perhaps below 10 nF, so more development is needed in this area as well.

14.4.3 High-Density Interconnect

As HDI technology evolves, it may be possible to include the development of pas-

sive integration, resulting in acceptable combined processes. Since HDI will be

more expensive per square inch anyway, with the promise of higher performance,

the initial higher cost of passive integration may be less of a problem. Vacuum pro-

cessing could be applicable here.

14.5 CONCLUSION

The implementation of integrated passives will be an evolution, not a revolution.

Passive arrays and networks will continue to increase their market share as they re-

place terminators, filters, and other natural groups of passives. This should top out

at some fraction of total passives, probably less than a quarter. The use of embed-

ded capacitors for decoupling is a certainty since their parasitic inductance is lower than can be achieved with any surface-mount components. Upcoming high-current

and high-speed microprocessors cannot be decoupled any other way. Penetration

into commodity boards is an important goal that will be realized gradually as the in-

terrelated issues are resolved. Once cost savings are demonstrated, market share

should increase steadily.

14.5 CONCLUSION 369



How far can this concept go? Figure 14.1 shows a hypothetical system with pas-

sives, chips, and other subsystems integrated together. In this format, all individual

component packaging is discarded and the layers of the “board” become the me-

chanical and environmental protection for each part so that there is very little massthat does not have electrical function. The chips are thinned to fit within one layer

of the stack, and the surface is left only for those components that require access to

the outside world. The system could hardly be smaller or have shorter intercon-

nects. On our way to this ideal, integrating passive components is essential.

Between the current rapid development of integrated passive component tech-

nology and the increasing requirements of future electronic systems, significant

commercial use appears assured, but when? For those of us “in the business,” this

never happens fast enough. There is always a gap between what can be done techni-

cally and what is economically viable at a given time, which is always a challengewhen drawing up roadmaps. For passive integration, this gap is especially large be-

cause of the vast number of materials and processes that have been demonstrated.

Now, the infrastructure needs of design tools, costing models, and supply chains

must be established and this will happen as a few tentative processes are commer-

cialized in the coming years. Once at least some technologies are available for

OEMs to consider, the first pieces of their associated infrastructure will provide nu-

cleation for the simultaneous solution of the interrelated issues of passive integra-

tion.

What year will more than 50% of passives be integrated? The microelectronicsindustry is full of cautionary tales; many of us remember other questions such as

“What year will more than 50% of ICs be made from GaAs instead of Si?” or

“What year will more than 50% of chip connections be TAB instead of wirebond?”


Figure 14.1 The complete integration of an electronic system.



But some technologies prove their economic viability and become industry stan-

dards, such as surface mounting. Is passive integration economically viable? Cer-

tainly for decoupling it is and, in fact, may be the only way to handle the future gen-

erations of high-power, high-frequency microprocessors. For discrete replacement

in general, the best processes and materials are still being identified, and this is the

most important task now. If we find suitable technologies, then passive integration

will probably show a long, steady climb to dominance in a manner similar to sur-

face mount as the infrastructure, supply chain, and industry acceptance grows si-

multaneously.

14.5 CONCLUSION 371



termination, 96, 294, 315

Assembly methods, 21

AVX, 315

Bandpass filter, 233

BaTiO3. See also Ferroelectrics

applied to integrated capacitors, 136

breakdown field, 90

capacitance from, 81Curie temperature, 78, 82

dielectric properties, 80, 93

hydrothermal processing, 125

mechanism of capacitance, 78

powder mixed with polymer, 127

size of integrated capacitors from, 104

temperature, frequency and voltage

effects, 82

BC2000™ (Sanmina), 135

BCB 102, 108Bedspring models, 184

Berry, Robert, 27

Bluetooth™, 24, 306

Board design

number of layers, 334, 363

size and routing, 332, 334

Breakdown voltage and field, 88, 90

Build-up

applications, 313

processing, 13Bypass capacitors, 178

C-Ply (3M) ,133

California Micro Devices, 313

Capacitance density, 79, 81

373

INDEX

AC impedance, 179

Accelerated testing

capacitors, 89

resistors, 39

AEPT (Advanced Embedded Passives

Technology Consortium), 27, 366

Al2O3


breakdown field, 90capacitance from, 81, 102

dielectric properties, 80

size comparison, integrated and discrete,

17

thickness from anodization, 119

Anodization, 117

anodizable metals, table, 118

ferroelectrics, 124

film thickness, 119

formation voltage, 121rectifying properties of oxides, 123

Anodized Ta, 120

applied to terminators, 296

leakage and breakdown, 86, 122

mechanism, 118

patterning, 123

rectifying properties, 123

technique, 120

Applications of integrated passives

DC/DC conversion, 26decoupling, 24, 177, 367

general, 23, 293, 367

filtering, 19

inductors, 224, 232

matched to dielectric properties, 93



ISBN: 0-471-24431-7



Capacitance density (continued)

maximum, 109

Capacitor(s). See also Integrated capacitors

arrays, 314in parallel, 181

range in cell phones, 4

Cell phones, passives in, 2

Ceramic substrates, see LTCC

Cermets, 61

Characteristic impedance, 249

Class 1 dielectrics, 92

Computers, passives in, 3, 5

Conversion costs, 2

Corner squares, 34Cost modeling, 22, 327

Coupled microstrip,

odd-mode, 254, 255

even- mode, 254, 255

Couplers, 304

CrSi, 16, 58

in voltage dividers, 298

Curie temperature, 78, 82

CVD, 116

CV product, 108

DC/DC conversion, 26

Decoupling

dielectrics for, 94

inductance issues, 25

overview, 24, 177

De-embedding, 259

Definitions of integrated passives, 7

Design issues, 362

Diamond-like carbon, 116Dielectric constants, table, 80

Dielectric materials. See also Integrated

capacitors

breakdown, 109, 87

capacitance density, 79

class 1 dielectrics, 92


CV product, 108

defects in, 145

diamond-like carbon, 116dielectric constants, table, 80

dissipation factor, 89

ferroelectric-filled polymers, 127

films, 15

FR4, 129

374 INDEX

leakage and breakdown, 86

matched to applications, 93

mechanisms, 76

paraelectrics and ferroelectrics, 77 polarizability and capacitance, 76

polymers, 126

processing, 113

silicon nitride, 318

specific capacitance, 79, 81, 95, 102

Ta2O5, 87

Ta2O5 /TiO2 composites, 115

temperature coefficient of capacitance,

82

Discrete passives0201 surface mount components, 7, 22

capacitor areas, 101

comparison of areas with integrated, 101

density, 3, 102, 354, 363

in consumer electronics, 3, 5

maximum theoretical density, 22, 102

range of values in consumer equipment, 4

replacement with integrated, 18, 23, 27

sizes, 2

Dissipation factor, 80, 89, 166Doping of semiconducting oxides, 41

Dow, 224

DuPont, 66, 132

Economics of integration, 327

cost of ownership, 338, 341

life cycle costs, 345

nonrecurring cost, 345

profit margin, 338, 340

recurring cost, 336warranty cost, 346

yielded cost, 343

Eddy currents, 195

EIA dielectric classifications, 91

Embedded Capacitance Project, 367

Emulators, 352

Environmental considerations, 347, 357

Equivalent circuits

capacitors, 154

ESR and ESL, 154, 166, 170

Ferroelectrics. See also BaTiO3

aging effects, 84, 90

anodization, 124

bottom plate materials, 131



compared to paraelectrics, 77, 94


dielectric constants, 80

dispersed in polymer, 127dissipation factor, 80

frequency effects, 83

matched to applications, 93

mechanisms, 77

sol-gel and hydrothermal methods, 124

temperature effects, 82

thickness effects, 85

voltage effects, 84

Films

processing in general, 14thick and thin, 16

Filters

bandpass, 302

general, 299

inductors in, 233

low-pass, 19

Flex substrates, 12

Footprints of passives, comparison, 17

Formation voltage, 121

FR4, 12, 369replacement of passives in, 27

Gate oxide, 186

GPS, passives in, 4

Ground plane effects, 252

HDI, 27, 369

HF etchants, 124

HiDEC, 137

High-frequency noise, 178Hybrids, 15

IMCE, 302–306

Impedance analyzer, 167

limits of, 169

Impedance from S parameters, 171

Inductance. See also Parasitics

calculation, 250

compared to discrete capacitors, 163

leads and contacts, 164mutual, 185

parasitic in capacitors, 153

reduced in integrated capacitors,160

Insite™ (Shipley), 70

Intarsia, 15, 316

INDEX 375

Integral Wave Technologies, 19, 299

Integrated active devices, comparison to, 10

Integrated capacitor(s). See also Dielectric

materialsapplication guide, 93

area compared to discretes, 101

capacitance density, 79, 81, 95, 109

commercialized processes, 132

CV product, 108

decoupling

dielectrics for, 94

inductance issues, 25

overview, 24, 177

defects in, 145dielectric materials for, 75, 80

electrical performance, 153

energy density, 81

ferroelectrics and paraelectrics, 77, 94

floating plate, 105

history of, 27

interdigitated, 130

layout options, 105, 107

leakage and breakdown, 86, 109

modeling, 153overview, 15

parallel and floating plate, 105

plate materials, 131

size 101, chart, 103

specific capacitance, 79, 81, 95, 102

status, 28

summary table, 136

temperature coefficient of capacitance,

82

tolerance, 106trimming, 132

yield issues, 145

Integrated inductor(s)

application examples, 224, 232

circuit model, 250

current crowding effect, 253, 254

eddy currents, 195

equivalent circuit, 196

first self resonant frequency, 263

general191ground plane effect, 252, 253

layout options, 192, 206

influence on performance, 213

LTCC, 230

MMIC, 224



Integrated inductor(s) (continued)

mutual inductance, 251

on silicon, 231, 265

options for high Q, 191 parasitic capacitance, 254-256

performance predictions, 216

Q factor, 200, 257

range in consumer electronics, 4

self and mutual inductance, 194

series resistance, 253

skin effect, 196, 289

effect on inductance, 199, 209

size comparison to discrete, 17

size reduction, 235spiral inductors, 217

coupled, 237

substrate losses, 210

transmission line configuration, 217

Integrated passive(s)

applications, 23

array, 7, 23

case studies, 348

compared to integrated actives, 10

cost modeling, 22, 327definitions, 7

fabrication in general, 14, 28, 364

future of, 361

history of, 27

implementation issues, 20, 368

network, 8, 23

scaling down

sizing, 21

status, 28, 362

substrates for, 11subsystems, 9

Integrated resistor(s) See also Resistivity of

materials

commercialized processes, 66

CrSi, 16, 58

fabrication, 14, 55, 72

ink jet deposited, 66

Insite™ (Shipley), 70

Interra™ (DuPont) resistor process, 66

LaB6 (DuPont), 66materials, 16, 35

network, 8, 23

NiCr, 16, 58

NiP, 38

M-Pass™ (MacDermid), 68

376 INDEX

Ohmega-Ply®, 66, 330

overview, 15

parasitic capacitance, 45, 49

performance equations, 33, 37 polymer thick film, 63, 70

problems with integration, 20

ranges required, 36

reasons for integration, 17

reworking, 341

sheet resistance, 16, 34

sizing, 45

stability, 38, 58

Ta, 57, 131

TaN, 16, 38, 59TCR™ (Gould), 332

temperature coefficient of resistance, 37,

43

thermal issues, 46

trimming, 52, 341

value drift, 39, 58

polymer thick film, 64

Interdigitated capacitors, 130, 264

Interlayer dielectrics, 129

Interra™ (DuPont)capacitor process, 132

resistor process, 66

Jet Propulsion Laboratory, 26, 299

Kapton, 12

LaB6

Interra™, 66

Langley Research Center, 19, 301Layer count in boards, 363

Leakage and breakdown, 86, 109, 167

lead-free, 20

LICA, 163

Life cycle costs, 327

Low-pass filter, 19, 263

LTCC 14, 307, 321

inductors, 230

Lumped versus distributed performance

capacitors, 173inductors, 247

resistors, 52

MacDermid, 68

Magnetic fields, 194



Maxwell's equations, solving for inductors,

221


MCM, 15MCM-D for inductors, 226

Mean time before failure (MTBF), 339

Mean time to repair (MTTR), 339

Meanders for resistors, 35

cause of parasitic capacitance, 50

Mezzanine capacitor (Motorola), 135

Micromachining for inductors, 192

Microstrip line, 284

characteristic impedance, 284

dispersion models, 286effective dielectric constant, 284

losses, 288

lumped element model, 288

step discontinuity, 273,274

Microstrip loss,

conductor loss, 288-290

dielectric loss, 291

Microwave

integrated circuits (MIC), 247

measurements, 261-263Miniature hybrid microwave integrated

circuit (MHMIC), 248

Mixed dielectric strategies, 107

MMIC inductors, 224

Mobility of charge carriers, 40

MOCVD, 116

Modeling

capacitors, 154

economics, 329

ideal passives, 154inductors, 196, 249

performance prediction, 216

Q factor, 201

resistors, 271

temperature for integrated resistors, 47

Modules, functional, 305

Monolithic microwave integrated circuit

(MMIC), 248

Motorola, 135

Mutual inductance, 185, 194, 251

nChip, 15, 135

NEMI (National Electronics Manufacturing

Initiative), 352, 366

Network analyzer, 170

INDEX 377

NiCr, 16, 58

NiP, 38


Ohmega Ply

®

, 66, 330 Nokia 6161 cell phone, 3

Number-up, 332, 336, 357

Ohmega-Ply®, 66, 330

Paraelectric dielectrics

compared to ferroelectrics, 77, 94

overview, 77

Parasitics, 18

capacitance in inductors, 212capacitance in resistors, 45, 49, 51

discrete versus integrated capacitors, 159,

163

inductance in capacitors, 153

inductance in decoupling, 25, 177

inductance in leads and contacts, 164

Penetration depth, 196, 289

Picocell board, 348

Polarizability of dielectrics, 76

Polymer dielectrics, 127Polymer thick film

fabrication, 16

resistors, 63, 70

value drift, 65

Power distribution, 177

Propagation constant, 249

Q factor, 200

RC terminators, 96, 294, 315Reliability test structures, 298

Resistivity of materials, 35. See also

Integrated resistors

alloys and metal-nonmetal compounds,

58

cermets, 61

definition, 34

films, 15

mechanisms of conduction, 40

NiP, 38 polymer thick film, 63

semiconducting oxides, 41

semiconductors, 61

single-component metals, 43, 56

Ta, forms of, 57



Resistivity of materials (continued)

table, 37, 71

TaN, 59

temperature coefficient of resistance,definition, 37

tunneling, 43

voltage coefficient of resistance,

definition, 37

Resonance frequency

capacitors, 155

in decoupling, 182

inductors, 193

resistors, 50

Reworking resistors, 341Routing

routing efficiency, 334

wiring blocked, 335

S parameters, 170

Sanmina, 135

Scheduled maintenance, 338

Self-inductance, 194, 251

Self-resonance frequency

capacitors, 155resistors, 50

Semiconducting oxides, 41, 61

Sheet resistance, 34

Shipley, 70

Siemens, 34, 40

Silicon substrates, 14

for inductors, 231

SiLK™ (Dow), 224

Skin effect, 196, 289

effect on inductance, 199, 209Solder joints, 19

Solenoid inductors, 192

Specific capacitance, 79, 81, 95, 102

Spiral inductor, see Integrated inductor

self-inductance, 251

synthesis, 258

Sputtering

cermets, 62

dielectrics, 114

TaN, 59Ti oxynitride, 60

Substrates for integrated passives

effects of roughness, 45, 114

high resistivity, 197

issues for integration, 362

378 INDEX

losses for inductors, 210

types, 11

Surface mount components, 2, 22

Surface roughnessadvantages of anodization, 118

effects on sputtering dielectrics, 114

effects on resistors, 45

Sustainment, 346

SyChip, 318

T junction, 303

Ta

alpha and beta, resistivity of 57, 131, 296

first use in integrated passives, 27TaN, 16, 38, 59

effects of surface roughness, 45

processing, 59

Ta2O5

anodized, 117, 120


leakage and breakdown, 87

MOCVD, 116

patterning, 123

sputtered, 114Telephus, 320

Temperature coefficient of capacitance, 82

Temperature coefficient of resistance

alloys, 58

definition, 37

pure metals, 43

Temperature effects

on capacitance, 82

on resistance, 43

Termination, 96, 294, 315Testing, 344

Thermal conductivity, 47

Thermal modeling, 48

effect of Cu cladding, 49

Thick and thin film processing, 16

Thin film polymer dielectrics, 126

Thin film resistor (TFR), 271

ABCD matrix, 274

experimental verification, 278

high sheet resistance microstrip model,274

measurement calibration, 278-281

scattering parameter measurements, 278

self capacitance, 276, 277

sheet resistance, 274



step discontinuity, 273

Throughput, 338

changeovers, 338

interdeparture time, 336, 340Ti oxy-nitride, 16, 60

Tolerance

capacitors, 106

resistors, 53, 342

Transmission line inductor, 217

Trimming

integrated capacitors, 131

integrated resistors, 52, 341

specification limits, 342

Tunneling, 43

UL certification, 346

University of Arkansas, 137

INDEX 379

Unscheduled maintenance, 338

Valve metals, 117

Voltage coefficient of resistance, definition,37

Voltage-controlled oscillator, 9, 235

Voltage dividers, 297

WLAN receiver, 308

X7R, 91

Yield issues, 11, 22, 147

enhancement strategies for capacitors,150

testing for, 343

Documents

Integrated Passive Component Technology