s t resses appl ied t o ch ips I - _

dur ing assembly and

Such test dies range from Te s t C h i D s packaging.

single purpose chips to multi- A

sensor ( in tegra ted) des igns . Typical transducer sets conta in (1 ) a resistor pattern and temperature-reading diodes for Improve measurement of the

h e a t - d i s s i p a t i o n properties of a IC Assembly package; (2) moisture,

Test dies integrated with a

semiconductor wafer effective 1 y

gauge environmental

stresses during the packaging and

processing phases

James N. Sweet

porated in semiconductor wafers f o r monitoring complex IC fabrication have gone a long way towards improving the overall process technology. Less well known but equally as valuable are the test

September 1990

- corros ion , and ion-

detection transducers to measure the threat of corrosion; and ( 3 ) surface-conductor serpentines and stress sensors to quantify mechanical abuse.

These transducers help production engi- neers address a basic irony of semiconduc- tor packaging. Packaging a semiconductor chip is meant to protect it from environ- mental insults, as well as to provide a convenient way of connecting it to other c i rcu i t e lements . Unfortunately, the stresses a chip experiences during the mechanica l assembly a n d packaging process can contribute to its failure. To complicate the situation further, failures of packaged ICs caused by these stresses can arise from faults on the semiconductor c h i p rather than f rom actual d a m a g e introduced dur ing the packaging and assembly processes , o r f rom a combination of the two.

Testing for What? Integrated-circuit (IC) manufacturers try to produce highly reliable assembled parts. To verify their reliability, packaged ICs are tested in a variety of ways. Screening tests at Sandia National Laboratories on pack- aged CMOS ICs, for example, are per- formed using a one week bum-in at 150°C with a supply voltage equal to 1.2 times the nominal voltage.

Tests such as these may detect weak or marginal members of an IC population, bu t they a r e not espec ia l ly useful in accelerating and subsequently detecting many types of failures that might occur

only after prolonged operation or storage of a part. One event of this type is an open circuit in a metal conductor line caused by a failure in the IC’s passivating glass overcoat, coupled with the presence of moisture and an ionic contaminant such as Cl+. Such failures can be detected and studied with specially designed test chips that are operated in extreme conditions.

Failures of packaged ICs are either chip- centered or package-centered (Fig. 1 ) . Chip-centered failures are associated with a chip malfunction associated with prob- lems in wafer fabrication or ex t reme conditions during ch ip operation. One fabrication-related failure is a defect in the gate oxide of an MOS device caused by contamination. An operationally induced failure that depends on chip properties is electromigration-caused damage of a thin- film metal conductor resulting from exces- sively high current density.

Failures associated with the package do not depend on details of the chip-fabrica- tion process. One example is a wire-bond break caused either by improper bonding or defective wire. But the largest number of failures are associated with defects on the die that may not be fatal in themselves, but become so when aggravated by some defect in the package or packaging materi- al. The corrosion failure mentioned previ- ously is an example. For corrosion to occur at a metal conductor on a chip, there must be a path t o the metal f rom the outside world. Such a path occurs only when there is a failure of the package’s “sealing structure” and, in most cases, also a fault in the chip’s passivation layer.

Special-purpose assembly test chips (ATCs) a r e des igned primarily f o r studying failures of the package-centered and composite types. These chips usually provide a way to stress the die, and they include transducers for monitoring the die’s response to the stress. A variety of structures have been used to measure parameters assoc ia ted with package- related failures (Table I).

Corrosion Detectors The vast majority of integrated circuits manufactured today use thin-film alumi-

87553996/90/0900-0039$1 .OO 0 1990 IEEE 39

I _ _

ure Modes - Packaged ICs

\ i Electromigration Lithographic Error -

IGate Oxide Defect1

. There are two kinds of failure modes for packaged ICs. Chip-related failures stem from errors in wafer fabrication or chip design. Package-related failures are caused by defects in the package or in the assembly process. Failures in the overlap region are caused by both package and chip defects or by interrelated chip-package problems.

num conductors to interconnect circuits defined on a silicon chip. Corrosion of the aluminum in the presence of moisture and ionic contaminants such as Cl" has been a serious and often-studied problem in IC manufacturing [ I ] .

Aluminum corrosion can usually be accelerated by applying 2 0 to 40 volts between adjacent conductors, and this gives rise to the most common structure used to study aluminum corrosion: the triple-track conductor pattern (Fig. 2 ) . Three serpentine conductor lines are used, with the outer lines biased at voltages equal in magni tude a n d somet imes opposite in sign relative to a grounded central conductor. Periodically during a test, the resistance of each line and the l ine-to-line leakage conductances are monitored.

Another useful structure is the "ladder" circuit, a group of equal-resistance metal lines connected in parallel between two "bus-bars.'' These lines corrode and pro- duce open circuits during life testing. so the structure resistance increases in a step- wise fashion. T h e resistance-vs.-t ime

curve yields information on the kinetics and statistical variability of corrosion failure.

Accelerated life tests on non-hermetic packaged ICs are usually conducted under conditions of high temperature, high hu- midity. and high bias voltage"frequent1y referred to as Temperature-Humidity-Bias (THB) tests. With the high quality of present-day chip-surface passivation layers and package encapsulation materials, these tests must be run for many thousands of hours to produce failures in 50% of the test population. As a result, more highly accelerated tests are now conducted in pressure vessels at temperatures in excess of 100°C and with humidities in the range 60-100 RH. These highly accelerated stress tests (HASTs) typically produce failures in hundreds of hours or less, so a test engineer can provide rapid feedback to the designer on the performance of the materials under test. Although actual IC circuits in non-hermetic packages are being eva lua ted with HAST [3], it is frequently difficult to determine exact fa i lure modes with the technique .

SpecialiLed corrosion-test circuits are more useful in characterizing failures of protective coatings on integrated circuits.

Moisture Detectors Moisture-or humidity-detectors $ense the presence of low-to-moderate levels of water vapor. S G S - T h o m s o n ' s mul t i - function test chip has a metal corrosion fuse biased at about 5 V with respect to nearby metallization at ground potential 1281. The fuse structure is located above a layer of glass with high phosphorous content (about eight percent). When liquid water is present. phosphoric acid forms and the fuse rapidly corrodes [4].

Other moisture sensors monitor surface- conductivity changes in the presence of condensed water. One example measures the increase in leakage current between interdigitated aluminum conductors when water condenses in the region between the fingers 151. The condensation is produced by cooling the part under study below its dew point. The sensor functions properly only if water condenses in the interdigitat- ed region, so this technique works only if the moisture content is very high.

With the advent of tight moisture control in IC packages there has been renewed interest in measuring moisture levels at a few parts per million by volume. (At 2 0 ° C 1% relative humidity corresponds to an water concentration of about 180 parts per million by volume). These moisture levels are too low to be detected reliably by surface-conductivity devices.

Fortunately, two types of capacitive device can detect low concentrations of water vapor. The devices utilize dielectric materials that can absorb water vapor, producing a capacitance change-and sometimes a resistance change-in the process.

The simplest of these sensor types incor- porates a dielectric that absorbs water quasi-randomly throughout its volume. Since the relative dielectric constant of water is about 80 and that of insulating materials commonly used in ICs is less than 10, the addition of relatively small amounts of water can frequently be detect-

Circuits and Devices 40

ed. Polyimide capacitors can double their capacitance as the RH varies from I O to 100 percent [6].

A more sensitive detector can be made with dielectrics, such as a porous alumi- num trioxide film formed by anodizing aluminum in an acidic electrolyte, and that have thin needle-like pores oriented parallel to the electric field [7] . T h e capacitance in this type of sensor can change by several orders of magnitude as the relativehumidity varies from zero to 100 p e r c e n t . T h i s s o m e w h a t myster ious behavior occurs because water that condenses is held in the pores by capillary actions. The water in the pores acts as an array of conducting nee- dles that can easily be polarized by an electric field. The electrical conductivity o f the w a t e r a c c o u n t s f o r the l a r g e

September 1990

change in capacitance with increasing moisture level.

Drift and lack of reproducibility are potential problems with porous-dielectric sensors [8], possibly through intermittent plugging of the pores or contamination the porous meta l l ic top e lec t rode . Nonetheless, aluminum trioxide moisture sensors have been used in microcircuit packages, with careful attention paid to variations of the sensor calibration curve with the sensor's thermal history [9].

The authors of this article recently cali- brated a commercial sensor (Fig. 3). The initial calibration was performed on an as- received sensor in die form. The die was then wire-bonded to a ceramic hermetic package and passed through a belt sealer with a dummy lid (no solder). The sealer had an nitroeen atmojphere and a peak

temperature of approximately 420°C. This operation produced a pronounced shift in the ca l ibra t ion , as d id a second pass through the sealer and a pass through a different sealer in an air environment. Finally, the open package was left sitting in the lab for a few days before we ob- tained the final calibration curve. These data show that a capacitance shift from an initial value of 100 pF to 200 pF or greater i s indicative of the presence of moisture, but that the actual moisture level can be anything from 1000 to 6000 ppmv. We are continuing our studies of aluminum triox- ide moisture sensors and we are currently integrating one into a multisensor silicon assembly test chip.

Mechanical stress sensors The application of excess mechanical stress to a d ie dur ing packaging can produce d ie fa i lure d u e to c racks or breakage. Excess stress levels are most likely to occur during die attachment or the encapsulation and molding of plastic- packaged ICs [10-15]. Since mechanical stress i s so important in packaging, chip fabricators have been interested in making stress measurements on a die surface for years. Many types of special-purpose stress and strain sensors have been proposed but most requi re special processing "s uc h a s mi c rom ac h i n i n gor etching of free-standing structures"not normally associated with IC fabrication [16]. An exception is the piezoresistive s t ress sensor, which incorpora tes a material whose resistivity change with stress [ I l l . Silicon and germanium exhibit large piezoresistive effects [ 171.

A general measurement of stress requires measurement of three compressive (or tensile) stresses, one along each coordinate axis, and three shearing stresses associated with a rotation or moment about each axis. Only three parameters or matrix elements are needed to completely determine the resistivity response to stress for cubic crystals like silicon [ 171. Typically, the fractional resistance changes are small for stresses that are large relative to the break- iny stress of silicon (about 350 MPa). A

41

-v Vdts

I

2. This aluminum “triple track” corrosion test structure works in two ways. Corrosion can produce either an open in one of the tracks or high leakage current between tracks. The tracks can be biased relative to one another to accelerate electrochemical corrosion.

measured fractional resistance change of 2 percent corresponds to about 30 percent of this breaking stress, so accurate measure- ment of typical packaging-induced stresses requires that small resistance changes be measured.

The stress sensor used by SGS-Thomson consists of three resistors formed with a common junction (Fig. 4). The resistors along the die edges are laid out with their edges in the (110) and ( i l 0 ) crystal direc- tions, while the diagonal resistor is in a (100) direction. It can be shown that a measurement of the series resistance of the [110] and [ilO] resistors yields a relative change in resistance proportional to the sum of the principal stresses [19]. As a result, L-shaped piezoresistive stress sen- sors are frequently used to make measure- ments because they respond in some ap- proximate way to the magnitude of the stress at their location. They can also be used to measure the relative stress levels for different molding compounds or die attachment techniques, which may be their most useful feature.

42

Recently described piezoresistive stress sensors can yield more quantitative results than earlier designs. Hitachi has fabricated a chip with both p- and n-type resistors and a diode thermometer [20]. The ther- mometer is used for temperature calibration of the resistors. Phillips [21] has described a chip with up to 128 strain- gage arrays of four resistors each, with on- chip addressing. The use of four-point bending experiments to calibrate the gauge represents a new advance in quantitative stress measurement on silicon.

The resist ive stress sensor is the industrystandard, but an MOS transistor is a potentially useful alternative. An MOS transistor has a drain current which is proportional to the e f fec t ive carrier mobility in an inversion layer and the charge per unit area in the layer, both of which are sensitive to strain [22, 231. Based on mobility arguments, the stress sensitivity of resistors and transistors should be the same since both vary directly as the mobility. The advantage of transistors is that they can be used to

fabricate sensitive bridge circuits. Initial circuits have exhibited drift problems, but the approach is promising [24].

Mobile ion sensors Mobile ions such as Na+ and K+ can cause large shifts in the threshold voltage of MOS devices [25]. Although current c h i p passivation materials such as phosphosilicate glass and silicon nitride can effectively seal MOS transistor gates, high reliability requires that mobile-ion concentrations in the package be kept as low as possible. Mobile-ion sensors use the MOS threshold-voltage sensitivity to make their measurements.

The mobile-ion sensor in the SGS-Thom- son ATC has two MOS transistors with a common source (Fig. 5). The passivation above one of the transistor’s gate metal- lization has holes cut in it. Mobile ions introduced through these holes can migrate to the gate oxide where they move to either the metal-oxide or the silicon-oxide interfaces under the influence of tempera- ture and a steady-state gate bias voltage. The resulting shift in threshold voltage can be determined, for example, by measuring the difference in the two transistors’ drain voltages when both have the same drain current and gate voltage.

Thermal resistance Thermal resistance is the temperature rise

on the chip’s surface per unit power input ( “ C / W ) , where the temperature is measured relative to some base temperature, such as a case or a board temperature. It differs from the other measurement quantities in Table I because it is associated with a package, package- assembly technique, and sometimes, the package environment. It is not associated with deterioration or contamination. But a knowledge of thermal resistance is required for new package designs, and thermal-resistance measurement circuits can be part of a packaging test chip. When determining thermal resistance, a resistive heater supplies the input power and a diode or the base-emitter junction of a bipolar transistor measures the tempera-

Circuits and Devices

ture 1261. The SGS-Thomson chip uses a diffused resistor heater formed in a mean- der pattern and has a centrally located temperature diode. A portion of the heater track is visible in Fig. 5 under metal lines used for surface-damage detection. A commercially available Texas Instruments thermal test c h i p has four banks of diffused resistor heaters and two diodes, one in the center and one at the die edge.

Although most thermal test chips have used diffused resistors for heating, they are not the only possibility. Polysilicon heaters would facilitate the integration of thermal test functions with the other functions of an ATC. Having a heater and diode thermometer on an integrated ATC also would also facilitate self-heating experiments with the moisture and mobile- ion sensors.

Multifunction test chips Most of today’s assembly test chips were designed to study the die’s response to only one type of stress. But in many cases mu1tifunction”or integrated’assembly test chips would be desirable for studying combined failure modes under extreme conditions. An appropriate multifunction chip could also become a standard, high- volume ATC for routine environmental testing. There has been little effort until recently to develop an integrated ATC that includes most or all of the elements listed in Table I , probably because the different quantitie5 listed in the first column of the table are studied by different development group5 at most companies. For example, package designers (mechanical engineers) usually make thermal resistance measure- ments in the course of package design. while chemical engineers (who design plastic-encapsulation techniques) make stress and chip-damage measurements.

A combined stress-and-corrosion test chip has been described by a group at Texas Instruments [27], but this chip is not commercially available. Martin Marietta and Tandem Computer, among others, have also fabricated multifunction ATCs for internal use. SGS-Thomson’s integrated assembly test ch ip is

September 1990

550

500 j, a 450

400

5 350

5 300 0

250

W

$ 200

150

100

0 Initial Calibration AAfter N2 Seal UAfter 2nd N2 Seal V After A i r Seal

1

After sitting in Lab / // , ’ ’ j

f ’ 0 2000 4000 6000 8000 1 E4

1

Moisture (PP Mv)

!. Capacitance vs. moisture content (in parts per million by volume) for a commercial aluminum trioxide moisture sensor. The shifts in the calibration curves were produced by various sealing and thermal-cycling procedures.

commercially available [28]. This chip has structures for measur ing most of the quantities in Table I, with an emphasis on surface damage.

At Sandia, we are developing an integrat- ed ATC in our IC fabrication facility that will be used for long-term package-relia- bility studies. This chip will include all of the transducers listed in Table I .

Con c I u s i o n As IC design lifetimes increase, operating conditions become more severe, and cost and size cons idera t ions lead to an increased use of organic chip coatings, there will be an increasing need for monitoring and testing at the package level. Test chips with the sensors we‘ve descr ibed will be important too ls i n conducting these studies. The development of standard multifunction assembly test chips will al low better correlation of results between different experimenters and between different fabrication facilities.

References I . G. L. Schnable, et al., “A Survey of Corrosion Failure Mechanisms in Micro- electronic Devices.” RCA Review, 40, p.

416, 1979. 2. J. E. G u m , et al., “Highly Accelerated Temperature and Humidity Stress Test Technique ( H A S T ) , ” 19th Annual Proceedings Reliabil i ty Physics Symposium, p. 48, 1981. 3. D. Danielson, et al., “HAST Applica- tions: Acceleration Factors and Results for VLSI Components,” 27th Annual Proceed- ings Reliability Physics Symposium, p. 1 I , 1989. 4. W. M. Paulson, R. W. Kirki, “The Ef- fects of Phosphorous-Doped Passivation Glass on the Corrosion of Aluminum,” 12th Annual Proceedings Reliability Phys- ics Symposium, p. 172, 1974. 5. D. Kane, M. Brizoux. “Recent Develop- ments on Moisture Measurement by Sur- face Conductivity Sensors,” 24th Annual Proceedings Reliability Physics Synipo- sium, p. 69, 1986. 6. M. C. Glenn, J . A. Schuetz. “An IC Compatible Polymer Humidity Sensor.” Transducers ‘ 8 5 , 1985 International Con- ference on Solid-state Sensors and Actua- tors; Digest of Technical Papers, IEEE. p. 217, 1985. 7. V. K. Khanna, R. K. Nahar, “Effect of Moisture on the Dielectric Properties of

43

4. This stress sensor is used on the SGS-Thomson “BERTC” integrated packaging test chip. The arms ofthe “L”are laid out in c110> directions, while the diagonal resistor is in a c 1 OO> direction. The light colored regions are AI metal, while the darker lines are diffused n-type regions forming resistors. If only planar stresses are present, the “L” resistance should be proportional to the sum of the principal stresses. On the right of the figure is the moisture detector. The dog-bone-shaped aluminum region in the center is biased with respect to the surrounding aluminum ring.

by Plast ic Packages,” 19th Annual Proceedings Physics Symposium3 p’ 74’ 1981. 12. D. R. et ‘Shear Stress Evaluation of Plastic Packages,” IEEE Trans. Components, Hybrids, Manufac. Technol., CHMT-12, p. 619, 1987.

Rel iabi l i ty

13. B. Natarajan, B. Bhattacharyya, “Die Surface Stresses in a Molded Plastic Pack- age,” 36th Electronic Components Confer- ence Proceedings, p. 544, 1986. 14. P. Lunds t rom, K . Gustafsson, “Mechanical Stress and Life for Plastic- Encapsulated, Large-Area Chip,” 38th Electronic Components Conference Proceedings, p. 396, 1988. 15. E. Suhir, “Thermal Stress Failures in Microelectronic Components’.Review and Extension,” in A. Bar-Cohen, A. D. Kraus, Advances in Thermal Modeling of Elec- tronic Components and Systems. Vol. I , Hemisphere, NY, p. 337, 1988. 16. J. C. Greenwood, “Silicon in Mechani- cal Sensors,” J. Phys. E: Sci. Instrum., 21, p. 1114, 1988. 17. C. S. Smith, “Piezoresistance Effect in Germanium and Silicon,” Phys. Rev., 94,

5. In this SGS-Thomson MOS mobile-ion sensor, the dual-gate electrode is powered from the corner bondpad, while the drains are connected to the pads on either side of the gate pad. The common source is powered from the third pad from the left on the top. “Windows” are opened through the p-glass over one of the gates to allow mobile ions to enter into the gate-oxide region of the associated MOS transistor.

44 Circuits and Devices

p, 42, 1954.18. 0. N. Tu+, E. L. Stelzer, ~~Piezores i s t ive Properties of Silicon Diffused Layers3” J. 34i p. 313, 1963.

19. W. G. Pfann, R. N. Thurston, “Semi- conducting Stress Transducers Utilizing the Transverse and Shear Piezoresistance Ef- fects,” J. Appl. Physics, 32, p. 2008, 1961. 20. H. Miura, et al., “Development and Application of the Stress Sensing Chip for IC Plastic Packages,” 64th Annual Meeting, Japan Society of Mechanical Engineers, 1967. 21. S. A. Gee, et al., “The Design and Calibration of a Semiconductor Strain Gauge Array”, 1988 IEEE Proc. on Micro- electronic Test Structures, 1-1, p. 185, 1988. 22. H. Mikoshipa, “Stress-Sensitive Proper- ties of Silicon-Gate MOS Devices,” Solid State Electronics, 24, p. 221, 1981. 23. A. P. Dorey, T. S. Maddem, “The Effect of Strain on MOS Transistors,” Solid State Electronics, 12, p. 185, 1969. 24. A. P. Dorey, “A High Sensitivity Semi- conductor Strain Sensitive Circuit,” Solid State Electronics, 18, p. 295, 1975. 25. R. F. Pierret, “Field Effect Devices,” Vol. IV in Modular Series on Solid State Devices, Ed. by R. E Pierret and G. W. Neudeck, Addison Wesley, NY, p. 64-67, 1983. 26. E E Oettinger, “Thermal Evaluation of VLSI Packages Using Test Chips, a Critical Review,” Solid State Technology, p. 169, Feb. 1984. 27. D. R. Edwards, et al., “Test Structure Methodology of IC Package Material Char- acterization,’’ IEEE Trans. Components, Hybrids, Manufactr. Techno]., CHMT-6, p. 560, 1983. 28. T. Turner, “Advanced Test Structures for Fab and Assembly,” in 1987 Wafer Reliability Workshop, ASIC Manufacturing, 0. D. Trapp, editor, p. 213, sponsored by Stanford Electronics Laboratories, Stanford, CA,(available from Technology Assoc., 5 1 Hillbrook Dr., Portola Valley, CA, 94025.

Biography James N. Sweet [MI is a Distinguished Member of the Technical Staff at Sandia National Laboratories in Albuquerque, New Mexico. He is responsible for the design and development of assembly test chips and for the development of non- hermetic packaging technology for high- reliabil i ty applications. CD

September 1990

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