Introducing Fault Testing in Dsch version 3 - INSA Toulousesrv-sicard/microwind/test-dsch35.pdf · This document introduces the concept for fault simulation at logic level in Dsch35

DSCH APPLICATION NOTE Fault Testing in Dsch

Page 1/18) [email protected] 12/01/10

Introducing Fault Testing in Dsch version 3.5

Etienne SICARD Professor

INSA-Dgei, 135 Av de Rangueil 31077 Toulouse – France

www.microwind.org

email: [email protected]

Belgacem HAMDI Assistant Professor

Electronic Laboratory, ISSAT Monastir – Tunisia

email: [email protected]

This document introduces the concept for fault simulation at logic level in Dsch35. The mechanisms

for logic fault injection, simulation and optimum test vector extraction are described. The testing

features of Dsch35 are illustrated with a set of logic designs.

1 INTRODUCTION

Design of logic integrated circuits in CMOS technology is becoming more and more complex since

VLSI is the interest of many electronic IC users and manufacturers. A common problem to be solved

by designers, manufacturers and users is the testing of these ICs. In this application note, we introduce

the concept of fault, concentrate on stuck-at-0 and stuck-at-1 hypothesis, and show how these faults

may appear. Then, using DSCH, we show how to build a reference truth-table, and how to simulate

these faults applied to input and output nodes of the circuit under test. We investigate how test patterns

detect these faults. The ultimate goal is to classify the efficiency of test patterns, in order to select the

most efficient test vectors, and therefore reduce the number of test patterns.

1.1 Testing an IC

Testing an integrated circuit can be expressed by checking if its outputs correspond to the inputs

applied to it. If the test is positive, then the system is good for use. If the outputs are different than

expected, the IC is rejected (Go/No Go test). A diagnosis may be applied to it, in order to point out

and identify the problem's causes.

Testing is applied to detect faults after several operations: design, manufacturing, packaging, as

illustrated in figure 1. If a test strategy is considered at IC level, the fault can be detected at early

system design stages, located and eliminated at a very low cost. When the faulty chip is soldered on a

printed circuit board, the cost of fault remedy would be multiplied by ten. And this cost factors

continues to apply until the system has been assembled and packaged and sent to final users, as

illustrated in Figure 2.



Probe Test Packaging

Marking Final Test Visual

inspection

Sample Test

Shipping

IC fabrication

Figure 1: typical IC production flow

This cost factors continues to apply until the system has been assembled and packaged and then sent to

users.

Chip level

Sub-system level

Board level

10

1

100

Test cost

System level

Figure 2: Test cost (The rule of ten)

The first idea to test an N input circuit would be to apply an N-bit counter to the inputs

(controllability), then generate all the 2N combinations, and observe the outputs for checking

(observability). This is called "exhaustive testing" (Fig. 3), and it is very efficient, but only for few-

input circuits. However, this technique becomes very time consuming when the input number

increases. Given a set of faults in the circuit under test (CUT), our goal is to obtain the smallest

possible number of test patterns which guarantees the highest fault coverage. Test compaction refers to

the process of reducing the number of test patterns in a test set without reducing its fault coverage.



Exhaustive testing

N inputs 2N Combinaisons

100 MHz tester: 32 inputs 0,7 Minutes

40 inputs 3 Hours 64 inputs 58 Centuries!!

Figure 3: The exhaustive testing time becomes prohibitive with a large number of IC inputs

A test pattern (or test vector) for a fault f in a circuit C is an input combination for which the output(s) of C is different when f is present than when it is not (Fig. 4).

Faulty system

Test pattern 1)()( =⊕ xCxC f

Fault free system

Fault

Figure 4: A test pattern detects a fault if the fault free response is different from the faulty response.

A test vector x detects fault f if: C(x) ⊕ Cf(x) = 1 Where: C(x) is the response of the fault free circuit, and Cf(x) is the response of the faulty circuit.

1.2 Fault Testing

1.2.1 Fault model

Failure modes are manifested on the logical level as incorrect signal values. A fault is a model that

represents the effect of a failure by means of the change that is produced in the system signal. Several

defects are usually mapped to one fault model, and it is called a many-to-one mapping. However,

some defects may also be represented by more than one fault model. Fault models have the advantage

of being a more tractable representation than physical failure modes. It is possible to mark most

commonly used fault models (Table 1).



Fault Model Description

Single stuck-at faults

(SSF)

One line takes the value 0 or 1.

Multiple stuck-at faults

(MSF)

One, two or more lines have fixed values, not necessarily the same.

Bridging faults Two or more lines that are normally independent become electrically

connected.

Delay faults A fault is caused by delays in one or more paths in the circuit.

Intermittent faults Caused by internal parameter degradation. Incorrect signal values occur for

some but not all states of the circuit. Degradation is progressive until

permanent failure occurs.

Transient faults Incorrect signal values caused by coupled disturbances. Coupling may be

via power bus capacitive or inductive coupling. Includes internal and

external sources as well as particle irradiation.

Table 1: Most commonly used fault models

As a model, the fault does not have to be an exact representation of the defects, but rather, to be useful

in detecting the defects. For example, the most common fault model assumes single stuck-at (SSF)

lines even though it is clear that this model does not accurately represent all actual physical failures.

The rational for continuing to use stuck-at fault model is the fact that it has been satisfactory in the

past. In addition, test sets that have been generated for this fault type have been effective in detecting

other types of faults. However, as with any model, a fault cannot represent all failures. Further will be

discussed a bit closer the fault models that have been brought in Table 1.

1.2.2 Stuck-at-faults

As it was mentioned earlier, a single stuck-at fault (SSF) represents a line in the circuit that is fixed to

logic value 0 or 1.

We consider here permanent faults that are faults that are continuous and stable, whose nature do not

change before, during, and after testing. These faults are affecting the functional behaviour of the

system permanently. These faults are usually localized and can be modeled. Other faults such as

temporary faults or intermittent faults are not considered in this application note.



Fig. 5 illustrates a possible origin for a node stuck at 0 voltage: the implementation is close to a VSS

node (here situated close, same layer), and a faulty metal bridge makes a robust connection to the

ground.

Designed interconnects

Fabricated interconnects with stuck-at-0 fault

Bridge

Node under test

VSS

Figure 5: Physical origin of a node fault stuck at 0.

There are several ways to nominate stuck-at faults, all having the same meaning. Considering a node

N, the fault “stuck-at 0” may be written:

N s-a-0, N s/0, N/0 or N@0

In DSCH, we shall use “N@0” for node N stuck-at 0 and “N@1” for node N stuck-at-1.

1.2.3 Other faults

The manufacturing of interconnects may result in interruptions or short-cuts, which may have

catastrophic consequences on the behavior of the integrated circuit. Fig. 6 illustrates the case of

“Open” and “Short” faults, not considered in DSCH for fault simulation.

Designed interconnects

Open fault

No connection Short-cut

Short fault

Figure 6: Physical origin of the “Open” and “Short” fault

Many other faults are also considered in the literature: transistor stuck-on and stuck-open faults

interconnect transition and delay faults, etc... These faults are not considered in this work.

Independent of how accurately the stuck-at fault represents the physical defect, we next continue

investigating how to generate patterns that detect these faults.



1.2.4 Testing and fault coverage

Testing is the process of determining whether a device functions correctly or not. The question is how

much testing of an IC is enough?

The Yield (Y) is defined as the ratio of the number of good dies per wafer to the number of dies per

wafer.

Fault coverage (FC) is the measure of the ability of a test set T to detect a given set of faults that may

occur on the DUT (Device Under Test). We shall try to achieve FC=1, that is a fault coverage of

100%.

FC= (#detected faults)/(#possible faults)

1) Defect level and fault coverage

Defect level (DL) is the fraction of bad parts among the parts that pass all tests. DL= 1 –Y(1-FC)

Where FC refers to the real defect coverage (probability that T detects any possible fault in F or not)

and DL is the DPM (defects per million). Typical values claimed are less than 200 DPM, or 0.02%.

2 Test Module in DSCH

2.1 Getting started

In DSCH version 3.5, build a simple circuit as shown in Fig. 6, including 2 inputs and one output, and

click “Simulate”→ “Logic Circuit Testing”.

Figure 7: Getting started with DSCH

The screen shown in Fig. 8 corresponds to the construction of the reference truth-table. In the table

situated in the left part of the screen, all inputs and outputs are displayed, and the input values are pre-

positioned. In the case of the AND gate, two inputs A and B are listed. DSCH always classifies inputs



by alphabetic order, followed by outputs also classified by alphabetic order. At this stage, the value of

the output is not yet computed and available.

Figure 8: Building the reference truth-table (test/And2_test.SCH)

Click “Logic Simulation”, click “Chronograms” to see how DSCH has simulated the circuit: clocks

have been automatically assigned to inputs, with period multiplied by 2 in order to cover the whole

truth-table in one single simulation. Click “Extract Truth-table” to feed the table with the values

obtained in the chronograms of the circuit logic simulation (Fig. 9).

Figure 9: Computing the reference truth-table from logic simulation (test/And2_test.SCH)



Click “Next”. The tool moves to 2nd section “2- Inject Fault”. The menu shown in Fig. 10 corresponds

to the fault injection. Select the type of fault (stuck-at-0, stuck-at-1, both), the nodes on which these

models will be applied and the output considered for test. By default, s@0 is applied to all inputs, and

the first output declared in the list is observed. Click “Generate Faults” to list the desired faults in the

test vector grid situated on the left of the screen. Notice that each column corresponds to one test

vector. As we have 2 inputs, we have 4 columns, each corresponding to one test vector for inputs AB,

respectively 00, 01, 10, and 11. The two faults considered here are A@0 and B@0.

Figure 10: Define the type of fault and the nodes of interest (test/And2_test.SCH)

Figure 11: Two logic simulations are necessary to extract the response to the A@0 and B@0 faults (test/And2_test.SCH)



In order to compute the response of the circuit to the A@0 and B@0 faults, proceed as follow:

- Click “Simulate fault n°1 – A@0”. Click “Chronograms” to see the response. The node A is stuck-

at-0, and consequently, the output C is 0.

Node A “Stuck-at-0

Figure 12: Chronograms showing the node A stuck-at-0 (test/And2_test.SCH)

- Click “Extract Fault Response”. The logic values are transferred to the corresponding line.

- Click “Simulate fault n°2 – B@0”.

- Click “Extract Fault Response”. The circuit response to the 2nd fault is also transferred, as shown in

Fig. 13.

Figure 13: Response of the circuit to A@0 and B@0 (test/And2_test.SCH)

By selecting “Stuck-at 0 & stuck-at 1”, and applying it to Inputs & Outputs, we obtain the following

response to the 6 faults:



Figure 13: Response of the circuit to all possible stuck-at faults (test/And2_test.SCH)

Figure 14: Detection score for all test patterns (test/And2_test.SCH)

Click “Next”. The tool moves to 3rd section “3- Analyse Vectors”. Click “Highlight Detection

Vectors”. From the results computed in Fig. 14, we may see that not all test vectors have the same

detection efficiency. The test vector <11> (last column) is able to detect 4 faults upon the total of 6.

This means that applying 11 to inputs A,B leads to a result on C different from the reference logic

value 1 (line “C(Fault-Free)”, which enables the test vector 11 to alert the user from the possibility of

4 possible faults: A@0, B@0, B@1, C@0. All faults may be tested (100% coverage) using three

vectors: 01, 10 and 11.



3 Case studies

In this section we investigate the testing of two circuits, a Nand-Or combination and a full-adder.

3.1 Nand-Or Circuit

The Nand-Or circuit is a simple combination of a 2-input NAND gate and a OR gate. The concept of

manual fault injection is presented in figure 15. The fault injection at a node N consists in opening the

connection and inserting a multiplexor circuit. An example of s@0 and s@1 injection circuit is

proposed, based on two multiplexors, one for fault/no_fault, the second for s@0/s@1. A practical

implementation in DSCH is reported in Fig. 16.

X

C

B

A

out Fault

injection

Vss

X (normal data)

Y

Vdd

s@0/s@1

Fault injection Mode

Y

Figure 15: Fault injection principles

Figure 16: Manual fault injection in a circuit (test/NandOr_fault.SCH)



s@0 fault injection

s@0 fault injection

Fault Injection=0: Normal Function Mode

Fault Injection=1: Test Mode

A

B

C

Fault injection

Fault type

Out

Figure 17: Simulation (test/NandOr_fault.SCH)

Figure 18: Computing the reference truth-table from logic simulation (test/NandOr_test.SCH)

The NandOr circuit has 5 nodes, therefore 10 possible stuck-at faults, if we also consider the internal

node linking the NAND2 output to the OR input.

- Click “File”→ “Open” and select “Test\NandOr-test.sch”

- Click “Simulate”→ “Logic Circuit Testing”.

- Click “Logic Simulation” and “Extract Truth-table” to feed the table with the values obtained in the

chronograms of the circuit logic simulation (Fig. 18).

- Click “Next”. The tool moves to 2nd section “2- Inject Fault”.

- In the parameter menu, Select the type of fault “s@0 & s@1”, and apply it to “All nodes” (Fig. 19).



Figure 19: Computing the response to fault injection (test/NandOr_test.SCH)

- Click “Generate Faults” to list the desired faults in the test vector grid.

- Click “Simulate fault n°1 – A@0”. Click “Chronograms” to see the response.


- Repeat the last two steps until the table is completed (Fig. 19).

- Click “Next”. The tool moves to 3rd section “3- Analyse vectors”.

- Click “Highlight Detection Vectors”. The result is shown in Fig. 20.

Figure 20: Vector detection efficiency(test/NandOr_test.SCH)

- The vector 110 detects A@0, B@0, C@1 and NandOr@1 (4/8 faults).

- The vector 100 detects B@1 and NandOr@0 (2/8 faults).

- The vector 010 detects the fault A@1.

- The vector 111detects the remaining fault C@0.



Therefore 4 test vectors (010, 100, 110, 111) detect all stuck-at faults (test time will be the half of an

exhaustive test).

3.2 Full-Adder Circuit

The Full-adder circuit proposed in Fig. 21 includes 3 inputs and 2 outputs. Its implementation is based

on XOR and NAND gates.

Figure 21: Full-adder based on XOR and NAND gates (test/Fadd_test.SCH)

The procedure for fault injection and analysis is as follows:

- Click “File”→ “Open” and select “Test\Fadd-test.sch”

- Click “Simulate”→ “Logic Circuit Testing”.

- Click “Logic Simulation” and “Extract Truth-table” to feed the table with the values obtained in the

chronograms of the circuit logic simulation (Fig. 22). Click “Chronograms” to observe the logic

simulation that serves as a reference to fill the truth-table. Notice the delay due to logic gates that

desynchronizes the signals.



Figure 22: Computing the reference truth-table from logic simulation (test/Fadd_test.SCH)

- Click “Next”. The tool moves to 2nd section “2- Inject Fault”.

- In the parameter menu, Select the type of fault “s@0 & s@1”, apply it to “All nodes”, and select

the output “Sum” (Fig. 23). The fault-free value is reported in the second line of the table. The first

line corresponds to the 8 test vectors. We have 10 possible faults.

Figure 23: Vector detection efficiency (test/Fadd_test.SCH)

- Click “Generate Faults” to list the desired faults in the test vector grid.

- Click “Simulate fault n°1 – A@0”. Click “Chronograms” to see the response.


- Repeat the last two steps until the table is completed.

- Click “Next”. The tool moves to 3rd section “3- Analyse vectors”.

- Click “Highlight Detection Vectors”. The result is shown in Fig. 25.All vectors reach the score

4/10 (See Fig. 23).

Therefore 2 test vectors detect all stuck-at faults (for example 000,111), except Carry@0 and Carry@1

which are not in the same path. The best fault coverage is 80%.



4 Fault injection in Microwind3: Layout level

We prospect to continue this work with a module for fault injection at the layout level using

Microwind3. The idea is to model the failure with a spot (at a specific layer) and then move it on the

layout, simulate with SPICE and observe its effect on the electrical behavior of the circuit in

comparison with the defect free circuit (reference).

The idea of the spot is good; however, it can be hard to implement. We can replace the spot by “a short

resistance” to simulate bridging faults from open circuit (infinite resistance) to short circuit (zero

resistance) especially as this is possible with Microwind3 because it allows the insertion and

simulation of passive elements in a layout. We suggest therefore, that the fault injection at the layout

level follows next steps:

1. Set up to electrical level from the layout (designed on Microwind3) by using the SPICE file

extracted from layout.

2. Consider fault models on this level of abstraction that are stuck-on/open MOS and / or bridging

faults.

3. For MOS on/open, we just have to short/cut Drain to/from Source of the MOS transistor.

4. For resistive short between two nodes in the circuit (bridging faults), we can treat only likely defects

(2 neighboring nodes of the same layer, breaking contact metal / poly ...). This list of faults can be

generated before the injection of defects or specified by the designer (for a given technology).

5. Placing a resistor (which models the default) between two nodes and to simulate values (few ohms:

shorts) to infinite value (open). This is achievable through the command "parametric analysis" of

Microwind3.

6. Finally, to analyze the effect of each defect, IDDQ current can be used to determinate incorrect

function. This analysis can be done by the designer or automatically by the tool, in order to classify

defects by type: catastrophic / Parametric / logic.

5 Conclusion

This application note has described a new feature of DSCH linked with fault injection and simulation

at logic level. The mechanisms for logic fault injection, simulation and optimum test vector extraction

have been described and illustrated on a AND gate, a complex gate and a full-adder.

6 Exercises

6.1 Exercise 1 – Multiplexor

Design the following circuit. Inject stuck-at faults on X1, X2, X3 and Y. Which test vectors would

achieve a 100% fault coverage?



Y

a

b

c

e f

g

h

i d

X1

X2

X3

Answer: vector 001 detects 3/8 faults, 011 detects three others, which leads to 6/8 faults using 2

vectors.

6.2 Exercise 2 – fault collapsing

Stuck-at fault collapsing typically reduces the total number of faults by 50 to 60% [Bushnell 2000].

Fault collapsing for stuck-at faults is based on the fact that a SA0 at the input to an AND (NAND) gate

is equivalent to the S@0 (S@1) at the output of the gate. Similarly, a S@1 at the input to an OR

(NOR) gate is equivalent to the S@1 (S@0) at the output of the gate. For an inverter, a S@0 (S@1) at

the input is equivalent to the SA1 (S@0) at the output of the inverter. Furthermore, a stuck-at fault at

the source (output of the driving gate) of a fanout-free net is equivalent to the same stuck-at fault at the

destination (gate input being driven). Therefore, the number of collapsed stuck-at faults in any

combinational circuit constructed from elementary logic gates (AND, OR, NAND, NOR, and inverter)

is given by:

Number of collapsed faults = 2×(number of POs+number of fanout stems)

+ total number of gate (including inverter) inputs −total number of inverters

A number of interesting properties are associated with detecting stuck-at faults in combinational logic

circuits; for example, two such properties are described by the following theorems:

Theorem 1

A set of test vectors that detects all single stuck-at faults on all primary inputs of a fanout-free

combinational logic circuit will detect all single stuck-at faults in that circuit.

Theorem 2

A set of test vectors that detect all single stuck-at faults on all primary inputs and all fanout branches

of a combinational logic circuit will detect all single stuck-at faults in that circuit. Given the example below:



- Evaluate the number of collapsed faults (answer: 10)

Y

a

b

c

e f

g

h

i d

X1

X2

X3

7 References

[Chen2002] Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002

[Sicard2005a] E. Sicard, S. Ben Dhia “Basic CMOS cell design”, McGraw Hill India, 450 pages, ISBN 0-07-0599335, June 2005 (international edition at McGraw Hill professional series in 2007)

[Sicard2005b] E. Sicard “Introducing 90-nm technology in Microwind3”, application note, July 2005, www.microwind.org

[Sicard2006a] E. Sicard “Microwind User’s Manual, lite version 3.1”, www.microwind.org, INSA editor, 2006

[Sicard2006b] E. Sicard “Introducing 65-nm technology in Microwind3”, application note, July 2006, www.microwind.org

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Introducing Fault Testing in Dsch version 3 - INSA Toulousesrv-sicard/microwind/test-dsch35.pdf · This document introduces the concept for fault simulation at logic level in Dsch35