INTRODUCTION GENERAL FEATURE - Diagramasde.com

3

INTRODUCTION

GENERAL FEATURE

SPECIFICATIONS1. SUPPORTED SYSTEM

• IBM Compatible Pentium 133MHz or Above (with PIO mode 4, TX chip set recommended)

2. SUPPORTED OS

3. GENERAL PERFORMANCE• Data Transfer Rate ...........................................................................................Sustained Data Transfer Rate

DVD (Outer side) : Approx. 21,600 kbytes/secDVD (Inner side) : Approx. 8,100 kbytes/secCD (Outer side) : Approx. 7,200 kbytes/secCD (Inner side) : Approx. 3,300 kbytes/sec

• Data Buffer Capacity.......................................................................................................................512 kbytes• Access Time.................................................................Random Access DVD : 120ms Typical (16X)

CD : 100ms Typical (48X)4. POWER REQUIREMENTS

• Voltage ........................................................................................................................................+5V DC +5%+12V DC +5%

• Ripple .....................................................................................................................................+5V : 100mVp-p+12V : 100mVp-p

• Current .........................................................................................+12V : 400mA (Average), 1.3A (Maximum)+5V : 500mA (Average), 1.2A (Maximum)

5. AUDIO PERFORMANCE• Frequency Response......................................................................................................20Hz~20KHz(+ 3dB) • S/N Ratio (IHF-A+20kHZ LPF) ..........................................................................75 dB (Typical at 1 KHz 0dB)

70 dB (Limit at 1 KHz 0dB)• T.H.D. (IHF-A+20kHZ LPF)...............................................................................0.05% (Typical at 1 KHz 0dB)

0.15% (Limit at 1 KHz 0dB)• Channel Separation (IHF-A+20kHZ LPF) .................................................................................75 dB(Typical)

70 dB(Limit)• Output Voltage (1kHz 0dB) 47KΩ Load ................................................................................0.75Vrms + 20%• Headphone Level (1kHz 0dB) 33Ω Load...............................................................................0.75Vrms + 20%

• Enhanced IDE interface• Internal 5.25 inch, halfheight DVD-ROM Drive• 120ms (Typical) Random Access Time (DVD)• 100ms (Typical) Random Access Time (CD)• Supports 16X (max) Rotational Modes in DVD Mode• Supports 48X (max) Rotational Modes in CD Mode• Max 21,600 kB/sec Sustained Transfer rate in DVD mode• Max 7,200 kB/sec Sustained Transfer rate in CD mode• Photo-CD Multisession Disc Spec compliant• DVD-R, DVD-RW, DVD dual (OTP, PTP) disc spec

compliant.• Multimedia MPC-3 Spec compliant• Power Tray Loading/Ejection Mechanism• 3-Way Eject Support (Software, Open/Close Button,

Emergency Eject)

• Closed Enclosure• Built-in ATAPI Interface Controller• Software Volume Control• Easy CD-Audio Play front panel Controls• Front panel Volume Control for Headphone Output• Built-in MODE-1 ECC/EDC• MTBF (125,000H) POH (at 10% Utilization)• PIO Mode 4 & Multiword DMA Mode 2 Support• ULTRA DMA 33 support• Horizontal/Vertical Mounting• Digital audio output connector• Digital audio through ATAPI Interface• Spin-down Mode for energy saving

• MS-DOS (Ver 3.1 or Higher)• Windows 3.1/95/98/2000/ME/XP• Windows NT (Ver 4.0)

• OS/2 Warp (Ver 3.0)• Solaris (Ver 2.4 or Higher)• Linux ’96 Slacware (Ver 3.1.0)

This service manual provides a variety of serviceinformation. It contains the mechanical structure ofthe DVD-ROM Drive together with mechanicaladjustments and the electronic circuits in schematic

form. This DVD-ROM Drive was manufactured andassembled under our strict quality control standardsand meets or exceeds industry specifications andstandards.

4

LOCATION OF CUSTOMER CONTROLS

(1) Digital Audio Ouput ConnectorThis is a digital audio output or Video CD outputconnector.You can connect this to a digital audio system or aVideo CD Board.

(2) Analog Audio Output ConnectorThe Audio Output Connector connects to a soundcard.

(3) Master/Slave/CSEL JumperThese three jumpers are used to set the DVD-ROMDrive to either a Master, Slave, or CSEL device.

(4) Interface ConnectorThis 40-pin connector is used to transfer data andcontrol signals between the DVD-ROM Drive and yourPC.

(5) Power-in ConnectorAttach a power cable from the computer to thisconnector.

R O MR O MR O MR O M

COMPACT

1 2 43 5 6

1 2 543

FRONT VIEW

BACK VIEW

(1) Headphone JackStandard 1/8″ (3.5mm) stereo jack for listening to theaudio signal from audio CDs.

(2) Headphone Volume ControlAdjusts the headphone sound level.

(3) Disc DrawerAccepts a CD-ROM/DVD-ROM disc on its tray.

(4) Busy Indicator The Busy Indicator lights during initialization and data-read operations.

(5) Emergency Eject HoleInsert a paper clip here to eject the drawer manually orwhen there is no power.

(6) Open/Close/Stop ButtonThis button is pressed to open or close the CD tray.If an audio CD is playing, pressing this button will stopit, and pressing it again will open the tray.

5

1. CABINET and CIRCUIT BOARDDISASSEMBLY

1-1. Bottom ChassisA. Release 4 screws (A) and remove the Bottom

Chassis in the direction of arrow (1). (See Fig. 1-1)

1-2. Front Bezel AssyA. Insert and Press a rod in the Emergency Eject

Hole and then the CD Tray will open in thedirection of arrow (2).

B. Remove the Tray Door in the direction of arrow (3)by pushing it outward.

C. Release 3 stoppers and remove the Front BezelAssy.

1-3. Cabinet and Main Circuit BoardA. Remove the Cabinet in the direction of arrow (4).

(See Fig. 1-3)B. Release 2 hooks (a) and remove the CD Tray.C. Remove the Soldering of the LD- and LD+ (B) for

the Loading Motor, and then remove the MainCircuit Board.

D. At this time, be careful not to damage the 3connectors of the Main Circuit Board.

2. MECHANISM ASSY2-1. Base Pick-Unit AssyA. Separate the Base Pick-Up Unit Assy from the

MechanismAssy.B. Release 2 screws (C) and 1hook and then

remove the Base Pick-Up Unit Assy.

DISASSEMBLY

(A)(A)

(A)

(A)

(1)

Bottom Chassis

(3)

(2)

Tray Door

Stoppers

CD Tray

Emergency Eject HoleFront Bezel Assy

(4)

Cabinet

MainCircuit Board

(B)Hooks (a)

Mechanism Assy

Base Pick-up Unit Assy

Hook

(C)(C)

Fig. 1-1

Fig. 1-2

Fig. 1-3

Fig. 2-1

INTERNAL STRUCTURE OF THE PICK-UP

1. Structure of the Pick-Up

11

CN14 DVD VCCCN05 DVD VCCN08 DVD GND

CN10 DVD A

CN09 DVD B

CN11 DVD C

CN12 DVD D

CN06 DVD RF+

CN07 DVD RF-

CN13 DVD GND

CN17 DVD VR

CN18 DVD MDCN15 DVD LD

CN16 DVD LD GND

CN01 F+CN02 F-CN03 T+CN04 T-

CN28 CD VCC

CN19 CD VC

CN20 CD GNDCN26 CD A

CN27 CD BCN24 CD C

CN29 CD E CN30 CD FCN25 CD RF

CN22 CD VR

CN23 CD MDCN21 CD LD

C001

A

B

C

E

F X2 X1 X1

C002

C003

VR02

TRACKING

FOCUS

Differential RF outputs circuit

HFM

ACTUATOR

VR01L004

L002

L003

C004

VCCLD

RF+A

BCD

RF-

GND Ri Rf

L001

Rb

LASER DIODE

LASER DIODE

PICK-UP UNIT

12

1) Focus Error Signal –> (A + C) - (B+C)

• In case of CD DiscThis signal is generated in RF AMP IC (IC301 : MT1326) and controls the pick-up’s up and down tofocus on CD Disc.

2) Tracking Error Signal (3-Beam Method) –> E - F

• In case of CD DiscThis signal is generated in RF AMP IC (IC301 : MT1326) and controls the pick-up’s left and right shift tofind the track on CD Disc.

3) RF Signal –> A+B+2C

• In case of CD DiscThis signal is converted to DATA signal in DSP IC (IC201 : MT1329).

2. Structure of the Photo Diode (CD)

Infrared laser

Pick-Up module

Photo Diode Tracking

Focusing

(As seen from light receiving side)

E

CB

F

A

13

1) Focus Error Signal –> (A+C) - (B+D)

• In case of DVD DiscThis signal is generated in RF AMP IC (IC301 : MT1326) and controls the pick-up’s up and down to focus on DVD Disc.

2) Tracking Error Signal (DPD Method) –> Differential phase of (A+C) and (B+D)

• In case of DVD DiscThis signal is generated in RF AMP IC (IC301 : MT1326) and controls the pick-up’s left and right shift to find the track on DVD Disc.

3) RF Signal –> A+B+C+D

• In case of DVD DiscThis signal is converted to DATA signal in DSP IC (IC201 : MT1329).

3. Structure of the Photo Diode (DVD)

(As seen from light receiving side)

Red laser

Pick-Up module

Photo Diode Tracking

Focusing

D C

A B

14

MDI

70k

500

500

Vref

LD1CTL,LD2CTL

LDC1,LDC2

70k

1k

LDO(Vp is the centralvoltage of MD)

(Inside block of IC301)

DESCRIPTION OF CIRCUIT1. ALPC (Automatic laser power control)

1-1. ALPC Circuit ConstitutionDual laser power control for DVD and CD are provided. The laser power for CD and DVD can be programmableby LD1CTL and LD2CTL and the lasers ON/OFF are controlled by LDC1 and LDC2 for CD and DVD,respectively. The following figure briefly describes the ALPC block. When the bit LDC1 is set low, the outputvoltage of LD0 will be pulled to VCC, hence the laser of CD will be turned off. Same manner is DVD lasercontrol with LDC2 bit.

ALPC (Automatic laser plower control)

15

EFRFATNRFATNRFISEL

RFIGMSEL

GM VGA Equalizer

AGC

DPD

DVD/CDSW

SW

direction

3BEAM TE

FE

CentralSERVO

EnvelopeDetector

RFOP

attenuator

86

RFON85

HRFRP7

DPFN38

DPFO39

TEO97

FEO95

CSO(DVD)

DVDC

DVDB 242

DVDD 43

41

DVDA 40

CDFPI 65

CDFNI 64

TNI 83

TPI 82

RFGC

DVDRFIP

59

39

DVDRFIN 38

DVDD 43

DVDC 42

DVDB 41DVDA 40

CDD 56CDC 55CDB 54CDA 53

A B

D C

2. RF Amplifier Circuit

RF signal flow chart

2-1. INPUT STAGE

This block, including programmable attenuators and transconductors, is used for proper attenuation of inputsignals for different pick-up heads. Three input modes, defined by RFISEL are available for multiple inputsselection. Input mode also affects Gm, as definded by RFIGNSEL. The following table describes therelationship between input modes and selected Gm multiplicators. For example, if user chooses RFISEL =’10’(RFIN, RFIP) and RFIGMSEL =’11’( ), then effective GM is equal

to . 4 = .

16

14K

14∗K

11∗K

RFISEL1 RFISEL0 INPUT Multiplicator of Gm Input pins for DVD-ROM Input pins for CD-ROM

0 0 A,B,C,D ∗1 DVDA,DVDB,DVDC,DVDD CDA,CDB,CDC,CDD

0 1 FEN FEP ∗2 DVDRFIN, DVDRFIP CDC,CDD

1 0 RFIN RFIP ∗4 DVDRFIN, DVDRFIP CDC, CDD

1 1 RFIN RFIP ∗4 DVDRFIN, DVDRFIP CDC,CDD

For DVD_ROM mode, RF signal may be the sum of DVDA, DVDB, DVDC and DVDD which is also apply toDPD tracking error circuit. Furthermore, RF signal also can be obtained from pins DVDRFIN and DVDRFIP,which are the differential signals from OEIC, if the RF signal from OEIC is single-ended, it is all still available formode ‘RFIN-RFIP’ by simply keeping DVDFIN floating. For CD_ROM mode, the differential RF inputs fromOEIC may feed into pins CDC and CDD, which have the same function as DVDRFIN and DVDRFIP. It meansthat the function about ‘RFIN-RFIP’ mode in CD-ROM is the same as DVD_ROM except input pins being fromCDC and CDD.

2-2. AGC (Automatic Gain Control) LOOPAGC loop, as shown in Fig.1, is carried out for amplifying the RF signal from PDIC to a constant level at the

output (RFON, RFOP). By controlling the gain of the GCA, the automatic gain control circuit holds the signal atthe output (RFON, RFOP) at a constant level independent of the signal at GCA input. The GCA output signallevel is determined by the DC voltage set on the pin RFGC. As the figure shown above, there are three AGCmodes, defined by AGCMOD : AGC enable, RFGC DAC enable, and AGC hold. For ‘AGC enable’ mode, AGCloop is activated and user can apply different attack and decay bandwidth by programming IAGCDEC andIAGCATT respectively to optimize the system performance. For ‘RFGC DAC enable’ mode, a built in DAC,defined in RFGC], is utilized to perform the function of off-line AGC. Users can set the signal gain viaprogramming the DAC after calculating the level of RFRP signal. For ‘AGC hold’ mode, RFGC pin becomeshigh impedance and the gain will keep almost at a constant level, even with low leakage current. Beside theAGC hold mode defined by AGCMOD, there is also a AGC hold function for defect protection. The destructiveRF signal caused by defect may confuse the AGC function, one can hold AGC during this period byprogramming R[4].

2-3. EQUALIZERThis filter is intended to be used in the read channel of CD-ROM and DVD-ROM drivers with 8x constant

linear velocity (CLV). As shown in following figure, the filter is placed in the automatic gain control (AGC) loopwhere it performs a dual role. It cuts off high frequency noise in the amplified read signal resulting in lower biterror rates.

For various operation speed, the filter cutoff frequency must be tunable over a wide range of about 3M-45MHz. The second filter objective is to boost the high frequency component of RF signal which suffers fromdifferent MTF (modulation transfer function) from 14T to 3T. The equalizer uses two real zeros symmetric aboutthe imaginary axis. The major requirement in the pulse equalizer design is phase linearity in the point ofreducing intersymbol interference. In addition, the group delay must be independent of the amount ofequalization to minimize jitter tolerance and be kept constant over 2*fc.

A tradition 7-pole 2-zero 0.05˚ equiripple type is determined for this filter design. In filter structureconsideration, feedforward technique has been realized for its easy implementation instead of signal flow graph.Consequently, the control of cutoff frequency ƒc and boost gain can be easily accomplished in the second ordersection, included in this filter.

17

EFRFATNRFATNRFISEL

RFIGMSEL

GM

VoltageDAC

CurrentDAC

comp

VGA Equalizer

Tracking

Top detector

Top detector

BottomDetector

M

DVDRF

BottomDetector

RFOP

attenuator

86

RFON85

HRFRP

CRTPLP

7

9

CRTP8

LRFRP 39

DEFECT 38

RFGC

DVDRFIP

59

39

DVDRFIN 38

DVDD 43

DVDC 42

DVDB 41DVDA 40

CDD 56CDC 55CDB 54CDA 53

A B

D C

compChargepump

VoltageDAC

RF signal flow chart

18

CDFPI65

45DVDFPI

1:CD

67k134k

10k

FEON1

FELG (1Eh, b5)

10k 3~21.6k

FEG(1Eh,b4-0)

FEOS(0.8h,b4-0)

10k67k134k

10k

0:DVD

CDFNI

DVDFNI

IDACFE

FEO

33k

64

44

96

95

3. SERVO SIGNAL

3-1. FOCUSING ERROR

Block diagram is shown in following figure. the signal gain for focusing error is programmable by FEG. ForCD_RW and dual layer DVD_ROM applications, the amplitude of input signals are about one third of the one fornormal CD_ROM and single layer DVD_ROM disk. Therefore, increasing the gain by three times, defined byFELG=0, is necessary for suitable gain range. In addition, the output voltage of FEO will suffer a offset voltageshift over normal operation range from semiconduction process. MT1326 provides a offset adjustment circuitcomprising with FEOS. By programming IDACFE, it will generate an offset current flowing through externalresistor R0, hence tuning the voltage of FEO back to the normal operation range. The offset voltage adjustment

is given as ∆Voffset = -(IDACFE. R0).

Focussing error

19

3-2. RF LEVEL (FLVL)

The signal FLVL which is the low-passed RF summing signal is used to indicate the focusing status for DVD-ROM mode, as shown in following figure. It also has the gain and offset programmability by LVLG and LVLOS,respectively.

CDFPI65

45DVDFPI

1:CD 54.5p

27.5p

67k134k

10k~72k

32p

FLVLNI0

FELG (1Eh, b5)

10k~72k

67k134k

27.5p

54.5p

10k

0:DVD

CDFNI

DVDFNI

LVLG(1Fh, b4-0)

LVLS(09h, b4-0)

IDACFE

0

11: CD0: DVD

FLVL

33k

SBAD

64

44

93

94

RF Level signal generator

20

CDCSPI

DVDCSPI

1:CD 54.5p

27.5p

67k134k

10k

32p

CSON11

FELG (1Eh, b5)

10k

10k67k134k

27.5p

54.5p

10k

0:DVD

CDCSNI

DVDCSNI

CSOS(0Ah, b4-0)

IDACFE

1

01 : CSO0 : REO

CSO SEL(01h)

CSO

2

370

47

69

46

33k

TEO

3-3. CENTRAL SERVOThis signal is for central servo application. It is also a one beam push-pull tracking error signal. User can

select either CSO or TEO as the output signal through output pin CSO by programming ‘CSOSEL’.

CSO signal generator

21

TPI

1:CD 54.5p

27.5p

67k

35k

134k

TEG3k~21.6K

10k

10k

FLVLNI

TELG (21h, b5)

3k~21.6k

TEB(0Bh, b4-0)8.4~15.2K

TEB(0Bh, b4-0)8.4~15.2K

67k

35k

134k

27.5p

54.5p

16k

0:DVD

TNI

CSOS(0Ah, b4-0)

IDAC

FLVL(SBAD)

33k

32k

SBAD

If select CDthen FLVL outputis SBAD

SABDOS(97h,b4-0)

94

82

83

93

3-4. SBAD (SUB_BEAM ADD)The SBAD signal, the summing signal of both satellite PDs, is applied toward monitoring the focusing status

for CD-ROM mode. The gain parameters setting for this signals is the same as 3-beam tracking error byTEGAIN. Offset cancellation DAC, defined SBADOS, is also required.

Sub beam Adder

22

TPI

1:CD 54.5p

27.5p

67k134k

TEG3k~21.6K

TEB (0Bh, b4-0)8.4~15.2K

TELG (21h, b5)

3k~21.6k 11.8k

32k

32k

33k

47P

32k

16k

11.8k

TEB(0Bk, b4-0)8.4~15.2K

TEOS(06h,b5-0)

67k

35k

134k

27.5p

54.5p

0:DVD

1:CD0:DVD

IDAC

35kTNI

DPDDVDA

DPFO

DPFN

TEOTEO

DVDBDVDCDVDD

*3

82

83

97

88

87

40

41

42

43

3-5. TRACKING ERRORTwo tracking error, 3-beam tracking error and DPD (differential phase detection), are available for CD_ROM

and DVD_ROM, respectively. The block diagram is shown in following figure. For 3-beam tracking error, onecan select different gain by TEGAIN, as well as adjust the gain ratio between these two satellite signals byTEBAL for unbalance compensation in satellite PDs. For DVD_ROM mode, the tracking error signals isswitched to DPD automatically.

Tracking error

23

Timemultiplexed

A/D

Paralleldigital

compensator

High passfilter

FE_hpf

Focussearch

algorithmD/A FOO12

RFLEVEL

FEI

199

198

3-6. FOCUS SERVO

Focus servo system

Focus search diagram

The focus servo system is shown on the above figure. The focus servo system is used to search the focuspoint of disk, and following that point a parallel digital compensator is used to control the focus actuator. Thefocus error signal (FEI) is sampled at 176.4kHz with an 8-bit flash A/D converter, then it is subtracted by FE,offset and is fed into the digital compensator. The digital compensator will output the result to FOO pin with a10-bit D/A converter (FOO). Both A/D and D/A operate within the range from 0 to 2Vref.

The DSP commands FACTION82hw, FSET83hw FLEVEL184hw and FLEVEL285hw are the associatedcommands for the focus loop control. The following figure is the typical focus search timing.

TFOK

TFNG

FOK

FOON

RFLEVEL

FOKL

FONL

Vref

FE_hpf

FEI

24

Timemultiplexed

A/D

Track numbercounter &

Timer

Shortseek

Alogrithm

Paralleldigital

compensatorD/A

PWM Sled

compensator

TEI

FMO

TEZC

RFZC

TRO196 13

18

3-7. TRACKING AND SHORT SEEK SERVO SYSTEM

Tracking servo system

The tracking servo system shown as the above figure is used to follow track center of disk. In addition, thereis a short seeking control block built in to move the lens from 0 to 2000 tracks. Two compensators are used tocontrol the dual actuator (track and sled) servo system. The tracking error signal (TEI) is sampled at 176.4 kHzwith an 8-bit flash A/D converter. It is then subtracted by TE-offset, which is generated from auto-calibration,added by SB_hpf, and fed into the digital compensators. The results of the compensators will output to TRO andFMO pins with a 10-bit D/A and an 8-bit PWM generator. Both the A/D and D/A operate within the range from 0to 2Vref, and the PWM generator operator operates from 0 to PWM2Vref.

The MT1329 supports actuator central servo control while cooperated with MT1326 RF chip. The TEI input ofthe MT1329 is connected to the CSO output of MT1326. When the central servo function is active, the MT1326will select push-pull signal as CSO output during tracking off state (seeking) and select tracking error signal asCSO output during tracking on state (following). So the MT1329 uses push-pull signal to control tracking servoduring seeking state and tracking compensator will let actuator to keep at central location around on pickuphead. This will enhance the stability of the DVD-ROM/CD-ROM system when it changes from seeking state tofollowing mode.

The initial tracking on can be done by using jump 0 track (SEEKSET4OFFW with 0000h and TACTION90hw),for the short seek unit provides high gain mode, peak hold brake, and quick seek-to-follow switching method.The short seek control unit is implemented with velocity control feedback to move tracking and sled actuator. Aslong as the target track reached, it will switch to tracking control mode to enter the close loop. In order to reducethe settling time, it will switch to high gain mode automatically and issue a peak hold brake to enter the steadystate_as soon as possible.

The DSP commands are the associated commands for the track loop control.

The micro controller can be programmed to focus search as follows:1. Light laser on through the MT1326.2. Move object lens up or down by using the FACTION command. If object lens moves too slowly or it doesn’t

cross focus point, try to adjust FSR or coefficient Kfsrch.

3. Normally FEI will have an S-shaped waveform. With the high pass filter to reduce offset voltage, the signalFE_hpf will be used to do the focus search.

4. After the absolute value of FE_hpf exceeds the level FONL, it will wait to enter focus servo loop (FOON flag1) as long as FE_hpf reaches the zero-cross point.

5. If the focus compensator is robust enough and RFLEVEL signal is higher than level FOKL, focus servo willenter a steady state and count the time for the steady state. As long as the duration for RFLEVEL higherthan the level FOKL exceed TFOK, the focus OK flag FOK will be set to indicate the focus servo is welllocked.

6. IF the RFLEVEL signal is lower than the level FOKL for the duration longer than TFNG, both the FOON andFOK flags will be reset to indicate the system loses the focus point. The both flags can be monitored throughthe flag pins.

TEZI

TEZC

TEZILP

Tracking error zero crosing for seek control

As the above figures shows, the TEZC is the output of the comparator that compares the TEZI with its slicelevel that is the output of the external low pass filter.

25

26

DESCRIPTION OF DATA PROCESSING1. Data Processing Flow

Com

man

d

Dat

a S

tatu

s

RF

EQ

& A

GC

SE

RV

OD

SP

Dec

oder

& C

SS

RF

dat

a sl

ice

EF

M d

emod

ulat

orC

iRC

err

or c

orre

ctio

nA

udio

DA

CC

3 de

code

rB

uffe

r/M

emor

y co

ntro

ller

CS

S c

ontr

olle

rA

tapi

inte

rfac

e co

ntro

l

Dat

a P

LLS

ervo

AD

CF

ocus

/trac

king

con

trol

out

put

Sle

d co

ntro

l out

put

CA

V S

pind

le c

ontr

ol

P-u

pU

nit

IC60

1(m

otor

driv

e)

IC30

1R

F A

MP

(MT1

326)

IC20

1D

SP

(MT1

329)

TE

/CS

O G

EN

FE

GE

N

FLA

SH

RO

M

DR

AM

27

MT1329HOST DVDPLAYER

(MPEG2 B/D)

Scrambled MPEG Data

Change the "KEY"

KEY Management Control

2. Copy Protection and Regional Code Management Block

Block Diagram

Brief Process1. Regional Code for DVD Disc

– DVD-ROM drive transfers the regional code of the control data to host by the command of host, the DVDplayer of host reads the regional code, and plays title in the case of allowed regional code only.

2. Management of DVD Disc for the scrambled of data (1) DVD-ROM and DVD player of host generate the “KEY 1” respectively, transfer to opposite part, the

“KEY 2” is received, recognizes the data transfer or not with this value, and generates the bus key encoded the data.

(2) Encoded “Disc Key” and “Title Key” host is transfer with the bus Key.(3) DVD player of host reads the key value, and uses the value to restore the scrambled data.* Refer to the next page for the details.

28

3. About Prevention the DVD-ROM from to be copyA data is able to encode and record in the disc, if a copyright holder wants to prevent the disc from copying.

In case of a disc enhanced movie of 3 titles......DISC KEY (2048 Bytes) is used to encode the whole contents in the disc and TITLEKEY (5 Bytes) is used to encode the title respectively.So, the data is encoded and stored in a disc through the unknown algorithmswith a disc key and title key. (At this time, the disc key and title key are storedin a disc.)…As above, the disc is able to copy when the disc key and title key areopened.Then, ROM-DRIVE encodes the disc key and title key and transfers to MPEG-2 board.

If you want to play the disc prevented from the copy......First of all, ROM-DRIVE and MPEG-2 board identify with each other through the procedure as describedbelow.

1. Drive and host gives and takes the ID of 2bit. This ID is AGID (Authentication Grant ID).The various decoder boards are attached to the host, in these, AGID sets the MPEG-2 board and drive.

2. After the AGID is set, MPEG-2 board generates the challenge key (10 Byte) and transfers to drive. Theboard and drive generate key 1 (5Byte) with the challenge key respectively. (Of course, the Algorithmgenerating the key 1 is not known.)

3. Compare with the generated key 1, if it corresponds each other, the first step of authentication iscompleted. This is a course to identify the MPEG-2 board with a drive.

4. The second step of authentication is a course to identify a drive with the MPEG-2 board.The dirve generates a challenge key and transfers it to the MPEG-2 board. The dirve and MPEG-2 boardgenerate the key 2 (5Byte) with the challenge key, compare with each other, and if it corresponds and thesecondary step of authentication is completed.

5. As above, the identification is completed.6. The dirve and MPEG-2 board generate the Bus key with the key 1 and key 2 and own it.7. Dirve encodes the disc key and title key with this Bus key and transfers to the MPEG-2 board.8. The MPEG-2 board reads the encoded disc key and title key with the Bus key only.9. MPEG-2 board lets data read from the drive to decode with the read disc key and title key and makes into

the video signal by decoding.

ROM-DRIVE

AGID HOST

MPEG-2BOARD

Challenge key

encoded disc key, title key

29

4. About the DVD-ROM Regional Code

DISC ROM - DRIVE MPEG-2 BOARD VGA CARD MONITOR

1

CAN

U.S.A

MIX

CUB

BHS

PRI. VIR

1

BMG

GRL

2

2 ZAFISOSWZ

FIN

POI

FSTLTU

BIR

UKR

TUR

FGY

JRN

TKM

AFGPAK

CHN

MMR

MNG

RUS

KOR JPN

HKGMAC

TWN

PHL

6

3

21

5

5

4

1

MDI

MNP

GUM

PLW

PNG

NZL

AUS

4

The disc hasthe regionalcode of 8 bit.

Example)The discmanufacturedin the U.S.A,has thenumber one.

Transfer toMPEG-2 boardreading theregional code.

Receivingdata from theMPEG-2board andoutputthrough themonitor

If the board is setting to the regionalcode 1 for the U.S.A. ...Check the received regional code tonumber 1, all or not, transfer thedata to VGA card in accordance withonly a case among the three case.

Regional code

30

IC301 (MT1326) : RF Signal Processing for CD/DVDIt amplifies or equalize the RF signal from Pick-up, and generate the TE (Tracking Error) and FE(Focus Error) signal for Servo respectively.The TE signal uses the DPD (Differential Phase Detect) method for DVD and 3 Beam method for CD.DVD FE = (A+C) - (B+D)CD FE = E - F

Block Diagram

MAJOR IC INTERNAL BLOCK DIAGRAM AND PINDESCRIPTION

ATTENUATOR

DVDA

VGA EQ

ENVELOPDETECTOR

AGC

DPD

SBAD

3 BEAMTE

RFLEVEL

FE

CENTRALSERVO

SERIALPORT

CDAPC

DVDAPC

REF and 2VREFVoltage Generator

OSP

OSN

RFOP

RFON

LRFRP

DEFECT

HRFRP

CRTP

CRTPLP

FLVLNI

FLVL

TEO

FEO

FEONI

CSO

CSONI

MDI2

LDO2

MDI1

LDO1

SDATA

SLCK

SDEN

CDA

DVDB

CDB

DVDC

CDC

DVDD

CDD

DVDRFIN

DVDRFIP

RFGC

DPFN

DPFO

IR

DPDMUTE

TPITNI

CDFNI

CDFPI

DVDFNI

DVDFPI

CDCSNI

CDCSPI

DVDCSNI

DVDCSPI

V2REFO

VREFO

IC301 (MT1326)• Pin Description

31

Pin Numbers Symbol Type Description

QFP100 and LQFP100

RF Flag Interface

14 DEFECT Digital output Flag of bad data output status

RF SIO interface

15 SLCK Digital input RF serial clock input

16 SDEN Digital input RF serial data enable

17 SDATA Digital IO RF serial data IO

12 RST Digital input Reset (active high)

13 XCK16M Digital input 16.9MHz for verification

RF

40 DVDA Analog input DVD RF signal input A

41 DVDB Analog input DVD RF signal input B

42 DVDC Analog input DVD RF signal input C

43 DVDD Analog input DVD RF signal input D

38 DVDRFIN Analog input DVD RF signal input RFIN

39 DVDRFIP Analog input DVD RF signal input RFIP

53 CDA Analog input CD RF signal input A

54 CDB Analog input CD RF signal input B

55 CDC Analog input CD RF signal input C

56 CDD Analog input CD RF signal input D

61 OSP Analog Offset cancellation capacitor connecting

60 OSN Analog Offset cancellation capacitor connecting

86 RFOP Analog output RF positive output

85 RFON Analog output RF negative output

59 RFGC Analog RF VGA control

TRACKING ERROR

88 DPFN Analog DPD amplifier negative input

87 DPFO Analog DPD amplifier output

24 IR Analog DPD reference resister connecting

18 DPDMUTE Digital input DPD mute control input

83 TNI Analog input 3 beam satellite PD signal input

82 TPI Analog input 3 beam satellite PD signal input

97 TEO Analog output Tracking error output

32


FOCUSING ERROR & RF LEVEL & CENTRAL SERVO SIGNAL

64 CDFNI Analog input CD focusing error negative input

65 CDFPI Analog input CD focusing error positive input

44 DVDFNI Analog input DVD focusing error negative input

45 DVDFPI Analog input DVD focusing error positive input

95 FEO Analog output Focusing error output

96 FEONI Analog input Focusing error amplifier negative input

93 FLVL Analog output RF level output

94 FLVLNI Analog input RF level amplifier negative input

69 CDCSNI Analog input CD central servo signal negative input

70 CDCSPI Analog input CD central servo signal positive input

46 DVDCSNI Analog input DVD central servo signal negative input

47 DVDCSPI Analog input DVD central servo signal positive input

2 CSO Analog output Central servo signal output

3 CSONI Analog input Central servo amplifier negative input

ALPC

80 MDI1 Analog input Laser power monitor input

81 LDO1 Analog output Laser driver output

51 MDI2 Analog input Laser power monitor input

52 LDO2 Analog output Laser driver output

RF RIPPLE

9 CRTP Analog RF top envelop filter capacitor connecting

10 CRTPLP Analog Defect level filter capacitor connecting

8 HRFRP Analog output High frequency RF ripple output

7 LRFRP Analog output Low frequency RF ripple output

POWER

25,26,30,34,62,63 AVDD Power RF power

22,23,29,37,57,58 AGND GND GND

89,90 SVDD Power Servo analog power

98,99 SGND GND GND

5, 6 VDD Power Digital power

19,20 GND GND GND

REFERENCE VOLTAGE

92 VREFO Analog output Reference voltage 2.0V

91 V2REFO Analog output Reference voltage 4.0V

33


ALPC TRIMMING

32 TM1 Analog input Trimming pin for ALPC1




HIGH SPEED TRACK COUNTING

1 TRLP Analog Low_pass filter capacitor connecting

100 TRLPA Analog Low_pass filter capacitor connecting

11 HTRC Digital output High speed track counting digital output

PCS

79 HALLSIN Analog input Negative input of amplifier for hall sensor signal

78 REFSIN Analog input Positive input of amplifier for hall sensor signal

77 SINPHI Analog output Amplifier output for hall sensor signal

76 HALLCOS Analog input Negative input of amplifier for hall sensor signal

75 REFCOS Analog input Positive input of amplifier for hall sensor signal

74 COSPHI Analog output Amplifier output for hall sensor signal

FOR MONITOR ONLY

27 MON Analog output

28 MOP Analog output

31 VCON Analog output

21 HTRCMPH Digital output

84 HTE Analog output

71 SWO Analog output Output from mux of SW1&SW2

72 SW2 Analog input External input for servo input select

73 SW1 Analog input External input for servo input select

34

IC201 (MT1329) : LSI processing for DVD-ROM Drive Signal

Block Diagram

RF

ZC

/T

EZ

CC

ircu

it

RF

RP

SLV

TE

ZI

TE

ZIS

LVH

RF

ZC

AD

CV

DD

FE

IT

EI

RF

RP

_D

CR

FR

P_

AC

RF

LE

VE

LA

DIN

AD

CV

SS

SL

CK

SD

EN

SD

ATA

FO

OT

RO

FM

OP

WM

OU

T1

PW

MO

UT

2

PD

MV

DD

PW

M2

VR

EF

PW

MV

RE

FP

DM

VS

S

FL

AG

AF

LA

GB

FL

AG

CF

LA

GD

IO[3

:0]

VPVDD

VCDCINVPVSS

ENDM

FG

DMO

LODACVREF

RO

DACVDDDACVSS

ADGO

HD[15:0]PDIAG#DASP#

HRST#DIOW#DIOR#

DMACK#HA[2:0]

CS1FX#CS3FX#

DMARQIORDYINTRQ

IOCS16#

URSTUINT#

UPSEN#UALE

UAD[7:0]UP2_7-UP2_0

UA[7:0]

UA16UWR#URD#

UP3_5-UP3_4UP3_2-UP3_0

IO4-IO9

RF

Fla

gIn

terf

ace

Da

taS

lice

rD

ata

PL

L

Syn

cp

rote

ctio

n

CIR

C/R

SP

CE

rro

r C

orr

ect

or

CD

RO

MS

ync

De

tect

ion

De

scra

mb

ler

Au

dio

/Effe

ctIn

terf

ace

Au

dio

Dig

ital O

ut

CS

SH

ost

Da

taF

IFO

ATA

PI

Pa

cke

tF

IFO

Mic

ro-c

on

tro

ller/

MP

EG

co

mm

an

d I

/F

80

32

Me

ga

Inte

rfa

ce

Ke

y/L

ED

Inte

rfa

ce

TR

OP

EN

PW

MT

RC

LO

SE

TR

AY

IN#

LE

D

PLY

#/P

AU

#E

J/S

TO

P#

BA

[1:0

]D

QM

CL

KC

KE

RO

E#

RW

E#

CA

SH

#/R

WE

H#

CA

S#

RA

S#

RA

[11

:0]

RD

[15

:0]

PR

ST

#

TE

ST

DMVSSDMVDD

IPLLVSSIPLLVDDXTALI

XTALO

JITFOVBDPLLLPIOLPFOPDO

JITFNPLLVSSLPINLPFNIREFPLLVDD

RFIPRFINSCORFDTSLV

BDO

LIM

IT#

TR

AY

OU

T#

25

6S

RA

M

Ho

st/M

PE

G A

/V I

nte

rfa

ce

CD

RO

M H

igh

-sp

ee

dA

ud

io P

layb

ack

C3

De

cod

er

Var

ipitc

h S

yste

mC

lock

Gen

erat

or

Sys

tem

Clo

ck

DR

AM

Clo

ckG

ener

ator

Res

etLo

gic

Buf

fer

Mem

ory

Con

trol

ler

EF

M/E

FM

+D

em

od

ula

tor

Su

bco

de

/ID

De

mo

du

lato

r

CLV

/CA

VC

on

tro

ller

PW

MD

AC

Va

rip

itch

CLV

Clo

ckG

en

era

tor

Fla

gs

&P

rog

ram

-m

ab

le I

/O

PD

M &

PW

MD

AC

Se

ria

l RF

Co

ntr

olle

r

Se

rvo

AD

C

Se

rvo

DS

P

35


RF data PLL interface

11 PLLVDD Power Power for data PLL and related analog circuitry.

10 JITFN Analog Input The input terminal of RF jitter meter.

9 JITFO Analog Output The output terminal of RF jitter meter.

8 PDO Analog Output Phase comparator output. Output the phasedifference of EFM and Pck. Sink or (source) aconstant current to loop filter over this pin whenphase difference occurs. Otherwise, this pin is highimpedance.

7 IREF Analog Input Current reference input. It generates referencecurrent for data PLL. Connect an external 100Kresistor to this pin and PLLVSS.

6 LPFN Analog Input The negative input terminal of loop filter amplifier.

5 LPFO Analog Output The output of loop filter amplifier.

4 LPIN Analog Input The negative input terminal of VCO intergrator.

3 LPIO Analog Ouput The output of VCO intergrator.

‘ 2 PLLVSS Ground Ground pin for data PLL and related analog circuitry.

1 VBDPLL Analog Output Reference voltage.

208 RFIN Analog Input The negative input terminal of RF differential signal.

207 RFIP Analog Input The positive input terminal of RF differential signal.

206 RFDTSLV Analog Output RF data slicer level output

205 SCO Analog Output Analog slicer current output. This pin is active when

TRONS=1, Otherwise this pin is high impedence.

Signal Amplifier Interface

204 ADCVDD Power Power pin for ADC circuitry.

203 HRFZC Analog Input High frequency RF ripple zero crossing.

202 RFRPSLV Analog Input RFRP slice level input.

201 RFRP_AC Analog Input RF ripple detect input (through AC-coupling)

200 RFRP_DC Analog Input RF ripple detect input.

199 RFLEVEL Analog Input Sub beam add input or RFRP low pass input.

198 FEI Analog Input Focus error input.

197 CSO Analog Input Central servo input.

196 TEI Analog Input Tracking error input.

195 TEZISLV Analog Input Tracking error zero crossing low pass input.

194 ADIN/IN0 Analog Input General A/D input/General digital input

193 ADCVSS Ground Ground pin for ADC circuitry.

Motor and Actuator Driver Interface

192 PDMVSS Ground Ground for PDM circuitry.

191 PWM2VREF Analog Input A reference voltage input for PWM circuitry. A typicalvalue of 4.0v.

IC201 (MT1329)• Pin Description

36


190 PWMVREF Analog Input A reference voltage input for PWM circuitry. A typicalvalue of 2.0v.

189 PDMVDD Power Power for PDM circuitry.

12 FOO Analog Output Focus servo output. PDM output of focus servocompensator.

13 TRO Analog Output Tracking servo ouput. PDM output of tracking servocompensator.

14 PWMOUT1 Analog Output 1st General PWM output.

15 PWMOUT2 Analog Output 2nd General PWM output.

17 DMO Analog Outout Disk motor control output. PWM output.

18 FMO Analog Output Feed motor control. PWM output.

19 TROPENPWM Analog Output Tray open control output.Controlled by µP.

20 FG CMOS 3.3V Input, Motor Hall sensor inputSchmitt Input, pull up

22 TRCLOSE CMOS 3.3V Tray close output.Output, 4mA

169 ENDM CMOS 3.3V Enable/disable disk motor. A logical high enable disk Output, 4mA motor.

Panel Interface

168 LED CMOS 3.3V LED control output controlled by µP.Output, 4mA

167 PLY#/PAU# CMOS 3.3V Input, Play/pause key input, active low.

166 EJ/STOP# CMOS 3.3V Input, Eject/stop key input, active low.

165 LIMIT# CMOS 3.3V Input, Sledge inner limit input, active low.

164 TRAYOUT# CMOS 3.3V Input, Tray_is _out input. A logical low indicates the tray isout. Feedback flag from tray connector.

163 TRAYIN# CMOS 3.3V Input, Tray_is_in input, A logical low indicates the tray is in.Feedback flag from tray connector.

Micro controller Interface

24 UALE TTL 5V I/O, Address Latch Enable.

25-33 UAD[7:0] CMOS 3.3V I/O, µP Address/Data Bus.4mA

35 UP2_7 CMOS 3.3V I/O µP Upper Address Bus/µP Chip Select 2(for Internal /UCS2 pull up, 4mA RAM)

36 UP2_6 CMOS 3.3V I/O, µP Upper Address Bus/µP Chip Select 1 (for InternalRAM)

37-42 UP2_5 ~ CMOS 3.3V I/O, µP Upper Address Bus

Schmitt Input,pull up, 4mA

pull up, 4mA

pull up, 4mA

/UCS1

UP2_0

Schmitt Input, pull up





37


44-51 UA[7:0] CMOS 3.3V I/O µP Lower Address Bus.pull up, 4mA

54 UA16/UP1_0 CMOS 3.3V I/O Default : UP1_0 for general programmable I/O 4mA, pull up Downflash, µP Address Bit 16.

55 UPSEN# CMOS 3.3V I/O, Programmable Store Enable Output.

56 UWR# CMOS 3.3V I/O, µP Write Strobe.

57 URD# TTL 5V I/O, µP Read Strobe.

58 URST TTL 5V Output, Reset signal output active high.4mA

59 UP3_0 TTL 5V I/O, pull Serial receive data/General Programmable I/O.up, 4mA

60 UP3_1 TTL 5V I/O, pull Serial transmit data/General Programmable I/O4mA

61 UP3_2 TTL 5V I/O, Pull External interrupt 0/General Programmable I/O.up, 4mA

63 UP3_4 TTL 5V I/O, pull Timer 0 Input/General Programmable I/Oup, 4mA

64 UP3_5 TTL 5V I/O, pull Timer 1 Input/General Programmable I/Oup, 4mA

178-180 IO6~IO4 CMOS 3.3V I/O, General Programmable I/O 4mA Alternate function:

IO4:pull up IO4: Serial clock.Default is input.IO5: pull down IO5: Serial receives data. Default is input.IO6: pull down IO6:Serial transmits data. Default is output =0.

176 IO8/CS# CMOS 3.3V I/O, General Programmable I/O, Alternate function:Chipselect signal for flash ROM selection. (When in IDEupdate flash ROM mode), active low. Default isoutput=0.

23 UA17/UP1_1 CMOS 3.3V I/O, Default : UP1_1 for general Programmable I/Opull up, 4mA Downflash : µP Address Bit 17.

62 UINT# Open Drain 5V µP InterruptOutput, 8mA

Crystal Interface & DRAM clock Interface

52 DMVSS Ground Ground pin for DRAM clock circuitry.

53 DMVDD Power Power pin for DRAM clock circuitry.

66 XTALI Crystal Input X’tal input. The working frequency is 33.8688MHz.

67 XTALO Crystal Output X’tal output.

Memory Interface

69 DQM CMOS 3.3V Output, SDRAM Input/Output Mask. Default is 4mA.Current programmable




pull down, 4mA

38


70 BA1 CMOS 3.3V Output, SDRAM Bank Address 1. Default is 4mA.Current programmable

71 BA0 CMOS 3.3V Output, SDRAM Bank Address 0. Default is 4mA.Current programmable

72 CKE CMOS 3.3V Output, SDRAM Clock Enable. Default is 4mA.Current programmable

73 CLK CMOS 3.3V Output, SDRAM Clock. Default is 4mA.Current programmable

74, 75 RA[11:10] CMOS 3.3V Output, RAM Address Bus[11:10]. Default is 4mA.Current programmable

77-83, 85, RA[9:0] CMOS 3.3V Output, RAM Address Bus[9:0]. Default is 4mA.86, 88 Current programmable

89 RAS# CMOS 3.3V Output, RAM Row Address Strobe. Default is 4mA.Current programmable

90 ROE# CMOS 3.3V Output, RAM Output Enable. Default is 4mA.Current programmable

91 RWE# CMOS 3.3V Output, RAM Write Enable (Low). Default is 4mA.Current programmable

92 CASH#/RWEH# CMOS 3.3V Output, RAM Colume Address Strobe/Write Enable Current programmable High. Default is 4mA.

93 CAS# CMOS 3.3V Output, RAM Colume Address Strobe(Low). Current programmable Default is 4mA.

95-103, RD[15:0] CMOS 3.3V I/O, Current RAM Data Bus. Default is 4mA. Default is pullup.

Audio Output Interface

114 ADGO TTL 5V Output, Audio digital output4mA

115 DACVSS Ground Ground pin for internal DAC circuitry

116 RO Analog Output Audio DAC Right output

117 DACVREF Analog output Reference Voltage for External Audio FilterCircuit

118 LO Analog Output Audio DAC Left Output

119 DACVDD Power Power Pin for Internal DAC circuitry

System Clock Interface

104 IPLLVDD Power Power pin for system varipitch circuitry.

105 IPLLVSS Ground Ground pin for system varipitch circuitry.

Host Interface

120 DASP# TTL 3.3V Input, Drive active/Slave present.Schmitt Input, pull up

121 CS3FX# TTL 3.3V Input, Host chip select 2 (for 3Fxh/37xh)Schmitt Input, pull up

122 CS1FX# TTL 3.3V Input, Host chip select 1 (for 1Fxh/17xh)Schmitt Input, pull up

programmable, pull up,pull down programmable

106-113

39


124, 125, 127 HA[2:0] TTL 3.3V Input, Host Address Bus.Schmitt Input, pull up

126 PDIAG# TTL 3.3V Input, Passed DiagnosticsSchmitt Input, pull up

129 IOCS16# TTL 3.3V Output, I/O 16-bit Chip Select10mA

130 INTRQ TTL 3.3V Output, Host Interrupt10mA

131 DMACK# TTL 3.3V Input, DMA AcknowledgeSchmitt Input, pull up

132 IORDY TTL 3.3V Output, I/O Channel Ready10mA

133 DIOR# TTL 3.3V Input, Drive I/O ReadSchmitt Input, pull up

135 DIOW# TTL 3.3V Input, Drive I/O WriteSchmitt Input, pull up

136 DMARQ TTL 3.3V Output, DMA Request10mA

137-155 HD[15:0] TTL 3.3V I/O, Schmitt Host Data Bus, Default is 6mA. Default is pullup.

157 HRST# CMOS 3.3V Input, Host Reset.Schmitt Input, pull up

CLV Varipitch Interface

159 VPVDD Power Power pin for varipitch VCO circuitry.

160 VCOCIN Analog Input Connect capacitor for compensator loop filter.

161 VPVSS Ground Ground pin for vapipitch VCO circuitry.

Miscellaneous

158 PRST CMOS 3.3V Input, Power-On Reset.Schmitt Input, pull down

162 TEST CMOS 3.3V Input, Test mode Pin.Schmitt Input, pull down

Flag and Programmable I/O Interface

171 FLAGD CMOS 3.3V I/O,4mA The internal f lags of servo DSP can beselected to output over FLAGD pin. Default isoutput=0.

172 FLAGC CMOS 3.3V I/O,4mA The internal f lags of servo DSP can beselected to output over FLAGC pin. Default isoutput=0.

173 FLAGB CMOS 3.3V I/O,4mA The internal f lags of servo DSP can beselected to output over FLAGB pin. Default isoutput=0.

Pull down, 4mA

input, current programmable, pull up,

pull down programmable

40


174 FLAGA CMOS 3.3V I/O, The internal flags of servo DSP can be selected tooutput over FLAGA pin. To program the selection µPmust write FLGMOD register. Default is output =0.

Alternate function: Internal or External µP select, “1”:use external µP (i.e. ICE mode determined by poweron reset) and disable internal µP.

181 IO3 CMOS 3.3V I/O, Programmable I/O or internal non-servo flags output.Default is input.




RF SIO interface & Defect

185 SDATA CMOS 3.3V I/O, RF serial data outputSchmitt Input, 4mA

186 SDEN CMOS 3.3V RF serial data latch enableOutput, 4mA

187 SLCK CMOS 3.3V RF serial clock outputOutput, 4mA

188 BDO CMOS 3.3V Input, Flag of defect data input statusSchmitt Input,

pull down

Digital Power & Ground

34, 65, 84, 94, DVDD3 Power +3.3V digital supply123,128,156,170

16,76,177 DVDD Power +5V digital supply

21, 29, 43,68, DVSS Ground digital ground87,101,134,140,146,151,175

Pull down, 4mA

Pull up, 8mA

Pull up, 4mA

4mA

Pull up, 8mA

41

IC601 (M63022FP): Drive IC

VMI

FG ReverseDetect

120MATRIX

FG

HU+HU-HV+

HV-HW+

HW-HB

SPIN

REF

SL1 IN

SL2IN

FOIN

TOIN

5VCC5V power supply

TO+

TO-

FO+

FO-

LO+

LO-

VM3

LOIN+

BRS

OSC

MU1

SL2

-S

L2+

RS

L2

VM

2

SL1

-S

L1+

RS

L1

WVURS

P

VM

1

SSS S

GN

D

X12 X12 X8

Hall Bias

CILamp.

Currentcomp.

Currentcomp. Current

comp.

LogicLogic

TSI

BIAS

Frequencygenerator

CTLamp. CTL

amp.

Directioncomp.

Directioncomp. Direction

comp.

Regulator

• Pin Description

Block Diagram

Terminal SYMBOL TERMINAL FUNCTION

1 SL1IN Slide control voltage input 1.

2 SL2IN Slide control voltage input 2..

3 VM2 Motor Power Supply 2(for Slide)

4 RSL2 Slide current sense 2.

5 SL2+ Slide non-inverted output 2

6 SL2- Slide inverted output 2

7 GND GND

8 RSL1 Slide current sense 1

9 SL1+ Slide non-inverted output 1

10 SL1- Slide inverted output 1

11 GND GND

12 W Motor drive output W

13 V Motor drive output V

14 U Motor drive output U

15 RSP Spindle current sense

16 HW- HW- sensor amp. input

17 HW+ HW+ sensor amp. input

18 HV- HV- sensor amp. input

19 HV+ HV+ sensor amp. input

20 HU- HU- sensor amp. input

21 HU+ HU+ sensor amp. input

Terminal SYMBOL TERMINAL FUNCTION

22 VM1 Motor power Supply 1(for Spindle)

23 HB Bias for Hall Sensor

24 FG Frequency generator output

25 REF Reference voltage input

26 SPIN Spindle control voltage input

27 FOIN Focus control voltage input

28 TOIN Tracking control voltage input

29 GND GND

30 5VCC 5V Power Supply (for FS. TS)

31 TO- Tracking inverted output

32 TO+ Tracking non-inberted output

33 GND GND

34 FO+ Focus non-inverted output

35 FO- Focus inverted output

36 LO+ Loading non-inverted output

37 LO- Loading inverted output

38 BRS Brake select control terminal

39 VM3 Motor Power Supply 3 (for Loading)

40 LOIN+ Loading control input (+)

41 MU1 mute 1

42 OSC PWM carrier oscillation set

42

TROUBLESHOOTING GUIDE

Reset or Power ON.

•Check the power short.•Check PC power cable, power

supply and fuse.Repair PC power supply.

NO

YES

OK

YES

Are the pin 44 and 41 of CN 201 +5V and +12V

respectively after the powercable connecting?

Replace IC101 (3.3V Regulator).NOIs the pin 3 of

IC101 3.3V?

Replace X201 when the powersupply of IC201 is OK.

NO

YES

Do the X201oscillating?

YES

Refer to “Tray open / closedoesn’t work.”

NODoes the tray open or

close?

(Check it after connecting the power cable only no interface cable)

A

43

Refer to “Laser Diode is not on.”

A

NO

Refer to “Servo part isabnormal”.

NO

YES

Is the Laser Diode“ON”?

Does the Focus moveup and down?

Refer to “Disc Readingoperation is abnormal.”

NO

YES

Is the TOC area on the disc read? (Does

the LED flicker?)

44

Check and replace theSW403 or peripheral resistorand pattern short.

Tray open/close doesn’t work.

NO

YES

Does the waveform appear at

the IC201 pin 163, 164 whenpush the SW403 (open/close)?

B

5V

Push period

Check and replace the R622,R625 or pattern short.

NO

Does the waveform appear

at the R622 connected to IC201 pin 19?

opennormal

close

Does the signal appear

at the IC601 pin 36 and 37?

closingperiod

Pin 37

Pin 36openingperiod

YES

Check and replace the IC201.NO

Does the IC201 pin 163 and

164 appear in the tray open/close mode ?

YES

YES

Check the cold soldering forthe IC601 and then replaceIC601.

NO

45

B

Is the connecting status normal

between the CN301 and loading motor?

Check the cold soldering forthe CN301 and wireconnecting status and thenreplace loading motor.

NO

YES

Open/close mode is normal.

46

Refer to “Reset or Power ON”.

Laser Diode is not ON.

YES


Check the cold soldering forthe transistor Q301 and thenreplace Q301.

Replace the Pick-up.

YES

YES

NO

NO

NO

CD PART

DVD PART

NO

Does the focusingactuator move up and

down?

Is the PN301 pin 16 about 2.3V at theinitial power on mode?

Does the signal appear at IC301

Pin 52?

Is the collector oftransistor Q301 about

2V?

YES

C

3.8V

5V

OK

47

C

Is the PN301 pin 10 about 2V

at the initial power on mode?

NO

NO

NO

YES

YES

Replace the Pick-up.

Check the cold soldering forthe transistor Q302 and thenreplace Q302.

Does the signal appear at IC301

Pin 81?

Is the collector oftransistor Q302 about

2V?

3.7V

5V


YES

OK

48

• Check the cold soldering forthe IC301 pin 53, 54, 55, 56.

• Check the FPC connectingstatus PN 301.

• Check the pick up.

Check the CD RF SIGNAL.

NO

YES

Does the RF out signaloutput?

(IC301 pin 86 : CD RF)

Check the cold soldering for theC234, C233.

NODoes the RF signal input to the

IC201 Pin 207?

49

• Check the cold soldering forthe IC302 pin 40, 41, 42, 43.

• Check the FPC connectingstatus PN301.

• Check the pick up.

Check the DVD RF signal.

NO

YES

Does the RF out signaloutput from the pick-up?(IC301 pin 86 : DVD RF)

Check the cold soldering for theC234, C233.

NODoes the RF signaloutput from the IC201

pin207?

50

Servo part is abnormal.

Insert a disc.

Refer to “Spindle motorRotation is failed”.

• Check the Flat cableconnecting status PN601.

• Check the cold soldering forthe pin 5, 6, 9, 10, of IC601.

Refer to “Laser Diode is notON”.

YES

YES

YES

YES

YES

YES

YES

YES

NO

NO

Check the RF signal flow.

A

B

NO

NO

NO

NO

NO

C

Does the pick-up slideinner track?

Does the disc rotate?

Is the Laser Diode on?

Does the focus move upand down?

Is the FEO signal “H”?(IC201 Pin 198)

Does the disc rotate inhigh speed repeatedly?

Is the RF signal Good?

OK

51

Check the cold soldering forthe IC601pin 34, 35.

Replace IC601.

Check the FG signal line.

Check the cold soldering forthe IC601.

YES

NO

YES

A

B

NO Check the circuit between theIC201 Pin 12

and the IC601 Pin 27.

C

Check the FOSO signal at theR207 connected to

IC201 pin 12.

Does the square wave output at the IC601 Pin 24

(FG)?

V

1.35V

T

Check the cold soldering for theIC301 pin95 and R234 and IC201

pin 198.

52

Check the spindle drivesignal.

(IC601 Pin 26)

Check the cold soldering forthe IC201 pin 17.

Replace the IC201.

Spindle Motor Rotation isfailed.

Check PN601.

Check the cold solderingfor the PN601.

Replace the spindle Motor.

Reassembled PN601.

NO

NO

YES

YES

YES

Does the above signal output after the

tray close?

Is the PN601 assembled ‘OK’?

Is the disc rotation OK?

V

2.2-2.4V

NO

T

53

No Audio output.

Check the headphone jack andcable.

Insert the audio disc.

YES

Check the DSP IC201 pin 179.

NO

NO

YES

NO

NO

Replace IC401.YES

Check the cold soldering for theVR401, R412, R413, R406 and

R407.

YES

YES

NO

YES

Check the IC401 andperipheral components.

NO

YES

Replace IC201

Check the cold solderingfor the CN301 andconnector CN401.

NO

Check the peripheral partsbetween the pin 97, 99 of

IC201 and CN301 pin 3, 6.

Does the signal output at theheadphone jack?

Is the Pin 2 of IC401 is 5V?

Does the Audio signal output atthe C409 and C408?

Does the Audio signal output atthe C403 and C404?

Does the Audio signal inputted at pin 3, 6,

of CN401?

Does the Audio signal output atIC201 pin 116, 118?

Does the signal output at the pin

Pin3, 6 of CN301?

A B C D

1

2

3

4

5

54

BLOCK DIAGRAM

Focus actuator

Drive

Tracking actuator

Drive

SlidemotorDrive

M63022FP

Audio Signal

Processor

SpindlemotorDrive

AGC

MT1316F(RF Amplifier)

HOST COMPUTER

Spindlemotor

OpticalPick up

Slide motor

SF-HD3SS

DVD PLL&

DVD SERVO DSP

Decoder/CSS & ATAPI

Interface

Equalizer APC

CD PLL&

CD SERVO DSP

MT1318F(DSP&interface)

Latch74HC373)

Focus actuator

Drive

Tracking actuator

Drive

SlidemotorDrive

M63022FP/M63023FP

Audio Signal

Processor

SpindlemotorDrive

AGC

MT1326F(RF Amplifier)

HOST COMPUTER

Spindlemotor

OpticalPick up

Slide motor

SF-H

DVD PLL&

DVD SERVO DSP

Decoder/CSS & ATAPI

Interface

Equalizer APC

CD PLL&

CD SERVO DSP

MT1329F(DSP&interface)

Flash Rom

(SST39SF010)

DRAM

(M11B416256A)

PBM00 (MAIN C.B.A)

007

002

003

030

020

A02

A01

A03

020

051

028

050

029

434

021

434

434

413413

413

001

413

430

028

027026

025

024

435

033434

010

009

008011

012

005034

013

434

017

016

015

004

006

022021

430

A B C D E F G H

1

2

3

4

5

014

7 8

EXPLODED VIEW

Documents

INTRODUCTION GENERAL FEATURE - Diagramasde.com