IPC-9121, Troubleshooting PCB Fabrication Processes ... · IPC-9121, Amendment 1 – New Via Fill Section for Section 7 Hole Preparation and Protection ... IPC-9121, Amendment 1 –

IPC-9121 Amendment 1 Draft Document for Industry Consensus October 2017

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IPC-9121, Troubleshooting PCB Fabrication Processes Amendment 1 Final Draft for Industry Review October 2017 Comment deadline: October 30, 2017 To send comments or request a comment form, contact [email protected]. To join the IPC-9121, Amendment 1 ballot group, visit https://www.surveymonkey.com/r/9121Am1 before IPC-9121, Amendment 1 is balloted.

mailto:[email protected]

https://www.surveymonkey.com/r/9121Am1


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IPC-9121, Amendment 1 Table of Contents

IPC-9121, Amendment 1 – New Via Fill Section for Section 7 Hole Preparation and Protection ........ 3 IPC-9121, Amendment 1 – Microvia Topics for Section 9 Interconnect Formation............................. 9 IPC-9121, Amendment 1 – Pattern Plating Rim Voids Topics for Section 9 Interconnect

Formation .................................................................................................................................. 13 IPC-9121, Amendment 1 – New Section – Section 13, Flexible Circuits .......................................... 15

Please note that not all figures have captions, because we will not know the figure numbers until they are merged into the document when it goes to full revision. Figures that are part of entirely new section numbers have captions.


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IPC-9121, Amendment 1 – New Via Fill Section for Section 7 Hole Preparation and Protection

7.13 Via Fill

The continued fast pace towards miniaturization is leading printed board designers to advance integration density. Because of this trend, fabricators are investigating methods and processes that will enable the move towards sequential lamination, blind and buried vias and via-in-pad technology. Many printed board fabricators are adopting techniques such as via filling capability with nonconductive, high-Tg, low-CTE plugging pastes.

Partially plugging some or all via holes with solder mask prevents solder from wicking through the holes (to the component side) during the assembly process, creates a vacuum for electrical test and can minimize flux residues in the holes.

The concern of plugging through holes with a standard liquid photoimageable (LPI) solder mask resides in the fact that these inks are typically 60 % to 80 % solids content. During the drying/curing process, the solvent evaporates and the hole plug shrinks, often resulting in a small gap between the through hole barrel and the plug. This can result in a lack of adhesion of the plug to the hole wall. Another concern is residual solvents from the LPI. During the curing process, operating conditions may lead to a “skinning over” of the plug. This scenario causes solvent to remain entrapped within the hole. As a result, the solvent will expand during the heat of the soldering operations, leading to cracking of the fill. As through hole aspect ratios increase, it may become impossible to evacuate all the solvent. Process curing temperatures and ramp-up time to cure must be carefully monitored, regardless of the technology level of the printed board.

LPIs have limitations that can only be addressed with the use of plugging pastes. These plugging pastes are nearly 100 % solids content and were primarily developed for blind and buried vias and sequential build technology. However, other formulations have been developed for filling through holes to replace the LPI inks, based on the same principle of 100 % solids content.

Via hole filling is used for nonplanar filling of plated through holes. Via hole plugging is the planarization of blind vias, buried vias and through holes. Via hole plugging is applicable to HDI and microvia designs. Brushing (or planarization) is required to remove the excess material and to create the flat surface.

Via hole plugging is in demand due to HDI designs with area array for IC packaging, via-in-pad and landless designs and to achieve planarity of the via for dielectric formation. Uniform dielectric spacing between layers of circuitry is critical, as is the ability to metallize the dielectric to achieve plating adhesion.

Figure 7.13-1 shows an HDI substrate with plated through holes, filled buried vias and microvias. In this example, all the via types would be candidates for filling.

Figure 7.13-1 HDI Substrate With Plugged Vias


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The vias can be described as follows:

• Completely plugged and over-metallized via-in-pad • Completely plugged buried vias over several layers as necessary • Completely plugged and over-metallized buried vias over several layers as necessary

One of the most widely used applications for plugging paste is for via-in-pad designs (see Figure 7.13-2).

Figure 7.13-2 Over-Metallized Via-in-Pad

Several OEMs are driving the industry to migrate to the high-Tg/low-CTE plugging paste formulations for high-density applications. These formulations are of a nonconductive nature that provides a high-quality plugged via and are also cost-effective.

7.13.1 Plugging Paste-material and properties for non-conductive paste

There are specific requirements for the plugging paste material. These are:

Good adhesion between copper and paste, even under temperature influences Good adhesion of copper, dielectrics or photo resist Solvent-free, one-pack system No air inclusions in the paste Tg > 140 °C CTE < 40 ppm (below Tg) No shrinkage during curing Easily planarized


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Additionally, the plugging paste material must maintain a reasonable shelf life at room temperatures. Some commercially available formulations have a one-month shelf, greatly reducing the processing window.

A 100 % solids content of the paste material with the thermally cross-linkable epoxy resin and specially designed ceramic fillers ensures a low CTE. CTE must remain in the 40 ppm to 60 ppm range to ensure no cracking occurs in the filled via. In addition, it is critical that z-axis expansion be minimized to prevent the plated cap from lifting (Figure 7.13-3).

Figure 7.13 Excessive CTE Leading to Plated Copper Lifting From Filled Via

7.13.2 The Relationship between CTE and Tg

Filled vias must be void free and maintain integrity throughout various thermal excursions. Despite Z-axis expansion, the second critical thermal characteristic is the Tg of the cured paste material. Typically, a Tg of 140 °C is ideal; however, the Tg can be increased by prolonging the final curing time and increasing curing temperature from 140 °C to approximately 175 °C to 180 °C. The manufacturer should attempt to achieve the highest possible Tg without impacting the flow and metallization properties.

As increased densification results in higher I/Os, smaller components, higher assembly temperatures and smaller vias, CTE will have increased importance. CTE values of the paste must be minimized to relieve stress that will cause the plug to over-expand, enabling the over-metallized copper deposit to lift. To attain long-term stability within the filled via under load conditions, load amplitudes must be minimized as much as possible. This means CTE must be as low as possible across the temperature ranges.

It should be noted that temperature control of the via fill material curing process influences the Tg. As a result, uncontrolled reactions that include excessively fast or aggressive curing times will result in a crosslinked network with many voids as well as cracking within the plugged via. This type of situation leads to low Tg and higher CTEs, which are both undesirable.

Figure 7.13-4 shows the effect of fast curing temperatures, leading to a sagging condition.


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Figure 7.13-4 Cracked Via Plug Caused By an Uncontrolled and Excessively Fast Curing Process

TROUBLESHOOTING TOPICS

Issue: Slight Depression in the Filled Material

Figure 7.13-5

Note: In and of itself, this is not a defect; however, there can be an issue with component mounting in the depressed area. The photo on the left shows the slight depression. The photo on the right shows a good example of a filled via with no plating adhesion issues and uniform resin fill.

CAUSE ACTION Excessive cure temperature of the via-fill paste

Check temperature and timer of cure and reduce temperature

Excessive smear removal prior to plating

Check concentrations of the chemistry in the alkaline permanganate chemistry Reduce operating temperatures and dwell times

Resin over-cured Adjust multilayer lamination parameters Potential test method (discover) Potential test method (verification)

DSC and TMA determine degree of cure Resin weight loss


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Issue: Insufficient Wrap Plating

Figure 7.13-6

CAUSE ACTION Over-planarization of paste after cure Adjust scrubbing/sanding parameters Plating is not continuous over knee of via

Investigate plating parameters Ensure sufficient time and current in plating operation

Potential test method (discover) Potential test method (verification) Microsection analysis

Issue: Plated Copper Separates From the Filled Via

Figure 7.13-7

CAUSE ACTION Excessive Z-axis expansion Check Tg of paste fill material

Check final cure temperature Under-cured paste fill material Check time of cure, and temperature Poor adhesion of plated copper over paste-filled material

Plating highly stressed or marginal desmear of the paste fill after cure

Potential test method (discover) Potential test method (verification) Temperature profile of curing oven Use standard oven profile equipment


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Issue: Voids in Filled Via

Figure 7.13-8

CAUSE ACTION Air entrapment due to action of pushing paste in via Air entrapment in paste material

Use vacuum table and different stencil if paste filling by manual operation Place paste material in vacuum to draw out air bubbles prior to use Use multiple passes of filling to push air out of via

Insufficient vacuum draw-down during paste filling operation

Adjust vacuum and fill head pressure as required

Viscosity of paste fill material too high Paste may have started to prematurely cure

Check storage conditions and stated shelf life Adjust temperature of fill head to reduce viscosity

Potential test method (discover) Potential test method (verification) Viscosity check If viscosity too high, either discard material or try to heat material while in

fill head


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IPC-9121, Amendment 1 – Microvia Topics for Section 9 Interconnect Formation

Issue: Etch Artifacts Observed After Microsectioning of Microvias

CAUSE ACTION Nonuniform etch rates of electroless and electroplated copper layers

Perform a comparison before and after etch Defocused microscopy Revise etch concentration, time or temperature

Potential test method (discover) Potential test method (verification) Surface profilometry


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Issue: Plating Artifacts in Microvia

CAUSE ACTION Non-uniform plating rates of electroless and electroplated copper layers

Check plating bath, solution and time setup.

Flaking or peeling electroless copper Check plating rates and optimize chemistry in electroless copper process Annular ring misregistration Perform alignment check Potential test method (discover) Potential test method (verification)


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Issue: Missing Surface Copper Plating

CAUSE ACTION Debris or other surface impurity present on foil prior to plating

Perform a thorough cleaning of the surface prior to imaging and plating

Incomplete development of resist Adjust developer pH and time to ensure it is complete Less than optimum etch resist thickness Review all parameters, including time and current density of plating

operation Potential test method (discover) Potential test method (verification)

Issue: Deformation-Induced Voiding in Flex Observed After Microsectioning

CAUSE ACTION Blunt drill tool Check drill tool Inadequate adhesion between layers Check type/compatibility of adhesive/prepreg and cure schedule Inadequate stiffness of inner layer adhesive/prepreg

Check stiffness of inner layer adhesive/prepreg

Potential test method (discover) Potential test method (verification) DMA


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Issue: Cap Plating Pulled Off

CAUSE ACTION Mismatched via fill – CTE too low Check the properties of via fill materials Under-cured via fill Check Tg and degree of cure of fill material Potential test method (discover) Potential test method (verification)

DSC/TMA/DMA

Issue: Design Issues With Stacked or Staggered Vias misregistration

CAUSE ACTION Laser drilling misregistered Add fiducials to that layer for laser drill to find and realign. Using tooling holes from x-ray or bomb-site of all layers

Decouple general tooling hole for mechanical drilling from laser drilling alignment

Laser drilling not properly tooled Present separate laser drill pad master for each layer with registration dim Potential test method (discover) Potential test method (verification)

Drill coupon on border for laser drilling


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IPC-9121, Amendment 1 – Pattern Plating Rim Voids Topics for Section 9 Interconnect Formation

Issue: Rim Void

CAUSE ACTION Tin breakdown Check chemistry make-up

Check for contamination Potential test method (discover) Potential test method (verification)

Microsection Lab analysis

Issue: Rim Void

CAUSE ACTION Burned tin Check plating current Incorrect current for plating area Check plating area and current settings Potential test method (discover) Potential test method (verification)

Microsection/Procedures Verify plating current settings


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Issue: Rim Void

CAUSE ACTION Thin/Low tin Verify current settings

Verify time in plating bath Verify plating area and current settings

Potential test method (discover) Potential test method (verification) Microsection, plating settings, procedures

Microsection

Issue: Rim Void

CAUSE ACTION Thin/Low tin Check plating concentration in plating bath Potential test method (discover) Potential test method (verification)

Lab analysis Microsection


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IPC-9121, Amendment 1 – New Section – Section 13, Flexible Circuits

Issue: Coverlay Coverage

Figure 13.1-1

CAUSE ACTION Insufficient time at temperature during lamination

Check the data from the press cycle Verify material supplier’s recommended parameters Use thermocouples to verify temperature gradients

Pressure failure during lamination Verify there are no low-pressure areas on the press platens Verify the data from the press cycle Conduct a pressure test on each press gap

Expired out-of-date material Verify material certificate of conformance is in date Moisture Check storage conditions Poor surface preparation Verify surface preparation procedure was followed

Verify adhesion promotion process is in specification Surface contamination Verify surface preparation procedure was followed Potential test method (discover) Potential test method (verification)

Visual inspection Visual inspection


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Issue: Coverlay Coverage

Figure 13.1-2

CAUSE ACTION Incorrect press temperature Check readings if thermocouple used/check procedures Pressure issue at lamination Check readings if data are available/check procedures Insufficient tacking Check procedure for tacking the coverlay Wrong packing during lamination Check for what was used to support the panel in the press/procedures Potential test method (discover) Potential test method (verification)

Visual Visual, verification of press parameters

Issue: Adhesive Squeeze-Out – Land Area

Figure 13.1-3

CAUSE ACTION Too much resin in dielectric gap Check stack-up Insufficient cut-back Check data Moisture in material Check storage conditions Too much pressure Check press parameters Potential test method (discover) Potential test method (verification)

Visual Visual


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Issue: Adhesive Squeeze-Out – Foil Surface

Figure 13.1-4


Visual Visual Issue: Access Hole Registration

Figure 13.1-5

CAUSE ACTION Misaligned during tacking Check alignment during tacking process Routed incorrectly Check data Scaling Check material movement Potential test method (discover) Potential test method (verification)

Visual Visual


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Issue: Plating Defects

Figure 13.1-6

CAUSE ACTION Rough drilling Verify drilling parameters, entry foil, backing material, speeds and feeds,

number of hits Copper bath concentration Verify plating solution is within specified limits Current density Verify plating area versus current Burring Check entry foil, backing material Electroless coverage Verify electroless solution is within specified limits Potential test method (discover) Potential test method (verification)

Microsection in process Microsection, pin gauge


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Issue: Transitional Zone Squeeze-Out

Figure 13.1-7


Visual Visual

Issue: Solder Wicking/Plating Under Coverlay

Figure 13.1-8

CAUSE ACTION Check coverlay adhesion See notes for coverlay coverage Multiple passes in solder process Check to determine if maximum number of passes was not exceeded during

HASL Potential test method (discover) Potential test method (verification)

Visual Visual


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Issue: Voids

Figure 13.1-9

CAUSE ACTION Insufficient time at temperature during lamination

Check the data from the press cycle Verify material supplier’s recommended parameters Use thermocouples to verify temperature gradients

Pressure failure during lamination Verify there are no low-pressure areas on the press platens Verify the data from the press cycle Conduct a pressure test on each press gap

Expired out-of-date material Verify material certificate of conformance is in date Insufficient resin Determine if stack-up has sufficient resin for in-fill of copper in low-pressure

areas Potential test method (discover) Potential test method (verification)

Microsection/Visual Microsection/Visual


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Issue: Etchback

Figure 13.1-10

CAUSE ACTION Insufficient time in plasma, resulting in desmear issues

Check process parameters as per supplier’s recommendations Ensure correct parameter settings were used

Cycle is too aggressive, resulting in too much etchback


Incorrect gas mixture in plasma chamber, resulting in too much/too little etchback


Too much time in chamber causes too much etchback


Potential test method (discover) Potential test method (verification) Microsection Microsection


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Issue: Smear Removal

Figure 13.1-11

CAUSE ACTION Insufficient time in permanganate, resulting in desmear issues


Permanganate concentration causes desmear issues

Check process parameters as per supplier’s recommendations Ensure correct parameter settings were used Verify using lab results

Material parameters result in insufficient desmear


Material Verify the material can be processed with permanganate If it is chemically resistant, it will need to be processed through plasma

Potential test method (discover) Potential test method (verification) Microsection Microsection, Lab testing for the chemistry


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Issue: Trimmed Edges

Figure 13.1-12

CAUSE ACTION Mechanically processed Check if depanelization was mechanical

Use laser trimming Worn router bits Check linear footage use for each router bit Flex not held down properly during routing

Check method for holding down flex

Potential test method (discover) Potential test method (verification) Visual Visual, CMM, Mechanical measurements

Issue: Silver Film

Figure 13.1-13

CAUSE ACTION Pinholes in screen Verify there are no pinholes in the silver-screen-printing process Potential test method (discover) Potential test method (verification)

Visual Visual

Documents

IPC-9121, Troubleshooting PCB Fabrication Processes ... · IPC-9121, Amendment 1 – New Via Fill Section for Section 7 Hole Preparation and Protection ... IPC-9121, Amendment 1 –