JLT Presentation

8/10/2019 JLT Presentation

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A Device Simulation Case Study: Junctionlessfield effect transistor for low power

applications in the deca nanometer regime

Anil Kottantharayil,

Suresh Gundapaneni, Naveen N., Shanky Jain, Amit Gaur, Srihari

Marni and Swaroop Ganguly

Department of of Electrical Engineering and Centre of Excellence inNanoelectronics, IIT Bombay, Powai, Mumbai -76, India.

E-mail: [email protected]


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1946 - Electronic NumericalIntegrator & Calculator ENIAC2.4 m X 1 m X 30 m30,000 kg

18,000 vacuum tubes5,000 additions/sec$ 500,000Pennsylvania University Archives.

2011 - A low-end IT device

0.02 m X 0.1 m X 0.15 m300 g

> 1000,000,000 transistors~ 100,000,000 HzNetworked, better interface$ 250

CNN

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Gate dielectric

Gate

p-type Si

VG

p-type silicon - has holes and ionized acceptors

holes - positive charge ionized acceptor - negative charge

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VG> 0

potential at the siliconsurface increases

holes are pushed into thesubstrate

surface is devoid of mobilecharges - depletion region

VGsufficiently > 0

potential at the siliconsurface increases further

surface potential favorable

for electrons

electron surface layerforms - inversion layer

p

p

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Where do the free electrons come from ?

! Thermally generated in the silicon close to thesurface - MOS Capacitor

!

Photo generated CCD camera ICs

! Can be provided by n-doped regions on thesurface - MOSFET

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VG~ 0

no path for electron flow

open switch

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VGsufficiently > 0

channel for electron flow

from source to drain

closed switch - abovethreshold

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G

S B D

source

drain

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body

gate dielectrictOX

spacer

isolation

doping = NA

xj

gate

L

n+

poly

W

xy

z

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High hole mobility due to quantum confinementTiwari et al., Nano Lett., 2011.

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