K64P144M120SF5RM

Document Number: K64P144M120SF5RM
2 Freescale Semiconductor, Inc.
1.1 Overview.......................................................................................................................................................................59
1.1.1 Purpose.........................................................................................................................................................59
1.1.2 Audience......................................................................................................................................................59
1.2 Conventions..................................................................................................................................................................59
2.2.2 System Modules...........................................................................................................................................63
Freescale Semiconductor, Inc. 3
3.2.4 FPU Configuration.......................................................................................................................................81
3.3.3 PMC Configuration......................................................................................................................................83
3.3.5 MCM Configuration....................................................................................................................................86
3.3.8 Peripheral Bridge Configuration..................................................................................................................92
3.3.12 Watchdog Configuration..............................................................................................................................99
3.4 Clock modules..............................................................................................................................................................100
3.4.1 MCG Configuration.....................................................................................................................................100
3.4.2 OSC Configuration......................................................................................................................................101
3.9.3 CAN Configuration......................................................................................................................................155
3.9.4 SPI configuration.........................................................................................................................................157
3.9.5 I2C Configuration........................................................................................................................................160
3.9.6 UART Configuration...................................................................................................................................161
3.9.7 SDHC Configuration....................................................................................................................................164
3.9.8 I2S configuration..........................................................................................................................................165
3.10 Human-machine interfaces...........................................................................................................................................169
3.10.1 GPIO configuration......................................................................................................................................169
4.4 SRAM memory map.....................................................................................................................................................175
4.5.1 Read-after-write sequence and required serialization of memory operations..............................................176
4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................177
4.5.3 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................180
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................184
Chapter 5 Clock Distribution
5.5.2 VLPR mode clocking...................................................................................................................................190
5.7.9 FlexCAN clocking.......................................................................................................................................197
6.1 Introduction...................................................................................................................................................................201
6.2 Reset..............................................................................................................................................................................202
7.4 Power mode transitions.................................................................................................................................................216
7.7 Clock Gating.................................................................................................................................................................221
8.3.1 Security interactions with FlexBus..............................................................................................................224
8.3.2 Security Interactions with EzPort................................................................................................................224
8.3.3 Security Interactions with Debug.................................................................................................................224
9.5.1 MDM-AP Control Register..........................................................................................................................233
9.5.2 MDM-AP Status Register............................................................................................................................235
9.11.2 ETB Counter Control...................................................................................................................................240
9.14.1 Debug Module State in Low Power Modes.................................................................................................242
K64 Sub-Family Reference Manual, Rev. 2, January 2014
10.1 Introduction...................................................................................................................................................................243
10.2.2 Port control and interrupt summary.............................................................................................................244
10.2.3 PCRn reset values for port A.......................................................................................................................245
10.2.4 Clock gating.................................................................................................................................................245
10.3.2 K64 Pinouts..................................................................................................................................................252
11.1 Introduction...................................................................................................................................................................273
11.2 Overview.......................................................................................................................................................................273
11.2.1 Features........................................................................................................................................................273
11.5.1 Pin Control Register n (PORT x _PCRn).......................................................................................................282
11.5.2 Global Pin Control Low Register (PORT x _GPCLR)..................................................................................284
11.5.3 Global Pin Control High Register (PORT x _GPCHR).................................................................................285
11.5.4 Interrupt Status Flag Register (PORT x _ISFR)............................................................................................286
11.5.5 Digital Filter Enable Register (PORT x _DFER)...........................................................................................286
11.5.6 Digital Filter Clock Register (PORT x _DFCR)............................................................................................287
11.5.7 Digital Filter Width Register (PORT x _DFWR)..........................................................................................287
11.6 Functional description...................................................................................................................................................288
11.6.1 Pin control....................................................................................................................................................288
12.1 Introduction...................................................................................................................................................................291
12.1.1 Features........................................................................................................................................................291
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................295
12.2.8 System Clock Gating Control Register 1 (SIM_SCGC1)............................................................................307
12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................320
12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................322
12.2.17 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................323
12.2.18 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................326
12.2.19 Unique Identification Register High (SIM_UIDH).....................................................................................327
12.2.20 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................327
12.2.21 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................328
12.2.22 Unique Identification Register Low (SIM_UIDL)......................................................................................328
13.1 Introduction...................................................................................................................................................................331
13.2.5 Mode Register (RCM_MR).........................................................................................................................337
14.1 Introduction...................................................................................................................................................................339
Chapter 15 Power Management Controller (PMC)
15.1 Introduction...................................................................................................................................................................359
15.2 Features.........................................................................................................................................................................359
15.4 I/O retention..................................................................................................................................................................361
15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................362
15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................363
15.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................364
Chapter 16 Low-Leakage Wakeup Unit (LLWU)
16.1 Introduction...................................................................................................................................................................367
16.1.1 Features........................................................................................................................................................367
16.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................376
16.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................378
16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................383
16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................384
16.3.11 LLWU Reset Enable register (LLWU_RST)...............................................................................................385
16.4.1 LLS mode.....................................................................................................................................................386
16.4.2 VLLS modes................................................................................................................................................386
17.1 Introduction...................................................................................................................................................................389
17.1.1 Features........................................................................................................................................................389
17.2.3 Control Register (MCM_CR)......................................................................................................................392
17.2.6 ETB Reload register (MCM_ETBRL).........................................................................................................398
17.2.8 Process ID register (MCM_PID).................................................................................................................399
18.1 Introduction...................................................................................................................................................................401
18.1.1 Features........................................................................................................................................................401
18.3 Functional Description..................................................................................................................................................408
18.3.1 General operation.........................................................................................................................................408
18.3.2 Register coherency.......................................................................................................................................409
19.1 Introduction...................................................................................................................................................................413
19.2 Overview.......................................................................................................................................................................413
19.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0)..............................................................................421
19.4.3 Power management......................................................................................................................................430
19.5 Initialization information..............................................................................................................................................431
19.6 Application information................................................................................................................................................431
20.1 Introduction...................................................................................................................................................................435
20.1.1 Features........................................................................................................................................................435
20.3.1 Access support.............................................................................................................................................452
21.1 Introduction...................................................................................................................................................................455
21.1.1 Overview......................................................................................................................................................455
21.1.2 Features........................................................................................................................................................456
21.4.3 Always-enabled DMA sources....................................................................................................................461
22.1 Introduction...................................................................................................................................................................467
22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................492
22.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................493
22.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................494
22.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................495
22.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................496
22.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................497
22.3.11 Clear Error Register (DMA_CERR)............................................................................................................498
22.3.13 Interrupt Request Register (DMA_INT)......................................................................................................500
22.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................509
22.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................510
22.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................511
22.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................511
22.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................513
22.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................514
22.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................515
22.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................515
22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................517
22.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................518
22.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................521
22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................522
23.1 Introduction...................................................................................................................................................................547
23.1.1 Features........................................................................................................................................................547
24.1 Introduction...................................................................................................................................................................557
24.2 Features.........................................................................................................................................................................557
24.3.2 Watchdog configuration time (WCT)..........................................................................................................561
24.3.6 Low-power modes of operation...................................................................................................................563
24.3.7 Debug modes of operation...........................................................................................................................563
24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................568
24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................569
24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................570
24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................570
24.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................571
24.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................571
24.7.7 Watchdog Refresh register (WDOG_REFRESH).......................................................................................572
24.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................572
24.7.11 Watchdog Reset Count register (WDOG_RSTCNT)..................................................................................573
24.7.12 Watchdog Prescaler register (WDOG_PRESC)..........................................................................................574
24.8.1 General guideline.........................................................................................................................................574
25.1 Introduction...................................................................................................................................................................579
25.1.1 Features........................................................................................................................................................579
25.3.7 MCG Status Register (MCG_S)..................................................................................................................591
25.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................594
25.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................594
25.3.11 MCG Control 7 Register (MCG_C7)...........................................................................................................594
25.3.12 MCG Control 8 Register (MCG_C8)...........................................................................................................595
25.4.6 MCG PLL clock ..........................................................................................................................................602
25.4.7 MCG Auto TRIM (ATM)............................................................................................................................603
25.5.3 MCG mode switching..................................................................................................................................607
27.1 Introduction...................................................................................................................................................................627
28.1 Introduction...................................................................................................................................................................631
28.1.1 Overview......................................................................................................................................................631
28.1.2 Features........................................................................................................................................................632
28.4.2 Flash Bank 0 Control Register (FMC_PFB0CR)........................................................................................639
28.4.3 Flash Bank 1 Control Register (FMC_PFB1CR)........................................................................................642
28.4.4 Cache Tag Storage (FMC_TAGVDW0Sn).................................................................................................644
29.1 Introduction...................................................................................................................................................................655
29.1.1 Features........................................................................................................................................................656
29.3.4 Register descriptions....................................................................................................................................665
29.4.6 Functional modes of operation.....................................................................................................................685
29.4.8 Read while write (RWW)............................................................................................................................686
29.4.9 Flash Program and Erase..............................................................................................................................686
30.3 Command definition.....................................................................................................................................................730
30.3.1 Command descriptions.................................................................................................................................731
31.1 Introduction...................................................................................................................................................................739
31.1.1 Definition.....................................................................................................................................................739
31.1.2 Features........................................................................................................................................................739
31.4.4 Connecting address/data lines......................................................................................................................751
31.4.9 Address/data bus multiplexing.....................................................................................................................754
31.4.10 Data transfer states.......................................................................................................................................755
31.4.11 FlexBus Timing Examples...........................................................................................................................755
31.4.14 Bus errors.....................................................................................................................................................783
31.5 Initialization/Application Information..........................................................................................................................784
32.1 Introduction...................................................................................................................................................................785
32.1.1 Features........................................................................................................................................................785
32.2.1 CRC Data register (CRC_DATA)...............................................................................................................787
32.2.2 CRC Polynomial register (CRC_GPOLY)..................................................................................................788
32.2.3 CRC Control register (CRC_CTRL)............................................................................................................788
33.1 Introduction...................................................................................................................................................................795
34.1 Introduction...................................................................................................................................................................815
34.1.1 Overview......................................................................................................................................................815
34.3.1 RNGA Control Register (RNG_CR)...........................................................................................................817
34.3.2 RNGA Status Register (RNG_SR)..............................................................................................................819
34.3.3 RNGA Entropy Register (RNG_ER)...........................................................................................................821
34.3.4 RNGA Output Register (RNG_OR)............................................................................................................821
35.1 Introduction...................................................................................................................................................................825
35.1.1 Features........................................................................................................................................................825
35.3.1 ADC Status and Control Registers 1 (ADC x _SC1n)...................................................................................831
35.3.2 ADC Configuration Register 1 (ADC x _CFG1)...........................................................................................834
35.3.3 ADC Configuration Register 2 (ADC x _CFG2)...........................................................................................836
35.3.4 ADC Data Result Register (ADC x _Rn).......................................................................................................837
35.3.5 Compare Value Registers (ADC x _CVn).....................................................................................................838
35.3.6 Status and Control Register 2 (ADC x _SC2)................................................................................................839
35.3.7 Status and Control Register 3 (ADC x _SC3)................................................................................................841
35.3.8 ADC Offset Correction Register (ADC x _OFS)...........................................................................................843
35.3.11 ADC Plus-Side General Calibration Value Register (ADC x _CLPD).........................................................844
35.3.12 ADC Plus-Side General Calibration Value Register (ADC x _CLPS)..........................................................845
35.3.13 ADC Plus-Side General Calibration Value Register (ADC x _CLP4)..........................................................845
35.3.18 ADC Minus-Side General Calibration Value Register (ADC x _CLMD).....................................................848
35.3.19 ADC Minus-Side General Calibration Value Register (ADC x _CLMS).....................................................848
35.3.20 ADC Minus-Side General Calibration Value Register (ADC x _CLM4).....................................................849
35.4.2 Voltage reference selection..........................................................................................................................853
35.4.4 Conversion control.......................................................................................................................................854
36.1.5 CMP block diagram.....................................................................................................................................882
36.2 Memory map/register definitions..................................................................................................................................884
36.2.4 CMP Status and Control Register (CMP x _SCR).........................................................................................887
36.2.5 DAC Control Register (CMP x _DACCR)....................................................................................................888
36.2.6 MUX Control Register (CMP x _MUXCR)..................................................................................................889
37.1 Introduction...................................................................................................................................................................907
37.2 Features.........................................................................................................................................................................907
37.4.3 DAC Status Register (DAC x _SR)...............................................................................................................911
37.4.4 DAC Control Register (DAC x _C0).............................................................................................................912
37.4.5 DAC Control Register 1 (DAC x _C1)..........................................................................................................913
37.4.6 DAC Control Register 2 (DAC x _C2)..........................................................................................................914
38.1 Introduction...................................................................................................................................................................919
38.1.1 Overview......................................................................................................................................................920
38.1.2 Features........................................................................................................................................................920
38.2.1 VREF Trim Register (VREF_TRM)............................................................................................................922
38.4 Initialization/Application Information..........................................................................................................................926
39.1 Introduction...................................................................................................................................................................927
39.1.1 Features........................................................................................................................................................927
39.1.2 Implementation............................................................................................................................................928
39.1.5 Block diagram..............................................................................................................................................929
39.3.1 Status and Control register (PDB x _SC).......................................................................................................933
39.3.2 Modulus register (PDB x _MOD)..................................................................................................................935
39.3.3 Counter register (PDB x _CNT).....................................................................................................................936
39.3.4 Interrupt Delay register (PDB x _IDLY).......................................................................................................936
39.3.5 Channel n Control register 1 (PDB x _CHnC1).............................................................................................937
39.3.6 Channel n Status register (PDB x _CHnS).....................................................................................................938
39.3.7 Channel n Delay 0 register (PDB x _CHnDLY0)..........................................................................................938
39.3.8 Channel n Delay 1 register (PDB x _CHnDLY1)..........................................................................................939
39.3.9 DAC Interval Trigger n Control register (PDB x _DACINTCn)...................................................................939
39.3.10 DAC Interval n register (PDB x _DACINTn)...............................................................................................940
39.3.11 Pulse-Out n Enable register (PDB x _POEN)................................................................................................940
39.4.3 DAC interval trigger outputs........................................................................................................................943
39.5 Application information................................................................................................................................................947
39.5.1 Impact of using the prescaler and multiplication factor on timing resolution.............................................947
Chapter 40 FlexTimer Module (FTM)
40.1 Introduction...................................................................................................................................................................949
40.3.1 Memory map................................................................................................................................................954
40.3.2 Register descriptions....................................................................................................................................955
40.3.4 Counter (FTM x _CNT).................................................................................................................................962
40.3.5 Modulo (FTM x _MOD)................................................................................................................................963
40.3.7 Channel (n) Value (FTM x _CnV).................................................................................................................966
40.3.8 Counter Initial Value (FTM x _CNTIN)........................................................................................................967
40.3.9 Capture And Compare Status (FTM x _STATUS)........................................................................................967
40.3.11 Synchronization (FTM x _SYNC).................................................................................................................971
40.3.13 Output Mask (FTM x _OUTMASK).............................................................................................................975
40.3.14 Function For Linked Channels (FTM x _COMBINE)...................................................................................977
40.3.15 Deadtime Insertion Control (FTM x _DEADTIME).....................................................................................982
40.3.16 FTM External Trigger (FTM x _EXTTRIG).................................................................................................983
40.3.17 Channels Polarity (FTM x _POL)..................................................................................................................985
40.3.18 Fault Mode Status (FTM x _FMS).................................................................................................................987
40.3.19 Input Capture Filter Control (FTM x _FILTER)...........................................................................................989
40.3.20 Fault Control (FTM x _FLTCTRL)...............................................................................................................990
40.3.21 Quadrature Decoder Control And Status (FTM x _QDCTRL)......................................................................992
40.3.22 Configuration (FTM x _CONF).....................................................................................................................994
40.3.24 Synchronization Configuration (FTM x _SYNCONF)..................................................................................997
40.3.25 FTM Inverting Control (FTM x _INVCTRL)................................................................................................999
40.3.26 FTM Software Output Control (FTM x _SWOCTRL)..................................................................................1000
40.3.27 FTM PWM Load (FTM x _PWMLOAD).....................................................................................................1002
40.4.1 Clock source.................................................................................................................................................1004
40.4.11 PWM synchronization..................................................................................................................................1029
41.1 Introduction...................................................................................................................................................................1083
41.3.4 Timer Control Register (PIT_TCTRLn)......................................................................................................1088
41.3.5 Timer Flag Register (PIT_TFLGn)..............................................................................................................1089
42.1 Introduction...................................................................................................................................................................1095
42.1.1 Features........................................................................................................................................................1095
42.3.1 Low Power Timer Control Status Register (LPTMR x _CSR)......................................................................1097
42.3.2 Low Power Timer Prescale Register (LPTMR x _PSR)................................................................................1099
42.3.3 Low Power Timer Compare Register (LPTMR x _CMR).............................................................................1100
42.3.4 Low Power Timer Counter Register (LPTMR x _CNR)...............................................................................1101
43.1 Introduction...................................................................................................................................................................1107
43.2 Features.........................................................................................................................................................................1107
43.6.5 CMT Output Control Register (CMT_OC).................................................................................................1115
43.6.6 CMT Modulator Status and Control Register (CMT_MSC).......................................................................1116
43.6.7 CMT Modulator Data Register Mark High (CMT_CMD1)........................................................................1118
43.6.8 CMT Modulator Data Register Mark Low (CMT_CMD2).........................................................................1119
43.6.9 CMT Modulator Data Register Space High (CMT_CMD3).......................................................................1119
43.6.10 CMT Modulator Data Register Space Low (CMT_CMD4)........................................................................1120
43.6.11 CMT Primary Prescaler Register (CMT_PPS)............................................................................................1120
43.6.12 CMT Direct Memory Access Register (CMT_DMA).................................................................................1121
44.1 Introduction...................................................................................................................................................................1133
44.1.1 Features........................................................................................................................................................1133
44.2.5 RTC Control Register (RTC_CR)................................................................................................................1138
44.2.6 RTC Status Register (RTC_SR)..................................................................................................................1140
44.2.7 RTC Lock Register (RTC_LR)....................................................................................................................1141
45.1 Introduction...................................................................................................................................................................1151
45.2 Overview.......................................................................................................................................................................1151
45.2.1 Features........................................................................................................................................................1152
45.4.5 Ethernet Control Register (ENET_ECR).....................................................................................................1169
45.4.8 MIB Control Register (ENET_MIBC)........................................................................................................1174
45.4.9 Receive Control Register (ENET_RCR).....................................................................................................1175
45.4.10 Transmit Control Register (ENET_TCR)....................................................................................................1178
45.4.13 Opcode/Pause Duration Register (ENET_OPD).........................................................................................1181
45.4.18 Transmit FIFO Watermark Register (ENET_TFWR).................................................................................1183
45.4.20 Transmit Buffer Descriptor Ring Start Register (ENET_TDSR)................................................................1185
45.4.21 Maximum Receive Buffer Size Register (ENET_MRBR)..........................................................................1186
45.4.22 Receive FIFO Section Full Threshold (ENET_RSFL)................................................................................1187
45.4.23 Receive FIFO Section Empty Threshold (ENET_RSEM)..........................................................................1187
45.4.24 Receive FIFO Almost Empty Threshold (ENET_RAEM)..........................................................................1188
45.4.25 Receive FIFO Almost Full Threshold (ENET_RAFL)................................................................................1188
45.4.26 Transmit FIFO Section Empty Threshold (ENET_TSEM).........................................................................1189
45.4.27 Transmit FIFO Almost Empty Threshold (ENET_TAEM).........................................................................1189
45.4.28 Transmit FIFO Almost Full Threshold (ENET_TAFL)..............................................................................1190
45.4.29 Transmit Inter-Packet Gap (ENET_TIPG)..................................................................................................1190
45.4.30 Frame Truncation Length (ENET_FTRL)...................................................................................................1191
45.4.33 Tx Packet Count Statistic Register (ENET_RMON_T_PACKETS)..........................................................1193
45.4.34 Tx Broadcast Packets Statistic Register (ENET_RMON_T_BC_PKT)......................................................1194
45.4.35 Tx Multicast Packets Statistic Register (ENET_RMON_T_MC_PKT)......................................................1194
45.4.36 Tx Packets with CRC/Align Error Statistic Register (ENET_RMON_T_CRC_ALIGN)..........................1195
45.4.37 Tx Packets Less Than Bytes and Good CRC Statistic Register (ENET_RMON_T_UNDERSIZE)..........1195
45.4.38 Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (ENET_RMON_T_OVERSIZE)........1196
45.4.39 Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_T_FRAG)...................1196
45.4.40 Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (ENET_RMON_T_JAB)... .. .1197
45.4.41 Tx Collision Count Statistic Register (ENET_RMON_T_COL)................................................................1197
45.4.42 Tx 64-Byte Packets Statistic Register (ENET_RMON_T_P64).................................................................1198
45.4.43 Tx 65- to 127-byte Packets Statistic Register (ENET_RMON_T_P65TO127)..........................................1198
45.4.44 Tx 128- to 255-byte Packets Statistic Register (ENET_RMON_T_P128TO255)......................................1199
45.4.45 Tx 256- to 511-byte Packets Statistic Register (ENET_RMON_T_P256TO511)......................................1199
45.4.46 Tx 512- to 1023-byte Packets Statistic Register (ENET_RMON_T_P512TO1023)..................................1200
45.4.47 Tx 1024- to 2047-byte Packets Statistic Register (ENET_RMON_T_P1024TO2047)..............................1200
45.4.49 Tx Octets Statistic Register (ENET_RMON_T_OCTETS)........................................................................1201
45.4.50 Frames Transmitted OK Statistic Register (ENET_IEEE_T_FRAME_OK)..............................................1201
45.4.51 Frames Transmitted with Single Collision Statistic Register (ENET_IEEE_T_1COL).............................1202
45.4.52 Frames Transmitted with Multiple Collisions Statistic Register (ENET_IEEE_T_MCOL).......................1202
45.4.53 Frames Transmitted after Deferral Delay Statistic Register (ENET_IEEE_T_DEF)..................................1203
45.4.54 Frames Transmitted with Late Collision Statistic Register (ENET_IEEE_T_LCOL)................................1203
45.4.55 Frames Transmitted with Excessive Collisions Statistic Register (ENET_IEEE_T_EXCOL)...................1204
45.4.56 Frames Transmitted with Tx FIFO Underrun Statistic Register (ENET_IEEE_T_MACERR)..................1204
45.4.57 Frames Transmitted with Carrier Sense Error Statistic Register (ENET_IEEE_T_CSERR).....................1205
45.4.58 Flow Control Pause Frames Transmitted Statistic Register (ENET_IEEE_T_FDXFC).............................1205
45.4.59 Octet Count for Frames Transmitted w/o Error Statistic Register (ENET_IEEE_T_OCTETS_OK).........1206
45.4.60 Rx Packet Count Statistic Register (ENET_RMON_R_PACKETS)..........................................................1206
45.4.61 Rx Broadcast Packets Statistic Register (ENET_RMON_R_BC_PKT).....................................................1207
45.4.62 Rx Multicast Packets Statistic Register (ENET_RMON_R_MC_PKT).....................................................1207
45.4.63 Rx Packets with CRC/Align Error Statistic Register (ENET_RMON_R_CRC_ALIGN)..........................1208
45.4.64 Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
(ENET_RMON_R_UNDERSIZE)..............................................................................................................1208
45.4.65 Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (ENET_RMON_R_OVERSIZE).1209
45.4.66 Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_R_FRAG)..................1209
45.4.67 Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (ENET_RMON_R_JAB)... ..1210
45.4.68 Rx 64-Byte Packets Statistic Register (ENET_RMON_R_P64).................................................................1210
45.4.69 Rx 65- to 127-Byte Packets Statistic Register (ENET_RMON_R_P65TO127).........................................1211
45.4.70 Rx 128- to 255-Byte Packets Statistic Register (ENET_RMON_R_P128TO255).....................................1211
45.4.71 Rx 256- to 511-Byte Packets Statistic Register (ENET_RMON_R_P256TO511).....................................1212
45.4.72 Rx 512- to 1023-Byte Packets Statistic Register (ENET_RMON_R_P512TO1023).................................1212
45.4.73 Rx 1024- to 2047-Byte Packets Statistic Register (ENET_RMON_R_P1024TO2047).............................1213
45.4.74 Rx Packets Greater than 2048 Bytes Statistic Register (ENET_RMON_R_GTE2048).............................1213
45.4.75 Rx Octets Statistic Register (ENET_RMON_R_OCTETS)........................................................................1214
45.4.77 Frames Received OK Statistic Register (ENET_IEEE_R_FRAME_OK)..................................................1215
45.4.78 Frames Received with CRC Error Statistic Register (ENET_IEEE_R_CRC)............................................1215
45.4.79 Frames Received with Alignment Error Statistic Register (ENET_IEEE_R_ALIGN)..............................1216
45.4.80 Receive FIFO Overflow Count Statistic Register (ENET_IEEE_R_MACERR)........................................1216
45.4.81 Flow Control Pause Frames Received Statistic Register (ENET_IEEE_R_FDXFC).................................1217
45.4.82 Octet Count for Frames Received without Error Statistic Register (ENET_IEEE_R_OCTETS_OK).......1217
45.4.83 Adjustable Timer Control Register (ENET_ATCR)...................................................................................1217
45.4.84 Timer Value Register (ENET_ATVR)........................................................................................................1219
45.4.85 Timer Offset Register (ENET_ATOFF)......................................................................................................1219
45.4.86 Timer Period Register (ENET_ATPER)......................................................................................................1220
45.4.87 Timer Correction Register (ENET_ATCOR)..............................................................................................1220
45.4.89 Timestamp of Last Transmitted Frame (ENET_ATSTMP)........................................................................1221
45.4.90 Timer Global Status Register (ENET_TGSR).............................................................................................1222
45.4.91 Timer Control Status Register (ENET_TCSRn)..........................................................................................1223
45.4.92 Timer Compare Capture Register (ENET_TCCRn)....................................................................................1224
45.5.3 IEEE 1588 message formats........................................................................................................................1232
Chapter 46 Universal Serial Bus Full Speed OTG Controller (USBFSOTG)
46.1 Introduction...................................................................................................................................................................1283
46.1.1 USB..............................................................................................................................................................1283
46.3.1 Buffer Descriptor Table...............................................................................................................................1286
46.3.2 RX vs. TX as a USB target device or USB host..........................................................................................1287
46.3.3 Addressing BDT entries...............................................................................................................................1288
46.3.4 Buffer Descriptors (BDs).............................................................................................................................1289
46.4.2 Peripheral ID Complement register (USB x _IDCOMP)...............................................................................1296
46.4.3 Peripheral Revision register (USB x _REV)..................................................................................................1296
46.4.4 Peripheral Additional Info register (USB x _ADDINFO).............................................................................1297
46.4.5 OTG Interrupt Status register (USB x _OTGISTAT)....................................................................................1297
46.4.6 OTG Interrupt Control register (USB x _OTGICR)......................................................................................1298
46.4.7 OTG Status register (USB x _OTGSTAT)....................................................................................................1299
46.4.8 OTG Control register (USB x _OTGCTL)....................................................................................................1300
46.4.9 Interrupt Status register (USB x _ISTAT).....................................................................................................1301
46.4.10 Interrupt Enable register (USB x _INTEN)...................................................................................................1302
46.4.11 Error Interrupt Status register (USB x _ERRSTAT).....................................................................................1303
46.4.12 Error Interrupt Enable register (USB x _ERREN).........................................................................................1304
46.4.13 Status register (USB x _STAT)......................................................................................................................1305
46.4.14 Control register (USB x _CTL)......................................................................................................................1306
46.4.15 Address register (USB x _ADDR).................................................................................................................1307
46.4.16 BDT Page register 1 (USB x _BDTPAGE1).................................................................................................1308
46.4.17 Frame Number register Low (USB x _FRMNUML).....................................................................................1308
46.4.18 Frame Number register High (USB x _FRMNUMH)...................................................................................1309
46.4.19 Token register (USB x _TOKEN)..................................................................................................................1309
46.4.20 SOF Threshold register (USB x _SOFTHLD)...............................................................................................1310
46.4.21 BDT Page Register 2 (USB x _BDTPAGE2)................................................................................................1311
46.4.22 BDT Page Register 3 (USB x _BDTPAGE3)................................................................................................1311
46.4.25 USB OTG Observe register (USB x _OBSERVE)........................................................................................1313
46.4.26 USB OTG Control register (USB x _CONTROL)........................................................................................1314
46.4.27 USB Transceiver Control register 0 (USB x _USBTRC0)............................................................................1314
46.4.28 Frame Adjust Register (USB x _USBFRMADJUST)...................................................................................1315
46.4.29 USB Clock recovery control (USB x _CLK_RECOVER_CTRL)................................................................1316
46.4.30 IRC48M oscillator enable register (USB x _CLK_RECOVER_IRC_EN)...................................................1317
46.4.31 Clock recovery separated interrupt status (USB x _CLK_RECOVER_INT_STATUS)..............................1318
46.5 OTG and Host mode operation.....................................................................................................................................1318
46.6 Host Mode Operation Examples...................................................................................................................................1319
Chapter 47 USB Device Charger Detection Module (USBDCD)
47.1 Preface...........................................................................................................................................................................1327
47.1.1 References....................................................................................................................................................1327
48.1 Introduction...................................................................................................................................................................1359
48.1.1 Overview......................................................................................................................................................1359
48.1.2 Features........................................................................................................................................................1360
Chapter 49 CAN (FlexCAN)
49.3.5 Rx Mailboxes Global Mask Register (CAN x _RXMGMASK)....................................................................1381
49.3.6 Rx 14 Mask register (CAN x _RX14MASK)................................................................................................1382
49.3.7 Rx 15 Mask register (CAN x _RX15MASK)................................................................................................1383
49.3.8 Error Counter (CAN x _ECR)........................................................................................................................1383
49.3.9 Error and Status 1 register (CAN x _ESR1)..................................................................................................1385
49.3.10 Interrupt Masks 1 register (CAN x _IMASK1).............................................................................................1389
49.3.11 Interrupt Flags 1 register (CAN x _IFLAG1)................................................................................................1389
49.3.12 Control 2 register (CAN x _CTRL2).............................................................................................................1392
49.3.13 Error and Status 2 register (CAN x _ESR2)..................................................................................................1395
49.3.14 CRC Register (CAN x _CRCR).....................................................................................................................1397
49.3.15 Rx FIFO Global Mask register (CAN x _RXFGMASK)..............................................................................1397
49.3.16 Rx FIFO Information Register (CAN x _RXFIR).........................................................................................1398
49.3.17 Rx Individual Mask Registers (CAN x _RXIMRn).......................................................................................1399
49.3.34 Message buffer structure..............................................................................................................................1400
49.3.35 Rx FIFO structure........................................................................................................................................1406
50.1 Introduction...................................................................................................................................................................1441
50.2.2 PCS1–PCS3—Peripheral Chip Selects 1–3.................................................................................................1447
50.2.3 PCS4—Peripheral Chip Select 4..................................................................................................................1447
50.2.4 PCS5/PCSS—Peripheral Chip Select 5/Peripheral Chip Select Strobe.......................................................1447
50.2.5 SCK—Serial Clock......................................................................................................................................1447
50.2.6 SIN—Serial Input........................................................................................................................................1447
50.2.7 SOUT—Serial Output..................................................................................................................................1448
50.3 Memory Map/Register Definition.................................................................................................................................1448
50.3.1 Module Configuration Register (SPI x _MCR).............................................................................................1451
50.3.2 Transfer Count Register (SPI x _TCR)..........................................................................................................1454
50.3.3 Clock and Transfer Attributes Register (In Master Mode) (SPI x _CTARn)................................................1454
50.3.4 Clock and Transfer Attributes Register (In Slave Mode) (SPI x _CTARn_SLAVE)...................................1459
50.3.5 Status Register (SPI x _SR)...........................................................................................................................1460
50.3.6 DMA/Interrupt Request Select and Enable Register (SPI x _RSER)............................................................1463
50.3.7 PUSH TX FIFO Register In Master Mode (SPI x _PUSHR)........................................................................1465
50.3.8 PUSH TX FIFO Register In Slave Mode (SPI x _PUSHR_SLAVE)............................................................1466
50.3.9 POP RX FIFO Register (SPI x _POPR).........................................................................................................1467
50.3.10 Transmit FIFO Registers (SPI x _TXFRn)....................................................................................................1468
50.3.11 Receive FIFO Registers (SPI x _RXFRn)......................................................................................................1468
50.4.2 Serial Peripheral Interface (SPI) configuration............................................................................................1470
50.4.3 Module baud rate and clock delay generation.............................................................................................1474
50.4.4 Transfer formats...........................................................................................................................................1478
50.5.4 Baud rate settings.........................................................................................................................................1490
51.1 Introduction...................................................................................................................................................................1495
51.1.1 Features........................................................................................................................................................1495
51.3.4 I2C Status register (I2C x _S)........................................................................................................................1502
51.3.5 I2C Data I/O register (I2C x _D)...................................................................................................................1504
51.3.6 I2C Control Register 2 (I2C x _C2)...............................................................................................................1504
51.3.7 I2C Programmable Input Glitch Filter register (I2C x _FLT).......................................................................1505
51.3.8 I2C Range Address register (I2C x _RA)......................................................................................................1507
51.3.9 I2C SMBus Control and Status register (I2C x _SMB).................................................................................1507
51.3.10 I2C Address Register 2 (I2C x _A2)..............................................................................................................1509
51.3.11 I2C SCL Low Timeout Register High (I2C x _SLTH)..................................................................................1509
51.3.12 I2C SCL Low Timeout Register Low (I2C x _SLTL)...................................................................................1510
51.4.1 I2C protocol.................................................................................................................................................1510
51.4.2 10-bit address...............................................................................................................................................1515
51.4.3 Address matching.........................................................................................................................................1517
52.1 Introduction...................................................................................................................................................................1529
52.1.1 Features........................................................................................................................................................1529
52.3.3 UART Control Register 1 (UART x _C1).....................................................................................................1543
52.3.5 UART Status Register 1 (UART x _S1)........................................................................................................1546
52.3.6 UART Status Register 2 (UART x _S2)........................................................................................................1549
52.3.8 UART Data Register (UART x _D)...............................................................................................................1552
52.3.9 UART Match Address Registers 1 (UART x _MA1)....................................................................................1554
52.3.10 UART Match Address Registers 2 (UART x _MA2)....................................................................................1554
52.3.13 UART Extended Data Register (UART x _ED)............................................................................................1557
52.3.14 UART Modem Register (UART x _MODEM).............................................................................................1558
52.3.15 UART Infrared Register (UART x _IR)........................................................................................................1559
52.3.16 UART FIFO Parameters (UART x _PFIFO).................................................................................................1560
52.3.17 UART FIFO Control Register (UART x _CFIFO)........................................................................................1561
52.3.18 UART FIFO Status Register (UART x _SFIFO)...........................................................................................1562
52.3.19 UART FIFO Transmit Watermark (UART x _TWFIFO).............................................................................1563
52.3.20 UART FIFO Transmit Count (UART x _TCFIFO).......................................................................................1564
52.3.21 UART FIFO Receive Watermark (UART x _RWFIFO)...............................................................................1564
52.3.22 UART FIFO Receive Count (UART x _RCFIFO)........................................................................................1565
52.3.23 UART 7816 Control Register (UART x _C7816).........................................................................................1565
52.3.24 UART 7816 Interrupt Enable Register (UART x _IE7816)..........................................................................1567
52.3.25 UART 7816 Interrupt Status Register (UART x _IS7816)............................................................................1568
Chapter 53 Secured digital host controller (SDHC)
53.1 Introduction...................................................................................................................................................................1615
53.2 Overview.......................................................................................................................................................................1615
53.4.2 Block Attributes register (SDHC_BLKATTR)...........................................................................................1622
53.4.3 Command Argument register (SDHC_CMDARG).....................................................................................1623
53.4.4 Transfer Type register (SDHC_XFERTYP)................................................................................................1623
53.4.5 Command Response 0 (SDHC_CMDRSP0)...............................................................................................1627
53.4.10 Present State register (SDHC_PRSSTAT)..................................................................................................1630
53.4.11 Protocol Control register (SDHC_PROCTL)..............................................................................................1635
53.4.12 System Control register (SDHC_SYSCTL)..........

Documents

K64P144M120SF5RM