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Verilog Laboratory Instruction CE-UIT Page 1 1. Tạo một project trên Quartus II : • Start -> Programs -> Altera -> Quartus II 7.2 -> Quartus II 7.2 ( 32 -Bit ) : Hình 1 : Màn hình chính. • Nhấn tab File trên màn hình chính : • Mở một project mới : File -> New Project Wizard…

Lab 1_Huong Dan Thiet Ke Verilog (Quartus II 7.2)

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  • 1. To mt project trn Quartus II :

    Start -> Programs -> Altera -> Quartus II 7.2 -> Quartus II 7.2 ( 32 -Bit ) :

    Hnh 1 : Mn hnh chnh.

    Nhn tab File trn mn hnh chnh :

    M mt project mi : File -> New Project Wizard

  • Nhn Next >

    Nhp ng dn th mc ca project ( c th to trc hoc nu cha to s c t ng to ).

    Nhp tn ca project. Nhp top-level ca thit k cho project ( nn cho ging tn ca project ). Nhn Next >

    Nu ng dn th mc ca project cha c to trc :

  • Nhn Yes

    Nhn Next >

    Chn Family : Cyclone II Chn Available devices : EP2C35F672C6 ( H ca Chip FPGA Cyclone II trn

    Kit DE2 ). Nhn Next >

  • Nhn Next >

    Nhn Finish ch v mn hnh chnh.

  • 2. Thit k mt mch in n gin ( cng XOR ) dng Verilog trn Quartus II:

    M File -> New :

    Chn Verilog HDL File

  • Save as file : File -> Save as

    Nhp Verilog design cho cng XOR vo ca s Text Editor. Nh phi tn ca top-level module phi ging tn ca Project. ( Trong th d ny l light).

    Save : File -> Save

  • Mt s cch to Verilog khc :

    Dng Verilog template : + Edit -> Insert Template -> Verilog HDL

    a File vo project ( c th a mt hoc nhiu File vo Project, chng hn nh File cha top-level module v nhng Files cha sub-level module ).

    + Assignments -> Settings + Chn Category : Files

    + Nhn vo button

  • + Ch ng dn ca nhng Files verilog cn a vo Project.

    Compiling design : Processing -> Start Compilation Review Compilation report : Processing -> Compilation Report

    Gn pin cho design : Assignments -> Pins Double click on Location, chn pin trn Chip FPGA cho design.

    Mt cch khc gn pins cho design : Assignments -> Import Assignments

  • !

    Click button , ch ng dn ca file dng gn pins. Format cua file.csv nh sau :

    Re- compiling design : Processing -> Start Compilation Review Compilation report : Processing -> Compilation Report

    3. M phng mch thit k : To input waveform : File -> New -> Other Files -> Vector Waveform File

    Nhn OK

  • "

    Chn thi gian thc hin m phng : Edit -> End Time Nhp thi gian thc hin m phng. Fit windown : View -> Fit in Windown

    To waveform cho inputs : Edit -> Insert Node or Bus

    Chn Node Finder

    Chn Filter : Pins : all Nhn button List Chn signal bn Nodes found ; nhn >> chuyn sang bn Selected Nodes Nhn OK

  • Chn mt input signal bng cch nhp chut vo signal . Chn biu tng mi tn con tr Di chuyn con tr sang mn hnh waveform . Nhn v gi chut v ko r ( left ) trong mt khong thi gian ( gi s ta mun

    trong khong thi gian t 40ns -> 60 ns , SW0 signal c gi tr 1, th ta nhn , gi v r chut trong khong thi gian t 40ns -> 60ns.

    Nhn button 1 pha bn tri mn hnh

    Tng t cho nhng tn hiu inputs khc, khng to waveform cho outputs ( XXX).

    Save File Waveform : File -> Save As

  • Thc hin m phng : Assignments -> Setting

    Chn Simulator Settings Chn Simulation mode : Functional / Timing Ch ng dn ca input waveform va to. Nhn OK

    To simulation netlist : Processing -> Generate Functional Simulation Netlist

    Chy m phng : Processing -> Start Simulation. Quan sat output waveform.

  • 4. Programming thit k Verilog trn FPGA : Kt ni Kit DE2 vi my tnh qua cng USB-Blaster ( phi ci t driver trc

    ). Bt ngun Kit DE2. C 2 mode : JTAG v Active Serial modes 4.1 JTAG mode : Trn Kit DE2 , chuyn Switch RUN/PROG v v tr RUN Trn mn hnh chnh Quantus II, chn Tools -> Programmer

    Nhn Hardware Setup , chn USB-Blaster[USB-0] ( Ch : phi ci t driver cho USB-Blater trc ).

    Nhn Close Chn Mode JTAG Nhn Add File , ch ng dn n File .sof (c to ra khi chy Compilation). Check box Program/Configure

  • Nhn Start. Quan st trn Kit DE2, switch SW0, SW1 v quan st LED.

    4.2 Active Serial Mode : Chn Assignments -> Devide

    Chn Family : Cyclone II Chn Available devices : EP2C35F672C6 Nhn Device & Pin Option Chn Tab Configuration

  • Chn Configuration device : EPCS64 ( h EPPROM trn Kit DE2 , dng lu chng trnh np cho FPGA mi khi power on ).

    Tng t JTAG nhng bc k tip . Trn Kit DE2 , chuyn Switch RUN/PROG v v tr RUN Trn mn hnh chnh Quantus II, chn Tools -> Programmer Chn Hardware Setup : USB-Blaster[USB-0] Chn Mode : Active Serial Programming Nhn Add File, ch ng dn n File .pof ( File c to ra trong qu trnh

    chy Compilation ).

    Check box Program/Configure. Nhn Start programming chng trnh cho EPPROM. Nhn Phm Restart trn Kit DE2, Quan st trn Kit DE2, switch SW0, SW1 v quan st LED.


Lab 1_Huong Dan Thiet Ke Verilog (Quartus II 7.2)

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