6.091 IAP 2008 Lecture 3 1

Lab 2 Revisited Exercise

• Wire up led display • Note the ground leads• LED orientation

1K

100k

+15V

2N2222

6.091 IAP 2008 Lecture 3 2

Comparator, Oscillator

Vo

V-

V+Vin

+5

1k2

3

6

+15

7

4

Notice that power connections are shown; bypass capacitors included for power supply filtering.

All voltage measurements are referenced to ground

6.091 IAP 2008 Lecture 3 3

Op-Amps

Vo

V-

V+

Vin

C

R1

Vo

V-

V+

Vin

R2

R1

ino vRRv

12

−= ∫−= dtRCvv in

o

Inverting Amplifier Integrator

For clarity, power connections and bypass capacitors not shown.

Vo

V-

V+

Vin

10k

1k

1

5

-15V

10k

Null Adjustment

6.091 IAP 2008 Lecture 3 4

Lab Exercise - Schmitt Trigger

Vo

V+

V-

R2

R1

Vin

• Schmitt trigger have different triggers points for rising edge and falling edge.

• Can be used to reduce false triggering

• This is NOT a negative feedback circuit.

6.091 IAP 2008 Lecture 3 5

Notes

• IC power supply connections generally not drawn. All integrated circuits need power!

• Use standard color coded wires to avoid confusion.

Potentiometer internals

6.091 IAP 2008 Lecture 3 6

Power Supplies, Voltage Regulators

• Conventional Power Supply– rectify (convert AC to

DC)– filter out the ripple– regulate the voltage

• 3 terminal IC regulator

3 terminal regulator

.

6.091 IAP 2008 Lecture 3 7

Wire Gauge• Wire gauge: diameter is inversely

proportional to the wire gauge number. Diameter increases as the wire gauge decreases. 2, 1, 0, 00, 000(3/0) up to 7/0.

• Resistance– 22 gauge .0254 in 16 ohm/1000 feet– 12 gauge .08 in 1.5 ohm/1000 feet– High voltage AC used to reduce loss

6.091 IAP 2008 Lecture 3 8

78XX Voltage Regulator+5V, +12V, +15V-5V, -12V, -15V

Reprinted with permission of National Semiconductor Corporation.

6.091 IAP 2008 Lecture 3 9

7805 Circuit

Reprinted with permission of National Semiconductor Corporation.

6.091 IAP 2008 Lecture 3 10

Zener Diode• Zener diodes will maintain a

fixed voltage by breaking down at a predefined voltage (zenervoltage).

4.7k

Lab exercise• Wire up the above circuit with a 1N752A (5.6V)

zener. • Set the FG for a 0-10V ramp. Display the

output of the FG and the voltage across the zener on the oscilloscope. Describe what is happening.

6.091 IAP 2008 Lecture 3 11

Adjustable Voltage Source

Vo

V+

V-

+15V

0.1uf

10K1N758

10v

270Ω

6.091 IAP 2008 Lecture 3 12

Adjustable Voltage Power Supply

+15V

1N758

10v

270Ω0.1uf

10K

Vo

V+

V-

.

1uf

6.091 IAP 2008 Lecture 3 13

LM317 Three Terminator Adjustable Voltage Regulator

• First 3 terminal adjustable voltage regulator• 1.2 - 25 Voltage output range• Short circuit protected• Thermal shutdown

Reprinted with permission of National Semiconductor Corporation.

6.091 IAP 2008 Lecture 3 14

LM317

Reprinted with permission of National Semiconductor Corporation.

6.091 IAP 2008 Lecture 3 15

Buck Converters

• Linear power supplies are very inefficient

• Power dissipated by regulating element

• Buck converters operating in switching mode (on/off)

+

.

6.091 IAP 2008 Lecture 3 16

555 Timers• Simple, versatile, low

cost IC for timing applications: oscillators,

+

_

+

_

1

2

6

5

5k

5k

5k

3

7

8

4

VCC

Threshold

Control Voltage

Trigger

Output

Discharge

Gnd Reset

CompA

CompB

FlipFlop

Inhibit/Reset

R

S

Q

one-shot pulse generator, pulse width modulator, missing pulse detector

• Circuit: two comparators, flip flop, resistor divider and a discharge transistor.

Figure by MIT OpenCourseWare.

ready

6.091 IAP 2008 Lecture 3 17

555 Block Diagram

Figure by MIT OpenCourseWare.S R Reset Output

1 1 1 last state

0 1 1 low

1 0 1 high

0 0 1 high

NA NA 0 low

ready

+

_

+

_

1

2

6

5

5k

5k

5k

3

7

8

4

VCC

Threshold

Control Voltage

Trigger

Output

Discharge

Gnd Reset

CompA

CompB

FlipFlop

Inhibit/Reset

R

S

Q

6.091 IAP 2008 Lecture 3 18

Vc

RC Equation

dtdVC c

cc V

dtdVRC +

Vs = 5 V

Switch is closed t<0

Switch opens t>0

Vs = VR + VC

Vs = iR R+ Vc iR =

Vs =

R

C

Vs = 5 V

⎟⎟⎞

⎜⎜⎛−=

−RCt

sc eVV 1⎠⎝

⎟⎟⎠

⎞⎜⎜⎝

⎛−=

−RCt

c eV 15

6.091 IAP 2008 Lecture 3 19

Monostable Circuit

Comp

555 or 1/2 556

Comp

Flip flop Output Output

Reset

R

R

R

Discharge

Control voltage

Threshold

Trigger

Ra

VCC

C

Reprinted with permission of National Semiconductor Corporation.Figure by MIT OpenCourseWare,

based on Philips Semiconductors datasheet.

6.091 IAP 2008 Lecture 3 20

Oscillator (Astable)

Reprinted with permission of National Semiconductor Corporation.

Figure by MIT OpenCourseWare,based on Philips Semiconductors datasheet.

Comp

555

Comp

Flip flop Output

Reset

R

C

R

R

RA

Discharge

Control voltage

Threshold

Trigger

Rb

VCC

1 4

2

36

5

7

8

6.091 IAP 2008 Lecture 3 21

Closet Light Timer – Lab Exercise

+15+15

+15 8

1

reset

trigger

control

threshold

discharge

output10k1k

0.1uf

0.01uf

1k

R

C

555

Switch closed = door closedton = 1.1RC

6.091 IAP 2008 Lecture 3 22

Lab Exercise

• Wire up zener diode circuit• Build variable voltage power supply• Build variable current source• Build 555 oscillator• Build closet light timer

6.091 IAP 2008 Lecture 3 23

Analog Circuit Summary

• 3 Terminal Regulators• Zener Diodes• Power Supplies• 555 Timers & circuits

6.091 IAP 2008 Lecture 3 24

Important Missing Links

• The real world is an analog world. However, computing is best performed via digital systems (i.e. the processing of data with 0’s and 1’s).

• Digital-Analog Conversion• Analog-Digital Conversion

6.091 IAP 2008 Lecture 3 25

Analog vs Digital

• Analog systems/devices work with information in a continuous stream: clock with hands, mercury thermometer, vinyl records, analog meters, calipers.

• Digital systems/devices work with information in a discontinuous stream (0,1): digital thermometer, digital meters, computers.

6.091 IAP 2008 Lecture 3 26

Music – An Example

• CD’s are digital systems that sample and stores audio data– sampling rate: 44.1 khz– data stored in 16 bit format; implies

216 = 65,536 possible output levels

• DVD Audio samples at 96-192kHz/24 bits

• Analog records have an infinite number of output levels.

6.091 IAP 2008 Lecture 3 27

D-A Conversion (DAC)• Problem: take a digital signal and convert to an analog voltage: R-2R ladder

0001 -> 1/16 * 5 volt 0010 -> 2/16 * 5 volt0011 -> 3/16 * 5 volt. . .1101 -> 14/16 * 5 volt1111 -> 15/16 * 5 volt

• Note that the outputs are at discrete levels – not continuous!

R

R

+5

R

+5

R

+5

R

+5

2R 2R 2R 2R

Vo

Bo B3B2B1

⎥⎦⎤

⎢⎣⎡ +++ 031223 2

121

21

21 BBBB 5

6.091 IAP 2008 Lecture 3 28

Digital Circuits• Real world analog signals have noise – unavoidable.• Digital circuits offers better noise immunity.• Use voltage to represent “0” and “1”

– Avoid forbidden voltage zone.– Make standards tighter for output than for inputs.

• Data (HCMOS family): 0 (low), 1 (high) – Input voltage low: 0.0 – 0.7v– Input voltage high: >2.0V– Output low: <0.4v– Output high: >3.98v

6.091 IAP 2008 Lecture 3 29.

Digital Circuits

HCMOS 1 (high) – Output high: >3.98v– Input voltage high: >2.0V

output highrange

input highrange

+5V

+3.98V

+2.0V

0.7V

0.4Vinput low

rage

output lowrange

noisemargin

noisemargin

Forbidden Zone

HCMOS 0 (low)– Output low: <0.4v– Input voltage

low: 0.0 – 0.7v

6.091 IAP 2008 Lecture 3 30

Power Requirements• The following power supplies are common for analog

and digital circuits:

+5v for digital circuits, +15v, -15v for analog,-5v, +12v, -12v also used

• Other voltages generally derived.

6.091 IAP 2008 Lecture 3 31

Boolean AlgebraA B = A & B

A = Inverse of A

A B = Inverse of [A&B]

DeMorgan's Law

A B = A + B

A + B = A & B

6.091 IAP 2008 Lecture 3 32

Digital System Implementation• Start with AND, OR, NOR, NAND gates and

add more complex building blocks: registers, counters, shift registers, multiplexers. Wire up design. High manufacturing cost, low fix costs. Examples 74LS, 74HC series IC

• For volume production, move to PALs, FPGAs, ASICs. Low manufacturing cost, high fix costs.

6.091 IAP 2008 Lecture 3 33

Basic Gates

Circle indicates inversion

6.091 IAP 2008 Lecture 3 34

74LS00 NAND Gate

1 2 3 4 5 6 7

A1 B1 Y1 A2 B2 Y2 GND

VCC

Dual-In-Line Package

14 13 12 11 10 9 8

B4 A4 Y4 B3 A3 Y3

This device contains four independent gates eachof which performs the logic NAND function.

Figure by MIT OpenCourseWare, adapted from the National Semiconductor 54LS00 datasheet.

6.091 IAP 2008 Lecture 3 35

74LS02 NOR Gate

1 2 3 4 5 6 7

Y1 A1 B1 Y2 A2 B2 GND

VCC

Dual-In-Line Package

14 13 12 11 10 9 8

Y4 B4 A4 Y3 B3 A3

This device contains four independent gates eachof which performs the logic NOR function.

Figure by MIT OpenCourseWare, adapted from the National Semiconductor 54LS02 datasheet.

6.091 IAP 2008 Lecture 3 36

74LS08 AND Gate

1 2 3 4 5 6 7

A1 B1 Y1 A2 B2 Y2 GND

VCC

Dual-In-Line Package

14 13 12 11 10 9 8

B4 A4 Y4 B3 A3 Y3

This device contains four independent gates eachof which performs the logic AND function.

Figure by MIT OpenCourseWare, adapted from the National Semiconductor 54LS08 datasheet.

6.091 IAP 2008 Lecture 3 37

Building Logic

• From basic gates, we can build other functions: Exclusive OR Gate

X Y Z0 0 00 1 11 0 11 1 0

XZ

Y

X

Y Z

6.091 IAP 2008 Lecture 3 38

74LS86 Exclusive OR

Figure by MIT OpenCourseWare, based on Motorola datasheet.

In

Truth Table

A

L

L

L

L

H H

H

H

H

H

L L

B Z

Out

1 2 3 4 5 6 7

14 13 12 11 10 9 8

GND

VCC