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LogicComponents&QMLogic

Minimization

Dr.A.Sahu

De t of Com . Sc. & En .

IndianInstituteofTechnologyGuwahati

1

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Outline

Karnaugh mapwith>=5variable

Stu yo ComponentsMultiplexor,Decoder

LogicImplementationUsing MUX&Decoder

4BitAdder

u ne c us ey og c n m zat on MoreExamples

2

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Manycircuitshavemorethanoneoutput

Cangiveeac aseparatecircuit,orcans aregates

Ex: F=ab +c, G=ab +bcab

a

c

F

c

F

GG

3

(a)

Option 1: Separate circuits Option 2: Shared gates

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Receptioncounter:Whenyoureacha

ReceptionistAsk:WhichDepttoGo?

ecep on s e rec you osome u ngaccordingtoyourAnswer.

: :

Ninput:2N output

MemoryAddressing

Addresstoaparticularlocation

4

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Decoder:Popularcombinationallogicbuilding,

Convertsinputbinarynumbertoonehighoutput

numbers

,binarynumber

i0

i1

d1

d21

1

0

0i0

i1

d1

d20

0

0

0 i0

i1

d1

d2

i0

i1

d1

d20

1

0

1

1

0

1

0

5

d3 1d3 0 d3 d30 0

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InternaldesignANDgateforeachoutputtodetectinputcombination

DecoderwithenableeOutputsall0ife=0,Regularbehaviorife=1

n nput eco er: outputsi0

i1

d0

d1

d21

1

0

0

0

d0 d3e 1

1

d1

d2

i1i0

i0

i1

d0

d1

d21

1

0

0

0d3i1i0

6

e d3 0

0i0i1

Minterms

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4to16Decoderusingtwo3to8

Decoders

D0toD7

D8toD15

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BooleanFunctionImplementation

usingDecoders

functionsofnvariablescanbeimplemented.

S(x,y,z)= (1,2,4,7), C(x,y,z)=(3,5,6,7) FunctionsSandCcanbeimplementedusinga

3to8decoderandtwo4inputORgates

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X

Z

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ConfigurableFunctionusingDecoder

&Memory

10

Decod

er

100

ab

11 AnyFunction canbe

8rowx1col memory FunctiondependonMemory

10

E ements,D rect

correspondencetoTruthTable

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Mux:Anotherpopularcombinationalbuildingblock

RoutesoneofitsNdatain utstoitsoneout ut basedon

binaryvalueofselectinputs 4inputmux needs2selectinputstoindicatewhichinputtoroute

throu h

8inputmux 3selectinputs

Ninputs log2

(N)selects

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d

i0

212121 i0 (1*i0=i0)

i01

i1d

i1d

i1d (0+i0=

i0)0

0

s1

s0

sa

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i0

i0

i1i1

i2

i3

di2

s1 s0 i3

4x1mux CoversAll

ss

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Muxes CommonlyTogether Nbit

Muxi0i1

2 1da3 Simplifying

s

i0i1

2 1d I0

4-bit2x1Aa2b2

4C44

i0

s0i1

2 1

ds0

I1B

a1

b1 c3

for

i0

s0i1

2 1d

s0a0b0

c2

c1

Ex:Two4bitinputs,A(a3a2a1a0),andB(b3b2b1b0)

s0 c

4bit2x1mux (justfour2x1muxes sharingaselectline)can

selectbetweenAorB

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HOUR MIN

HR1

HR2

MUX

7

Segment

4

4 7

DEMUXMIN1

eco er4

MIN2 4

15

2bitcounter

Ruuning AtKhZ

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ImplementinglogicFunctionusing

MUX

i0

i1

1

0

i2

i3

d1

0

, = m ,

s1 s0

A B

4x1mux

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