Lecture 16,17 - IO Interfacing and Interrupts

8/7/2019 Lecture 16,17 - IO Interfacing and Interrupts

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Interfacing to the Real World

Peripheral Chip Interfacing Memory vs. IO Mapped Software Interaction with IO Chips

Polled IO vs. Interrupt Driven IO Advantages and Disadvantages

Operation, Rom and Ram based Vector tables - Example 6811

Vectored and Auto Vectored IRQ example using 68000

Exceptions User and Supervisor Mode Processing

Memory Management Unit (MMU) Interfacing

Software Interrupts - Trap instructions


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IO Interfaces to the Real World Most microcomputer systems are designed for use in small embedded applications

where they typically interface to and control data from the real world.

CPU manufacturers provide their own family ofperipheral interface chips to make themore common interfacing functions fairly straight forward and these chips areinterfaced to the CPU in more or less the same way as memory by hooking them upto the Address and Data Buses and using R/W and Chip Selects off Address and IOdecoders.

CPU

CPU(68000)

CPU

CPU

ParallelIO

(M6821)

DigitalPush

ButtonInputs

PB1

PB2

PB3

PB4

CPU

Address and

Data BusSerialComms(M6850)

CPU

Events Analog InADC/DAC

(ADC8100)

Timer/Counter(M6840) Analog OutClock

RS-232


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Peripheral Chip Interfacing Manufacturers differ slightly in their interfacing

between peripheral chips and CPU: Twomethods supported IO Mapped (supported mainly by Intel) Memory mapped (supported by most other

manufacturers)

IO Mapped Peripherals

Occupy a separate address space to memory. Primitive attempt to segregate Memory and IO. CPU issues a Signal (M/IO) to distinguish a

Memory access from an IO access. IO/Memory decoders are enabled offM/IO Special IO instructions are needed to access

address in the IO Space, i.e. ones that drive theM/IO signal low.

For example Intel CPUs have the following 2instructions.

IN Port #, Register

OUT Port #, Register

Port # is presented as an 8 bit address. Data transfer between register/IO over data bus. Separate IO space approach fallen out of favour

as it means IO devices cannot be accessedusing C/C++ pointers, (which generate Msignal not IO) meaning that you have to embedassembly language into your C++ source code.

CPU

IOMapped

PeripheralChip

55

M/IO

R/W

Intel CPU

Reg AXAddress Bus

Logic 0 - IO AccessLogic 1 Memory Access

Logic 0 (Write Operation)

CPU

IO Port

Decoder

ChipSelect

ROMIO Ports

RAM

000000

007FFF

100000

8FFFFF

Memory Space

IO Space

000000

0000FF

void func1(){#asm

OUT 82, ax

IN 83, ax#endasm}

FFFFFF

Data Bus


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main()

{char *ports = 0xC00000;char x ;

*ports = 0x55 ;x = *(ports + 1) ;

}

Peripheral Chip Interfacing

Memory Mapped Peripherals

Share the same address space as main

memory (i.e. they behave like memory). System designerpartitions an area of the

system memory space for use by memorymapped peripherals simply by extending theaddress decoder concept used by memory.

No need for separate IO space. No special instructions needed to access IO. Programs can use a pointer in C/C++ to access

IO adding versatility. IO devices vulnerable to programs accidentally

overwriting them.

CPU

MemoryMapped

PeripheralChip

R/W

MotorolaCPU

Address Bus

Logic 0 (Write Operation)

CPU

AddressDecoder

ChipSelect

ROM

IO Ports

RAM

000000

007FFF

C00000

C07FFF

100000

8FFFFF

ExampleMemoryMap

AS

Memory Access used for IO

void func1()

{ char *IOports = 0xC00000;char c ;

*IOports = 0x55 ;c = *(IOports + 1) ;

}

FFFFFF

Data Bus

Memory Space


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Peripheral Registers All peripheral chips regardless of how they are mapped, contain a number of

internal registers that control the configuration of the chip and supply the CPU

with important status information about the device. In addition, read and writeregisters facilitate communication between CPU and outside world.

CPU

CPUCPU

CPU

RS-232

DigitalPush

Buttoninputs

PB1

PB2

PB3

PB4

Address andData BusSerial

CommsChip

ParallelIO

Chip

Control

Status

Read Data

Write Data

Control

Status

Read Data

Write Data


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Peripheral Registers

Example 6850 Serial Comms Chip Control Register

Bits in this register control important functions in the chip. By writing to this register we can control the behaviour of our chip.

Bits2-4: Frame FormatData width (7 or 8 bits), Parity (odd, even,none), Number of stop bits (1 or 2).

Bit 7 : Receiver ControlControls generation of an interrupt when acharacter has been received.

ReceiverInterruptEnable

TransmitterControl

Word Select Clock Divisionand Reset

B7 B6 B5 B4 B3 B2 B1 B0Control Reg 6850

Bits 5-6: Transmitter ControlControls the state of the RTS line used with amodem. Controls generation of interrupt whentransmitter empty.

Bits 0-1: Reset and Clock divisorProvides a software master reset for the device.Clock division ratio (1, 16 or 64) i.e. effectivebaud rate for transmitter and receiver sections.


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Peripheral Registers

Example 6850 Serial Comms Chip Status Register

Individual bits in this register indicate the state of play within the chip. By reading this register we can determine the operating status of the chip.

Bit 5: Receiver Overrun

Bit 4 : Framing Error

Bit 6: Parity Error

Bit 3: Clear to Send (From a Modem)

Bit 2: Data Carrier Detect (From a Modem)

Bit 1: Transmit Data Register Empty

Bit 0: Receive Data Register Full

Bit 7: Device is generating an interrupt

Status Reg 6850


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6811s On-Chip Memory Mapped IO

A 64 byte area of the 6811 address space between locations [1000-103F] has beenset aside for the large number of IO ports, (digital, serial, analog, time, watchdog etc.)

that exist on-chip. Some of the memory mapped registers are shown below for the parallel IO ports.

Port B: 8 Bit Output port.

Port C: 8 Bit Bidirectional port.

Port C Data Direction Register0 = Input, 1 = Output

Port E: 8 Bit Input port.

Port D: 6 Bit Bidirectional port.

Port A: 8 Bit port. In or Out


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Polled IO

Communicating with an IO Chip? Once initial configuration of the chip has been performed in software, the

question of how to communicate with the outside world arises. One simple approach is to poll each device in turn as part of a program loop. That is, we read the status of the device by interrogating its status register. When we determine that a device has something to say, we deal with it. A system with 3 peripheral IO chips might contain a polling loop like this one.

while(1){

if( serial IO port status registerindicates character received)// Get Character from device and buffer it somewhere.

if( parallel IO device status registerindicates a push button pressed)// get robot to back-up and change direction.

if( timerstatus registerindicates time has elapsed)// measure a critical temperature/pressure/speed or whatever.

}


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Polled IO

Advantages of Using Polling

Software is pretty easy to write, involving nothing more than a simple loopand a few if tests to interrogate each device status in turn.

Polling has the advantage that we make recognition of the asynchronousinputs of the real world, synchronous to the execution of our program, i.e.we get to chose when we recognise and respond to a real world input,which makes testing and debugging of software much easier.


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Polled IO

Disadvantages of Using a Polling Loop

Adding more IO devices to the system, degrades the response time to anyone of them since it takes longer to poll more devices in software.

An input (such as a push button being momentarily pressed) could bemissed, if the signal is too briefto be recognised within the polling loop timeperiod or if the CPU is busy dealing with something else at the time.

It is not very efficient. The execution time for one iteration of a polling loopcould take longer than the time required to generate the response.

No Slack - A polling approach consumes 100% of CPU time leaving nospare capacity for other activities that the system might need to perform. OKif the system isnt doing anything else then fine, but not so good if it is.

Lack ofprioritisation. If the CPU is busy dealing with less importantinputs/events, there is no way for a more important input to pre-empt it.

In real-time systems, polling leads to non-deterministic response times andinefficient utilisation of the CPU.


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Interrupt Driven IO A better solution to overcome the problems of polling would be to use interrupts. Here, instead of our CPU asking each I/O device in turn if they have anything

important to report (i.e. polling), the I/O device itself can be programmed toattract the attention of the CPU by asserting an Interrupt request signal (IRQ )when it requires the attention of the CPU.

CPUs have varying numbers of interrupt request pins that are generallyprioritised, the 6811/8051 has 2, the 68000 has 7.

IRQ

IRQ

IRQ

CPUCPU

CPU

CPU

Parallel

IOChip

RS-232

Digital

PushButtoninputs

PB1

PB2PB3

PB4

CPUTimer

Address and Data BusSerialComms

Chip

IRQ Control Register programschips IRQ capability

Data ReceivedIRQ1

IRQ2

IRQ3

Button Pressed

Time-Out


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Advantages of Interrupt Based Systems

The response time to each IO device interrupt is independent of the numberof IO devices in the system (provided the system is not overloadedwith

interrupt requests). This makes response times more predictable and leadsto a more deterministic system.

IO devices can be prioritised in hardware thus a high priority IO device canoverride (i.e. interrupt) a lower priority one.

Inputs from the real world should never be missed even if the system isbusy. The interrupt signal will stay asserted until the CPU deals with it.

Creates Spare Processing Capacity: The system is able to perform othermore mundane tasks at a lower priority level, or even sit idle, while waitingfor an IO device to inform it of the need to respond and thus CPU utilisationis reduced enabling the CPU to do other things.

This last point is particularly important in a multi-tasking operating systemenvironments where many programs may be scheduled simultaneously andare time-sliced.

In summary the use of interrupts leads to betterresponse time andimproved CPU utilisation.


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Disadvantages to Interrupt Driven Systems

Usually require more complex/expensive hardware and software architectures.For example the system may require

The use of IO devices capable ofgenerating an interrupt (not all of themcan or may not be able to generate them under the conditions you want).

More complex (multi-threaded) code to deal with the interrupt and route therequest for service to a users program where the data is then madeavailable to the main code (i.e. there are possibly problems ofmutualexclusion and threadsynchronisation associated with the use of interrupts).

More difficult to debug.

Interrupts are asynchronous to the operation of the rest of the system andcan occur with unpredictable frequency and timing relative to the executionof the program, making it very difficult to debug.

Recreating the set of circumstances that led to the bug in your code isvirtually impossible since the real world cannot be single stepped and it maybe difficult to recreate the combination of asynchronous inputs that lead to

the failure/bug being identified in the first place.


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Interrupts: the Basics

An interrupt then is an asynchronous signal generated by an IO chip torequest service from a CPU.

In response to an interrupt request (IRQ), the CPU:-

Finishes the current instruction (which cannot be interrupted).

Saves the value of the Program counter(PC) onto the hardwarestack this is to enable the CPU to remember where it was in yourprogram so that it can resume after the interrupt has been dealt with.

Saves the internal state of the processor onto the stack including

The Condition Code Register (CCR)

Other registers depending upon the particular CPU.


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Interrupts: the Basics

Identifies and prioritises which external IRQ pin(s) are being

asserted. If two different IRQ pins are active at the same instant thehighest priority IRQ is dealt with first.

Executes an Interrupt Service Routine (ISR) which must as aminimum

Save additional CPU registers that might be overwritten by code within the ISR.

Identify the chip asserting the IRQ by interrogating its status register.

Deal with the reason for the interrupt (e.g. data has been received)

Clearthe interrupt within the device requesting service.

Restore the additional registers saved above.

Execute a return from Interrupt (RTI) instruction at the end of the ISR whichrestores the CCR and PC registers stacked earlier.

This last instruction (RTI) returns control of the CPU back to theprogram immediately following the instruction where the interruptoccurred. This action is summarised in the next diagram.


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Interrupt Action (the basics)

Normal Processing

Interrupt Service Routine (ISR)

Interrupt(s)

Save Additional CPU Registers

Service Highest Priority Requesting Device(+ Clear its IRQ)

Restore Additional Registers

RTI

CompleteCurrent

Instruction

Main ProgramSuspended for

Duration ofISR

Ideally Keep ISRShort and Fast

Interrupt Latency is a measure of the time taken toservice the IRQ. This is important in real-time systems as

all other processing is suspended during this time.

ResumeWithRestOf

Program


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Question: How does the CPU find its way to the Interrupt Service Routine (ISR)?That is, how do we get it to execute the code that deals with the interrupt?

At a purely hardware level, the CPU has been designed to fetch the address of theInterrupt Service Routine from a special Vector Table located in Rom (so that it isalways there when power is applied.) when the interrupt occurs.

The Vector Table also deals with Resets and otherExceptions in the same way.

The Vector Table contains one entry foreach IRQ that the CPU has been designedto deal with (2 for the 6811 external interrupts, 7for the 68000).

Each entry in the vector table contains an address. It is to this address that theCPU jumps and expects to find your ISR code to deal with the interrupt.

If you are designing your own embedded microcontroller application, you mustplace the address of yourISR into the Vector Table before you blow the ROM.

Note: If you are running under an Operating system (Windows/Linux) or a debugmonitor (such as buffalo) these programs build an additional jump table (in RAM)which allows you to install your ISR with a suitable system call afterthe system has

booted and afteryour main program begins execution.

Interrupt Action (the basics)


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The table opposite is the interruptVector table for the 6811 which resides

at the top of the64

k memory map. Each vector table entry is 2 bytes in size

and contains a 16 bit addresscorresponding to an ISR for that IRQ.

The 6811 has a lot of built in IOcapability and many of these are able togenerate their own IRQ thus there are alot of entries in the vector table one foreach source of internal interrupt.

Two external sources of interrupt aretriggered by the IRQ and XIRQ pins.

When an XIRQ interrupt request isreceived the 6811 fetches a 16 bit entryfrom the vector table corresponding tothe XIRQ, i.e. the 16 bit address storedat [FFF4,FFF5]

It then jumps to the address specified bythat table entry and expects to find yourISR to deal with devices connected tothe XIRQ pin.

Note reset vector (FFFE,FFFF) works inthe same way as do all other kinds ofinterrupt, each with its own vector exceptthat reset never returns

6811 Interrupt Vector Table

Vector for XIRQ found at$FFF4/FFF5Each vector comprises a two byte entry


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Normal Processing

XIRQ Interrupt S. Routine $C000

XIRQ

Stack Additional CPU Registers

Service Requesting DeviceClear its IRQ

Restore Additional RegistersRTI

CompleteCurrent

Instruction

ResumeRestOf

Program

Main ProgramSuspended for

Duration of ISR

Contents = $C000 XIRQ=[FFF4,FFF5]

ROM Vector Table

Stack PC, CCR

Index intoVector Table

for XIRQ Entry

PC = $C000

Hardware Processing

FFC0

FFFF

6811 XIRQ Interrupt Action (Detail)

Store address of your XIRQISR in locations $FFF4-$FFF5,

i.e. ISR can be found at$C000 in this example


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Maskable Interrupts

All interrupt capable peripherals have the ability to control whether the chip shouldgenerate an interrupt or not via interrupt mask bits in the chips control register.

In addition, all CPUs have the ability to postpone recognition of some or all of theirinterrupts until later, by masking the recognition of the interrupt within the CPUstatus orcondition code register

In the case of the 6811, the IRQ and XIRQ external interrupts are controlled by the Iand X bits in the 6811s condition code register.

These interrupts are initially masked after a reset to prevent spurious interrupts beingrecognised while the system is being initialised.

In the 6811 all internal memory mapped peripherals with interrupt generatingcapability can be masked (disabled) by setting the I bit in the 6811s condition coderegister

There are two assembly language instructions in the6

811 instruction set to changethe value of the I bit

CLI - Clear Interrupt bit (allowing recognition of interrupts) SEI - Set Interrupt bit (postpone recognition until I cleared)

To enable the X input, use the TAP instruction transfer accumulator A to conditioncode register to clear the X bit.


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Interrupts/Exceptions on otherProcessors

The 68000, MIPS and ARM processor are typical of more modern 16/32/64 bit CPUs in that they offer awider range of prioritised interrupt levels.

Support forVectored interrupt handling, (the Peripheral chip directly points the CPU to its ISR). Interrupts are part of a more general exception

handling policy which (for the 68000) is closely linkedto Userand Supervisorstates within the CPU (see later)

The 68000 Interrupt Interface

7 prioritised IRQ levels encoded via IPL0 IPL2 Level 7 is non-maskable (cannot be ignored). Status register controls IRQ masking via bits I2 I0 Function code pins FC0-FC2 indicate type ofbus

cycle and state. (Note interrupt acknowledge cycle).

Note Supervisorand Usermodes and S bit (see later)

s

Status Register

I2 I1 I0

FC2 FC1 FC0 Memory access type0 0 0 Undefined --reserved0 0 1 User data access0 1 0 User program access0 1 1 Undefined --reserved1 0 0 Undefined --reserved1 0 1 Supervisor data access1 1 0 Supervisor program access1 1 1 Interrupt Acknowledge


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The 68000 Exception Table and Operation

The table opposite shows the vector table for the68000. Each entry is 4 bytes in size.

Auto-Vectored Interrupts : Vectors 25 - 31

Intended for use by dumb peripherals For IRQ levels 1-7, the CPU uses one of the auto

vectors 25-31 based on the level of the interrupt. Thus a dumb peripheral asserting a level 3 IRQ will

eventually be serviced by the ISR whose addresscan be found at location [00 006C-00 006F]

UserProgrammable Vectored Interrupts: Vectors64 - 255

Intended for modern 16-bit peripherals to provide afaster, more direct response to the IRQ.

Such devices are able to supply an 8 bit vectornumber(programmed into them as part of theirinitialisation) during an interrupt acknowledge(IACK) cycle (i.e. pins FC2-FC0 = {1,1,1}).

This vector number is multiplied by 4 (i.e. shiftedleft 2 bit positions) to generate the address of thecorresponding vector table entry.

For example, an interrupting peripheral chip thatsupplies vector#64 during an InterruptAcknowledge cycle will eventually be serviced byan ISR whose address can be found at location

[00 0100 00 0103

]

VectorNumber

VectorAddress

ExceptionType/Description

0 000 Reset Initial Stack Pointer

1 004 Reset Initial Program Counter2 008 Bus Error3 00C Address Error4 010 Illegal Instruction5 014 Divide by Zero6 018 CHK Instruction7 01C TRAPV Instruction8 020 Privi lege Violation9 024 Trace Exception10 028 Line 1010 Emulation11 02C Line 1111 Emulation12 030 (Unassigned Reserved)13 034 (Unassigned Reserved)14 038 (Unassigned Reserved)15 03C Uninitialised Interrupt Exception16 040 (Unassigned Reserved) 23 05C (Unassigned Reserved)24 060 Spurious Interrupt Exception25 064 Level 1 Interrupt Auto Vector26 068 Level 2 Interrupt Auto Vector27 06C Level 3 Interrupt Auto Vector28 070 Level 4 Interrupt Auto Vector29 074 Level 5 Interrupt Auto Vector30 078 Level 6 Interrupt Auto Vector

31 07C Level 7 Interrupt Auto Vector32 080 TRAP #0 Instruction Vector33 084 TRAP #1 Instruction Vector 47 0BC TRAP #15 Instruction Vector48 0C0 (Unassigned - Reserved) 63 0FC (Unassigned Reserved)64 100 User Programmable Vectored Interrupt 255 3FC User Programmable Vectored Interrupt


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68000 Vectored Interrupts

The 68000 supports seven levels ofPrioritised Interrupts 1-7 via the

3 external CPU pins [IPL2 - IPL0]

Level 0 indicates that no interrupt is present. Levels 1-7 are prioritised with 7 being the highest. The 68000s status register bits (I2, I1, I0) indicate the current level of

interrupt request being serviced. Interrupt requests with a priority less than or equal to the current value

ofI2, I1, I0 will be postponed until later. Level 7 interrupts are non-maskable and thus can never be ignored.

The sequence of operations required to generate an interruptrequest is

A peripheral requests attention by asserting its (IRQ*) output The IRQ* is connected to a priority encoderwhich generates a 3-bit

code indicating the highest level of Interrupt request currently beinggenerated.

The 3 bit output from this encoder is connected to pins IPL0-IPL2


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Upon receipt of an Interrupt Request

The 68000 compares the level of the interrupt request with the value of its interrupt

mask flags (I2, I1, I0) in the Status register.

If the requested interrupt level is greater than (I2, I1, I0), the interrupt is serviced,otherwise it is postponed.

In servicing the interrupt: The interrupt mask flags (I2, I1, I0) in the status registerare set to the level of the

interrupt being serviced and the supervisor S bit is also set to 1.

The function code pins (FC2,FC1, FC0) are set to {111} to inform the system that aninterrupt acknowledge (IACK) is in progress

The level of the interrupt being acknowledged is placed on (A3, A2, A1).

A read of the data bus is performed (during which an intelligent peripheral has theoption to supply a vector numberto the CPU during this IACK cycle).

An external interrupt acknowledge decoder, decodes the address lines(A3, A2, A1) in conjunction with the function code pins (FC2,FC1, FC0) and assertsone of seven IACK* lines that connect back to the peripheral.

The asserted IACK* line informs the interrupting device that it is about to beserviced.


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After the appropriate IACK* line is asserted by the 68000, the following

operations are performed. The peripheral supplies its Vector numberonto the data bus lines (D0-D7).

The peripheral drives DTACK*.

The 68000 reads the vector number on (D0-D7), shifts this left 2 places (x4),and accesses the interrupt service routine using the vector number as anindex into the vector table.

Only one vector capable device should be wired directly to each IACK* lineto prevent multiple devices responding with their own vector number duringan interrupt acknowledge cycle.

Note: There are two variations to this procedure

IfDTACK* is not asserted, BERR* (Bus Error) must be asserted by anexternal timer to force a spurious interrupt exception. Vector24 is then called(see vector table). This would occur if no peripheral owned up to generatingthe interrupt.

If a peripherals vector registerhas not been initialized with an appropriatevector number in software, it will generate $0F as the vector to force an

uninitialized interrupt vector exception. Vector15is called (see vector table).


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68000

IPL0IPL1IPL2

FC0FC1FC2

A01A02

A03

EncodedInterruptRequestInputs

Function Code[1,1,1] = IACK

Cycle

IACK Level onAddress Bus

Address Bus

Data Bus

0000

Status Reg

InterruptMask bits set

to level ofIRQ beingrecognised

PriorityEncoder

InterruptAcknowledge

Decoder

Peripheral 1

120

IRQ* IACK*

IACK1*IACK2*IACK3*IACK4*

IACK5*IACK6*

IACK7*

IRQ1*

IRQ2*IRQ3*IRQ4*

IRQ5*

IRQ6*IRQ7*

Peripheral 2

130

IRQ* IACK*

7Levels

ofIRQ

7Levels

ofIACK

PeripheralsuppliesVector #onto Data

Bus

IRQ onLevel 2

IACKReceived

ROM Vector Table

Stack Pointer

Reset Vector

Vector 120

Vector 130

010

111

01

0

130

Level 2 IRQ at CPU

CPU acknowledges level 2 IRQ

DTACK*

PeripheralDrives

DTACK*

Vector RegisterVector RegisterGet

ISR

0101

S bit


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PeripheralSuppliesVector

Normal Processing(User Mode)

Level 1 ISR at $0000D000

Level 1 IRQ

Stack Additional CPU RegistersService Requesting Device

Clear its IRQRestore Additional Registers

RTE

CompleteCurrent

Instruction

ResumeRestOf

Program

MainProgram

Suspendedfor

Duration ofISR

ROM Vector Table

Save PC, SR, S=1

IACK Cycle

Address = Vector


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IACK5*IACK6*

IACK7*

IRQ1*

IRQ2*IRQ3*IRQ4*

IRQ5*

IRQ6*IRQ7*

7Levels

ofIRQ

7Levels

ofIACK

IACK*Propagator

IACK*Propagator

IACK*Propagator

IACK*Propagator

Peripheral 3

122

IRQ* IACK*

Peripheral 4

123

IRQ* IACK*

Vector # 123 supplied

Vector Register

Vector Register

Peripheral 1

120

IRQ* IACK*

Vector Register

Peripheral 2

121

IRQ* IACK*

Vector Register

If IACK* receivedand CHIP is notasserting IRQ,

propagator passes

on IACK* to nextin line. Furthestaway has lowest

priority

IRQ Sharing in a Vectored Environment:Leads to faster Response than Polling

DTACK*

Address Bus

Data Bus


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Auto-Vectored Interrupts

Auto-vectored interrupts are intended for dumber peripherals that cannot

supply a vector during an Interrupt acknowledge cycle like the6850,6821 etc.

The process is similar to Vectored interrupts except that after the appropriateIACK* line is asserted during an interrupt acknowledge cycle by the 68000:

The interrupting device will assert the 68000s VPA* line (Valid PeripheralAddress)

Upon receiving an asserted VPA* line, the 68000 knows that the peripheralis a dumb device incapable of supplying a vector. The 68000 then:

Generates its own interrupt vector numberinternally based upon the prioritylevel of the IRQ* line that is being asserted.

The 68000 reserves vector numbers 25-31 forauto vectored interrupts on

IRQ1*-IRQ7* Several peripherals can be assigned to the same IRQ* level, in which case

the appropriate auto-vectored interrupt handler routine will have to resort toPOLLING each of the possible peripheral by reading their interrupt statusregisters to determine which of them is generating the interrupt.


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68000

IPL0*

IPL1*

IPL2*

FC0FC1FC2

A01A02

A03

EncodedInterruptRequestInputs

Function Code[1,1,1] = IACK

Cycle

IACK Level onAddress Bus

Address Bus

Data Bus

0000

Status Reg

PriorityEncoder

InterruptAcknowledge

Decoder

IRQ*


IACK5*IACK6*

IACK7*

IRQ1*

IRQ2*IRQ3*IRQ4*

IRQ5*

IRQ6*IRQ7*

7Levelsof IRQ

7Levels

ofIACK

IRQ onLevel 2

IACKReceived

Vector Table

Stack Pointer

ResetVector

Vector 25

Vector 26

010

111

01

0

Level 2 IRQ at CPU

IACK on level 2

VPA*

DumbPeripheral

VPAGenerated

GetISR

InterruptMask bits set

to level ofIRQ beingrecognised

S bit

0101


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Normal Processing(User Mode)

Level 3 ISR at $0000F000

Level 3 IRQ

Stack Additional CPU RegistersService Requesting Device

Clear its IRQRestore Additional Registers

RTE

CompleteCurrent

Instruction

ResumeRestOf

Program

MainProgram

Suspendedfor

Duration ofISR

$0000F000

ROM IRQ Auto Vector Table

Save PC, SR, S=1

Index into VectorTable for Level 3

IRQ

PC = $0000F000

Hardware Processing

(Supervisor Mode)

00000000

$0000E000

$0000D000 Level 1 IRQ (Auto Vector) $000064 - $000067

$00012000

$00011000

$00010000

$00012000

68000 Auto Vectored Interrupt Operation

Level 2 IRQ (Auto Vector) $000068 - $00006B

Level 3 IRQ (Auto Vector) $00006C - $00006F

Level 4 IRQ (Auto Vector) $000070 - $000073

Level 5 IRQ (Auto Vector) $000074 - $000077

Level 6 IRQ (Auto Vector) $000078 - $00007B

Level 7 IRQ (Auto Vector) $00007C - $00007F

S=0


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68000 Processing and Privilege States To fully appreciate how the 68000 and other advanced processors deal with exceptions one

has to appreciate that the 68000 is always operating in one of two states. The state information is used by memory management units (MMUs) which are used to

enforce protection between Kernel and Process code

Supervisormode (S-bit in 68000s Status register is 1) is reserved for executingoperating system code and is associated with a higher level of privilege that user mode.

Usermode (S-bit in 68000s status register is 0) is reserved for executing userprograms, and is associated with a lower level of privilege than supervisor mode.

Certain instructions and access to memory and memory mapped peripherals may belimited in user mode to constrain the process to accessing only the resources allocated

to it by an operating system.

From the state transition diagram below, we see that once the CPU enters user mode, theonly way to move to the Supervisor mode is via an exception, such as a reset, interrupt, etc.

An RTE instruction is used to restore the state of the CPU to that which it was in prior to theexception occurring, for example to change state back to usermode.

The RTE instruction itself is privileged: You can only execute it in the supervisor mode

UserMode

SupervisorMode

Exception: IRQ, Reset etc


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MMUAddressDecoder

MemorySystem

(Decoder plusMemory)

Typical 68000 MMU Interface

16 bit wide Data Bus

68000

A1 A23

D0 D15

MemoryManagement

UnitBERR

FC0 FC2

AS

Memory/IOSystem

(Decoder plusMemory)

AddressAddress Bus

Type of memory access andPrivilege

Page Fault exception

AS

MMUAddressDecoder

MMU validates each access to memory made by the code.If the code is running in supervisor mode, access is always

allowed, if in user mode, address is validated against a setof look up tables and a Page fault/exception may be

generated by the 68000s BERR* signal to signal an invalidaccess

CS

Logical

AddressPhysical

Address

TranslationLook aside

Buffer


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Trap Exceptions

These 15 instructions provide a means to execute

an OS Kernel call via an exception. Sometimes known as a software interrupt since

the behaviour is similar to hardware but initiatedvia an instruction rather than a physical signal

Imagine an OS kernel that contains 1000s ofsystem level calls.

The user program needs to make these calls, buttheir execution requires the CPU be in supervisormode as the call often involves accessing

resources that are not normally accessible by theprogram e.g. Kernel Code/IO devices etc. so theycannot be called like a conventional subroutinebecause that would lead to an access made inusermode (and the MMU would not permit it).

Instead the OS call is allocated a number, e.g.open file might be 250, the kernel call is made byloading 250 into CPU registerD0 and thenexecuting one of the trap instructions associatedwith calling the Kernel.

The exception handler for the Trap instruction iscalled and it interprets the number in D0 and callsthe correct kernel function (with the CPU now insupervisormode so that the MMU will permit it).

At the end of the Kernel call, an RTE instructionreturn the CPU back to the calling program inUserMode.

Software Interrupts and System CallsVectorNumber

VectorAddress

ExceptionType/Description

0 000 Reset Initial Stack Pointer1 004 Reset Initial Program Counter2 008 Bus Error3 00C Address Error4 010 Illegal Instruction5 014 Divide by Zero6 018 CHK Instruction7 01C TRAPV Instruction8 020 Pr ivi lege Violation9 024 Trace Exception10 028 Line 1010 Emulation11 02C Line 1111 Emulation12 030 (Unassigned Reserved)13 034 (Unassigned Reserved)

14 038 (Unassigned Reserved)15 03C Uninitialised Interrupt Exception16 040 (Unassigned Reserved) 23 05C (Unassigned Reserved)24 060 Spurious Interrupt Exception25 064 Level 1 Interrupt Auto Vector26 068 Level 2 Interrupt Auto Vector27 06C Level 3 Interrupt Auto Vector28 070 Level 4 Interrupt Auto Vector29 074 Level 5 Interrupt Auto Vector30 078 Level 6 Interrupt Auto Vector

31 07C Level 7 Interrupt Auto Vector32 080 TRAP #0 Instruction Vector33 084 TRAP #1 Instruction Vector 47 0BC TRAP #15 Instruction Vector48 0C0 (Unassigned - Reserved) 63 0FC (Unassigned Reserved)64 100 User Programmable Vectored Interrupt 255 3FC User Programmable Vectored Interrupt


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Full Privileges

Limited Privileges

S = 1

S = 0

Operating System(Supervisor Mode)

User Program 1(User Mode)

Operating System(Supervisor Mode)


Device1Device1

Device1RTC

Interrupt

Device1Device2

Interrupt

Device1

Device3

Interrupt

Device1Device4

Interrupt

Interrupt

Device1Push Button

Reset

System Call(Trap Exception)

Exit()





Full Privileges

Limited Privileges

S = 1

S = 0

Entry to Supervisor mode triggered by an exception

System Call(Trap Exception)CreateThread()

System Call(Trap Exception)

OpenFile()

Documents

Lecture 16,17 - IO Interfacing and Interrupts