Lecture 3: MOSFET Modeling - eng.biu.ac.il · ©Adam Teman, March 29, 2020 MOSFET Current Modeling •In Digital Electronic Circuits, we used the Shockley Model or Unified Model for

29 March 2020

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Digital Integrated Circuits(83-313)

Lecture 3:

MOSFET Modeling

mailto:[email protected]

March 29, 2020© Adam Teman,

MOSFET Current Modeling

• In Digital Electronic Circuits, we used the

Shockley Model or Unified Model for hand-

analysis of circuit operation.

• However, there are many models with varying

levels of accuracy to estimate the I-V curves of

a MOSFET.

• In this section, we will overview several models

that will come in use throughout this course

and your future.

2

Source: Wikipedia


Lecture Content

3

Basic MOS Models

4

1

Basic MOS Models

2

Advanced

MOS Models

4

Simulating

Variation

3

VT Revisited

5

Leakage


TCAD vs. Compact Models

• Technology CAD (TCAD) is a simulation environment

for accurately simulating device behavior:

• Provide a process “recipe” and device layout

• Produce IV or CV curves through device simulator

• Used to predict device and process physics

• Takes 1hr-1day per IV curve and 100s MB RAM per transistor

• Compact models (a.k.a. SPICE models or ECAD) are

simple models used for circuit simulation

• Provide a set of equations that SPICE uses to

calculate IV or CV curves

• Should take <100us per IV curve

and a few KB per transistor

• Usually extracted empirically from measurements

TCAD is

too slow and memory

hungry to be used for

circuit simulation!

SPICE uses compact

models for calculating

device behavior


Switch Model

• The most simple MOSFET model is the Switch Model.

6

VGS

IDS

VT

VDS

IDS

1/Ron

VGS > VT

S D

Ron

The Switch Model

The Piece-Wise Linear

The Square Law Model

The V-Sat Model

The Unified Model

The VT* Model

The α- Power Law

BSIM


The Piece-Wise Linear Model

• As we know, when the channel pinches off,

the current saturates.

• This can be depicted with the simple

Piece-Wise Linear Switch Model

7

VDS

IDS

1/Ron

IDSAT

VGT

linear saturation

The Switch Model



The V-Sat Model

The Unified Model

The VT* Model

The α- Power Law

BSIM


Adding Channel Length Modulation

• Channel Length Modulation modeled as a finite output

resistance, causes a saturation current dependence on VDS.

8

VDS

IDS

1/Ron

IDSAT

VGT

Channel

Length

Modulation

λIDSAT

-1/λ

IDSAT

1/λ

I DS

AT

D

S

VDS

IDS

The Switch Model



The V-Sat Model

The Unified Model

The VT* Model

The α- Power Law

BSIM


Square Law (Shockley) Model

• To get a more accurate model, we already are familiar with the

Shockley or Square Law Model.

• Current is just charge times velocity, so at any point, x, along the channel:

• We found that charge can be approximated as:

• And the velocity is the mobility times the electrical field:

9

( ) ( ) ( )DI x x Q x Wdx= −

( ) ( )ox GS CS TQ x C V V x V= − − −

( ) ( ) n

dVx E x

dx = − =

The Switch Model



The V-Sat Model

The Unified Model

The VT* Model

The α- Power Law

BSIM



• So we get:

• And integrating from source to drain, we get

• At pinch-off (VDS=VGS-VT), the voltage over the channel is constant, so we get:

• This is where the “Square-Law” name comes from.

10

( )D n ox GS TI dx C W V V V dV= − −

( )0 0

1

2

DSL V

DS D n ox GS T n ox DS GS T DS

WI I dx C W V V V dV C V V V V

L

= = − − = − −

( )2

2DSAT n ox GS T

WI C V V

L= −

The Switch Model



The V-Sat Model

The Unified Model

The VT* Model

The α- Power Law

BSIM



• Replacing VDS with VDSeff=min(VGS-VT, VDS) we get:

11

( ) ( )2

12

DSeff

DS n ox GS T DSeff DS

VWI C V V V V

L

= − − +

The Switch Model



The V-Sat Model

The Unified Model

The VT* Model

The α- Power Law

BSIM


The Velocity Saturation Model

• However, when looking at a short channel device,

we see a linear dependence on VGS.

• This can be attributed to Velocity Saturation.

12

510satm

s

The Switch Model



The V-Sat Model

The Unified Model

The VT* Model

The α- Power Law

BSIM



• A good approximation of the mobility curve is:

• For continuity:

• After integration, we get:

13

1crit

crit

sat crit

+=

2 satcrit

=

( )2

21

n ox DSDS GS T DS

DS

crit

C VWI V V V

V LL

= − −

+

The Switch Model



The V-Sat Model

The Unified Model

The VT* Model

The α- Power Law

BSIM



• This is hard to use, but we can reach an important conclusion.

• We found that:

• And we know that for a velocity saturated device:

• Equating, we get:

14

( )( )

GS T crit

DSAT

GS T crit

V V LV

V V L

−=

− +

( )2

21

n ox DSDS GS T DS

DS

crit

C VWI V V V

V LL

= − −

+

( )DS ox GS DSAT T satI WC V V V = − −

( )DSAT crit GT GS TV L V V V pinchoff = −

( )DSAT crit GT critV L V L vel sat =

The Switch Model



The V-Sat Model

The Unified Model

The VT* Model

The α- Power Law

BSIM


The Unified Model for Hand Analysis

• A few simple estimations will make the V-Sat model more user-friendly:

• The mobility is piecewise linear, saturating at ξ>ξcrit/2

• VDSAT is piecewise linear, saturating at VDSAT=ξcritL/2, when VGT>ξcritL/2

15

The Switch Model



The V-Sat Model

The Unified Model

The VT* Model

The α- Power Law

BSIM


The Unified Model for Hand Analysis

• This brings us to the Unified Model:

16

( ) ( )2

12

DSeff

DS n ox GS T DSeff DS

VWI C V V V V

L

= − − +

( )min , ,DSeff GS T DS DSATV V V V V= −

2

critDSAT

LV

=

2 satcrit

=

The Switch Model



The V-Sat Model

The Unified Model

The VT* Model

The α- Power Law

BSIM

Advanced MOS Models

17

1

Basic MOS Models

2

Advanced MOS

Models

4

Simulating

Variation

3

VT Revisited

5

Leakage


VT* Model

• Sometimes we want to use a really simple model.

• We can assume that if the transistor is on, it’s velocity saturated.

18

( )

*

2

2

2

T

DSATDS n GS T DSAT

DSATn GS T DSAT

V

VI k V V V

Vk V V V

= − − =

= − +

( )

*

* *

0 GS T

DS

n GS T DSAT GS T

V VI

k V V V V V

=

−

The Switch Model



The V-Sat Model

The Unified Model

The VT* Model

The α- Power Law

BSIM


The Alpha Power Law Model

• Sakurai found that by changing the exponent of the square law, a better fit

can be found with simple calculations.

19

( ) ( )2

DSAT n ox GS T

WI C V V

L

= −

Shockley (α=2) Alpha (α=1.3)

The Switch Model



The V-Sat Model

The Unified Model

The VT* Model

The α- Power Law

BSIM


BSIM and Newer Models

• BSIM (Berkeley Short-channel IGFET Model) is the primary compact model family

used for SPICE simulation for the last three decades.

• These model use hundreds of parameters

to achieve a good fit.

• BSIM4 is the main model for bulk CMOS

• Takes into account most physical effects

as well as many fitting parameters.

• The Compact Model Coalition (CMC) chooses,

maintains and promotes new models

• Additional models include EKV, PSP, and

models for non-MOS devices.

20

The Switch Model



The V-Sat Model

The Unified Model

The VT* Model

The α- Power Law

BSIM and more

Source: Yen Ki Lin, UC Berkeley


Time to Kahoot!

www.kahoot.com

VLSI Lecture 3a

http://www.kahoot.com/

Threshold Voltage Revisited

22

1

Basic MOS Models

2

Advanced

MOS Models

4

Simulating

Variation

3

VT Revisited

5

Leakage


Energy Band Diagrams

• To understand the threshold voltage and other secondary effects of the MOS

device, we often use energy band diagrams.

• The first approach is looking in from the gate:

23


Energy Band Diagrams

• The second approach is looking from the source to the drain.

24


Threshold Voltage - Basic Theory

• The basic definition of threshold voltage is

the gate voltage (VG) required to invert the channel

25

0 2depOX

T MS F

ox ox

QQV

C C= − − −

2 2dep A si FQ qN = −

ln AF T

i

N

n = −

T

kT

q

Basic TheoryClassic Body

EffectModern Body

EffectHot Carriers VT Roll-Off DIBL RSCE Measuring VT


Body Effect

• The appearance of a voltage difference between the

source and body (VSB) is known as “The Body Effect”

• This can be modeled by the additional

charge that needs to be depleted.

26

( )2 2dep A si F SBQ qN V= − +

( )0 2 2T T F SB FV V V= + − + − −

2 si A

ox

q N

C

=

0

0 2depox

T MS F

ox ox

QQV

C C − − −


EffectModern Body



Modern Body Effect

• A different approach is to look at the capacitive voltage divider between the

gate and body (CGB)

27

( ) ( )

( )

0

0

max

31 1

inv oxe GS CS T dep SB CS

oxe GS CS T

dep oxe

oxe d

Q C V V V C V V

C V nV V

C Tn

C W

= − − − + +

= − − −

+ = +

maxd

sdep

WC

=

VGG

C

B

S

Coxe

Cdep

VS

VB


EffectModern Body



Modern Body Effect

• This can be shown to redefine VT as:

• In modern technologies, Cdep/Coxe is a constant,

so VT is linearly dependent on VSB!

28

dep

T SB T0 SB

oxe

( )C

V V V VC

= +


EffectModern Body



Poly Depletion and Channel Depth

The threshold voltage is affected by two additional

factors that we have disregarded until now:

• Polysilicon Depletion

• Since polysilicon is, itself, a semiconductor,

the depletion layer into the poly effectively

increases the oxide thickness.

• Channel Depth

• Since the channel is not a 2-dimensional

line along the surface, the oxide thickness

is essentially increased.

29

max

31 1

dep oxe

oxe d

C Tn

C W+ = +


EffectModern Body



Hot Carrier Effects

• Electrons can get so fast that they can tunnel into the gate oxide

and increase the threshold voltage.

• This is a reliability issue as it happens over time.

30

0 2depOX

T MS F

ox ox

QQV

C C= − − −


EffectModern Body



VT Roll Off (Short Channel Effect)

• As channel length is reduced, effective

channel length is reduced by depletion regions.

• A trapezoid is created under the gate, dividing

the channel into the region controlled by the

gates and by the drain.

• In essence,

VT is reduced.

31

K. Goto et al., IEDM 2003

65nm technology.

tox=1.2nm

Vdd=1V


EffectModern Body



DIBL (Drain Induced Barrier Lowering)

• In short channels, the barrier of the channel is

essentially lowered, as the drain causes the energy

band to drop closer to the source.

• This is exponentially dependent on VDS.

32

( ) dT T,long DS

oxe

0.4C

V V VC

= − +


EffectModern Body



Roll Off / DIBL combined

33Basic Theory

Classic Body Effect

Modern Body Effect

Hot Carriers VT Roll-Off DIBL RSCE Measuring VT

Source: Chris Kim, U. Minn


Reverse Short Channel Effect (RSCE)

• VT actually increases at channel lengths a bit higher than minimum…

34Basic Theory

Classic Body Effect

Modern Body Effect



How to Measure VT

• There are various ways to measure VT

• One classic way takes a small VDS and sweeps VGS.

• So we can find the VGS at which the linear part

crosses Ids=0.

35

VDS=50mV

2( ) 0.5d gs t ds dsI k V V V V= − − gs tV V −

VT,gm


EffectModern Body



How to Measure VT

• One of the more common ways is to find the VGS at which IDS=100 nA x W/L.

• For VT,lin, set a low VDS (VDS=50mV)

• For VT,sat set a high VDS (VDS=VDD)

36Basic Theory

Classic Body Effect

Modern Body Effect


The Computer Hall of Fame

• We generally consider the ENIAC to be the first computer, but the official first fully electronic computer was the

• Atansoff-Berry Computer

Conceived in 1937, operational in 1942

• Built at Iowa State University by Prof. John Atansoffand his student Clifford Berry.

• Not programmable nor Turing-complete, but included binary arithmetic and electronic switching elements.

• A patent dispute over the first electronic computer was settled in 1973, when the patent of the ENIAC was invalidated.

Source: wikipedia

Source: wikipedia

Add-Subtract Module

Simulating VariationProcess Corners and Monte Carlo Simulation

1

Basic MOS Models

2

Advanced

MOS Models

4

Simulating

Variation

3

VT Revisited

5

Leakage


Reminder: Impact of Process Variations

39 Source: Rabaey, et. al.

How do we take this

into consideration

during simulation?


Remove the Rust: Probability Basics

• Properties of Random Variables

• The probability distribution function (PDF) f(x) specifies the probability that a

value of a continuous random variable X falls in a particular interval:

• The cumulative distribution function (CDF) F(x) specifies the probability that X

is less than some value x:

• The mean (µ) and variance (σ2) are defined as:

40

( )b

aP a X b f x dx =

( ) ( )x

F x P X x f u du−

= = ( ) ( )d

f x F xdx

=

( ) ( )X X E X x f x dx

−= = = ( ) ( ) ( ) ( )

2 22 X E x X x X f x dx

−

= − = −


Remove the Rust: Probability Basics

• Normal Random Variables

• A normal (Gaussian) random variable, shifted to have a zero mean (µ=0) and a

normalized standard variation (σ2=1) has:

41

( )21

21

2

x

f x e

−

= ( )1

1 erf2 2

xF x

= +

3σ=99.8%

6σ =1 in a billion


Global Variation Modeling: Process Corners

• Global Variation assumption:

• If a certain process step is skewed, the entire chip is affected equivalently.

• We will define “corner cases” of fabrication, i.e., 3σ from the mean.

• We also assume the voltage and temperature are globally affected.

• Devices are modeled for fast, slow and nominal corners.

• Changes in VT, W, L, tox

• Devices are tested at various temperatures

• Temperature affects mobility and VT.

• Typically 0°C – 85°C or -40°C – 125°C

• Devices are tested at various supply voltages

• Higher voltages cause increased currents

• Typically ±10%VDD42


Process Corners

• What are the PVT (=Process, Voltage, Temperature)

settings for each simulation corner?

43

Corner VT Leff tox VDD T

Fast

Typical X X X X X

Slow


What about Local Variation?

• Often there are too many parameters to think about

and setting a specific corner case is insufficient.

• For example: Pelgrom’s Law

• VT variance is inversely proportional

to transistor area

44Source: Stanford, EE380

𝜎 𝑉T =𝐾

𝑊 ⋅ 𝐿

Source: Asenov, IEEE TED 1998

How do we

deal with this?


Monte Carlo Simulation

• The basic approach is to “roll the dice” for each

parameter and run a simulation.

• These are called Monte Carlo Statistical Simulations.

• The result is a distribution plot of design constraints,

e.g., delay or noise margin

• Both Global and Local Variations can be

taken into consideration.

Source: Stanford, EE380


Simulation tip: OP and MP in Spectre

• How do you know what the parameters of a device are in a given simulation

(in light of bias, corner, random variation)?

• For example, how do I know what the VT of a transistor is?

• To find VT0, use the “MP” option.

• To find VT,lin, VT,sat, VT,gm, use the “OP” option.

• Example – plot VT Roll Off (SCE)

46


Time to Kahoot!

www.kahoot.com

VLSI Lecture 3b


Leakage in NanoScaled Transistors

48

1

Basic MOS Models

2

Advanced

MOS Models

4

Simulating

Variation

3

VT Revisited

5

Leakage


Leakage in Nanoscaled Transistors

• Transistors that are supposed to be off actually leak!

49


Main Types of Leakage

50

P-substrate

n+n+

Source Drain

Polysilicon Gate

Oxide

subthreshold

Ga

te

Punchthrough

GS TV V

subI e−

1,gate GC

ox

I Vt

GIDL DGI V

DSVDIBL e


Subthreshold Leakage

• When VGS<VT, there is still a finite carrier

concentration at the surface:

• As we saw with the body effect, due to bulk to channel

capacitance, the surface voltage isn’t only controlled

by the gate:

51

s GS T

T T

V Vn

s subn e I e

−

1s oxe

g oxe dep

d C

dV C C n

= =

+Cdep

S

Cox

VG

1dep

oxe

Cn

C +


Gate Leakage GIDL Diode Leakage Punchthrough Corners Revisited



• Let’s make things easier:

• Remember that:

• And we now defined the threshold

voltage according to current:

• So the boundary

condition requires:

• And we can now calculate

subthreshold current as:

52

( )GS T

DS sub T

V VnW

I Const eL

−

=

GS T

sub 100 T

V VnW

I nA eL

−

=

( )DS GS T= 100nAW

I V VL

=

( )GS T

0

DS sub 100nATn

V V

W W WI Const e Const

L L L

== = =





• An even easier way is to look at the plot of log(IDS)=f(VGS):

• The slope of this curve is called the “Subthreshold Slope”

• The inverse of this slope is known as the

“Subthreshold Swing” (S):

• And Ioff, which is defined as

the current when VGS=0 is:

53

GS T GS T

sub 100 100 10T

V V V Vn S

W WI nA e

L L

− −

= =

T

off 100 10V

SW

I nAL

−

=

( ) dep

ox

ln 10 1 2.3 T

CkTS n

q C

+ =





• So subthreshold leakage is:

• Exponentially dependent on VGS.

• Exponentially dependent on VT.

• S is the subthreshold swing coefficient.

• Optimally, Sopt=60 mV/dec

• Realistically S ≈100 mV/dec

54

ln10 0.06TS n dep

oxe

1C

nC

+





Example:

• We want to design a transistor with:

• What is the minimum VT?

55

4on

off

10I

I

mV60

decS =




Impact of DIBL

• DIBL causes an additional exponential increase

in subthreshold leakage with VDS.

56

90nm technology.

Gate length: 45nm

Intel, T. Ghani et al., IEDM 2003

GS T DS DS

sub 0 (1 )T T T

V V V V

n nI I e e e

− − = −




Subthreshold Dependence on Temperature

• This is rather complex, as mobility degrades with temperature and other device

values (such as flatband voltage) are temperature dependent.

• Altogether, subthreshold leakage rises

exponentially with temperature*.

* Without considering temperature inversion

57

GS T

subT

V V

I e −

TkT

q




Temperature Inversion

• Classic approach to temperature effect on delay:

• BUT!

• VT decreases by as much as -3mV/°C

• The point of temperature inversion is the voltage at which speed

increases with temperature (~VDD=1V)!

58

1

I

T

pdt T→

1T

pd T

V T

t V

1pdt T→



So speed decreases

with temperature

So speed actually

increases with

temperature!


Gate Leakage

• Two mechanisms:

• Direct tunneling (dominant)

• Fowler Nordheim tunneling

• Exponentially Dependent on:

• Gate Voltage (VG)

• Oxide Thickness (tox).

• Non-dependent on temperature.

• Much stronger in nMOS than pMOS

(higher barrier for holes)

• Minimum tox=1.2nm!!!

59



ox2

gate ox

BE

I AE e−

=

DD Tox

ox

V VE

t

−=


Gate Induced Drain Leakage

• GIDL current flows from the drain to the substrate.

• Caused by high electric field under the gate/drain

overlap, causing e-h pair creation.

• Main phenomena is Band-to-Band Tunneling

60




Diode Leakage

• JS=10-100pA/μm2 @25°C for 0.25μm CMOS.

• JS doubles for every 9°C

• Much smaller than other leakages in deep sub-micron.

• But a bigger factor in low subthreshold leakage processes, like FinFET.

61

DL SI J A=


Gate Leakage GIDL Diode Leakage Punchthrough Latchup


Punchthrough

• As VDS grows, so does the drain depletion region,

and the channel length decreases.

• In severe cases, the source and drain are connected

causing non-controllable leakage current.

62

rjWs

xo

rjWD

L +VD

rjWs

xo

rjWD

L++VD

e-




Leakage Summary• Subthreshold Leakage:

• IDS>0 when VGS<VT due to weak inversion.

• Grows with VGS, VDS, lower VT

• Gate Leakage:• IG>0 due to direct tunneling through the oxide.

• Grows with VGB, tox

• Gate Induced Drain Leakage (GIDL):• IDB>0 due to high electric field in

the GD overlap region (VGD).

• Reverse Biased Diode Leakage• ISB, IDB Due to diffusion and thermal generation.

• Punchthrough:• IDS due to drain and source depletion layers touching.

63




Process Corners - Revisited

• Should we now redefine the PVT settings?

64

Corner VT Leff tox VDD T

Fast

Typical X X X X X

Slow

Max Leakage



But what about

Temperature Inversion?


Time to Kahoot!

www.kahoot.com

VLSI Lecture 3c



Further Reading

• J. Rabaey, “Digital Integrated Circuits” 2003, Chapters 2.5, 3.3-3.5

• Weste, Harris “CMOS VLSI Design”, Chapter 7

• C. Hu, “Modern Semiconductor Devices for Integrated Circuits”, 2010, Chapters 4-7

• Tzividis, et al. “Operation and Modeling of MOS Transistor”Chapters 1-5

• E. Alon, Berkeley EE-141, Lecture 9 (Fall 2009)

• M. Alam, Purdue ECE-606 – lectures 32-38 (2009) nanohub.org

• A. B. Bhattacharyya “Compact MOSFET models for VLSI design”, 2009,

• T. Sakurai, “Alpha Power-Law MOS Model” – JSSC Newsletter Oct 2004

• Managing Process Variation in Intel’s 45nm CMOS Technology, Intel Technology Journal, 2008

• Berkeley “BSIM 4.6.4 User’s Manual”

http://www-device.eecs.berkeley.edu/~bsim/BSIM4/BSIM464/BSIM464_Manual.pdf

66

Documents

Lecture 3: MOSFET Modeling - eng.biu.ac.il · ©Adam Teman, March 29, 2020 MOSFET Current Modeling •In Digital Electronic Circuits, we used the Shockley Model or Unified Model for