LIN Controller with Position Detection E521 Controller with Position Detection E521.31 PRODUCTION DATA – Oct 6, 2015 Pin Description No Name Type Description 1 IO0 D_IO GPIO / JTAG

LIN Controller with Position Detection E521.31 PRODUCTION DATA – Oct 6, 2015

Features• Integrated16 bit microcontroller• 32kByte Flash• 28kByte Flash for EEPROM-emulation, bootblock

and up-time-counter• 1 kByte RAM• 4 PWM generator 16 bit: 16 bit resolution with

fPWM,CYCLE up to 500Hz• 2 timer + 2 capture compare timer 16bit• ADC 12 bit resolution / fS=1MHz• 2 wire JTAG debug interface (IAR compatible)• Hardware divider / multiplier• LIN-Bus transceiver (V2.1) including optional

slave node position detection (SNPD)• LIN UART with autobaud detection < 0.15%• Voltage regulator 5.0V / 100mA output• Four LED highside driver (5V)• Battery supply range 5V to 28 V• Package QFN32L5

Applications• Interior light modules

General DescriptionThe device E521.31 is a LIN controller providing a 16bit microcontroller with two independent Flash memory blocks, a 5V voltage regulator with up to 100mA and a LIN transceiver providing optional auto addressing.The integrated high side driver controlled by a 16 bit PWM can be used to drive external loads with current up to 50mA each.For temperature compensation the device provides an integrated temperature sensor.

Ordering InformationOrdering No. Temp Range Package

E52131B61C -40°C to +125°C QFN32L5

Typical Operating Circuit

Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

Elmos Semiconductor AG Data Sheet QM-No.: 25DS2131E.03 1 / 139

VDDIO

Optional JTAG access port

LIN_M

GND

LIN_S

VBAT

Internalvoltage

regulators

LDO voltage regulator

5V/100mA 2%

uController32kByte FLASH

1kByte RAM

4x 16bit PWM

Timer

ADC12bit1us

LINUART

LIN transceiverwith autoaddressing

GPIO

ADCMUX

Temp.sensor

JTAGdebug IF

Powermanagement

E521.31

NVM

1.8Vcore VR

Watchdog

MUXOTXD

RXD

IN2

IN1

IN0

IN3

VSGND

VDD3

VDDUCVDDCDGND

NRST

VDD5

OUT1OUT2OUT3OUT4

LIM_MLIN_GNDLIN_S

SIN4SIN3SIN2SIN1

IO5IO4IO3IO2IO1/TDAIO0/TCKTST


Functional Diagram

Pin Configuration




Pin DescriptionNo Name Type Description

1 IO0 D_IO GPIO / JTAG TCK / PWM0 (internal pull-up)

2 IO1 D_IO GPIO / JTAG TDA / PWM1 (internal pull-up)

3 IO2 D_IO GPIO / TXD / CCTIMER MEAS / PWM2 (internal pull-up)

4 IO3 D_IO GPIO / RXD / CCTIMER PWM / PWM3 / CLK_EXT (internal pull-up)

5 NRST D_I nReset input (internal pull-up)

6 IO4 D_IO GPIO / AIN1 (internal pull-down)

7 IO5 D_IO GPIO / AIN2 (internal pull-down)

8 TMODE D_I test mode (internal pull-down)

9 VDDC S core voltage pad (internal regulator: 1.8V)

10 DGND S GND-Pin, IO ground pad, core ground pad

11 AGND S GND-Pin, analog ground pad

12 VDDUC S 3.3V analog supply input of uC, analog voltage pad (3.3V)

13 VDD3 S 3.3V voltage regulator for µC part (up to 35mA)and VDDIO-supply voltage input pin of uC

14 GND HV_S ground

15 VDD5 S peripheral voltage supply

16 VS HV_S battery supply voltage

17 OUT1 A_O high side driver for LED1




21 SIN1 A_I sense input 1




25 LIN_GND HV_S LIN ground

26,29-32

n.c.

27 LIN_S HV_A_IO LIN bus line (direction to next slave)Optional: If auto addressing is not used keep pin open or connect to pin LIN_M

28 LIN_M HV_A_IO LIN bus line (direction towards master)Note: A = Analog, D = Digital, S = Supply, I = Input, O = Output, B = Bidirectional, HV = High Voltage




1 Functional SafetyThe development of this product is based on a process according to an ISO/TS 16949 certified quality manage-ment system. Functional safety requirements according to ISO 26262 have not been submitted to Elmos and there-fore have not been considered for the development of this product.

Implementation of functional safety requirements according to ISO 26262 will have a significant impact on the development process and the technical concept.Therefore, in case functional safety requirements according to ISO 26262 are submitted, both parties have to agreeon a DIA (Development Interface Agreement) before start of development.




2 Absolute Maximum RatingsStresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. These are stress ratings only; operation of the device at these or any other conditions beyond those listed in the operational sections of this document is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltages referred to VGND. Currents flowing into terminals arepositive, those drawn out of a terminal are negative.

No. Description Condition Symbol Min Max Unit

1 Digital IO voltage maximum rating (pins, IO0, ... IO5, TMODE, NRST)

continuous VIOx,DC -0.3 VDDuC+0.3

V

2 Microcontroller power supply and I/O voltage continuous VDDuC,DC -0.3 3.6 V

3 DC voltage at pin VS continuous VVS,DC -0.3 40 V

4 Junction temperature continuous TJUNC -40 125 °C

5 Storage temperature continuous, unsoldered

TSTG -40 125 °C

6 Voltage at pins LIN_M, LIN_S continuous VLIN,x -27 40 V

7 DC current at each other pin, if not specified oth-erwise

continuous IIO,LUP -10 10 mA

8 DC voltage at pin VS continuous VS,DC -0.3 40 V

9 DC voltage at pin VDD5 continuous VDD,DC5.0 -0.3 5.5 V

10 DC current at pin VDD5 continuous IDD,DC -150 1 mA

11 DC voltage at pin VDD3 continuous VVDD3,DC -0.3 3.6 V

12 DC current at pin VDD3 continuous IVDD3,DC -40 0.5 mA

13 minimum and maximum voltage at pins OUT1-OUT4

continuous VOUTx,DC -0.3 5.5 V

14 Current at pins OUT1-OUT41) continuous IOUTx,DC -75 0.5 mA

15 minimum and maximum voltage at pins SIN1-SIN4

continuous VSIN,MAX -0.3 5.5 V

16 Absolute Temperature Range TABS -40 150 °C

17 Analog Power Supply = Chip Supply VDDIO_ABS -0.3 3.6 V

18 Digital Core Power Supply VDDC_ABS -0.3 1.98 V

19 Pin Voltage VPORT_ABS -0.3 VDDIO+0.3

V

20 number of FLASH erase cycles Endurance 10000 cycles

21 FLASH data retention time T = 85°C Data_Retention

10 years

22 number of allowed "same address FLASH pro-gram cycles" before next erase

Same_Addr_Program

2 cycles

23 cumulative FLASH row program time Row_Program_Time

32 ms

1) The suppling VDD5 voltage regulator provides about 150mA to the HS-Drivers, although the all 4 drivers are able to handle 75mA each, the entire IC provides a sum current over all drivers of about 150mA peak




3 ESD, Latch Up and EMC

3.1 Electro Static Discharge (ESD)Standard AEC-Q100-002

Model Human Body Model (HBM)

Capacitance 100 pF

Resistance 1,5 kΩ

Minimum withstand Voltage +/- 8 kV for LIN to system ground

Minimum withstand Voltage +/- 4 kV for VS to system ground

Minimum withstand Voltage +/- 2 kV for all other pins

Pulse rise time (10%-90%) < 10 ns

Test point pin to supply

Number of pulses 1 of each poarity

Standard AEC-Q100-003

Model Machine Model (MM)

Test point Pin to system ground

Capacitance 200 pF

Resistance 0 kΩ

Minimum withstand Voltage +/- 100 V for Pins VS, LIN_M, LIN_S to system ground

Standard AEC-Q100-011

Model Charged Device Model (CDM)

Resistance 1 Ω

Minimum withstand Voltage +/- 750 V for edge pins

+/- 500 V for all other pins

Pulse rise time (10%-90%) <400 ps

Optional ESD Test Test equipment similar IEC 61000-4-2

Capacitance 150pF

Resistance 330Ω

Minimum withstand Voltage +/- 8kV(According to document "OEM hardware requirements for LIN, CAN and FlexRay Interfaces", version 1.3)

3.2 Latch-upLatch-up performance is validated according JEDEC standard JESD 78 in its valid revision.

3.3 EMC The device needs to fulfil the OEM EMC requirements specified in the "Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications", V1.3, dated 04.05.2012




4 Recommended Operating ConditionsDescription Condition Symbol Min Typ Max Unit

functional range, besides LIN, LIN > 7V VS,FUNC 5.5 - 18 V

limited functional range VS,FL,HR 18 27 V

external load capacitance at pin VDD51) CVDD5,LF 2.2 10 100 uF

ESR of external load capacitor CVDD5,LF at pin VDD52)

ESRC_VDD5,LF - 100 500 mΩ

External buffer capacitance range at pin VDD3 CVDD3 10 100 470 nF

ESR of external buffer capacitor pin VDD3 ESRC_VDD3 - 0.2 1 Ω

operating temperature TOP -40 25 125 °C

chip supply voltage VDDuC 3.0 3.3 3.6 V

buffer capacitance at VDDC pin CDDC 7 10 13 nF1) this capacitor is mandatory for proper functioning of the IC2) this capacitor parameter is mandatory for proper functioning of the IC




5 Electrical Characteristics(VVS = 5.5V to 27V, Tamb=-40°C to + 125°C, unless otherwise noted. Typical values are at VVS=12.0V and Tamb=+25°C. Positive currents flow into the device pins.)

Description Condition Symbol Min Typ Max Unit

uC analog Supply, pin VDDuC

Supply and I/O voltage of the integrated micro-controller*)

VDDuC 3.1 3.3 3.6 V

Power Supply and References; pin VS

current consumption in active mode LIN dominant, IDD=0mA

IS,ACT,DOM - - 5 mA

current consumption in active mode LIN recessive, IDD=0mA

IS,ACT,REC - - 5 mA

sleep current at temperatures less than 40°C sleep mode,LIN recessive,VS =VLIN=13.5VTAMB<40°C

IS,SLEEP_LT - 9 15 µA

sleep current at temperatures higher than 40°C sleep mode,LIN recessive,VS =VLIN=13.5VTAMB>40°C

IS,SLEEP_HT - 13 20 µA

power on reset according to pin VS power on threshold

VS,POR 4.0 - 5.0 V

power down threshold according to pin VS power down threshold

VS,PD 3.0 - 3.8 V

Voltage Regulator 5V; pin VDD5

Output voltage at pin VDD5 active mode, VS > 5.5V, IDD5 >= -100mA, -40 °C <= TJUNC <= 125°C

VDD5 4.9 5.0 5.1 V

VDD5 programming range lower limit (5Bit) active mode, VS > 5.2V, IDD5 >= -100mA, -40 °C <= TJUNC <= 125°C,CAL_5V = 0x0

VDD5_PROG_LRL - - 4.6 V

VDD5 programming range upper limit (5Bit) active mode, VS > 6V, IDD5 >= -100mA, -40 °C <= TJUNC <= 125°C,CAL_5V = 0x1F

VDD5_PROG_URL 5.4 - - V

VDD5 programming resolution*) active mode, VS > 5.5V, IDD5 >= -100mA, -40 °C <= TJUNC <= 125°C

VDD5_RES - 26 50 mV/LSB

output current limitation IDD5,LIM -350 - -200 mA





Output Resistance of the VDD5 voltage regulator inthe LowDrop region*)

active mode,3.8V <= VS <= VDD5 + ROUT5_LD*(-IDD5), IDD5 >= -100mA, -40 °C <= TJUNC <= 125°C

ROUT5_LD - 2.5 4 Ω

Voltage Regulator 3.3V ; pin VDD3

Output voltage at pin VDD3 5V <= VS <= 27V IDD3 >= -35mA

VDD3 3.15 3.3 3.55 V

output current limitation 5V <= VS <= 27V

IDD3,LIM -80 - -40 mA

Characteristics

functional range LIN transceiver VLIN,VS 7 - 18 V

recessive output voltage TXD = 1 VLIN,REC VS -1V - VS -

dominant output voltage TXD = 0, VS = 7.0V, RLIN = 0.5kΩ to VS

VLIN,DOM - - 1.2 V

dominant output voltage TXD = 0, VS = 18V, RLIN = 0.5kΩ to VS

VLIN,DOM1 - - 2.0 V

receiver dominant level VLIN,THDOM - - 0.4 VS

receiver recessive level VLIN,THREC 0.6 - - VS

LIN bus center voltage VLIN,BUSCNT = (VLIN,THDOM + VLIN,THREC) / 2

VLIN,BUSCNT 0.475 - 0.525 VS

receiver hysteresis VLIN,THREC - VLIN,THDOM

VLIN,HYS - - 0.175 VS

output current limitation VLIN = VVS,MAX = 18V

ILIN,LIM 40 - 200 mA

pull up resistance RLIN,SLAVE 27.66 - 40 kΩ

leakage current flowing into pin LIN transmitter pass-ive, 7V < VS < 18V, 7V < VLIN < 18V, VLIN > VS

ILIN,BUSREC - - 20 μA

pull up current flowing out of pin LIN transmitter pass-ive, 7V < VS < 18V, VLIN = 0V

ILIN,BUSDOM -1 - - mA

leakage current, ground disconnected (GND device = VS)

VS = 13.5V, 0V <VLIN < 18V

ILIN,NOGND -1 - 0.1 mA

leakage current, supply disconnected VS = 0V, 0V < VLIN < 18V

ILIN - - 20 μA

clamping voltage *) VS = 0V, ILIN = 1mA

VLIN,CLAMP 40 - V

input capacitance *) 7V < VS < 18V CLIN,PIN - - 30 pF

receive propagation delay tRXD,PDR - - 6 μs

receive propagation delay symmetry tRXD,SYM -2 - 2 μs





LIN bus pulse receiver debounce time*) tLIN,DB 0.3 - 6 μs

wake up debounce time tLIN,WU 70 - 150 μs

Duty cycle 11) VLIN,THREC(max) = 0.744*VS, VLIN,THDOM(max) = 0.581*VS, VS = 7-18V, tBIT = 50us, DLIN,1 = tBUS-

REC(min)/(2*tBIT)

DLIN,1 0.396 - - -

Duty cycle 21) VLIN,THREC(min) = 0.422*VS, VLIN,THDOM(min) = 0.284*VS, VS = 7-18V, tBIT = 50us, DLIN,2 = tBUS-

REC(max)/(2*tBIT)

DLIN,2 - - 0.581 -

Duty cycle 31) V,LIN,THREC(max) = 0.778*VS, VLIN,THDOM(max) = 0.616*VS, VS = 7-18V, tBIT = 96us, DLIN,3 = tBUS-

REC(min)/(2*tBIT)

DLIN,3 0.417 - - -

Duty cycle 41) VLIN,THREC(min) = 0.389*VS, VLIN,THDOM(min) = 0.251*VS, VS = 7-18V, tBIT = 96us, DLIN,4 = tBUS-

REC(max)/(2*tBIT)

DLIN,4 - - 0.590 -

receive data baud rate*) high speed mode,VS = 13.5V

BLIN,RXD 115 kBd/s

transmit data baud rate*) high speed mode,VS = 13.5V

BLIN,TXD 115 kBd/s





LIN Failure detection and recovery

time out for TXD dominant clamping failure tLIN,TXD,DOM 10 ms

Auto addressing

Bus pull-up current source for auto-addressing VBUS = 0V ... 2.5V, VS >= VBUS + 6V

IPU,AA -2.26 -2.050 -1.84 mA

bus shunt resistor2) RSHUNT 0.5 - 1.25 Ω

temperature coefficient of bus shunt resistor*) TKSHUNT 0.376 0.4 % / K

AA trans-impedance amplifier input current range (current into LIN_S)

0V<VLIN_M<2.5V IAA_AMP -5 25 mA

Differential amplifier common mode input voltage range3)

VCMM_AMP 0.00 2.50 V

Offset voltage of the GAA amplification. This voltage is present at IN3 in AA-mode if the cur-rent into LIN_S is 0.

0V<VLIN_M<2.5VILIN_S = 0mA

VG_AA_0 440 550 660 mV

common mode error voltage,result of VG_AA_0(VLIN_M=0V) - VG_AA_0(VLIN_M=2.5V),to be calibrated via registerCAL_AA_CMRR to the value closest to 0

0V<VLIN_M<2.5VILIN_S = 0mA

VCMM_ERR_AMP -15 - 15 mV

Auto-Zero and settling time of the AA-amplifier after any change of the PU-configuration, not tested on ATE*) 4)

tBIT = 50 us tAA_SET - 1 - tbit

validity of the AA-amplifier output voltage after a tAA_SET cycle, not tested on ATE*) 4)

tBIT = 50 us tAA_MEAS 3 - 5 tbit

Trans-impedance of the RSHUNT - ADIFF combina-tion5)

0V<VLIN_M<2.5V125°C >=TJUNC >= 0°C

GAA_DIFF 45 - 95 V/A

0V<VLIN_M<2.5V-40°C <= TJUNC < 0°C

GAA_DIFF_LT 35 - 95 V/A

HS driver; pins OUT1-OUT4

RDSON at pin OUTn, normal VS range VS >= 5VVIN,n = H,VDD5 = 5V,IOUTn = -30 mA

RDSON,OUTn - 4 7.5 Ω

RDSON at pin OUTn, low VS range (low drop range)*)

VS < 5VVIN,n = H,programmed value of VDD5 = 5V,IOUTn = -30 mA

RDSON,OUTn_LD - 5 9 Ω

leakage current at pin OUTn VIN,n = 0 V,VOUTn = 0V

ILEAK,OUTn -50 -0.2 - nA

pull down resistor at pin OUTn VIN,n = L RPD,OUTn 50 100 kΩ





Sense pins SIN1-SIN4

Leakage current into Pins SIN1, SIN3 and SIN4 ifnot selected, no POR and no Testmode active

0V <= VSINx <= 5V, Channel SINx is not selected

ISINx,LEAK - 10 - nA

Leakage current into Pins SIN2, for voltages <= 3.3V if SIN2 is not selected, no POR and no Test-mode active

0V <= VSIN2 <= 3.3V,Channel SIN2 is not selected

ISIN2,LEAK,3V - 10 - nA

Leakage current into Pins SIN2, for voltages between 3.3V and 5V if SIN2 is not selected, no POR and no Testmode active

3.3 < VSIN2 <= 5V,Channel SIN2 is not selected

ISIN2,LEAK,5V - - 1.2 uA

Input resistance of Pin SINx if selected as MUXO input source

VSINx <= 5V, Channel SINx selected

RSINn,ACT 500 kΩ

Multiplexer; pin MUXO

Gain/attenuation of MUX_Channels SINx, x = 1...4, VDD3, VDDA

VSINx = 0.5 ... 5V AMX,SINx 0.49 0.5 0.51

Output Voltage Offset of MUX_Channels SINx, x = 1...4, VDD3, VDD(intern)

VSINx = 0.5 ... 5V VOFFSET,SINx,VDDA,V

DD

-25 25 mV

High Precision Output Voltage Accuracy of MUX_Channels SINx, x = 1...4, VDD3, VDD(intern)6)

VSINx = 0.5 ... 5V ACCHigh_MX,SINx,V

DDA,VDD

-5 5 mV

Gain/attenuation of MUX_Channels OUTx, x = 1...4 and VDD5

VOUTx,VDD5 = 2.5 ... 5V

AMX,OUTx,VDD5 0.435 0.444 0.453

Output Voltage Offset of MUX_Channels OUTx, x= 1...4 and VDD5

VOUTx,VDD5 = 2.5 ... 5V

VOFFSET, _OUTx,VDD5 -25 25 mV

High Precision Output Voltage Accuracy of MUX_Channels OUTx, x = 1...4 and VDD57)

VOUTx,VDD5 = 2.5 ... 5V

ACCHigh_MX,OUTx,V

DD5

-5 5 mV

delay of MUXO SPI-Write to Output*) MUX-Outputs 1...14, start at rising edge CSN

TMX,DEL 6 10 μs

Offset of the Multiplexer at VTEMP measurement*) MUX-Channel 10(0xA) selected

VOFF_VTEMP -5 5 mV

Gain/attenuation of MUX_Channel VS VS > 10V, MUX-Channel 13(0xD)selected

AMX,VS 0.120 0.130

Output Voltage Offset of MUX_Channel VS VS > 10V, MUX-Channel 13(0xD)selected

VOFFSET, _VS -50 50 mV

Analog Part

per FLASH IP standby (no access) current*) no FLASH access

IDDIO_FLASH_STBY 0.05 mA

per FLASH IP standby (no access) current*) no FLASH access

IDDC_FLASH_STBY 0.06 mA

per FLASH IP active read current*) FLASH read access

IDDIO_FLASH_READ 2.5 mA





per FLASH IP active read current*) FLASH read access

IDDC_FLASH_READ 7.5 mA

per FLASH IP program mode current*) FLASH program mode

IDDIO_FLASH_PROG 7.0 mA

per FLASH IP program mode current*) FLASH program mode

IDDC_FLASH_PROG 3.0 mA

per FLASH IP erase mode current*) FLASH erase mode

IDDIO_FLASH_ERASE 10 mA

per FLASH IP erase mode current*) FLASH erase mode

IDDC_FLASH_ERASE 3.0 mA

Fcore dependent SRAM access current*) IDDC_SRAM 0.08 mA/MHz

Fcore dependent digital core current*) IDDC_CORE 0.22 mA/MHz

Fcore independent fast digital modules current*) IDDC_FAST 1.92 mA

analog part supply current at VDDAincluding IADC_SUPPLY

8)typ.: ADC ON time < 1%max: ADC ON time = 100%

IDDA 1.5 5.5 mA

analog part supply current at VDDC*) IDDCA 0.65 mA

Core Supply Regulator

output voltage VDDC ADC VREFH trimmed

VOUT 1.74 1.8 1.86 V

output current (range)*) IOUT 0.5 25 mA

Power On Reset

power on threshold (monitors VDDA) VPOR 1.75 2.28 2.68 V

Brownout Detection

VDDIO OK Threshold (rising edge)

VDDIO_OK_RE 2.8 2.9 3.00 V

VDDIO Brown Out Threshold (falling edge)

VDDIO_OK_FE 2.7 2.8 2.90 V

VDDC OK Threshold(rising edge)

ADC VREFH trimmed

VDDC_OK_RE 1.45 1.55 1.65 V

VDDC Brown Out Threshold(falling edge)

ADC VREFH trimmed

VDDC_OK_FE 1.30 1.40 1.50 V

VDDIO_OK_RE - VDDIO_OK_FE(hysteresis)*

VDDIO_OK_HYST 50 100 200 mV

VDDC_OK_RE - VDDC_OK_FE(hysteresis)*

VDDC_OK_HYST 100 150 200 mV

System Clock RC Oscillator

output frequency calibrated FOSC_SYS 23 24 25 MHz

Watchdog Clock RC Oscillator

output frequency FOSC_WDOG 0.6 0.8 1 MHz

frequency temperature drift*) TCF_OSC_WDOG 200 ppm/K





NRST and NRSTD2D debouncer

nReset signal debounce timepulses shorter than TDEBOUNCE.min will be sup-pressedpulses longer than TDEBOUNCE.max will pass the debouncer*

tDEBOUNCE 3 5 8 us

SAR-ADC

reference low voltagesince the low reference is sensed at the VSSA pin internally small shifts due to bond wire, bond pad and package resistance have to be taken intoaccount.*)

VREFL 0 2 mV

bandgap derived reference high voltagemeasured at ADC reference buffer outputThe gain error will be digitally eliminated by an automatic gain and offset compensation logic.

ADC VREFH trimmed

VREFH 2.45 2.5 2.55 V

resolution (bit)*) N 12 Bit

conversion rateADC clock = system clock / 2*)

ADC clock = 12MHz

FCONV 0.86 MSample/s

differential non-linearity*) VREFL < VIN < VREFH

DNL -1 4 LSB

integral non-linearity*) VREFL < VIN < VREFH

INL -4 4 LSB

input capacitance*) CIN 3.8 4.8 5.8 pF

ON resistance of sample switch*) RIN 300 Ohm

Effective Number of Bits*) VREFL < VIN < VREFH

ENOB 10 10.5 Bit

sampling time (number of ADC clock cycles)see ADC_CTRL.SAMPLE_EXT for additional information*)

CYCLESSAMPLE 2

conversion time (number of ADC clock cycles)*) CYCLESCONVER

T

12

ADC supply current ADC ON time = 100%

IADC_SUPPLY 3.0 3.5 mA

ADC warm-up time between ADC standby and run mode*)

tWARM-UP 1 us

ADC standby mode supply current ADC in standby mode

IADC_STANDBY 0.2 0.3 mA





ADC Multiplexer

on resistance RON - 400 700 Ohm

temperature sensor voltage(ADC channel 3)

T = 25°C VT 1.50 1.55 1.60 V

VT temperature coefficient TCVT -3.3 mV/K

IO Port Characteristics

IO Supply Voltage (driving to external)*) VDDIO 3.0 3.3 3.6 V

Schmitt-Trigger Low to High Threshold Point no pull down or pull up enabled

VTP - - 2.0 V

Schmitt-Trigger High to Low Threshold Point no pull down or pull up enabled

VTN 0.8 - - V

pad leakage current when IO is not driven (outputis HI-Z) and pull is disabled

VO = 3.3V or 0V IOZ -1000 1000 nA

Pull Up Resistor pull up enabledVIN = 0V

RPU 30 48 74 kOhm

Pull Down Resistor pull down enabledVIN = 3.3V

RPD 29 47 86 kOhm

Low Level Output Voltage with smaller (4mA) driver strength.

IIO = 4mA VOL_4 0.4 V

Low Level Output Voltage with higher (8mA) driver strength.

IIO = 8mA VOL_8 0.4 V

High Level Output Voltage with smaller (4mA) Driver Strength.

IIO = -4mA VOH_4 2.4 V

High Level Output Voltage with higher (8mA) Driver Strength.

IIO = -8mA VOH_8 2.4 V

NRST pad Schmitt-Trigger Low to High ThresholdPoint

NRST_VTP - - 1.2 V

NRST pad Schmitt-Trigger High to Low ThresholdPoint

NRST_VTN 0.50 - - V

LIN-SCI Module (SCI)

value of accuracy of the byte field detection*) tBFS 1/16 2/16 TBIT

earliest bit sample timetEBS <= tLBS

*)tEBS 7/16 TBIT

latest bit sample timetEBS <= tLBS

*)tLBS 10/16 -

tBFS

TBIT





HV Control Module (HV_CTRL)

bit duration time = 1 / baudrate*)9) TB 80 250 5000 ns

CSB falling to SCK rising*) T1 TB/2 -10

TB/2 +10

ns

SCK falling to CSB rising*) T2 TB/2 -10

TB/2 +10

ns

SCK rising to MOSI delay*) T3 10 ns

CSB high time*) T4 TB ns

MISO setup time*) TS 10 ns

MISO hold time*) TH 10 ns*) Not production tested1) for definition of tBIT see figure Figure 6.3.3.1-1, bus load conditions (CLIN,RLIN): 1nF,1kΩ / 6.8nF,660Ω / 10nF,500Ω2) TKSHUNT is contained in this value range3) Operation outside of common mode and/or differential input voltage range will not result in damage, but will produce invalid results on the differential amplifier's output.4) for definition of tBIT see figure Figure 6.3.3.1-1,5) the total transimpedance of auto-addressing path is determined by RSHUNT and ADIFF, range of the parameter dominated by the TKSHUNT6)

ACCHigh_MX,SINx,VDDA,VDD = VMX - ACAL_MX,x * Vx - OffsetCAL_MX,x, VDD3,VDD respectively; for high precision absolute voltage measurements EOL calibration is required7) ACCHigh_MX,OUTx,VDD5 = VMX - ACAL_MX,OUTx * VOUTx - OffsetCAL_MX,OUTx,VDD5 respectively; for high precision absolute voltage measurements EOL calibration is required8) Can only be measured on wafer test since VDDA and VDDIO are bonded to the same lead-finger on the package.9) to be set via register SPI_CONFIG , typical value is recommended to be used in application

Notes on table section Multiplexer; pin MUXOCalibration for High Precision Absolute Voltage Measurements:

1. Choose 2 input voltage values VIN_A and VIN_B, which are inside or at the borders of the desired measurement range ot the channel to be calibrated. These sample voltages should not be to close to each other to minimize the influence of random measurement errors.

2. Measure and store GAIN:ACAL_IN=VMX(VIN_B)-VMX(VIN_A))/(VIN_B-VIN_A)

3. Measure and store OFFSET:OffsetCAL_MX,IN=VMX(VIN_A)-ACAL_IN*VIN_A

4. Use the stored GAIN and OFFSET in the application to calculate the measured quantity value from the ADC output.




6 Functional Description

6.1 OverviewThe device E521.31 is a LIN controller system. It is realized as a dual die system consisting of a controller part and an anlaog high-voltage part. In the following description the analog part is called "HV-Part" and the microcontroller part is called "Microcontroller"

The "HV-Part" consists of 5V / 100mA and 3.3V / 35mA voltage regulators, LIN transceiver with autoaddressing feature and four 5V-highside drivers to supply externally connected loads with current up to 50mA each.

The "Microcontroller" part provides a 16bit microcontroller with two independed 32k Byte Flash memory blocks and many peripheral blocks explained in the according sub chapters.For temperature compensation the device provides an integrated temperature sensor.

The two parts are internally connected by inter-die bonds. System management between analog and microcontrol-ler part is done by SPI connection. The block diagram below shows details.

Figure 6.1-1: Block Diagram



Internalvoltage

regulators

LDO (voltage regulator)

5V/100mA 2%

uController32kByte FLASH

1kByte RAM

4x 16bit PWM

Timer

ADC12bit1us

LINUART

LIN transceiverwith autoaddressing

GPIO

ADCMUX

Temp.sensor

JTAGdebug IF

Powermanagement

E521.30

SPI-Interface

Status/Config-Registers

32kByteFlash

1.8Vcore VR

Watchdog

E521.99

IN1

IN2

IN3

IN4

RX

DT

XD

MUXOCS

N

SD

IS

CK

E521.31

TM

OD

E

interface

VSGND

VDD3

VDDuC

VDDC DGND

NRST

VDD5

OUT1 OUT2 OUT3 OUT4

LIM_M LIN_GND LIN_S

SIN1 SIN2 SIN3 SIN4

IO5 IO4 IO3 IO2

IO1 IO0 TMODE


6.2 uC analog Supply, pin VDDuC

The IC-pin VDDuC corresponds to the internal microcontroller pin VDDA in Section 7.4. (for parameters see 5.3.1).

6.3 Design Description HV-Part

6.3.1 Voltage Regulator 5V; pin VDD5

The primary on chip low drop voltage regulator provides a typical voltage of 5V at pin VDD5. It supplies the LED-drivers with up to 150mA. Its output is current limited to typical 240mA. The current limitation is always activated.

The scaled output voltage of this regulator can be measured via the pin MUX if correctly configured by SPI.

The output voltage of this regulator can be adjusted in a wide range via SPI even during operation in order to matchthe requirements of the connected LEDs.

After power up or remote wake up the regulator is activated. Setting the bit SLEEP in the SPI register POWER to high, the device is switched into the very low power mode and the regulator is switched off.

6.3.2 Voltage Regulator 3.3V ; pin VDD3

The second on chip low drop voltage regulator provides a voltage of 3.3V at pin VDD3. It supplies the uC and the digital IOs with up to 35mA. Its output current is limited to typical 60mA. The current limitation is always activated. Itis not recommended to apply the maximum load current at pin VDD3 during start up or activation continuously.After power up or remote wake up regulator is activated. Setting bit SLEEP in SPI register POWER to high sets th device into very low power mode and the regulator is switched off.

6.3.3 LIN Transceiver; pins LIN_M, LIN_S, TXD, RXD, GND

6.3.3.1 CharacteristicsThe LIN BUS physical interface is implemented as a LIN 2.2 standard high-voltage single wire interface (ISO 9141) for baud rates from 2.4kBds to 20.4kBds. The LIN BUS Interface can be operated in Master or Slave Mode. The LIN bus has two logical values; the dominant state (BUS voltage near GND) represents logical LOW level and the recessive state (BUS voltage near VS) represents logical HIGH level. In the recessive state the BUS is pulled high by an internal pull-up resistor (typ. 30 kΩ) and a diode in series, so no external pull-up components are required forslave applications. Master applications require an additional external pull-up resistor and a series diode. The LIN protocol output data stream on the TXD signal is converted into the LIN bus signal through a current limited, wave-shaping low-side driver with control as outlined by the LIN Physical Layer Specification Revision 2.2. The receiver converts the data stream from the bus and outputs it to RXD.




Figure 6.3.3.1-1: LIN 2.2 physical layer timing

The LIN transceiver can handle a bus voltage swing from +40V down to ground and survives -27V. The device alsoprevents back feed current through the LIN pin to the supply pin in case of a ground shift / loss or supply voltage disconnection.In sleep mode the LIN block requires a very low quiescent current by using a special wake up comparator allowing the remote wake up via the LIN bus. The sleep mode can be activated during recessive or dominant level of the LIN bus line.

To receive and transmit data via LIN transceiver must be activated. Therefore bit LIN_CFG.tr must be set to H. Set-ting bits POWER.sleep or POWER.STANDBY to H sets LIN_CFG.TR to L.If LIN_CFG.tr is L the transceiver can detect wake ups.

6.3.3.2 LIN High Speed ModeThe device supports a LIN high speed mode. This mode allows an increasing of the transmit and receive baud rate up to 115 kBdsTo enter this mode see register LIN_CFG.




6.3.3.3 LIN Wake UpThe device can be woken up remotely via pin LIN. The wake up capability is enabled in low power states only (see register LIN_CFG).A falling edge at the LIN pin followed by a dominant bus level VLIN,DOM maintained for a time period tLIN,WU, ended by a rising edge results in a remote wake up request. The request is signalized via driving pin RXD to low. Setting bit LIN_CFG.TR to H clears wake up.

Figure 6.3.3.3-1: LIN wake up at rising edge if VDD3 is off

6.3.3.4 LIN Failure detection and recoveryThe device provides a failure detection for TXD dominant clamping. If TXD is clamped for tLIN,TXD,DOM to dominant thetransmitter is disabled. If TXD is released the failure is cleared and the transmitter is enabled again.




6.3.4 Auto addressing

The device supports auto addressing feature using the bus shunt method. This feature can be used optional. If it is not used the pin LIN_S has to be kept open or connected to pin LIN_M. In this case the device behaves like a standard LIN transceiver.

The auto addressing feature added to the normal LIN bus functionality allows that slaves detect their relative posi-tion within a bus system. The hardware extensions needed for that purpose are a shunt resistor between nodes LIN_M and LIN_S, a pull-up current source of typically 2mA and a circuitry that allows to measure the differential voltage over the shunt resistor. The slaves within such a bus system have to be connected as a daisy-chain. The following diagram shows such a bus architecture:

To enable the auto addressing feature, set bit onamp in registerLIN_AA to high as well a bit tr in register LIN_CFG. The internal LIN pull up resistor can be controlled by bit on30k in registerLIN_AA. The integrated 2mA current source can be controlled by bit on2ma in registerLIN_AA.The voltage difference across the shunt is amplified to a single ended voltage and can be observed at pin MUXO when selected by setting register ADC_MUX to 0x01.

Figure 6.3.4-1: single_BSM_AA_principle

Principle of a Single LIN-Slave with BSM Auto Addressing




Bus

V_in

Diode

R_Shunt

ADCADCADC

Pul

l-Up

I_LI

N_C

S

I_LI

N_C

S

I_LI

N_C

S

R_L

IN_P

U

R_L

IN_P

U

R_L

IN_P

U

0 to 5 Standard Transceiver

Diode

Slave n+1ECU Slave n - 1 Slave n

R_Shunt R_Shunt

R_M

aste

r

DiodeDiode - + - + - +

Figure 6.3.4-2: LIN Bus auto addressing architecture

On the left side of the schematic the ECU is terminating the LIN bus. Next there is a group of addressable slaves, each of them having its own auto-addressing circuitry. Finally, shown on the right side of the schematic, there may be some standard LIN bus transceivers without auto-addressing capability. As well they may be mixed up with the addressable slaves in any possible position.

The start of the addressing sequence is initialized by the ECU, with a command sent to the slaves telling them that the addressing sequence starts with the next break field. During the next break field each slave starts its sequence.The sequence is divided up in measuring the offset current on the bus line, measuring the bus load and, dependingon the bus load, switching on the current source for the detection of the last not addressed slave in the line.It is recommended to use a threshold value of 1 mA for the decision in the following flow chart. This give the max-imum noise immunity to the low value (0 mA) and the high value (2 mA if only one other slave is behind).




All slavesdetect break field

All addressable slavesswitch off 30kW LIN pullup

Slave alreadyaddressed ?

Measure bus current ISHUNT1

All not addressed slavesswitch on 30kW LIN pullup


Calculate differenceIDIFF21

= ISHUNT2

- ISHUNT1

IDIFF21 > threshold ?

All not addressed slavesswitch on 2mA pullup source


Calculate differenceIDIFF31 = ISHUNT3 - ISHUNT1

IDIFF31

> threshold ?

Slave saves address containedin autoaddressing command

All slaves switch off2mA pullup source and

switch on 30kW LIN pullup

Master sends autoaddressingcommand

Masterchecks: all slaves

addressed ?

START

STOP

Switch off 30kW LIN pullup,wait for end of procedure

Y

N

N

N

N

Y

Y

Y

Step 1

Step 2

Step 3

Step 4

Step 5

Step 6

Step 7

Figure 6.3.4-3: Flowchart auto addressing process




In order to assure that the different steps of the auto-addressing sequence are executed synchronously by all the slaves, a timing scheme for the break field is defined. The time reference is the bit time tBIT,SLAVE. The following tim-ing diagram shows the requested timing for the different steps executed during the break field.

Figure 6.3.4-4: Timing diagram auto addressing process




6.3.5 HS driver; pins OUT1-OUT4

The LED HighSideDriver switches the VDD5 voltage to the pins or disconnects these pins from VDD5 to open cir-cuit. The driver must be activated via SPI. The driver is controlled via pins INx.To prevent a gleaming LED if the driver is switched off, a pull down resistor can be switched on.For minimising EMC the slewrate of the driver can be limited internaly.The configuration is done in register LED_DRIVER.

6.3.6 Sense pins SIN1-SIN4

Pins SIN1-SIN4 can be used to sense external voltages up to 5V. The intented application is to measure the for-ward voltages of the LEDs. The attenuated voltage is shown at pin MUXO if the required channel is selected in the SPI register ADC_MUX.

6.3.7 SPI; pin SCK, CSN, SDI

Figure 6.3.7-1: spi data

Figure 6.3.7-2: spi timing

Table 6.3.7-1: RegisterTable

Register Name Address Description

ADC_MUX 0 ADC multiplexer channel selection

LIN_AA 1 configuration of LIN AA

LIN_CFG 2 configuration of LIN

LED_DRIVER 3 configuration of LED driver

POWER 4 selection of power modi

CAL_I5U 5 calibration data of internal current reference

CAL_5V 6 calibration data of external 5 V regulator

CAL_AA_CMRR 7 calibration of auto addressing amplifier common mode rejection




Table 6.3.7-2: Register ADC_MUX (0)

MSB LSB

Content mux_sel[3] mux_sel[2] mux_sel[1] mux_sel[0]

Reset value 0 0 0 0

Access W W W W W

Bit Description mux_sel[0] : 0:no channel selected1:VDIFF (LIN AA amplifier)2:OUT03:OUT14:OUT25:OUT36:SIN07:SIN18:SIN29:SIN310:VTEMP11:VDD312:VDD513:VS14:VDDA15:VBG

Table 6.3.7-3: Register LIN_AA (1)

MSB LSB

Content enaaz - on30k on2ma onamp

Reset value 0 0 0 0 0

Access - - W W W

Bit Description enaaz : enable autozero (mandatory to be set during auto addressing)on30k : enables pull up resistoron2ma : enables 2 mA current sourceonamp : enables LIN AA amplifier

Table 6.3.7-4: Register LIN_CFG (2)

MSB LSB

Content - - TR - HS


Access W W

Bit Description TR : transmitter enable0..wake up1..transmit & receiveHS : high speed mode




Table 6.3.7-5: Register LED_DRIVER (3)

MSB LSB

Content - ena pull slew


Access W W W

Bit Description ena : high-side driver enablepull : enables usage of driver pull-down resistance0 : pull-down resistance is not used1 : pull-down resistance is automaticaly enabled when high-side driver is offslew : configures driver slew rate0 : without slew rate limiting1 : with slew rate limiting

Table 6.3.7-6: Register POWER (4)

MSB LSB

Content vddd ioff - standby sleep


Access W W - W W

Bit Description vddd : use internal 3.3 V for LIN transmitterioff : switch off sink current from VDD3standby : system standby mode activation; LED & LIN are offsleep : system sleep mode activation; V3 & V5 are off

Table 6.3.7-7: Register CAL_I5U (5)

MSB LSB

Content - I5U[3:0]

Reset value 0 X

Access W W

Bit Description I5U[3:0] : trim value for internal current reference master

Table 6.3.7-8: Register CAL_5V (6)

MSB LSB

Content TR5V[4:0]

Reset value X

Access W

Bit Description TR5V[4:0] : Trimvalue for 5V voltage regulatr

Table 6.3.7-9: Register CAL_AA_CMRR (7)

MSB LSB

Content - TR_AACMRR[3:0]

Reset value 0 X

Access W W

Bit Description TR_AACMRR[3:0] : trimvalue of AA common mode rejection




6.3.8 Multiplexer; pin MUXO

Table 6.3.8-1: multiplexer output

adc_mux source relation

1 VDIFF 1:1

2 OUT1 4:9

3 OUT2 4:9

4 OUT3 4:9

5 OUT4 4:9

6 SIN1 1:2

7 SIN2 1:2

8 SIN3 1:2

9 SIN4 1:2

10 VTEMP 1:1

11 VDD3(3V3) 1:2

12 VDD5(5V) 4:9

13 VS 1:8

14 VDDA/VDDD 1:2

15 VBG 1:1

The pin MUXO provides access to several internal and functional voltages. The selection is done in the SPI registerADC_MUX. A resistor network at the inputs attenuates higher voltages to the maximum VMX,LIM. The physical gain ofthe MUX-Buffer channel 1 (VDIFF) is 2, however, this factor is already included in parameter GAA_DIFF and GAA_DIFF_LT.




6.4 Design Description Microcontroller

Figure 6.4-1: Functional Diagram




6.4.1 Analog Part

Figure 6.4.1-1: Analog Block Diagram

The block diagram above shows eFlash1 and eFlash2 which represent the 2 embedded FLASH IPs.One can be used as customer FLASH area. The second is divided into BOOT ROM area and EEPROM emulation area.

The analog part of 521.99 consists of the ADC, the power watch and required reference voltages and currents.The block diagram shows the general concept of the analog part.

The ADC input is connected via a multiplexer to the pins AIN0, AIN1 and AIN2.• pin AIN0 is located at the Die-To-Die boundary• pins AIN1 and AIN2 are analog input paths on IO4 and IO5 external input pads




6.4.1.1 Internal ReferencesThe internal reference voltages and accurate currents are derived from a bandgap reference. All currents required during startup are generated by a self-biasing current generator which cannot be calibrated.

6.4.1.2 Core Supply RegulatorThe regulator generates the digital core voltage VDDC from VDDIO. It receives an internal 1.8V reference voltage derived from the bandgap voltage and regulates with it the digital core voltage VDDC.The external Buffer Capacitance CDDC is connected to the output.

6.4.1.3 Oscillators and ResetOscillators:• System Clock RC Oscillator• Watchdog Clock RC Oscillator

System Reset Sources:• Power ON reset• Power watches for brownout detection• Reset inputs (device pin)• Several digital core exceptions• For details see SYS_STATE module RESET_STATUS and RESET_ENABLE registers.

6.4.1.3.1 Power On ResetThe Power-On-Reset is connected to the VDDA Power Supply.Its main purpose is to reset the level shifter from the VDDC to VDDIO voltage domain.

• The Power-On-Reset will assert a system reset on system start-up

6.4.1.3.2 Brownout DetectionThere are two Brown-Out watches:• one for the VDDIO voltage• one for the VDDC voltage

Since VDDIO is bonded onto the same pin as VDDA in current targeted applications the brown-out effectively mon-itors VDDA and VDDIO voltage for outages.In case the device will be used in an application where the two pins will be supplied by independent power suppliesno reset may be generated if the vdda supply fails!

• VDDC brownout will cause a System Reset when VDDC falls below brownout (VDDC_OK_FE) level• VDDIO brownout will cause a System Reset when VDDIO falls below brownout (VDDIO_OK_FE) level

6.4.1.3.3 System Clock RC OscillatorThis oscillator clocks the digital system.

6.4.1.3.4 Watchdog Clock RC OscillatorThe oscillator is used to clock a part of the digital watchdog module.

6.4.1.3.5 NRST and NRSTD2D debouncerNRST and NRSTD2D low active reset input signal debouncer - prevents system from reset by short spikes.




6.4.1.4 SAR-ADCThe pin AIN is the input to a single ended SAR ADC with a resolution of 12 Bits and at least an effective number of 10 Bits. The ADC has a single high reference voltages of 2.5V derived from the bandgap voltage reference. The low reference voltage is fixed to VSSA.

6.4.1.5 ADC MultiplexerThe ADC multiplexer is switching one of 4 input signals (AIN0, AIN1, AIN2, VT) to the ADC input.

6.4.1.6 IO Port Characteristics

The following analog inputs are implemented:• AIN0 : located at the Die-To-Die side• AIN1 : external analog input shared with digital IO4• AIN2 : external analog input shared with digital IO5• supported analog input voltage range corresponds to ADC input voltage range (0-2.5V)

6.4.2 Digital Part

6.4.2.1 Base Addresses (Memory Map)

Table 6.4.2.1-1: Address Table

base address size module name instance name description

0x8000 0x8000 FLASH_MAIN FLASH_MAIN FLASH Memory Instance 1 (Customer Instruction Memory)

0x2800 0x5800 FLASH_EE FLASH_EE FLASH Memory Instance 2 (may be used to imple-ment an EEPROM Emulation)

0x1000 0x1800 SYS_ROM SYS_ROM System ROM Memory

0x0C00 0x0400 SRAM SRAM SRAM Memory

0x0640 0x40 FLASH_CTRL FLASH_EE_CTRL

FLASH (EEPROM Emulation) Control Module

0x0600 0x40 FLASH_CTRL FLASH_CTRL FLASH Control Module

0x0480 0x40 HV_CTRL HV_CTRL Analog Part Controller Module

0x0440 0x40 PWM PWM PWM Module

0x0400 0x40 ADC_CTRL ADC_CTRL ADC Control Module

0x0240 0x40 CCTIMER CCTIMER CCTIMER Module

0x0200 0x40 GPIO GPIO GPIO Module

0x01C0 0x40 SCI SCI LIN SCI Module

0x0180 0x40 SYS_STATE SYS_STATE System State Module

0x0140 0x40 DIVIDER DIVIDER Divider Module

0x0100 0x40 H430_MUL H430_MUL H430 Multiplier Module

0x00C0 0x40 TIMER TIMER Timer Module

0x0080 0x40 WDOG WDOG Watchdog Module

0x0040 0x40 VIC VIC Vector Interrupt Controller Module

0x0000 0x40 ROM ROM Start-up ROM




6.4.2.2 Memory IPs6.4.2.2.1 FLASHThe micro controller system includes 2 instances of a FLASH IP which are mapped into the address space as defined by the above Memory Map Table.Each FLASH IP block consists of to logical blocks: a large one which is called MAIN block and a small one which iscalled INFO block. MAIN and INFO block cannot be accessed at the same time. A FLASH mode change is requiredto do this. Each FLASH instance is controlled by its own FLASH_CTRL module. These two FLASH_CTRL modulesimplement the same functionality and are mapped to different module base addresses. Pleas see above Memory Map Table.

• FLASH instance 1:• FLASH_MAIN area size: 32K byte

• FLASH instance 2:• FLASH_EE area size: 22K byte• SYS_ROM area size: 6K byte (read only by CPU, write possibility via JTAG)• the partitioning of FLASH instance 2 (28K byte) into System ROM and FLASH_EE may vary depending on

customer requirements and is flexible configurable using FLASH control area protection registers. This config-uration has a granularity of 2K byte.

• both FLASH instances include a 6 bit ECC per 16 bit data -> Hamming distance 4• SEC-DED logic (single error correction - double error detection)• FLASH IP geometry:• 32K byte = 8K x 32 (44) bit• MAIN block: 64 pages• INFO block: 2 pages• 1 page = 128 x 32 (44) bit = 4 rows• 1 row = 32 x 32 (44) bit

SYS_ROM - System ROM MemoryThis memory region is set up during System ROM boot to be write protected by use of FLASH_CONTROL area protection registers.The System ROM content may vary depending on customer requirements and may contain for example:• a standard ELMOS boot loader• a customer specific boot loader delivered by ELMOS• a customer boot loader

6.4.2.2.2 SRAM• size: 1K byte• byte write support• per byte parity protection




6.4.2.3 System Start-upThe digital system start up is done as follows:

• the CPU executes the ROM start up code which checks the FLASH INFO memory for a valid boot vector• if a valid FLASH INFO memory boot vector exists:• the CPU executes the FLASH INFO memory start up code which usually is used to initialize the micro con-

troller analog part calibration registers as well as the analog IC calibration data. The calibration data usuallyis included in the FLASH INFO memory code.

• if the power ON reset (POR) or watchdog flag is set the CPU checks for System ROM boot loader vector• if a valid System ROM boot loader vector exists, this vector will be called and the System ROM boot

loader code will be executed• if set, the watchdog flag has to be handled by System ROM boot loader code !• the CPU returns to INFO boot code, clears the power ON reset (POR) flag and does a software reset

which reboots the device• if the power ON reset (POR) and watchdog flag are not set the CPU checks for System ROM post boot

loader vector• if a valid System ROM post boot loader vector exists, this vector will be called and System ROM post

boot loader code will be executed• the System ROM area protection has to be handled by System ROM post boot loader code !• the CPU returns to INFO boot code

• the CPU returns to ROM start up code• the CPU switches to FLASH MAIN memory area access• the CPU fetches the user program reset vector which is located at address 0xFFFE in the FLASH MAIN

memory which also enables the JTAG interface for CPU debugging• the CPU starts executing the user programNote: the System ROM boot loader vector address is 0x1000, the post boot loader vector address is 0x1002Note: a valid System ROM vector address has to be even (bit 0 = 0) and has to be smaller than 0x8000Note: the FLASH INFO memory start up code area is only visible during ROM start up code execution and will not be accessible during user program execution.

Boot code flow chart:




Figure 6.4.2.3-1: boot code flow chart




6.4.2.4 CPU - H430Features• 16 bit CPU• MSP430 binary code compatible• Harvard architecture with AHBL data and instruction bus interfaces• RISC architecture with 27 instructions and 7 addressing modes• Orthogonal architecture: every instruction usable with every addressing mode• Full register access including program counter, status registers, and stack pointer• 16 x 16-bit register• 64 KByte linear address space• 16-bit native data bus width• Constant generator provides six most used immediate values and reduces code size• Direct memory-to-memory transfers without intermediate register holding• Word and byte addressing and instruction formats• IAR development IDE compatible JTAG debug interface• Several C compilers are available

Figure 6.4.2.4-1: H430 Environment Example




InterruptsThe embedded H430 IP core does not contain a primary interrupt controller. It has only a IRQ request signal and an address, pointing to a vector table in memory, which contains addresses of the interrupt handlers.Therefore the H430 IP does not support a fixed number of interrupts. Any number fitting reasonable in the 64k memory range is supported.All interrupts can be enabled or disabled with the GIE bit in the status register.

Handling an interrupt (other than RESET) consists of:• Push PC on stack.• Push SR on stack.• Choose the highest priority interrupt to service.• If there are multiple possible sources, leave them for software to poll.• Clear the SR, which disables interrupts and power-saving.• Fetch the interrupt vector into the PC• Start executing the interrupt handlerA reset is similar, but doesn't save any state.

You can nest interrupt handlers by disabling the current source and setting the GIE bit back to 1.

Byte and Word IssuesThe H430 is byte-addressed, and Little-Endian. Word operands must be located at even addresses.Most instructions have a byte/word bit, which selects the operand size. Appending ".B" to an instruction makes it a byte operation. Appending ".W" to an instruction, to make it a word operation, is also legal. However, since it is alsothe default behavior, if you add nothing, it is generally omitted.A byte instruction with a register destination clears the high 8 bits of the register to 0. Thus, the following would clear the top byte of the register, leaving the lower byte unchanged:

MOV.B Rn,Rn

Mostly the on-chip peripherals supports only one bus size, e.g. the data width of the processor. These peripherals must be accesses only with the supported access mode and with correct alignment. Any other access may producean undefined behavior.When performing a word access, address bit 0 is undefined and has to be ignored.

CPU StatesThe CPU supports the following states:

Table 6.4.2.4-1: CPU States

state description

RUN • normal operation of the CPU• the CPU accesses program storage (e.g. Flash) and RAM• the CPU returns to RUN state on any interrupt

STANDBY • the CPU is halted• the STANDBY state is entered when setting standby flag (CPUOFF) in status register• the CPU does not access program storage or RAM• the CPU returns to RUN state on any interrupt




CPU Standby EntryAfter setting the standby bit in the CPU status register the following instruction will be executed, then standby modewill be entered. A good idea is to use the following sequence to ensure a later wake up.

BIS #0x18, SR ; sets standby flag and enables interrupts for wake upNOP ; needed for correct standby entry behavior

CPU Standby Exit• an interrupt will force the CPU to exit the standby mode. The CPU will enter the interrupt service routine directly.• after the interrupt routine has been finished the CPU will NOT return to previous standby mode.• a system reset (e.g. by the watchdog) will restart the device and therefore exit the standby mode.

6.4.2.4.1 CPU RegistersThe processor has 16 16-bit registers, although only 12 of them are truly general purpose. The first four have ded-icated uses:

6.4.2.4.1.1 Program Counter (PC)The 16-bit Program Counter (PC/R0) points to the next instruction to be executed. Each instruction uses an even number of bytes (two, four, or six), and the PC is incremented accordingly. Instruction accesses in the 64-KB address space are performed on word boundaries, and the PC is aligned to even addresses. The PC can be addressed with all instructions and addressing modes.

6.4.2.4.1.2 Stack Pointer (SP)The Stack Pointer (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a pre-decrement, post-increment scheme. In addition, the SP can be used by software with all instructions and addressing modes. The SP is initialized into RAM by the user, and is aligned to even addresses.

6.4.2.4.1.3 Status Register (SR)The Status Register (SR/R2), used as a source or destination register, can be used in the register mode only addressed with word instructions. The remaining combinations of addressing modes are used to support the con-stant generator.

Table 6.4.2.4.1.3-1: Register Table


Status Register SR/R2

Table 6.4.2.4.1.3-2: Register Status Register (SR/R2)

MSB LSB

Content - - - - - - - 8 - - 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R R R R R R

Bit Description 8 : V5 : OSC OFF4 : CPU OFF3 : GIE2 : N1 : Z0 : C




V: Overflow bitThis bit is set when the result of an arithmetic operation overflows the signed-variable range.

OSCOFF: Stop flagOSCOFF (oscillator off), and CPUOFF are used to enter low-power states. OSCOFF may not be evaluated by the system if other clock controllers are implemented

CPUOFF: Standby flagSee "CPU States" for details

GIE: Global Interrupt EnableGIE is the global interrupt enable. Turning off this bit masks interrupts. (NOTE: it may be delayed by 1 cycle, so an interrupt may be taken after the instruction after GIE is cleared. Add a NOP or clear GIE one instruction earlier thanyour "critical section".)

N: Negative bitThis bit is set when the result of a byte or word operation is negative and cleared when the result is not negative.Word operation: N is set to the value of bit 15 of the resultByte operation: N is set to the value of bit 7 of the result

Z: Zero bitThis bit is set when the result of a byte or word operation is 0 and cleared when the result is not 0.

C: Carry bitThis bit is set when the result of a byte or word operation produced a carry and cleared when no carry occurred.

6.4.2.4.1.4 Constant Generation Registers (CG1 / CG2)Six commonly-used constants are generated with the constant generator registers R2 and R3, without requiring an additional 16-bit word of program code. This is one of the important features of the H430 instruction set, allowing it to achieve a high level of code density, and a flexible instruction set.These constant registers can provide the numbers -1, 1, 2, 4 or 8. So, for example, the "CLR x" is actually emu-lated by the instruction "MOV #0,x". The constant "0" is taken from the constant register r3. The assembler under-stands both "CLR x" and "MOV #0,x", and produces the same code for either.The constants are selected with the source-register addressing modes (As):

Table 6.4.2.4.1.4-1: Register Table

Register As Value Remarks

R2 00 - register mode (access R2)

R2 01 (0) used for absolute address mode

R2 10 0x0004 constant +4


R3 00 0x0000 constant 0



R3 11 0xFFFF constant -1




The constant generator advantages are:

• No special instructions required• No additional code word for the six constants• No code memory access required to retrieve the constantThe assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand. Registers R2 and R3, used in the constant mode, cannot be addressed explicitly; they act as source-only registers.

6.4.2.4.1.5 General Purpose Registers (R4 - R15)The twelve registers, R4-R15, are general-purpose registers. All of these registers can be used as data registers oraddress pointers and can be used with byte or word instructions.

6.4.2.4.2 Addressing ModesThe available H430 instruction addressing modes have at most two operands, a source and a destination.All instructions are 16 bits long, followed by at most two optional offsets words, one for each of the source and the destination.

As Modes

The source operand is specified with 2 addressing mode bits (As):

Table 6.4.2.4.2-1: As Modes

As mnemonic remarks

00 Rn Register direct

01 X(Rn) Register indexed

10 @Rn Register indirect

11 @Rn+ Register indirect with post-increment

Ad Modes

The destination operand is specified with 1 addressing mode bit (Ad):

Table 6.4.2.4.2-2: Ad Modes

Ad mnemonic remarks

0 Rm Register direct

1 Y(Rm) Register indexed

The only addressing mode that uses an extension word is the indexed mode.The destination operand in a two-operand instruction has only one addressing mode bit, which selects either register direct or indexed. Register indirect can obviously be faked up with a zero index.When r0 (the program counter) is used as a base address, indexed mode provides PC-relative addressing. This is, in fact, the usual way that the H430 assembler accesses operands when a label is referred to.@r0 just specifies the following instruction word, but @r0+ specifies that word and skips over it. In other word, an immediate constant! You can just write #1234 and the assembler will specify the addressing mode properly.r1, the stack pointer, can be used with any addressing mode, but @r1+ always increments by 2 bytes, even on a byte access.




Table 6.4.2.4.2-3: Addressing Modes Table

As/Ad Addressing Mode Syntax Description

00/0 Register mode Rn Register contents are oper-and

01/1 Indexed mode X(Rn) (Rn + X) point to the oper-and. X is stored in the next word.

01/1 Symbolic mode ADDR (Rn + X) point to the oper-and. X is stored in the next word. Indexed mode X(PC) is used.

01/1 Absolute mode &ADDR (Rn + X) point to the oper-and. X is stored in the next word. Indexed mode X(0) isused.

10/- Indirect Register mode @Rn Rn is used as a pointer to the

11/- Indirect auto increment @Rn+ Rn is used as a pointer to the operand. Rn is incre-mented afterwards by 1 for .B instructions and by 2 for .W instructions

11/- Immediate mode #N The word following the instruction contains the immediate constant N. Indirect auto-increment mode @PC+ is used.

Register Direct

Table 6.4.2.4.2-4: Register Direct

Assembler Code MOV R10,R11

Length One or two words

Operation Move the content of R10 to R11. R10 is not affected.

Comment Valid for source and destination

Note The data in the register can be accessed using word or byte instructions. If byte instruc-tions are used, the high byte is always 0 in the result. The status bits are handled accord-ing to the result of the byte instruction.




Register Indexed

Table 6.4.2.4.2-5: Register Indexed

Assembler Code MOV 2(R5),6(R6)

Length Two or three words

Operation Move the contents of the source address (contents of R5 + 2) to the destination address (contents of R6 + 6). The source and destination registers (R5 and R6) are not affected. In indexed mode, the program counter is incremented automatically so that program execu-tion continues with the next instruction.

Comment Valid for source and destination

Register Indirect

Table 6.4.2.4.2-6: Register Indirect

Assembler Code MOV @R10,0(R11)


Operation Move the contents of the source address (contents of R10) to the destination address (contents of R11). The registers are not modified.

Comment Valid only for source operand. The substitute for destination operand is 0(Rd).

Register Indirect with post increment

Table 6.4.2.4.2-7: Register Indirect with post-increment

Assembler Code MOV @R10+,0(R11)


Operation Move the contents of the source address (contents of R10) to the destination address (contents of R11). Register R10 is incremented by 1 for a byte operation, or 2 for a word operation after the fetch; it points to the next address without any overhead. This is useful for table processing.

Comment Valid only for source operand. The substitute for destination operand is 0(Rd) plus second instruction INCD Rd.




6.4.2.4.3 Instruction SetThe complete H430 instruction set consists of 27 core instructions and 24 emulated instructions. The core instruc-tions are instructions that have unique op-codes decoded by the CPU. The emulated instructions are instructions that make code easier to write and read, but do not have op-codes themselves, instead they are replaced automat-ically by the assembler with an equivalent core instruction. There is no code or performance penalty for using emu-lated instruction.All instructions are 16 bits long, and there are only three instruction formats:

Figure 6.4.2.4.3-1: Instruction Coding

All single-operand and dual-operand instructions can be byte or word instructions by using .B or .W extensions. Byte instructions are used to access byte data or byte peripherals. Word instructions are used to access word data or word peripherals. If no extension is used, the instruction is a word instruction.The source and destination of an instruction are defined by the following fields:

Table 6.4.2.4.3-1: Source and destination of an instruction

Abbr. Description

src The source operand defined by As and S-reg

dst The destination operand defined by Ad and D-reg

As The addressing bits responsible for the addressing modeused for the source (src)

S-reg The working register used for the source (src)

Ad The addressing bits responsible for the addressing modeused for the destination (dst)

D-reg The working register used for the destination (dst)

B/W Byte or word operation:0: word operation1: byte operation

Dual Operand Instructions

These basically perform dst = src op dst operations. However, MOV doesn't fetch the destination, and CMP and BIT do not write to the destination. All are valid in their 8 and 16 bit forms.

+ The status bit is affected- The status bit is not affected0 The status bit is cleared1 The status bit is set




Table 6.4.2.4.3-2: Dual Operand Instructions

Opcode Mnemonic S-Reg, D-Reg Operation V N Z C Remark

0100 MOV(.B) src, dst dst = src - - - - The status flags are NOT set.

0101 ADD(.B) src, dst dst += src + + + +

0110 ADDC(.B) src, dst dst += src + C + + + +

1000 SUB(.B) src, dst dst += ~src + 1 + + + +

0111 SUBC(.B) src, dst dst += ~src + C + + + +

1001 CMP(.B) src, dst dst - src + + + + Sets status only; the destina-tion is not written.

1010 DADD(.B) src, dst dst += src + C, BCD

0 + + +

1011 BIT(.B) src, dst dst & src 0 + + + Sets status only; the destina-tion is not written.

1100 BIC(.B) src, dst dst &= ~src - - - - The status flags are NOT set.

1101 BIS(.B) src, dst dst |= src - - - - The status flags are NOT set.

1110 XOR(.B) src, dst dst ^= src + + + +

1111 AND(.B) src, dst dst &= src 0 + + +




Single Operand Instructions

The status flags are set by RRA, RRC, SXT, and RETI.The status flags are NOT set by PUSH, SWPB, and CALL.

+ The status bit is affected- The status bit is not affected0 The status bit is cleared1 The status bit is set

Table 6.4.2.4.3-3: Single Operand Instructions

Opcode Mnemonic S-Reg, D-Reg Operation V N Z C Remark

000 RRC(.B) dst C -> MSB -> ... -> LSB -> C

0 + + + 9-bit rotate right through carry. Clear the carry bit beforehand to do a logical right shift.

010 RRA(.B) dst MSB -> MSB ->... LSB -> C

0 + + + Badly named, this is an 8-bitarithmetic right shift.

100 PUSH(.B) src SP-2 -> SPsrc -> @SP

- - - - Push operand on stack. Push byte decrements SP by 2.

001 SWPB dst swap bytes - - - - The destination operand high and low bytes are exchanged. This has no byte form.

101 CALL src SP-2 -> SPPC+2 -> @SPsrc -> PC

- - - - Fetch operand, push PC, then assign operand value to PC.Note: the immediate form is the most commonly used. There is no easy way to per-form a PC-relative call; the PC-relative addressing mode fetches a word and uses it as an absolute address. This has no byte form.

110 RETI TOS -> SRSP+2 -> SPTOS -> PCSP+2 -> SP

+ + + + Pop SP, then pop PC.Note: The CPUOFF flag will not be stored to stack on interrupt entry, so the CPU will NOT return to low-powermode it was previously in.

011 SXT dst Bit 7 -> Bit 8........Bit 15

0 + + + Sign extend 8 bits to 16. No byte form.




Emulated Instructions

There are a number of zero- and one-operand pseudo-operations that can be built from these two-operand forms. These are usually referred to as "emulated" instructions:

Table 6.4.2.4.3-4: Emulated Instructions

Instruction Emulation Remark

NOP MOV r3,r3 Any register from r3 to r15 would do the same thing.Note: that other forms of a NOP instruction can be constructed as emu-lated instructions, which take different numbers of cycles to execute. These can sometimes be useful in constructing accurate timing patterns in software.

POP dst MOV @SP+,dst

BR dst MOV dst,PC Branch and return can be done by moving to PC (r0)

RET MOV @SP+,PC Branch and return can be done by moving to PC (r0)

CLRC BIC #1,SR The constants were chosen to make status register (r2) twiddling efficient

SETC BIS #1,SR The constants were chosen to make status register (r2) twiddling efficient

CLRZ BIC #2,SR The constants were chosen to make status register (r2) twiddling efficient

SETZ BIS #2,SR The constants were chosen to make status register (r2) twiddling efficient

CLRN BIC #4,SR The constants were chosen to make status register (r2) twiddling efficient

SETN BIS #4,SR The constants were chosen to make status register (r2) twiddling efficient

DINT BIC #8,SR The constants were chosen to make status register (r2) twiddling efficient

EINT BIC #8,SR The constants were chosen to make status register (r2) twiddling efficient

RLA(.B) dst ADD(.B) dst,dst Shift and rotate left is done with add

RLC(.B) dst ADDC(.B) dst,dst Shift and rotate left is done with add

INV(.B) dst XOR(.B) #-1,dst Some common one-operand instructions

CLR(.B) dst MOV(.B) #0,dst Some common one-operand instructions

TST(.B) dst CMP(.B) #0,dst Some common one-operand instructions

DEC(.B) dst SUB(.B) #1,dst Increment and decrement (by one or two)

DECD(.B) dst SUB(.B) #2,dst Increment and decrement (by one or two)

INC(.B) dst ADD(.B) #1,dst Increment and decrement (by one or two)

INCD(.B) dst ADD(.B) #2,dst Increment and decrement (by one or two)

ADC(.B) dst ADDC(.B) #0,dst Increment and decrement carry.

DADC(.B) dst DADD(.B) #0,dst Increment and decrement carry.

SBC(.B) dst SUBC(.B) #0,dst Increment and decrement carry.




Relative Jumps

Conditional jumps support program branching relative to the PC and do not affect the status bits. The possible jumprange is from -511 to +512 words relative to the PC value at the jump instruction. The 10-bit program-counter offsetis treated as a signed 10-bit value that is doubled and added to the program counter:

PCnew = PCold + 2 + PCoffset × 2

Table 6.4.2.4.3-5: Relative Jumps

Opcode Mnemonic Jump Condition

000 JNE/JNZ Z == 0

001 JEQ/JZ Z == 1

010 JNC/JLO C == 0

011 JC/JHS C == 1

100 JN N == 1

101 JGE N == V

110 JL N != V

111 JMP unconditionally




6.4.2.4.4 Instruction Cycle Counts

Figure 6.4.2.4.4-1: Cycle Count Table




6.4.2.4.5 JTAG Debug InterfaceTo access the debug structures a standard JTAG interface is used.

The debugging logic provides the following features:

• CPU register read and write access• Data bus (memory) read and write access• Breakpoint logic• IAR can be use as debug IDEThe H430 embedded breakpoint logic provides the following features:

• 3 breakpoint triggers• each trigger can match a separate address or data bus value• a trigger value compare mask can be defined• trigger can match a greater, smaller, equal or non equal value• trigger can be configured for read / write or instruction fetch / non instruction fetch bus cycles• triggers can be combined (trigger dependency)• all breakpoints can be used for stepping and run-stop a program




6.4.2.5 Sub Parts6.4.2.5.1 Vector Interrupt Control Module (VIC)Two Stage Vector Interrupt System

Description

The Vector Interrupt System is a two stage interrupt handling structure. The first stage is located inside the interruptcapable digital modules. The second stage collects all module interrupts and provides a single interrupt signal to the CPU. All module interrupts provided to the main interrupt controller are level interrupts.The Vector Interrupt Control (VIC) logic - included in every module and the main interrupt controller - is build as fol-lows :The incoming interrupt sources are latched by hold elements if the interrupt source is classified to be an "event". "level" interrupt sources are not latched to hold elements. "event" interrupt sources are usually conditions which areactive for a very short time and they need to be latched to be handled. Their latched status flag has to be cleared by the interrupt handling routine. "level" interrupt sources are usually slow signals and their status changes by the interrupt handling itself which removes the interrupt condition.The unmasked interrupt status can be read via the IRQ_STATUS register. Writing to the IRQ_STATUS register clears all "event" status bits which are written as one. The value of IRQ_MASK bit wise makes the interrupt status. The IRQ_MASK register can be written directly or modified using the IRQ_VENABLE and IRQ_VDISABLE registers. These two registers implement a fast vector based mask modification possibility.The masked interrupt status is converted to an integer value and compared with the value of the IRQ_VMAX register. It defines a maximum interrupt vector level for the outgoing interrupt.The IRQ_VNO register implements the possibility to read the current interrupt vector of the highest priority. Low vector numbers have high priority. This value can be used for a fast table based interrupt routine entry. A write access to the IRQ_VNO register clears the interrupt status bit of the written vector.

VIC Logic Structure:

Figure 6.4.2.5.1-1: VIC logic structure




Two Stage Interrupt System Structure:

Figure 6.4.2.5.1-2: Two stage interrupt system structure

Features

• IRQ number for fast IRQ processing• Main IRQ enable to enable or disable all IRQs• Main IRQ enable MIE for easy cli() and sei() implementation• IRQ base address for IRQ vector table in memory• Prioritized IRQ sources where irq 0 has highest priority• Fast vector based interrupt enable and disable• Nested IRQ support

Table 6.4.2.5.1-1: Registers


TABLE_BASE 0x00 table base register

TABLE_TYPE 0x02 table type register

MAIN_ENABLE 0x04 IRQ main enable register

IRQ_STATUS 0x30 IRQ status register 0

IRQ_MASK 0x34 IRQ mask register 0

IRQ_VENABLE 0x38 IRQ vector enable register

IRQ_VDISABLE 0x3A IRQ vector disable register

IRQ_VMAX 0x3C IRQ max vector register

IRQ_VNO 0x3E IRQ vector number register




Table 6.4.2.5.1-2: Register TABLE_BASE (0x00)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 15:0 : base - base address of vector table in memory

Table 6.4.2.5.1-3: Register TABLE_TYPE (0x02)

MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R R R R R R/W

Bit Description 0 : type - auto combine vector number and table base to create vectornumber related CPU interrupt pointer.0: base value is combined with vector number to be used asCPU interrupt pointer (an interrupt service routine per module)1: base value is directly used as CPU interrupt pointer (onecommon interrupt service routine)

Table 6.4.2.5.1-4: Register MAIN_ENABLE (0x04)

MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1


Bit Description 0 : enable - main interrupt enable / disable1: enabled0: disabled

Table 6.4.2.5.1-5: Register IRQ_STATUS (0x30)

MSB LSB

Content - - - - - - 9 8 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R\W R\W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 9 : cctimer (level)8 : gpio (level)7 : timer (level)6 : sci (level)5 : pwm (level)4 : adc_ctrl (level)3 : hv_ctrl (level)2 : divider (level)1 : wdog (level)0 : sys_state (level)




Table 6.4.2.5.1-6: Register IRQ_MASK (0x34)

MSB LSB

Content - - - - - - 9:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 9:0 : mask - enable irq source1: enabled0: disabled

Table 6.4.2.5.1-7: Register IRQ_VENABLE (0x38)

MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R R W W W W

Bit Description 3:0 : vno - vector number of interrupt to enable

Table 6.4.2.5.1-8: Register IRQ_VDISABLE (0x3A)

MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 3:0 : vno - vector number of interrupt to disable

Table 6.4.2.5.1-9: Register IRQ_VMAX (0x3C)

MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0

Access R R R R R R R R R R R R R/W R/W R/W R/W

Bit Description 3:0 : vmax - needed for nested interrupt supportsoftware writes current vector number to this register, so only interrupts with higher priority (lower vector number) can nest

Table 6.4.2.5.1-10: Register IRQ_VNO (0x3E)

MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0


Bit Description 3:0 : vno -read: vector number of enabled pending interrupt with highest priority (smallest vector number). when no IRQ is pending the first unused irq number is returned.write: vector number of interrupt event to clear




6.4.2.5.2 Watchdog Module (WDOG)Features• 8 bit pre-scaler• 16 bit decrementing timer• the window-watchdog triggers a system reset when counter value = 0• when system clock is not running or stops the watchdog will assert a system reset• a second watchdog clock oscillator is used to implement this feature

• when watchdog clock oscillator is not running or stops a system reset is asserted• window-watchdog timer is disabled after reset and has to be armed by software• window-watchdog generates an interrupt when watchdog is restarted outside specified window• window-watchdog cannot be disabled or changed when armed• NOTE: watchdog will be halted during FLASH erase / program• NOTE: watchdog will be halted during CPU debug halt

Figure 6.4.2.5.2-1: Timing



CONTROL 0x00 control register

WINDOW 0x02 window configuration register

PRESCALER 0x04 pre-scaler configuration register

RELOAD 0x06 counter reload value register

COUNTER 0x08 current counter value register

IRQ_STATUS 0x30 IRQ status register

IRQ_MASK 0x34 IRQ mask register








Table 6.4.2.5.2-2: Register CONTROL (0x00)

MSB LSB

Content 15:8 - - - - - - 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R W R/W

Bit Description 15:8 : password -must be written as 0xA5will always be read as 0x961 : restart -0 : no influence1 : restart watchdog0 : run_enable -0 - watchdog stopped1 - watchdog enabled

Table 6.4.2.5.2-3: Register WINDOW (0x02)

MSB LSB

Content - - - - - - - - - - - 4 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1

Access R R R R R R R R R R R R/W R/W R/W R/W R/W

Bit Description 4 : enable -0 - no window1 - window active3:0 : size -reset window is defined as: counter value < (2^window size)

Table 6.4.2.5.2-4: Register PRESCALER (0x04)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Access R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 7:0 : pre-scaler - watchdog counter pre-scaler (cycles = pre-scaler+1)

Table 6.4.2.5.2-5: Register RELOAD (0x06)

MSB LSB

Content 15:0

Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


Bit Description 15:0 : reload - counter restart value




Table 6.4.2.5.2-6: Register COUNTER (0x08)

MSB LSB

Content 15:0

Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


Bit Description 15:0 : value - current counter value


MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : evt_window (event) - watchdog restart before the "watchdog reset window"


MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : mask - enable irq source1: enabled0: disabled


MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R R R R R W

Bit Description 0 : vno - vector number of interrupt to enable


MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : vno - vector number of interrupt to disable





MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1


Bit Description 0 : vmax - needed for nested interrupt supportsoftware writes current vector number to this register, so only interrupts with higher priority (lower vector number) can nest


MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1


Bit Description 0 : vno -read: vector number of enabled pending interrupt with highest priority (smallest vector number). when no IRQ is pending the first unused IRQ number is returned.write: vector number of interrupt event to clear

6.4.2.5.3 Multiplier Module (H430_MUL)The hardware multiplier is a memory mapped peripheral (at a fixed address range from 0x130 to 0x13F). It can be accessed by CPU with full support of common compilers. Though the hardware architecture is different, the unit is fully compatible with the MPY16 multiplier unit in chips of the MSP430 family, providing the same interface, soft-ware support, and arithmetic results.The barrel shifter extension allows to shift either the 32/33 bit result of the multiply/MAC operation or any other 32 bit value by a variable number of bits. This unit can be accessed by a normal register interface.

Features

• unsigned/signed multiplication (MPY / MPYS)• unsigned/signed MAC (multiply and accumulate) operation (MAC / MACS)• using the old result and adding the new product• 16*16, 8*16, 16*8, and 8*8 bit input data width• 32/33 bit output data width• 1 system clock cycle calculation time• no CPU wait states (no NOP required)The type of operation to be performed is selected by writing the first operand to one of the following four registers. Writing the first operand does not start the operation. The first operand (and thus the type of operation) may remainconstant for more than one operation. Writing the second operand starts the operation.

SumLo stores the low word of the result, SumHi stores the high word of the result, and SumExt stores information about the result.For signed operations, results are provided in 2's complement format. The sum extension register SUMEXT allows calculations with results exceeding the 32-bit range. This read-only register holds the most significant part of the result (bits 32 and higher). The register simplifies multiple word operations, because straightforward additions can be performed without conditional jumps.




Figure 6.4.2.5.3-1: Multiplier Structure



LAST_MODE 0x00 last mode of multiply/MAC unit

MPY 0x30 multiply unsigned register

MPYS 0x32 multiply signed register

MAC 0x34 mac unsigned register

MACS 0x36 mac signed register

OP2 0x38 operand 2 register

SUMLO 0x3A sum register (low 16 bit)

SUMHI 0x3C sum register (high 16 bit)

SUMEXT 0x3E sum extension register




Table 6.4.2.5.3-2: Register LAST_MODE (0x00)

MSB LSB

Content - - - - - - - - - - - - - - 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 1:0 : last mode of multiply/MAC unit:0x0 = MPY0x1 = MPYS0x2 = MAC0x3 = MACS

Table 6.4.2.5.3-3: Register MPY (0x30)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op1 - unsigned multiply

Table 6.4.2.5.3-4: Register MPYS (0x32)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op1 - signed multiply

Table 6.4.2.5.3-5: Register MAC (0x34)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op1 - unsigned multiply accumulate

Table 6.4.2.5.3-6: Register MACS (0x36)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op1 - signed multiply accumulate




Table 6.4.2.5.3-7: Register OP2 (0x38)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op2 - write access starts multiplication

Table 6.4.2.5.3-8: Register SUMLO (0x3A)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : sum_lo - lower 16 bit of result

Table 6.4.2.5.3-9: Register SUMHI (0x3C)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : sum_hi - In case of operation:MPY: upper 16 bit of resultMPYS: The MSB is the sign of the result. The remaining bits are the upper 15-bits of the result. Two's complement notation is used for the result.MAC: upper 16 bit of resultMACS: Upper 16-bits of the result. Two's complement notation is used for the result.

Table 6.4.2.5.3-10: Register SUMEXT (0x3E)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : sum_ext - In case of operation:MPY: always 0x0000MPYS: contains the extended sign of the result0x0000 if result was positive0xFFFF if result was negativeMAC: contains the carry of the result0x0000 no carry result0x0001 result with carryMPYS: contains the extended sign of the result0x0000 if result was positive0xFFFF if result was negative




6.4.2.5.4 Divider Module (DIVIDER)Features

• unsigned and signed integer divide arithmetic• 32bit / 16bit• 32 bit result• 16 bit remainder

• 16 system clock cycles calculation time• if a result or remainder register is accessed before calculation has finished the read access is halted until the

calculation has finished and the value is valid



OP1LO 0x00 operand 1 (low 16 bit)

OP1HI 0x02 operand 1 (high 16 bit)

OP2 0x04 unsigned operand 2 register

OP2S 0x06 signed operand 2 register

RESULTLO 0x08 result register (low 16 bit)

RESULTHI 0x0A result register (high 16 bit)

REMAINDER 0x0C remainder register







Table 6.4.2.5.4-2: Register OP1LO (0x00)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op1 - operand 1 (lower 16 bit)

Table 6.4.2.5.4-3: Register OP1HI (0x02)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op1 - operand 1 (higher 16 bit)




Table 6.4.2.5.4-4: Register OP2 (0x04)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op2 - write access starts unsigned operation

Table 6.4.2.5.4-5: Register OP2S (0x06)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op2 - write access starts signed operation

Table 6.4.2.5.4-6: Register RESULTLO (0x08)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : result - equals "op1 div op2" (lower part)

Table 6.4.2.5.4-7: Register RESULTHI (0x0A)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : result - equals "op1 div op2" (higher part)

Table 6.4.2.5.4-8: Register REMAINDER (0x0C)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : remainder - equals "op1 mod op2"


MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : evt_div_by_zero (event) - divide by zero event





MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : mask - enable irq source1: enabled0: disabled


MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : vno - vector number of interrupt to enable


MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : vno - vector number of interrupt to disable


MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1


Bit Description 0 : vmax - needed for nested interrupt supportsoftware writes current vector number to this register, so only interrupts with higher priority (lower vector number) can nest


MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1


Bit Description 0 : vno -read: vector number of enabled pending interrupt with highest priority (smallest vector number). when no IRQ is pending the first unused IRQ number is returned.write: vector number of interrupt event to clear




6.4.2.5.5 System State Module (SYS_STATE)Features• system clock frequency selection• influences CPU and module clock frequency• PWM, ADC_CTRL and HV_CTRL will always run at 24MHz

• module clock enable (disabled modules save power)• Note: module has to be enabled before used by software

• reset source status• reset enable• reset sources which are disabled can assert an interrupt

Note: Once set, RESET_ENABLE and CALIBRATION_LOCK bits cannot be cleared again.



MODULE_ENABLE 0x00 module enable register

CONTROL 0x02 system control register

RESET_STATUS 0x04 reset status register

RESET_STATUS_CLEAR

0x06 reset status clear register

RESET_ENABLE 0x08 reset enable registerNote: Once set, RESET_ENABLE bits cannot be cleared again.

SW_RESET 0x0A software reset register

PULL_ENABLE 0x0C IO pads pull resistor enable

SYS_CLK_CON-FIG

0x28 sys clock divider and adc clock control







Table 6.4.2.5.5-2: Register MODULE_ENABLE (0x00)

MSB LSB

Content - - - - - - - - - - - - - 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R R R R/W R/W R/W

Bit Description 2 : cctimer - CCTIMER module enable1 : gpio - GPIO module enable0 : sci - SCI module enable





MSB LSB

Content - - - - 11:8 7:6 5:4 3 2 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Access R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 11:8 : pwm_io_sel -select PWM output configuration (PWM IO MUX)bit 0 : PWM0bit 1 : PWM1bit 2 : PWM2bit 3 : PWM3meaning of the bits:0 : output related PWM channel on die-to-die side1 : output related PWM channel external : PWM0 -> IO0, ...7:6 : io3_sel - select IO3 function (signal)0: GPIO31: SCI RXD2: CCTIMER PWM signal3: external clock source configuration5:4 : io2_sel - select IO2 function (signal)0: GPIO21: SCI TXD2,3: CCTIMER MEAS signal3 : sel_clk_ext - switch to IO3 based clock input signal0 : on chip RC oscillator based clock is used as system clock1 : external clock source (IO3) is used as system clockNote: first configure io3_sel !2 : ds - IO drive strength0: 4mA1: 8mA1:0 : sys_clk_sel - system clock selection (all modules except PWM, ADC_CTRL and HV_CTRL)0: 24 MHz1: 12 MHz2: 8 MHz3: 4 MHz




Table 6.4.2.5.5-4: Register RESET_STATUS (0x04)

MSB LSB

Content - - - 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1


Bit Description 12 : flash_1bit_err_ee - FLASH_EE single bit error corrected reset flag11 : flash_2bit_err_ee - FLASH_EE double bit error detected reset flag10 : flash_1bit_err - FLASH single bit error corrected reset flag9 : flash_2bit_err - FLASH double bit error detected reset flag8 : sram_parity - SRAM parity reset7 : software - software reset flag6 : watchdog - watchdog reset flag5 : sys_clk_fail - watchdog system clock watch reset flag4 : nrstd2d - NRSTD2D pad reset flag3 : nrst - NRST pad reset flag2 : vddc_ok - vddc_ok reset flag1 : vddio_ok - vddio_ok reset flag0 : por - power on and power watch reset flag

Table 6.4.2.5.5-5: Register RESET_STATUS_CLEAR (0x06)

MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : clear - writing clears RESET_STATUS register

Table 6.4.2.5.5-6: Register RESET_ENABLE (0x08)

MSB LSB

Content - - - - - - - - - 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W

Bit Description 6 : flash_1bit_err_ee - FLASH_EE single bit error corrected reset enable5 : flash_2bit_err_ee - FLASH_EE double bit error detected reset enable4 : flash_1bit_err - FLASH single bit error corrected reset enable3 : flash_2bit_err - FLASH double bit error detected reset enable2 : sram_parity - SRAM parity reset enable1 : software - software reset enable0 : watchdog - watchdog reset enable




Table 6.4.2.5.5-7: Register SW_RESET (0x0A)

MSB LSB

Content - - - - - - - - - - - - - - 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Access R R R R R R R R R R R R R R W R

Bit Description 1 : sw_reset - assert a system reset which also clears SW_RESET.por_flagNote: RESET_ENABLE.software has to be set to 1 before0 : por_flag - separate Power-On-Reset flag for boot loader usage

Table 6.4.2.5.5-8: Register PULL_ENABLE (0x0C)

MSB LSB

Content - - - - - - 9 8 7:0

Reset value 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0

Access R R R R R R R/W R/W R R R R R R R R

Bit Description 9 : sci - LIN SCI pads pull enable (enabled by default)8 : spi - SPI pads pull enable (enabled by default)7:0 : gpio - GPIO pads [7:0] pull enable (disabled by default)

Table 6.4.2.5.5-9: Register SYS_CLK_CONFIG (0x28)

MSB LSB

Content - - - - - 10:8 - 6:5 4:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W

Bit Description 10:8 : sys_clk_div -primary system clock frequency dividerdivide primary system clock by (sys_clk_div + 1)Note: may be used to reduce digital core clock frequency6:5 : adc_clk_phase -selects an ADC clock phase signal to be sampled by non delayed sys_clk (sys_clk_osc) to gener-ate ADC clock signal0 : use FSM generated signal as ADC clock (non shift variant)1 : same as 02 : use minimum left shifted FSM signal to be sampled3 : use maximum left shifted FSM signal to be sampled4:0 : sys_clk_delay -ADC clock to system clock delay0 .. 21 analog delays (see analog parameters for details)





MSB LSB

Content - - - - - - - - - 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 6 : flash_1bit_err_ee (event) - FLASH_EE single bit error corrected5 : flash_2bit_err_ee (event) - FLASH_EE double bit error detected4 : flash_1bit_err (event) - FLASH single bit error corrected3 : flash_2bit_err (event) - FLASH double bit error detected2 : sram_parity (event) - SRAM parity reset event1 : software (event) - software reset event0 : watchdog (level) - watchdog event


MSB LSB

Content - - - - - - - - - 6:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - - 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - - 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - - 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1







MSB LSB

Content - - - - - - - - - - - - - 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1


Bit Description 2:0 : vno -read: vector number of enabled pending interrupt with highest priority (smallest vector number). when no IRQ is pending the first unused IEQ number is returned.write: vector number of interrupt event to clear

6.4.2.5.6 Timer Module (TIMER)This module implements the following features:

Features• 2 timers• Pre-divider with:• Reload value• Trigger reload possible by software• Event when zero

• Counter with:• Reload value• Trigger reload possible by software• Can be started / stopped• Automatic reload possible, otherwise counter stops when reaching zero (single shot mode)• Event when zero

Using the timers:

1. Set reload values for the counter and pre-scaler2. Enable the counter via the register CONFIG, choosing between free running and single shot mode3. Reload/restart the counter and or its pre-scaler by triggering a reload via the command register, e.g. to realign the phase of several counters



CONFIG 0x00 config register

COMMAND 0x02 command register

CNT0_RELOAD 0x04 counter 0 reload value register

CNT1_RELOAD 0x06 counter 1 reload value register

DIV0_RELOAD 0x08 pre-divider 0 reload value register

DIV1_RELOAD 0x0A pre-divider 1 reload value register

CNT0_VALUE 0x0C counter 0 current value register

CNT1_VALUE 0x0E counter 1 current value register










Table 6.4.2.5.6-2: Register CONFIG (0x00)

MSB LSB

Content - - - - - - - - - - - - 3:2 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 3:2 : cnt_auto_reloads1: auto reload for counter n enabled, 0: disabled1:0 : enables1: counter n and prescaler n enabled, 0: disabledDisabling a running counter will stop the counter and prescalerimmediately.

Table 6.4.2.5.6-3: Register COMMAND (0x02)

MSB LSB

Content - - - - - - - - - - - - 3:2 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 3:2 : div_reload_cmd1: trigger pre-divider n reload / restart1:0 : cnt_reload_cmd1: trigger counter n reload / restart

Table 6.4.2.5.6-4: Register CNT0_RELOAD (0x04)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : cnt_reload -counter reload value (cnt_reload_val = clock cycles -1)

Table 6.4.2.5.6-5: Register CNT1_RELOAD (0x06)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : cnt_reload -counter reload value (cnt_reload_val = clock cycles -1)




Table 6.4.2.5.6-6: Register DIV0_RELOAD (0x08)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : div_reload -pre-divider reload value (div_reload_val = clock cycles -1)

Table 6.4.2.5.6-7: Register DIV1_RELOAD (0x0A)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : div_reload -pre-divider reload value (div_reload_val = clock cycles -1)

Table 6.4.2.5.6-8: Register CNT0_VALUE (0x0C)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : cnt_val -current counter value (clock cycles = cnt_val +1)

Table 6.4.2.5.6-9: Register CNT1_VALUE (0x0E)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : cnt_val -current counter value (clock cycles = cnt_val +1)


MSB LSB

Content - - - - - - - - - - - - 3:2 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 3:2 : evt_div_zero (event) -pre-divider n has been zero1:0 : evt_cnt_zero (event) -counter n has been zero





MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - - - 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R R R R R/W R/W



MSB LSB

Content - - - - - - - - - - - - - - 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R R R R R/W R/W



MSB LSB

Content - - - - - - - - - - - - - 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0




MSB LSB

Content - - - - - - - - - - - - - 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0


Bit Description 2:0 : vno -read: vector number of enabled pending interrupt with highest priority (smallest vector number). when no IRQ is pending the first unused IRQ number is returned.write: vector number of interrupt event to clear




6.4.2.5.7 LIN-SCI Module (SCI)Features• Full duplex operation• 8N1 data format, standard mark/space NRZ format• Extended baud rate selection options• Interrupt-driven operation with four flags: receiver full, transmitter empty, measurement finished, break character

receivedSpecial LIN Support:• 13 Bit break generation• 11 Bit break detection threshold• A fractional-divide baud rate pre-scaler that allows fine adjustment of the baud rate• Measurement counter which has 16 bits and can be used as a mini-timer to measure break and bit times (baud

rate recovery).• Baud Measurement Results can directly be fed into the baud register to adjust the baud rate (Baud self-syn-

chronization with SYNC byte)• SYNC Byte plausibility check• DMA support• Timer-Compare Module for• LIN Bus Idle measurement• LIN Break measurement (used for auto addressing)• LIN Frame Length measurement

Figure 6.4.2.5.7-1: SCI block diagram




Functional DescriptionGeneral function can be derived from Register description.

Additional description follows:Concurrent Break MeasurementConcurrent break measurement works independent from the receiver status and detects breaks of length of 10 nominal bit length (respectively 11 nominal bit length when LIN mode is set) in combination with AUTO_MEAS a valid break signal starts measurement of a SYNC byte. After the SYNC byte measurement the MF (measurement finish) flag is set and must be processed by the software. The concurrent break measurement will only work when the MF bit is cleared.

Note: Since concurrent break measurement is based on the actual baud_rate and concurrent break measurement is also enabled during sync byte measurement the actual baud_rate must not exceed 10 times ( respectively 11 times when LIN mode is set) the expected baud rate of the external sci. Otherwise low bits of the sync byte are detected as breaks and sync break measurement will be canceled:Condition: Actual baud_rate < 11 x expected external baud_rateExample: When setting internal baud_rate = 115200 concurrent baud measurement works with external baud_rates down to 10472 baud. The external baud_rate = 9600 baud can not be synchronized.

Concurrent break measurement can be used to support LIN requirement of interrupting ongoing frames by a new break/sync header.

Baud rateThe divider can be used to achieve divisor values between 1 and 2047,96875. The baud divisor fine adjust can be used to fine tune the baud rate in 1/32 steps of the divisor.Use the following formula to calculate the SCI baud rate:

• baud rate = sys clock frequency / (16 * (BD + BDFA))Note: The 16 bit baud divisor value represents the number of system clock cycles of two bit lengths. The result of a baud measurement(see measurement counter below) can directly be written to the baud rate register.

DMAStart DMA transfer by writing a length to the LENGTH register. Set a valid base address to the DMA_ADDRESS register before. Write access to the Address register during DMA operation will be ignored.The LENGTH register will be decremented, the ADDRESS register will be incremented with each transferred data. If an error occurs the DMA finish flag will be raised and the DMA controller will stop operation and has to be restar-ted by accessing the LENGTH register.Check DMA_LENGTH register and SCI error flags when DMA finished flag is set to check if the DMA transfer abor-ted abnormally. Possible error cases are:for TX: transmitter disabled, bus_collisionfor RX: receiver disabled, frame error, overflow errorSCI flags are not suppressed during DMA operation. The RDRF flag and the TDRE flag will be handled and reset by the DMA controller. Reading/writing of the DATA_IO register is prohibited during DMA operation.






BAUD_RATE 0x00 baud config register


STATUS 0x04 status register

DATA_IO 0x06 data register

MEAS_CONTROL 0x08 measurement control register

MEAS_COUNTER 0x0A measurement counter register

LIN_CONFIG 0x0C LIN SCI Configuration

LIN_MODE 0x0E LIN Mode Register

ADDON_IRQ_EN 0x10 Add-on Interrupt Enable

ADDON_IRQ_STAT

0x12 Add-on Interrupt Status

TIMER_COUNTER 0x14 Timer Counter

TIMER_COMPARE 0x16 Timer Compare

DMA_TX_ADDRESS

0x18 Transmit DMA Address

DMA_TX_LENGTH 0x1A Transmit DMA Length

DMA_RX_ADDRESS

0x1C Receive DMA Address

DMA_RX_LENGTH 0x1E Receive DMA Length










Table 6.4.2.5.7-2: Register BAUD_RATE (0x00)

MSB LSB

Content 15:5 4:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:5 : BD - SCI baud divisor selectDivisor:0x000 --> 1 (bypass divider)0x001 --> 20x002 --> 3...0x007 --> 8...

4:0 : BDFA - SCI baud divisor fine adjustThese bits select the number of clocks inserted in each 32 output cycle frame to achieve more timing resolution on the average baud frequency shown in the following table.

BDFA[00000] = 0/32 = 0BDFA[00001] = 1/32 = 0.03125BDFA[00010] = 2/32 = 0.0625...BDFA[10000] = 16/32 = 0.5...BDFA[11111] = 31/32 = 0.96875

The divider can be used to achieve divisor values between 1 and 2047.96875. The baud divisor fine adjust can be used to fine tune the baud rate in 1/32 steps of the divisor.Use the following formula to calculate the SCI baud rate:

Baud rate = clksys/(16*(BD+BDFA))

Note: The 16 bit baud divisor value represents the number of system clock cycles of two bit lengths. The result of a baud measurement(see measurement counter below) can directly be writ-ten to the baud rate register.





MSB LSB

Content - - - - - - - - 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7 : TIE - TXD interrupt enable (generates interrupt when TDRE is set)6 : LIN - LIN-Mode: LIN break transmit enable (13 bit break symbol instead of 10 bit),LIN break receive detection enable (detects a 11 bit break symbol instead of 10 bit)5 : RIE - RXD interrupt enable (generates interrupt when RDRF is set)4 : BIE - break detection interrupt enable (generates interrupt when BRF is set)3 : TE - transmitter enableIf software clears TE while a transmission is in progress (TC = 0)a) lin=0: the frame in the transmit shift register continues to shift out. To avoid accidentally cuttingoff the last frame in a message, always wait for TDRE to go high after the last frame before clear-ing TE.b) lin=1: the transmitter immediately fills the transmit shift register with ones and sets the TDRE flag. Wait until TC = 1 before re-enable the transmitter.2 : RE - receiver enableRE set to '0' suppresses start bit recognition, setting RE to '1' during an ongoing transfer can cause erroneous data reception and interrupt generation (RDRF)setting RE to '0' during an ongoing transfer can cause erroneous data reception and interrupt generation (RDRF), received data should be ignored1 : MFIE - measurement finish interrupt enable (generates interrupt when MF is set)0 : SBK - send break bitToggling SBK sends one break character (10 logic 0s, respectively 13 logic 0s if LINT is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 bits respect-ively 13 bit).

reset value: 0x0000




Table 6.4.2.5.7-4: Register STATUS (0x04)

MSB LSB

Content - - - - - - 9 8 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 9 : AB_TRIG - AUTO_BAUD_TRIGGEREDset when new Baud value was copied automatically to baud config register after avalid SNYC byte (0x55) measurement (see also measurement control register ->AUTO_BAUD)cleared when reading the MSB of the status wordNote: If a SYNC byte error is detected during auto baud measurement the measurement finish flag MF will be set but the ABT flag will not be set.8 : AM_TRIG - AUTO_MEAS_TRIGGEREDset when measurement was started automatically after reception of a valid break(see also measurement control register -> AUTO_MEAS)cleared when reading the MSB of the status word7 : TDRE - transmit data register emptyClear TDRE by writing to SCI data reg. Write will be ignored when transmit registeris not empty -> check if TDRE = 1 before writing to transmit register6 : TC - transmit complete flagTC is reset to '0' when a transmission is in progress5 : RDRF - receive data register full flagClear RDRF by reading SCI status with RDRF set and then reading SCI data regNOTE: RDRF will be set:a) in case of data reception: 1/8 nominal bit length after the recognized stop bit,e.g. since the bits are sampled in the middle of a nominal bit length the flags and with it the irq willbe set after the estimated end of the active stop bit.b) in case of break reception: see BRF description below4 : BRF - break received flag (LIN-Mode dependent)Clear BRF by reading SCI status with BRF set and then reading SCI data reg.The BR flag will be set when the start bit is followed by 8 (respectively 9 when LIN-Mode is set) logic 0 data bits and a logic 0 where the stop bit should be.When BRF is set also FE and RDRF will be set, the SCI data register will be clearedNote: flag generation (incl. BRF) will be suppressed when AUTO_MEAS is set3 : OV - receiver overrun detectedClear OV by reading SCI status with OV set and then reading SCI data reg.OV will be set when a received data byte is not read before the data byte of the next frame or a break character arrives. The second data byte will be disallowed2 : MRUN - measurement running1 : MF - measurement finish flagClear MF by read accessing the measurement counter0 : FE - framing error flagFE is set when the logic does not detect a logic 1 where the stop bit should be.FE will be set and reset together with RDRF




Table 6.4.2.5.7-5: Register DATA_IO (0x06)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : data - SCI data register, write for transmitting byte, read received byte

Table 6.4.2.5.7-6: Register MEAS_CONTROL (0x08)

MSB LSB

Content - - 13:8 - - - 4 3 2 1 0

Reset value 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0

Access R R R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W

Bit Description 13:8 : DBC - debounce filter threshold for baud rate measurement (MMODE=0), filter based on system clock period(Tsys_clk)Filter Threshold [6:0] is mapped to register bits:Threshold[6:1] -> MEAS_CONTROL[13:8]Threshold[0] -> forced to logic 1

Example: Debounce filter threshold set to decimal 81 results in a minimum filter delay of 81*Tsys_clk (-> 10.125us@8MHz)4 : BUS_COLLISION_E: bus collision check enable0: disable function1: check for LIN SCI bus collision during transmit, the actual transmitted bit will be checked against the actual received bit. In case of a detected collision the transmitter will be halted imme-diately (TE reset to 0), a running DMA transfer will be stopped, lin_bus_collision irq will be raised3 : AUTO_BAUD - automatically copy baud measurement result to baud config register after a valid baud measurement (expecting SYNC Byte)--> AUTO_BAUD_TRIGGERED will be setNOTE: During baud measurement the receiver is disabled an therefore no data will be received, only the measurement logic is active which will generate ameasurement finish flag (configurable as interrupt)2 : AUTO_MEAS - automatically start a baud rate measurement after reception of a valid break--> AUTO_MEAS_TRIGGERED will be setNOTE: AUTO_MEAS mode suppresses the flag specific flag generation (see sci_status -> BRF)1 : MMODE - measurement mode select0: baud rate measurement, counter runs with system clock and measures time between 4 falling edges (8 bit length are measured), debouncer is enabledNOTE: baud measurement expects a 0x55 data byte to measure, this is the SYNC byte in the LIN protocol1: break time measurement, counter runs with 16 x baud rate, measures time when RXD line is zeroNOTE: only applicable together with MEN control bit0 : MEN - measurement enableSet to '1' to start a measurementWhen measurement is finished, MEN bit will be cleared automaticallyNOTE: When AUTO_MEAS bit is set MEN must not be usedNOTE: Writing a '0' to MEN resets the measurement logic and allows a clean restart




Table 6.4.2.5.7-7: Register MEAS_COUNTER (0x0A)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : count - MEASUREMENT COUNTERCounter is cleared by every start of a new measurementWhen the measurement counter overflows the counter value is saturated to 0xFFFF and the measurement will be stopped (MF flag set). The measurement should berepeated with an adapted baud rate setting.Note: In Baud measurement mode the result of the baud measurement (8 bit length) is divided by4 and rounded (resulting 2 bit length value) the resulting 16 bitcan be fed into the baud divider register to adjust the baud rate.

Table 6.4.2.5.7-8: Register LIN_CONFIG (0x0C)

MSB LSB

Content - - - - - - - - 7:4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1


Bit Description 7:4 : 0x0 and 0x8 reserved for former products3 : DMA module implemented2 : SCI internal timer module implemented1 : TXD time-out enable register implemented0 : Concurrent break measurement implemented




Table 6.4.2.5.7-9: Register LIN_MODE (0x0E)

MSB LSB

Content - - - - - - - 8 7 6:5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Access R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R

Bit Description 8 : TXD time-out enableEnable TXD time-out counter7 : timer_clk_base - Timer counts with0: 1us clock1: 16 x baud rate6:5 : 0: normal operation1: restart timer from 0 when a falling RXD edge is detected.timer_prepare bit will be reset immediately2: restart timer from 0 when a falling RXD edge is detectedtimer_prepare bit will be reset when a valid break is detected3: restart timer from 0 when a falling RXD edge is detectedtimer_prepare bit will not be reset automaticallyNote: As long as timer_prepare is >0 no compare events will be generated, this allows preloadingof the timer compare register. Timer_prepare works only with timer_enable=14 : Timer Enable0: timer not running(reset counter to 0)1: timer runningtimer counter is incremented by timer_clk_base3 : High speed - unused, use signal from HV_Control Block2 : SCI disable0: SCI enabled, use SCI generated TXD1: SCI transmission disabled, incoming RXD signal forced to '1', use txd_val as TXD signal (allows CPU generated TXD)1 : TXD ValueTxd value taken from register0 : RXD ValueReceiver signal (direct input)

Table 6.4.2.5.7-10: Register ADDON_IRQ_EN (0x10)

MSB LSB

Content - - - - - - - - 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7 : lin_bus_collision IRQ enable6 : rx_dma_finished IRQ enable5 : tx_dma_finished IRQ enable4 : sci_timer_ov IRQ enable3 : sci_timer_cmp IRQ enable2 : txd_timeout IRQ enable1 : rxd_rising IRQ enable0 : rxd_falling IRQ enable




Table 6.4.2.5.7-11: Register ADDON_IRQ_STAT (0x12)

MSB LSB

Content - - - - - - - - 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7 : lin_bus_collisionLIN bus collision detected,write '1' to clear interrupt6 : rx_dma_finishedReceive DMA transfers finished, e.g. dma_rx_length = 0 error condition occurredwrite '1' to clear interrupt5 : tx_dma_finishedTransmit DMA transfers finished, e.g. dma_tx_length = 0 or error condition occurredwrite '1' to clear interrupt4 : sci_timer_ovSCI Timer Overflow eventwrite '1' to clear interrupt3 : sci_timer_cmpSCI Timer Compare eventwrite '1' to clear interrupt2 : txd_timeout12ms LIN timeout exceededwrite '1' to clear interrupt1 : rxd_risingRXD line rising edge detectedwrite '1' to clear interrupt0 : rxd_fallingRXD line falling edge detectedwrite '1' to clear interrupt

Table 6.4.2.5.7-12: Register TIMER_COUNTER (0x14)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : timer_counterTimer counter is running when timer is enabled with timer_enable. sci_timer_ov flag is set when timer overflows.8bit access: read LSB first, MSB data will be stored during LSB read (atomic read)




Table 6.4.2.5.7-13: Register TIMER_COMPARE (0x16)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : timer_comparetimer_cmp flag is set when timer reaches timer_compare value8bit access: write LSB first, value will be written to register with MSB access; read LSB first, MSBdata will be stored during LSB read (atomic read/write)Note: Timer compare flag will NOT be set as long as timer_prepare>1. Timer overflow events will be generated

Table 6.4.2.5.7-14: Register DMA_TX_ADDRESS (0x18)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : dma_tx_addrStart address of source of transmit data.For 8 bit write access write LSB first then MSB.Note: Address is incremented with each DMA transfer executed.

Table 6.4.2.5.7-15: Register DMA_TX_LENGTH (0x1A)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : dma_tx_lengthLength of data to be transmitted via DMA in BYTE.Value will be decremented with each transfer.Write access to register will stop current DMA operation and will restart DMA controller.

Table 6.4.2.5.7-16: Register DMA_RX_ADDRESS (0x1C)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : dma_rx_addrStart address of destination of receive data.For 8 bit write access write LSB first then MSB.Note: Address is incremented with each DMA transfer executed.




Table 6.4.2.5.7-17: Register DMA_RX_LENGTH (0x1E)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : dma_rx_lengthLength of data to be transmitted via DMA in BYTE.Value will be decremented with each transfer. Write access to register will stop current DMA operation and will restart DMA controller.


MSB LSB

Content - - - - 11 10 9 8 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 11 : bus_collision (level) - (event is held by SCI internal logic and has to be cleared otherwise)10 : rx_dma_finished (level) - (event is held by SCI internal logic and has to be cleared otherwise)9 : tx_dma_finished (level) - (event is held by SCI internal logic and has to be cleared otherwise)8 : sci_timer_ov (level) - (event is held by SCI internal logic and has to be cleared otherwise)7 : sci_timer_cmp (level) - (event is held by SCI internal logic and has to be cleared otherwise)6 : txd_timeout (level) - (event is held by SCI internal logic and has to be cleared otherwise)5 : rxd_rising (level) - (event is held by SCI internal logic and has to be cleared otherwise)4 : rxd_falling (level) - (event is held by SCI internal logic and has to be cleared otherwise)3 : transmit (level) - transmit data register empty2 : receive (level) - receive data register full1 : evt_meas (level) - measurement finish (event is held by SCI internal logic and has to be cleared otherwise)0 : evt_break (level) - break received (event is held by SCI internal logic and has to be cleared otherwise)


MSB LSB

Content - - - - 11:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 11:0 : mask - enable IRQ source1: enabled0: disabledNOTE: IRQ_STATUS read: unmasked status of all pending IRQs1: pending0: no request

NOTE: IRQ STATUS write: clear event flags1: clear related flag0: do not change flag





MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0






6.4.2.5.8 GPIO Module (GPIO)This module gives access to general purpose digital IOs.

Features• 8 IOs ( ports )• Interrupt capable• Positive IO signal edge interrupt• Negative IO signal edge interrupt

• 6 external IOs (IO0..5)• IO6 and IO7 are not externally available (die-to-die)

Figure 6.4.2.5.8-1: Structure



DATA_OUT 0x00 data out register

DATA_OE 0x02 output enable register

DATA_IN 0x04 data in register

DATA_IE 0x06 input enable register

DIRECTION_LOCK 0x08 input enable register










Table 6.4.2.5.8-2: Register DATA_OUT (0x00)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : data - output data

Table 6.4.2.5.8-3: Register DATA_OE (0x02)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : enable -0: input1: output

Table 6.4.2.5.8-4: Register DATA_IN (0x04)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : data - input data

Table 6.4.2.5.8-5: Register DATA_IE (0x06)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : enable -0: input path is disabled1: input path is enabled

Table 6.4.2.5.8-6: Register DIRECTION_LOCK (0x08)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : lock -lock corresponding bits of OUTPUT_ENABLE and INPUT_ENABLE0: unlocked1: lockedNote: once set, bits cannot be cleared again.





MSB LSB

Content 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15 : evt_neg_7 (event) - negative edge event at IO port bit 714 : evt_pos_7 (event) - positive edge event at IO port bit 713 : evt_neg_6 (event) - negative edge event at IO port bit 612 : evt_pos_6 (event) - positive edge event at IO port bit 611 : evt_neg_5 (event) - negative edge event at IO port bit 510 : evt_pos_5 (event) - positive edge event at IO port bit 59 : evt_neg_4 (event) - negative edge event at IO port bit 48 : evt_pos_4 (event) - positive edge event at IO port bit 47 : evt_neg_3 (event) - negative edge event at IO port bit 36 : evt_pos_3 (event) - positive edge event at IO port bit 35 : evt_neg_2 (event) - negative edge event at IO port bit 24 : evt_pos_2 (event) - positive edge event at IO port bit 23 : evt_neg_1 (event) - negative edge event at IO port bit 12 : evt_pos_1 (event) - positive edge event at IO port bit 11 : evt_neg_0 (event) - negative edge event at IO port bit 00 : evt_pos_0 (event) - positive edge event at IO port bit 0


MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : mask - enable IRQ source1: enabled0: disabled


MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







MSB LSB

Content - - - - - - - - - - - 4:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0




MSB LSB

Content - - - - - - - - - - - 4:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0






6.4.2.5.9 Capture Compare Timer Module (CCTIMER)This module includes two 16 bit timers which can also be used to measure incoming signal waveforms.

Features• 8 bit counter clock pre-scaler• 2 x 16 bit timer / measurement / event counter• Waveform measurement : counter A measures period, counter B measures signal high time• Waveform measurement : counter A measures signal low time, counter B measures signal high time• Period meas / timer : counter A measures period, counter B is used as timer• Timer : both counters are used as timers• PWM generate : counter A defines period, compare value B defines pulse width• Event counting : counter A defines period, counter B counts measurement signal events

• Measurement counter "start" and "stop" signal edges can be configured• Timer "once" and "loop" modes are possible• Counter clock source selection• Up to 256*2^16 clock cycle measurement / timer duration• Power saving pre-scaled architecture• PWM generator• Event counting + threshold IRQ• Windowed event counting• CCTIMER MEAS (IO pad input) signal will be connected to IO2 as an alternative signal• IO2 signal selection is done by SYS_STATE.CONTROL register bit

• CCTIMER PWM (IO pad output) signal will be connected to IO3 as an alternative signal• IO3 signal selection is done by SYS_STATE.CONTROL register bit







PRESCALER 0x00 pre-scaler register


CONFIG_A 0x04 config A register

CONFIG_B 0x06 config B register

CAPCMP_A 0x08 capture compare A register

CAPCMP_B 0x0A capture compare B register

COUNTER_A 0x0C counter A register

COUNTER_B 0x0E counter B register

PRESEL_A 0x10 pre_select A register

PRESEL_B 0x12 pre_select B register







Table 6.4.2.5.9-2: Register PRESCALER (0x00)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : val - counter clock pre-scale value (clock prediv by val+1)


MSB LSB

Content - - - - - - - - - - - 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R W W W R/W R/W

Bit Description 4 : restart_p - restart pre-scale counter3 : restart_b - restart counter B2 : restart_a - restart counter A1 : enable_b - enable sub-timer B0 : enable_a - enable sub-timer A




Table 6.4.2.5.9-4: Register CONFIG_A (0x04)

MSB LSB

Content - - - - - - 9:8 - 6:5 4:2 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R/W R/W R R/W R/W R/W R/W R/W R/W R/W

Bit Description 9:8 : mode - mode selection0: compare mode (CAPCMP is used as compare value)1: like 0, but "enable" will be cleared at compare event (once)2: like 0, but counter will be restarted at compare event (loop)3: capture mode (CAPCMP is used to capture)6:5 : capture_sel - capture event selection (capture mode only !)0 : other counter compare event1 : MEAS signal positive edge2 : MEAS signal negative edge3 : system signal (see pre-select PRESEL_*.capture_sel)4:2 : restart_sel - restart event selection0: counter enable gets active / own compare event ( loop )1: other counter compare event2: MEAS signal positive edge3: MEAS signal negative edge4: system signal (see pre-select PRESEL_*.restart_sel)1:0 : clk_sel - counter clock source selection0: pre-scaled system clock1: MEAS signal positive edge (up)2: MEAS signal negative edge (up)3: system signal (see pre-select PRESEL_*.clk_sel)




Table 6.4.2.5.9-5: Register CONFIG_B (0x06)

MSB LSB

Content - - - - - - 9:8 - 6:5 4:2 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R/W R/W R R/W R/W R/W R/W R/W R/W R/W

Bit Description 9:8 : mode - mode selection0: compare mode (CAPCMP is used as compare value)1: like 0, but "enable" will be cleared at compare event (once)2: like 0, but counter will be restarted at compare event (loop)3: capture mode (CAPCMP is used to capture)6:5 : capture_sel - capture event selection (capture mode only !)0 : other counter compare event1 : MEAS signal positive edge2 : MEAS signal negative edge3 : system signal (see pre-select PRESEL_*.capture_sel)4:2 : restart_sel - restart event selection0: counter enable gets active / own compare event ( loop )1: other counter compare event2: MEAS signal positive edge3: MEAS signal negative edge4: system signal (see pre-select PRESEL_*.restart_sel)1:0 : clk_sel - counter clock source selection0: pre-scaled system clock1: MEAS signal positive edge (up)2: MEAS signal negative edge (up)3: system signal (see pre-select PRESEL_*.clk_sel)

Table 6.4.2.5.9-6: Register CAPCMP_A (0x08)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : val - compare value OR captured value

Table 6.4.2.5.9-7: Register CAPCMP_B (0x0A)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : val - compare value OR captured value

Table 6.4.2.5.9-8: Register COUNTER_A (0x0C)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : val - current counter value




Table 6.4.2.5.9-9: Register COUNTER_B (0x0E)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : val - current counter value

Table 6.4.2.5.9-10: Register PRESEL_A (0x10)

MSB LSB

Content - - - - 11:8 7:4 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 11:8 : capture_sel - pre-select a system signal as capture trigger0: IO4 positive edge1: IO5 positive edge2: IO6 positive edge3: IO7 positive edge4: IO4 negative edge5: IO5 negative edge6: IO6 negative edge7: IO7 negative edge8: HV_CTRL muxed signal positive edge9: HV_CTRL muxed signal negative edge-> see HV_CTRL CCTIMER_SEL register for details7:4 : restart_sel - pre-select a system signal as restart trigger0: IO4 positive edge1: IO5 positive edge2: IO6 positive edge3: IO7 positive edge4: IO4 negative edge5: IO5 negative edge6: IO6 negative edge7: IO7 negative edge8: HV_CTRL muxed signal positive edge9: HV_CTRL muxed signal negative edge-> see HV_CTRL CCTIMER_SEL register for details3:0 : clk_sel - pre-select a system signal as timer clock0: IO4 positive edge1: IO5 positive edge2: IO6 positive edge3: IO7 positive edge4: IO4 negative edge5: IO5 negative edge6: IO6 negative edge7: IO7 negative edge8: HV_CTRL muxed signal positive edge9: HV_CTRL muxed signal negative edge-> see HV_CTRL CCTIMER_SEL register for details




Table 6.4.2.5.9-11: Register PRESEL_B (0x12)

MSB LSB

Content - - - - 11:8 7:4 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 11:8 : capture_sel - pre-select a system signal as capture trigger0: IO4 positive edge1: IO5 positive edge2: IO6 positive edge3: IO7 positive edge4: IO4 negative edge5: IO5 negative edge6: IO6 negative edge7: IO7 negative edge8: HV_CTRL muxed signal positive edge9: HV_CTRL muxed signal negative edge-> see HV_CTRL CCTIMER_SEL register for details7:4 : restart_sel - pre-select a system signal as restart trigger

0: IO4 positive edge1: IO5 positive edge2: IO6 positive edge3: IO7 positive edge

4: IO4 negative edge5: IO5 negative edge6: IO6 negative edge7: IO7 negative edge

8: HV_CTRL muxed signal positive edge9: HV_CTRL muxed signal negative edge-> see HV_CTRL CCTIMER_SEL register for details3:0 : clk_sel - pre-select a system signal as timer clock

0: IO4 positive edge1: IO5 positive edge2: IO6 positive edge3: IO7 positive edge

4: IO4 negative edge5: IO5 negative edge6: IO6 negative edge7: IO7 negative edge

8: HV_CTRL muxed signal positive edge9: HV_CTRL muxed signal negative edge-> see HV_CTRL CCTIMER_SEL register for details





MSB LSB

Content - - - - - - - 8 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 8 : compare_b (event) - counter 1 compare event7 : compare_a (event) - counter 0 compare event6 : capture_b (event) - counter 1 capture event5 : capture_a (event) - counter 0 capture event4 : restart_b (event) - counter 1 restart event3 : restart_a (event) - counter 0 restart event2 : overflow_b (event) - counter 1 overflow (counter type is signed int)1 : overflow_a (event) - counter 0 overflow (counter type is signed int)0 : restart_p (event) - pre-scaler restart event


MSB LSB

Content - - - - - - - 8:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W



MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1






6.4.2.5.10 ADC Control Module (ADC_CTRL)This module implements ADC control functionality.

Features• PWM based trigger to start ADC conversion• variable PWM trigger to ADC channels assignment• register based conversion trigger• will not trigger a DMA copy

• ADC result data DMA to a 16 word memory area• PWM channel based DMA data copy• 4 PWM channel related dynamic sized data areas• the size of each area corresponds to the number of configured ADC channels of the related PWM trigger

• cyclic measurement mode• copy trigger: related PWM channel trigger• copies all PWM channel related ADC result data

• non-cyclic measurement mode• no data copy will be done

• 16 result data update interrupts• 4 copy data update interrupts• configurable DMA base address• ADC data valid status• valid, when related PWM channel was ON during ADC sampling

• ADC channel 0 has highest priority• ADC channel 15 has lowest priority• ADC conversions will be done in order of their priority• all trigger events will be halted until the corresponding conversion is executed

• when AIN1, AIN2 or VT are sampled a channel corresponding SPI mux configuration shift is also executed• this will have no effect because in these cases AIN0 is not connected to the ADC• AIN1 and AIN2 sampling will have their own sample extension configuration• VT sampling has its own sample extension configuration to handle slow analog VT node





Cyclic Measurement Timing:

Figure 6.4.2.5.10-2: Cyclic Measurement Timing

post shift delay >= mux delay + ADC sample time - SPI transfer time

cycle time = SPI transfer time + post shift delay

example:

post shift delay >= 4µs + 0.2µs - 4µspost shift delay >= 0.2µs

cycle time = 4µs + 0.2µscycle time = 4.2µs

The cyclic trigger is automatically generated inside the ADC_CTRL module if the cyclic measurement mode is used.• when a SPI shift has finished and the post shift delay has elapsed this trigger starts the next SPI transfer and the

ADC conversion timing.




Figure 6.4.2.5.10-3: Memory Map Example

Note: When PWMx_CONFIG registers are changed while PWM-ADC system is running the dynamic memory map will change too and the ADC copy data will be placed to the new areas. All copy data values are "invalid" until the next data copy DMA fills the newly configured areas !

Trigger Flags Behavior Description

• trigger events from PWM channels, register trigger or in cyclic mode by the state of the PWMx_CONFIG registers will be halted by internal trigger flags until they are processed

• the internal trigger flag behavior depends on the cyclic configuration bit• non-cyclic mode:• PWM triggers will set internal trigger flags of all channels configured by the PWM channel related

PWMx_CONFIG registers• when software writes to REG_TRIGGER register, bits are written as 1 will immediately set related internal trig-

ger flags• internal trigger flags will be processed in order of their priority (from bit 0 to bit 15)• an internal trigger flag will be cleared when its processing has been started• when the processing has been finished, the ADC result value will be written to the related ADC channel result

data address• cyclic mode:• PWM triggers will not set internal trigger flags




• when software writes to REG_TRIGGER register, bits are written as 1 will immediately set related internal trig-ger flags

• when all internal trigger flags are cleared (are in a cleared state), the internal trigger flags will be set to the ORed PWMx_CONFIG which means that all bits set in the PWMx_CONFIG registers will lead to set internal trigger flags

• internal trigger flags will be processed in order of their priority (from bit 0 to bit 15)• an internal trigger flag will be cleared when its processing has been started• when the processing has been finished, the ADC result value will be written to the related ADC channel result

data address• when a PWM trigger event occurs, all ADC result data values configured by the related PWMx_CONFIG

register will be copied to their ADC channel copy data addresses



REG_TRIGGER 0x00 register trigger register

PWM0_CONFIG 0x02 PWM 0 trigger configuration register




CONTROL 0x0A control register

STATUS 0x0C conversion status register

SAMPLE_EXT_VT 0x0E VT sample time extension

MUX_DELAY 0x10 MUX switch delay register

SAMPLE_EXT 0x12 ADC sample time extension

DMA_BASE_ADDR

0x14 DMA base address

ADC_OFFSET 0x16 ADC offset calibration register

ADC_GAIN 0x18 ADC gain calibration register

TRIGGER_DELAY0

0x20 PWM 0 trigger delay register

TRIGGER_DELAY1


TRIGGER_DELAY2


TRIGGER_DELAY3


IRQ_STATUS0 0x30 IRQ status register 0

IRQ_STATUS1 0x32 IRQ status register 1

IRQ_MASK0 0x34 IRQ mask register 0

IRQ_MASK1 0x36 IRQ mask register 1








Table 6.4.2.5.10-2: Register REG_TRIGGER (0x00)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access W W W W W W W W W W W W W W W W

Bit Description 15:0 : trigger - register based triggerwhen software sets bits in this register the related ADC channel conversions will be triggered. Bits can only be added but not cleared by software. Bits will be cleared when related conversion is started. When bits need to be cleared in this register it's possible to do this by a '1', '0' sequence of these bits in the ORed PWMx_CONFIG (e.g. by a write sequence to PWM0_CON-FIG).bit 0 : ADC channel 0...

Table 6.4.2.5.10-3: Register PWM0_CONFIG (0x02)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : config - configures which ADC channel conversions will be triggered by PWM channel 0Note: When bits in the ORed PWMx_CONFIG are change from '1' to '0' the related pending con-version flags are cleared immediately.


MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 6.4.2.5.10-7: Register CONTROL (0x0A)

MSB LSB

Content - 14:8 - - - - 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W

Bit Description 14:8 : adc_mux_addr - SPI address of ADC multiplexer control register3 : ch15_sel - selects ADC channel 15 input source0: analog IC multiplexer channel 15 is used1: VT temperature voltage is used2 : ch14_sel - selects ADC channel 14 input source0: analog IC multiplexer channel 14 is used1: AIN1 analog input (IO4) is used1 : ch13_sel - selects ADC channel 13 input source0: analog IC multiplexer channel 13 is used1: AIN2 analog input (IO5) is used0 : cyclic - configures ADC conversion behavior0 : non-cyclic measurement which uses PWM or register triggers to start a ADC channel conver-sion - no result data copy will be done1 : cyclic measurement which converts all configured PWM related channels continually and usesa PWM trigger only for DMA data copy




Table 6.4.2.5.10-8: Register STATUS (0x0C)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : valid - Related PWM channel was active during ADC conversion.

0 : related PWM channel was inactive (OFF) during ADC conversion1 : related PWM channel was active (ON) during ADC conversion

At the moment the ADC samples an ADC channel the status bit related to this ADC channel is setto 1 when ALL configured (enabled by PWMx_CONFIG) PWM channels are active (ON) other-wise the status bit is cleared to 0.When an ADC channel is only configured (enabled) in one PWMx_CONFIG register, the status bit is set to 1 when the related PWM channel is active at the moment the ADC samples and cleared to 0 otherwise.

Delayed PWM triggers will be scheduled and "executed" in order of their priority. It may be hap-pen that a conversion is done some system clock cycles later than determined by the trigger delay. The valid flag is set after a conversion when the related PWM output was active during the ADC conversion else it is cleared.

bit 0 : ADC channel 0 conversion status...bit 15 : ADC channel 15 conversion status

Table 6.4.2.5.10-9: Register SAMPLE_EXT_VT (0x0E)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0


Bit Description 7:0 : cycles -extend ADC sample time of VT by given number of ADC half clock cycles

Table 6.4.2.5.10-10: Register MUX_DELAY (0x10)

MSB LSB

Content - - - - - - 9:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 9:0 : delay - mux switch delay (24 MHz clock cycles)Note: When using ADC power-mode cycling, please make sure, that the MUX_DELAY value is greater than t_WARMUP (see ADC electrical parameter table)

When using ADC power-mode cycling, the ADC is switched to run mode at the beginning of the MUX_DELAY and switched to standby mode after conversion has been finished.




Table 6.4.2.5.10-11: Register SAMPLE_EXT (0x12)

MSB LSB

Content 15:8 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:8 : cycles_ain12 - extend channels AIN1 and AIN2 ADC sample time by given number of ADChalf clock cycles7:0 : cycles_ain0 - extend channel AIN0 ADC sample time by given number of ADC half clock cycles

Table 6.4.2.5.10-12: Register DMA_BASE_ADDR (0x14)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : base_addr - ADC DMA result base address

Table 6.4.2.5.10-13: Register ADC_OFFSET (0x16)

MSB LSB

Content - - - 12:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 12:0 : val - ADC offset correction value (signed)Note: Once written, this register changes to read-only !

Table 6.4.2.5.10-14: Register ADC_GAIN (0x18)

MSB LSB

Content - - - 12:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 12:0 : val - ADC gain correction valueNote:if bit 12 = 0 : gain < 1if bit 12 = 1 : gain >= 1Note: Once written, this register changes to read-only !

Table 6.4.2.5.10-15: Register TRIGGER_DELAY0 (0x20)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : delay - PWM channel 0 trigger delay (pre-scaled PWM clock cycles between PWM period start event and ADC conversion triggering)





MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 6.4.2.5.10-19: Register IRQ_STATUS0 (0x30)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : evt_update (event) - ADC channel result data update events

bit 0 : ADC channel 0...bit 15 : ADC channel 15




Table 6.4.2.5.10-20: Register IRQ_STATUS1 (0x32)

MSB LSB

Content - - - - - - - - - - - 4 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 4 : ready (level) - ADC control ready (no ADC conversion pending or running)3:0 : evt_copy (event) - PWM channel related copy data update events

bit 0 : PWM channel 0...bit 3 : PWM channel 3

Table 6.4.2.5.10-21: Register IRQ_MASK0 (0x34)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 6.4.2.5.10-22: Register IRQ_MASK1 (0x36)

MSB LSB

Content - - - - - - - - - - - 4:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - 4:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - 4:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







MSB LSB

Content - - - - - - - - - - - 4:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0




MSB LSB

Content - - - - - - - - - - - 4:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0






6.4.2.5.11 PWM Module (PWM)This module implements the PWM functionality.

Features• 4 x 8 bit pre-scaler• 4 x 16 bit PWM channel with independent period length, pulse start and pulse stop timestamps• External PWM signal polarity configuration• Period, pulse start and pulse stop interrupts per channel• PWM channel related trigger delay (timestamp) configuration (see ADC_CTRL module)• Pre-scaler, period, pulse start, pulse stop, polarity and ADC_CTRL.trigger_delay configurations will be loaded

into active (current) registers with channel related period event• START-STOP cases• start < stop : PWM pulse length > 0• ON at start• OFF at stop

• start == stop : PWM pulse length = 0• 0% ON

• start == 0, stop == period• 100% ON

• start > stop : PWM pulse length > 0 (inverted pulse form behavior)• OFF at stop• ON at start

• PWM output will be HIZ (floating) when related channel is not enabled





PWM ON cycles in relation to (stop-start):

Please note: The picture shows the none continuous transition at 0 where (stop-start) changes its sign.

Figure 6.4.2.5.11-2: Relation ship of output duty cycle to stop-start

POLARITY.pwm_term:

Figure 6.4.2.5.11-3: PWM termination




Start Stop PWM Timing Examples:

Figure 6.4.2.5.11-4: PWM output behavior in relation to the setting of start and stop(1)

Figure 6.4.2.5.11-5: PWM output behavior in relation to the setting of start and stop(2)







STATUS 0x04 status registers

POLARITY 0x06 polarity config register

PRESCALER0 0x08 pre-scaler 0 config register

PRESCALER1 0x0A pre-scaler 1 config register

PRESCALER2 0x0C pre-scaler 2 config register

PRESCALER3 0x0E pre-scaler 3 config register

PERIOD0 0x10 channel 0 period config register

START0 0x12 channel 0 pulse start config

STOP0 0x14 channel 0 pulse stop config

COUNTER0 0x16 channel 0 current counter value


START1 0x1A channel 1 pulse start config

STOP1 0x1C channel 1 pulse stop config

COUNTER1 0x1E channel 1 current counter value


START2 0x22 channel 2 pulse start config

STOP2 0x24 channel 2 pulse stop config

COUNTER2 0x26 channel 2 current counter value


START3 0x2A channel 3 pulse start config

STOP3 0x2C channel 3 pulse stop config

COUNTER3 0x2E channel 3 current counter value








MSB LSB

Content - - - - - - - - - - - - 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 3 : pwm_3_enable - enable PWM channel 3 and output PWM signal2 : pwm_2_enable - enable PWM channel 2 and output PWM signal1 : pwm_1_enable - enable PWM channel 1 and output PWM signal0 : pwm_0_enable - enable PWM channel 0 and output PWM signal





MSB LSB

Content - - - - - - - - - - - 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 4 : running - "running" is set if at least one PWM channel is enabled. After disabling all PWM channels, the PWM may run some clock cycles until it is stopped. This time is caused by the PWM pre-scaler logic. When PWM enters stopped state, the "running" flag will be cleared.3 : pwm3 - PWM channel 3 state2 : pwm2 - PWM channel 2 state1 : pwm1 - PWM channel 1 state0 : pwm0 - PWM channel 0 state

Table 6.4.2.5.11-4: Register POLARITY (0x06)

MSB LSB

Content - - - - 11:8 7:4 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 11:8 : pwm_zero - PWM signal behavior selection0 : no end of period PWM signal clear1 : clear PWM signal at end of period to zero levelNote: pwm_zero has higher priority than pwm_term7:4 : pwm_term - PWM signal behavior selection0 : no end of period PWM signal terminate1 : terminate PWM signal at end of period to next period default level (0 at normal mode, 1 at inverse mode)Note: inverse mode means : stop < start3:0 : pwm_polarity - PWM signal polarity configuration0 : off level = 01 : off level = 1

Table 6.4.2.5.11-5: Register PRESCALER0 (0x08)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : val - PWM pre-scaler reload config registerperiod = val+1 [24MHz cycles]




Table 6.4.2.5.11-6: Register PRESCALER1 (0x0A)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 6.4.2.5.11-7: Register PRESCALER2 (0x0C)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 6.4.2.5.11-8: Register PRESCALER3 (0x0E)

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 6.4.2.5.11-9: Register PERIOD0 (0x10)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : val - channel 0 period reload value configPWM period = val+1 [pre-scaled cycles]

Table 6.4.2.5.11-10: Register START0 (0x12)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : val - channel 0 start timestamp configtimestamp = val+1 [pre-scaled cycles]




Table 6.4.2.5.11-11: Register STOP0 (0x14)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : val - channel 0 stop timestamp configtimestamp = val+1 [pre-scaled cycles]

Table 6.4.2.5.11-12: Register COUNTER0 (0x16)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : counter - current PWM period counter value


MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 6.4.2.5.11-14: Register START1 (0x1A)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 6.4.2.5.11-15: Register STOP1 (0x1C)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0






Table 6.4.2.5.11-16: Register COUNTER1 (0x1E)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 6.4.2.5.11-18: Register START2 (0x22)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 6.4.2.5.11-19: Register STOP2 (0x24)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 6.4.2.5.11-20: Register COUNTER2 (0x26)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 6.4.2.5.11-22: Register START3 (0x2A)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 6.4.2.5.11-23: Register STOP3 (0x2C)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 6.4.2.5.11-24: Register COUNTER3 (0x2E)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







MSB LSB

Content - - - - 11 10 9 8 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 11 : evt_stop3 (event) - channel 3 pulse stop event10 : evt_pulse3 (event) - channel 3 pulse start event9 : evt_period3 (event) - channel 3 period reload event8 : evt_stop2 (event) - channel 2 pulse stop event7 : evt_pulse2 (event) - channel 2 pulse start event6 : evt_period2 (event) - channel 2 period reload event5 : evt_stop1 (event) - channel 1 pulse stop event4 : evt_pulse1 (event) - channel 1 pulse start event3 : evt_period1 (event) - channel 1 period reload event2 : evt_stop0 (event) - channel 0 pulse stop event1 : evt_pulse0 (event) - channel 0 pulse start event0 : evt_period0 (event) - channel 0 period reload event


MSB LSB

Content - - - - 11:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0






6.4.2.5.12 HV Control Module (HV_CTRL)This module implements the HV analog IC control ( via SPI ).Features• SPI transfer protocol• MSB first, SCK default level: 0, SCK rising edge: shift, SCK falling edge: sample• 16/12 bit write mode:• transmit: 1 write bit, 7 address bits, 8 or 4 data bits• receive: 8 bit status, 8 bit status extension

• 16/12 bit read mode:• transmit: 1 write bit, up to 7 address bits, 8 or 4 data bits• receive: 8 bit status, 8 or 4 bit read data• address LSBs on read mode may be used to provide read data

• 8 bit write mode:• transmit: 3 bit address, 5 bit data• receive: 8 bit status

• 8 bit one-hot (MAX349 / MAX350 control) mode:• transmit: 8 bit one-hot data

• a 16 or 12 bit read at address 0 returns status extension bits as read data• configurable ADC multiplexer address• ADC_CTRL:CONTROL.adc_mux_addr

• the 4 bit ADC_CTRL mux value alignment can be adjusted by setting• SPI_CONFIG.shift

• SPI baud rate adjustment• post SPI shift delay adjustment• SPI inter shift interrupt signalling (MISO = 0 while CSB = 1)• CCTIMER input "signal" (receive data) selection• HV_CTRL register based SPI transfer have higher priority than an ADC_CTRL based SPI transfer• if an ADC_CTRL based SPI transfer is currently running, a HV_CTRL based SPI transfer will be halted and

executed as soon as the current transfer has been finished• if a HV_CTRL register based transfer is executed the ADC_CTRL module will be halted until the transfer has

been finished• pending ADC conversions will be halted as long as HV_CTRL based SPI transfers are executed

• SPI_SEND must not be written as long as IRQ_STATUS.ready_wr is 0





SPI Shift Protocol:

Figure 6.4.2.5.12-2: SPI Shift Protocol




Figure 6.4.2.5.12-3: SPI Timing Diagram

single SPI_SEND request

Figure 6.4.2.5.12-4: single SPI_SEND request




dual SPI_SEND request with IRQ_STATUS.ready_wr polling

Figure 6.4.2.5.12-5: dual SPI_SEND request with ready_wr polling

dual SPI_SEND request with IRQ_STATUS.ready_rd polling

Figure 6.4.2.5.12-6: dual SPI_SEND request with ready_rd polling






SPI_SEND 0x00 SPI 12/16 bit send register

SPI_RDATA 0x04 SPI read data register

POST_SHIFT_DELAY

0x06 Post shift delay register

CCTIMER_SEL 0x08 CCTIMER signal selection register

SPI_CONFIG 0x0A SPI config register







Table 6.4.2.5.12-2: Register SPI_SEND (0x00)

MSB LSB

Content 15 14:8 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access W W W W W W W W W W W W W W W W

Bit Description 15 : write - write flag0 : read1 : write14:8 : addr - address valueSPI_CONFIG.mode dependent address usage:0,1 : address bits 14:8 are used2 : address bits 14:12 are used3 : no address7:0 : data - write data byteSPI_CONFIG.mode dependent data usage:0 : data bits 7:0 are used1 : data bits 7:4 are used2 : data bits 7:3 are used3 : data bits 7:5 are used to generate one hot data byte




Table 6.4.2.5.12-3: Register SPI_RDATA (0x04)

MSB LSB

Content 15:8 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:8 : status - status byte

will be updated on both SPI_SEND and ADC_CTRL triggered transfers

SPI_CONFIG.mode dependent RDATA usage:0,1 : received data bits 15:8 are used as 8 bit status2 : received data is used as 8 bit status3 : no status will be received7:0 : data - read data byte

will only be updated on SPI_SEND triggered transfer

SPI_CONFIG.mode dependent RDATA usage:0 : data bits 7:0 are used1 : data bits 7:4 are used, data bits 3:0 are cleared2 : data bits 7:0 are cleared3 : data bits 7:0 are cleared

Table 6.4.2.5.12-4: Register POST_SHIFT_DELAY (0x06)

MSB LSB

Content - - - - - - 9:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 9:0 : val - delay after SPI EOT (end of transfer) is signalled to ADC_CTRL to allow the next SPI transfer [24MHz cycles]

Table 6.4.2.5.12-5: Register CCTIMER_SEL (0x08)

MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 3:0 : sel - select an SPI_RDATA bit to connect to CCTIMER input0 : bit 0...15 : bit 15




Table 6.4.2.5.12-6: Register SPI_CONFIG (0x0A)

MSB LSB

Content - - - - - 10:8 7:6 5:0

Reset value 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1

Access R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 10:8 : shift - ADC_CTRL mux control value alignment (left shift value)7:6 : mode - SPI protocol mode selection0 : 16 bit shift1 : 12 bit shift2 : 8 bit shift3 : 8 bit one-hot shift (MAX349 / MAX350 control)5:0 : baud_div - SPI baud configurationbaud rate = 24 MHz / (2 * (baud_div + 1))


MSB LSB

Content - - - 12 11 10 9 8 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 12 : ready_rd (level) - ready state of SPI_RDATA (read mode)11 : ready_wr (level) - ready state of SPI_SEND (write mode)10 : eot_send (event) - end of SPI_SEND triggered SPI transfer event9 : eot (event) - end of SPI transfer event8 : spi (event) - SPI inter shift interrupt (when MISO is detected as 0 when SPI CSB is 1)7:0 : status (event) - SPI_RDATA.status events (set when status bits are read by SPI as 1)


MSB LSB

Content - - - 12:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1






6.4.2.5.13 FLASH Control Module (FLASH_CTRL)This module implements FLASH protection, erase and program functionality.

Execution of program code located in FLASH memory strictly requires "read" mode.When switching to other FLASH modes (program or erase) the user has to ensurethat during this time code is not executed from the same FLASH instance.Before returning to code in FLASH, mode has to be switched back to "read".

Features

• MAIN area protection (16 x 2K byte areas)• protected bits prevent related FLASH MAIN areas parts from changes by erase or program• once protect bits are set they cannot be cleared again (protection can only be added)

• INFO area protection ( 2 x 512 byte areas)• this protection configuration can only be set once and not changed afterwards• this configuration will be set by INFO boot program after power up

• INFO read protection ( 2 x 512 byte areas)• this protection configuration can only be set once and not changed afterwards• this configuration will be set by INFO boot program after power up

• supported modes (MAIN and INFO when not protected):• mass erase• page erase (512 byte)• program• read

• down to double-word (32 bit) programming• system frequency adaptive• SECDED ECC protection• each 16 bit data word is extended by a 6 bit ECC• Hamming distance: 4 (1 bit error correctable, 2 bit errors detectable)

Erase and Program Sequences

The following sequence has to be done to do some FLASH erase:

1. set up FREQ_CONFIG register to use proper FLASH erase timing2. select erase mode by MODE register

- MAIN mass erase / MAIN page erase / INFO page erase3. do a single (16 bit) write to the base address of the area which has to be erased to start erase process4. poll STATUS.busy bit to determine when erase has been finished by the FLASH control module5. switch back to previous FLASH mode (normally MAIN read)




The following sequence has to be done to do some FLASH program:

1. set up FREQ_CONFIG register to use proper FLASH program timing2. select program mode by MODE register

- MAIN program / INFO program3. split data into FLASH row (32 x 32 bit) aligned packets4. for all these packets do:

1. set WORD_CONFIG to number of 16 bit words which need to be programmed to FLASH row- only aligned 32 bit words are valid to be programmed !- for this only even number of 16 bit words are valid ! (2, 4, 6, ... up to 64)- to align a 16 bit words use the value 0xFFFF !

2. for all 32 bit words of current packet do:1. write lower 16 bit word to desired FLASH address2. write upper 16 bit word to desired FLASH address to start 32 bit word program process3. poll STATUS.busy bit to determine when word program has been finished by FLASH control

module3. at this point STATUS.incomplete has to be 0 !

5. switch back to previous FLASH mode (normally MAIN read)6. verify written data by read and compare



AREA_MAIN_L 0x00 lower main area protection register

AREA_MAIN_H 0x02 upper main area protection register

MODE 0x04 mode register

STATUS 0x06 status register

AREA_INFO 0x08 info area write/erase protection

READ_INFO 0x0A info area read protection

BIT_ERROR_ADDR

0x0C bit error address register

WORD_CONFIG 0x0E word prog config register

FREQ_CONFIG 0x10 frequency config register




Table 6.4.2.5.13-2: Register AREA_MAIN_L (0x00)

MSB LSB

Content 15:8 7:0

Reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0


Bit Description 15:8 : password -must be written as 0xA5will always be read as 0x967:0 : area -lower 8 FLASH MAIN area write and erase protection1 : area protected0 : area writable / erasableMAIN protection areas offset address spaces:MAIN area 0 : 0x0000 - 0x07FFMAIN area 1 : 0x0800 - 0x0FFF...MAIN area 6 : 0x3000 - 0x37FFMAIN area 7 : 0x3800 - 0x3FFF

Note: Bits set to '1' (protected) cannot be cleared again !

Table 6.4.2.5.13-3: Register AREA_MAIN_H (0x02)

MSB LSB

Content 15:8 7:0

Reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0


Bit Description 15:8 : password -must be written as 0xA5will always be read as 0x967:0 : area -upper 8 FLASH MAIN area write and erase protection1 : area protected0 : area writable / erasableMAIN protection areas offset address spaces:MAIN area 8 : 0x4000 - 0x47FFMAIN area 9 : 0x4800 - 0x4FFF...MAIN area 14 : 0x7000 - 0x77FFMAIN area 15 : 0x7800 - 0x7FFF

Note: Bits set to '1' (protected) cannot be cleared again !




Table 6.4.2.5.13-4: Register MODE (0x04)

MSB LSB

Content 15:8 7:0

Reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1


Bit Description 15:8 : password -must be written as 0xA5will always be read as 0x967:0 : mode -0x01: MAIN read0x02: INFO read0x04: MAIN program0x08: INFO program0x10: MAIN page erase0x20: INFO page erase0x40: MAIN mass erase0x80: MAIN and INFO mass eraseany other written mode value results in FLASH MAIN read mode,program/erase modes: write access to appropriate flash addressstarts program/erase cycle (see busy flag of status register, considerword config and row programming incomplete flag in programmode)


MSB LSB

Content - - - - - - - - - - - - 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 3 : recall_busy -1: FLASH recall is active(only used at system startup and will be handled by Startup-ROM code)2 : write_error -1: unexpected write to area protected memory occurred, will be cleared when STATUS is read1 : incomplete -1: row programming incompletecurrent number of programmed row words != word_config (see below)0 : busy -0: ready1: busy (program or erase is still in progress)




Table 6.4.2.5.13-6: Register AREA_INFO (0x08)

MSB LSB

Content 15:8 7:0

Reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0


Bit Description 15:8 : passwordmust be written as 0xA5will always be read as 0x967:0 : area2 FLASH INFO area write and erase protection1 : area protected0 : area writable / erasableINFO protection areas offset address spaces:INFO area 0 : 0xFC00 - 0xFDFFINFO area 1 : 0xFE00 - 0xFFFF

Note: This register can only be written once !

Table 6.4.2.5.13-7: Register READ_INFO (0x0A)

MSB LSB

Content 15:8 7:0

Reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0


Bit Description 15:8 : passwordmust be written as 0xA5will always be read as 0x967:0 : area2 FLASH INFO area read protection in user program1 : area protected (read data will be 0x0000)0 : area readableINFO protection areas offset address spaces:INFO area 0 : 0xFC00 - 0xFDFFINFO area 1 : 0xFE00 - 0xFFFF

Note: This register can only be written once !

Table 6.4.2.5.13-8: Register BIT_ERROR_ADDR (0x0C)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : addr - address offset of last FLASH bit error




Table 6.4.2.5.13-9: Register WORD_CONFIG (0x0E)

MSB LSB

Content 15:8 - - 5:0

Reset value 1 0 0 1 0 1 1 0 0 0 1 1 1 1 1 1

Access R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W

Bit Description 15:8 : password -must be written as 0xA5will always be read as 0x965:0 : config - number of 16 bit words to program within row0: 1 word1: 2 words...31: 32 words...63: 64 words (complete row)Note: number of words has to be even (double-word-programming only, low address has to be written first)

Table 6.4.2.5.13-10: Register FREQ_CONFIG (0x10)

MSB LSB

Content 15:8 - - - - - - 1:0

Reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1

Access R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R/W R/W

Bit Description 15:8 : password -must be written as 0xA5will always be read as 0x961:0 : config - system frequency config to get a correct erase and program timing0: system frequency is 24 MHz1: system frequency is 12 MHz2: system frequency is 8 MHz3: system frequency is 4 MHz




7 Package ReferenceThe E521.31 is available in a Pb free, RoHs compliant, QFN32L5 plastic package according to JEDEC MO-220K, variant VHHD-4. The package is classified to Moisture Sensitivity Level 3 (MSL 3) according to JEDEC J-STD-020 with a soldering peak temperature of 260°C.Note: Thermal resistance junction to ambient Rth,ja is 35 °C/W, based on JEDEC standard JESD-51-6 and JESD.

Figure 7-1: Package Outline

Note: Contact factory for specific location and type of pin 1 identification.

Table 7-1: Package Characteristics

Description Symbol mm inch

min typ max min typ max

Package height A 0.80 0.90 1.00 0.031 0.035 0.039

Stand off A1 0.00 0.02 0.05 0.000 0.00079 0.002

Thcikness of terminal leads, including leadfinish

A3 - 0.20REF

- - 0.0079REF

-

Width of terminal leads b 0.18 0.25 0.30 0.007 0.010 0.012

Package length / width D / E - 5.00BSC

- - 0.197BSC

-

Length /width of exposed pad D2 / E2 3.50 3.65 3.8 0.138 0.144 0.150

Lead pitch e - 0.5 BSC - - 0.02BSC

-

Length of terminal for soldering to sub-strate

L 0.35 0.40 0.45 0.014 0.016 0.018

Number of terminal positions N 32 32Note: the mm values are valid, the inch values contains rounding errors




8 General

8.1 WARNING - Life Support Applications PolicyElmos Semiconductor AG is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing Elmos Semiconductor AG products, to observe standards of safety, and to avoid situations in which malfunction or failure of an Elmos Semiconductor AG Product could cause loss of human life, body injury or damage to property. In development your designs, please ensure thatElmos Semiconductor AG products are used within specified operating ranges as set forth in the most recent product specifications.

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8.3 Application DisclaimerCircuit diagrams may contain components not manufactured by Elmos Semiconductor AG, which are included as means of illustrating typical applications. Consequently, complete information sufficient for construction purposes isnot necessarily given. The information in the application examples has been carefully checked and is believed to beentirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of Elmos Semiconductor AG or others.




9 Contact Information

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10 ContentsTable of ContentFeatures...................................................................................................................................................................... 1Applications................................................................................................................................................................. 1General Description.................................................................................................................................................... 1Ordering Information................................................................................................................................................... 1Typical Operating Circuit............................................................................................................................................. 1Functional Diagram..................................................................................................................................................... 2Pin Description............................................................................................................................................................ 31 Functional Safety..................................................................................................................................................... 42 Absolute Maximum Ratings..................................................................................................................................... 53 ESD, Latch Up and EMC......................................................................................................................................... 6

3.1 Electro Static Discharge (ESD)........................................................................................................................ 63.2 Latch-up........................................................................................................................................................... 63.3 EMC ................................................................................................................................................................ 6

4 Recommended Operating Conditions...................................................................................................................... 75 Electrical Characteristics.......................................................................................................................................... 86 Functional Description .......................................................................................................................................... 17

6.1 Overview........................................................................................................................................................ 176.2 uC analog Supply, pin VDDuC....................................................................................................................... 186.3 Design Description HV-Part........................................................................................................................... 18

6.3.1 Voltage Regulator 5V; pin VDD5............................................................................................................186.3.2 Voltage Regulator 3.3V ; pin VDD3........................................................................................................186.3.3 LIN Transceiver; pins LIN_M, LIN_S, TXD, RXD, GND.........................................................................18

6.3.3.1 Characteristics............................................................................................................................... 186.3.3.2 LIN High Speed Mode.................................................................................................................... 196.3.3.3 LIN Wake Up................................................................................................................................. 206.3.3.4 LIN Failure detection and recovery................................................................................................20

6.3.4 Auto addressing..................................................................................................................................... 216.3.5 HS driver; pins OUT1-OUT4..................................................................................................................256.3.6 Sense pins SIN1-SIN4........................................................................................................................... 256.3.7 SPI; pin SCK, CSN, SDI........................................................................................................................256.3.8 Multiplexer; pin MUXO........................................................................................................................... 28

6.4 Design Description Microcontroller................................................................................................................296.4.1 Analog Part............................................................................................................................................ 30

6.4.1.1 Internal References........................................................................................................................ 316.4.1.2 Core Supply Regulator................................................................................................................... 316.4.1.3 Oscillators and Reset.....................................................................................................................31

6.4.1.3.1 Power On Reset.................................................................................................................... 316.4.1.3.2 Brownout Detection................................................................................................................316.4.1.3.3 System Clock RC Oscillator...................................................................................................316.4.1.3.4 Watchdog Clock RC Oscillator...............................................................................................316.4.1.3.5 NRST and NRSTD2D debouncer..........................................................................................31

6.4.1.4 SAR-ADC....................................................................................................................................... 326.4.1.5 ADC Multiplexer............................................................................................................................. 326.4.1.6 IO Port Characteristics................................................................................................................... 32

6.4.2 Digital Part............................................................................................................................................. 326.4.2.1 Base Addresses (Memory Map).....................................................................................................326.4.2.2 Memory IPs.................................................................................................................................... 33

6.4.2.2.1 FLASH................................................................................................................................... 336.4.2.2.2 SRAM.................................................................................................................................... 33

6.4.2.3 System Start-up............................................................................................................................. 346.4.2.4 CPU - H430................................................................................................................................... 36

6.4.2.4.1 CPU Registers....................................................................................................................... 38




6.4.2.4.2 Addressing Modes.................................................................................................................406.4.2.4.3 Instruction Set........................................................................................................................436.4.2.4.4 Instruction Cycle Counts........................................................................................................486.4.2.4.5 JTAG Debug Interface...........................................................................................................49

6.4.2.5 Sub Parts....................................................................................................................................... 506.4.2.5.1 Vector Interrupt Control Module (VIC)....................................................................................506.4.2.5.2 Watchdog Module (WDOG)...................................................................................................546.4.2.5.3 Multiplier Module (H430_MUL)..............................................................................................576.4.2.5.4 Divider Module (DIVIDER).....................................................................................................616.4.2.5.5 System State Module (SYS_STATE).....................................................................................646.4.2.5.6 Timer Module (TIMER)..........................................................................................................696.4.2.5.7 LIN-SCI Module (SCI)............................................................................................................736.4.2.5.8 GPIO Module (GPIO).............................................................................................................866.4.2.5.9 Capture Compare Timer Module (CCTIMER)........................................................................906.4.2.5.10 ADC Control Module (ADC_CTRL)......................................................................................986.4.2.5.11 PWM Module (PWM).........................................................................................................1096.4.2.5.12 HV Control Module (HV_CTRL).........................................................................................1206.4.2.5.13 FLASH Control Module (FLASH_CTRL)............................................................................128

7 Package Reference............................................................................................................................................. 1348 General................................................................................................................................................................ 135

8.1 WARNING - Life Support Applications Policy..............................................................................................1358.2 General Disclaimer...................................................................................................................................... 1358.3 Application Disclaimer.................................................................................................................................. 135

9 Contact Information.............................................................................................................................................. 13610 Contents............................................................................................................................................................. 137

Illustration IndexFigure 6.1-1: Block Diagram..................................................................................................................................... 17Figure 6.3.3.1-1: LIN 2.2 physical layer timing..........................................................................................................19Figure 6.3.3.3-1: LIN wake up at rising edge if VDD3 is off.......................................................................................20Figure 6.3.4-1: single_BSM_AA_principle................................................................................................................21Figure 6.3.4-2: LIN Bus auto addressing architecture...............................................................................................22Figure 6.3.4-3: Flowchart auto addressing process..................................................................................................23Figure 6.3.4-4: Timing diagram auto addressing process.........................................................................................24Figure 6.3.7-1: spi data............................................................................................................................................. 25Figure 6.3.7-2: spi timing........................................................................................................................................... 25Figure 6.4-1: Functional Diagram.............................................................................................................................. 29Figure 6.4.1-1: Analog Block Diagram...................................................................................................................... 30Figure 6.4.2.3-1: boot code flow chart....................................................................................................................... 35Figure 6.4.2.4-1: H430 Environment Example..........................................................................................................36Figure 6.4.2.4.3-1: Instruction Coding.......................................................................................................................43Figure 6.4.2.4.4-1: Cycle Count Table...................................................................................................................... 48Figure 6.4.2.5.1-1: VIC logic structure......................................................................................................................50Figure 6.4.2.5.1-2: Two stage interrupt system structure..........................................................................................51Figure 6.4.2.5.2-1: Timing......................................................................................................................................... 54Figure 6.4.2.5.3-1: Multiplier Structure...................................................................................................................... 58Figure 6.4.2.5.7-1: SCI block diagram......................................................................................................................73Figure 6.4.2.5.8-1: Structure..................................................................................................................................... 86Figure 6.4.2.5.9-1: Structure..................................................................................................................................... 90Figure 6.4.2.5.10-1: Structure................................................................................................................................... 98Figure 6.4.2.5.10-2: Cyclic Measurement Timing......................................................................................................99Figure 6.4.2.5.10-3: Memory Map Example............................................................................................................100Figure 6.4.2.5.11-1: Structure................................................................................................................................. 109Figure 6.4.2.5.11-2: Relation ship of output duty cycle to stop-start.......................................................................110Figure 6.4.2.5.11-3: PWM termination.................................................................................................................... 110




Figure 6.4.2.5.11-4: PWM output behavior in relation to the setting of start and stop(1)........................................111Figure 6.4.2.5.11-5: PWM output behavior in relation to the setting of start and stop(2)........................................111Figure 6.4.2.5.12-1: Structure................................................................................................................................. 120Figure 6.4.2.5.12-2: SPI Shift Protocol....................................................................................................................121Figure 6.4.2.5.12-3: SPI Timing Diagram................................................................................................................122Figure 6.4.2.5.12-4: single SPI_SEND request.......................................................................................................122Figure 6.4.2.5.12-5: dual SPI_SEND request with ready_wr polling.......................................................................123Figure 6.4.2.5.12-6: dual SPI_SEND request with ready_rd polling........................................................................123Figure 7-1: Package Outline................................................................................................................................... 134



Documents

LIN Controller with Position Detection E521 Controller with Position Detection E521.31 PRODUCTION DATA – Oct 6, 2015 Pin Description No Name Type Description 1 IO0 D_IO GPIO / JTAG