LOGIC SYSTEM AND DESIGN - Yolamnitians.yolasite.com/resources/LSD Lab Manual Scan.pdf · LOGIC SYSTEM AND DESIGN LAB MANUAL (scan) Computer ... Binary Adder/ Subtractor ... Flip Flops

LOGIC

SYSTEM

AND DESIGN

LAB MANUAL (scan) Computer (2010-2014) Branch

Third Semester

rilffF5

INSTRUCTION IVIANUALS

FOR

IUODULES OFDIGITAL I.AB

EXPERIMENTS

2245, OPP. DHULA HOUSE BAPU BAZAR, JAIPUR - 302 OO3E : (OFF.) 2579523,2572194,(RES.) ZST0EI}I

E,MAI L : sujataj prl @hotmail.com

INDEXDecriPtion of Module

Logic Gates

Universal Gates - NAND / NOR Gates

EX-OR Gate lmPlimentation

EX-OR Gate APPlications

Demorgan's Theorem

Code Conversion (Binary to Gray & Gray to Binary)

Code Conversion (Binary to Excess - 3 Codes)

Binary Adder/ Subtractor

Encoder/ Decoder (8 to 3 Line Encoder' 3 to 8 Line Decoder)

Multiplexer/ Demultiplexer (4.1 Line Multiplexei & 1:4 Line Demultiplexer)

Flip Flops (RS, D, JK & T Type Flip Flops)

4-Bit Shift Register (Serial in Parallel Out)

4-Bit Synchronous Binary Counter (UP Counter)

4-Bit Binary Ripple Counter (UP/ DOWN Counter)

BCD to 7-Segement Decoder

Digitalto Analog Converter (R-2R Ladcjer Network)

_lC's Pin Confi gurations

Page No'

?

o

8

10

11

14

16

1 8

21

23

25

28

30

31

32

v36

Page No. Z 39

INSTRUCTION MANUALFOR

Logic Gates

OBJECTIVE : To study Operation of all Logic Gates'

Modure Description : Modure provided with berow mentioned rc's with Logic Diagram printed

on the front panel & connections brought out at 2mm sockets'

ComPonents

1. lC 7408 2 inPutAND Gate'

2. lC743?2 inPutOR Gate'

3. \C74OO2 inPut NAND Gate'

4. lC74O22 inPut NOR Gate'

5. 1C74862 inPut EX-OR Gate'

6. 1C7404 NOTGate'

QuantitY

1

11I

14

I

4

PROCEDURE:

1. connect +5V DC supply & GND point from the Digital Logic Trainer to the supply terminals of

module.

2. Setthe Digital Logic Trainer in TTL mode'

AND Gate

3. ConnectAl & B1 input terminals to Logic outputs of Digital Lab Trainer'

4. Observe the logic ouiput Y1 on Logic lndicator section of Digital Lab Trainer.

5. Verify Truth Table of AND Gate.

NAND Gate

6. Connect A4 & 84 input terminals to Logic outputs of Digital Lab Trainer.

7. Observe the logic outputY4 on Logic Indicator section of Digital Lab Trainer.

8. VerifyTruth Table of NAND Gate.

OR Gate

9. Connect42 & 82 input terminals to Logic outputs of Digital Lab Trainer.

1 0. Observe the logic output Y2 on Logic Indicator ser, tion of Digital Lab Trainer.

11. Verify Truth Table of OR Gate.

Page No. 3/ 39

Y

5l., Y

" G.)

" GOR GATE

NOT GATE

INPUT 1 INPUT 2 OUTPUT

A B o0

0

1

1

0

1

0

1

1

1

1

0

NAND GATE


A B oU

0

1

1

0

1

0 '

1

't

0

0

0

NOR GATE

AND GATE

NOR GATE

NAND GATE

EX-OR GATE


A B o0

0

I

1

0

1

0

1

0

0

0

1

AND GATE


A B on

0

1

1

0

1

0

1

v

1

1

1

OR GATE


A B o0

0

1

1

0

1

0

1

0

1

1

0

EX-OR GATE

INPUT OUTPUT

0 1

1 0

NOT GATE

P a g e N o 4 / 3 9

*r '

i-lOR Gate

12. ConnectA5 & 85 input terminals to Logic outputs of Digital Lab Trainer'

13 Observe the logic output Y5 on Logic lndicator section of Digital Lab Trainer'

14. V'erifyTruth -rable of NOR Gate'

EX-ORGate

1 5 . C o n n e c t A 3 & 8 3 i n p u t t e r m i n a l s t o L o g i c o u t p u t s o f D i g i t a l L a b T r a i n e r .

16. observe the logic output Y3 on Logic lndicator section of Digital Lab Trainer'

17. VerifyTruth Table of EX-OR Gate'

NOT Gate

1g. connectAo input terminal to logic output of Digital Lab Trainer.

19. Observe the logic outputYO on Logic Indicator section of Digital Lab Trainer'

20. VerifY Truth Table of NOT Gate.

.f

Page No. 5/ 39

INSTRUCTION MANUALFOR,

Universat Gates - NAND / NOR Gates

OBJECTIVE : To study the NAND & NOR Gates as Universal Gates'

Modure Description : Modure provided with berow mentioned rc's with Logic Diagram printed


Quad 2-input NAND Gate TTL lC-741S00

Quad 2-input NOR Gate TTL lC-74LS02

Ti-re ExPeriment lncludes

1 .

2 .

3.

4.

5.

6.

7.

8.

AND gate Using NAND Gates'

OR Gate Using NAND Gates'

NOR Gate Using NAND Gates.

NOT Gate Using NAND Gates'

NAND Gate Using NOR Gates.

NOT Gate Using NOR Gates.

OR Gate Using NOR Gates.

AND Gate Using NOR Gates.

Mddule Panel

.'l""

IA5

B 5

A5

86

Page No. 6/ 39


A B o

0

0

1

1

0

1

0

1

0

0

0

1

AND GATE

Truth Table:-


A B o0

0

1

1

0

1

0

1

0

1

1

1

OR GATE

PROGEDURE:

l . C o n n e c t t h e + 5 r / D C s u p p | y & G r o u n d f r o m D i g i t a | L a b T r a i n e r t o

the module Points i,e + 5V & GND.

2. Set ihe Digital Lab Trainer ln TTL mode.

3. Connect the logic inputs from the Dlgital Lab Trainer to the module points A1 & B1 & verify the

truth table of AND Gate output Y1.

4. Apply the procedure 3 for

" oR gate using NAND Gates; Apply inputs at A3 & 83 and observe at Y3

* NOR (ate using NAND Gates; Apply inputs at 42 & 82 and observe at Y2.

* NOT gate using NAND Gates; Apply inputs atA4 & observe at Y4.

* NAND gate using NOR Gates; Apply inputs atA5 & 85 and observe at Y5.

* NOT gate using NOR Gates; Apply inputs at A7 & observe at Y7.

* oR gtae using NoR Gates; Apply inputs at A6 & 86 and observe at Y6.

. AND gate using NOR Gates; Apply inputs atAS & BB and observe at YB.

INPUT OUTPUT

0 1

1 0

NOT GATE


A B o

0

0

1

1

0

1

0

1

1,l

1

0

NAND GATE


A B o

0

0

1

1

0

I

0

1

1

0

0

0

NOR GATE

Page No. 7/ 39


EX-OR Gate lmplementation

OBJECTTVE : EX-OR Gate lmplementation as ODD Parity Generator & Even Farity Generator.

Module Descript ion : Module Provided with below mentioned lc 's with Logic Diagram printed

on the front panel & connect ions brought out at 2mm sockets.

Quad 2 InPut LX-OR Gate

Hex. lnverter

Quad 2 InPut OR Gate

Module Desiqne

- 74LS86

- 74LS 04

-74L532.

EX-OR GSTE I}lP tEI'IEHT6TIO II

Truth Table:-

A B c OUTPUT

0

0

0

0

1At

1

1

0

0

1

1

0

0

1

1

0

1

0

I

0

1

0

1

1

0

0

1

0

1

1

0

FOR ODD PARITY GENERATOR

A B c OUTPUT

0

0

0

0

1

1

1

1

0

0

1

1

0

0,l

1

0' 1

0

1

0

1

0,l

0

1

1

1

1

1

0

I

FOR EVEN PARITY GENERATOR

Page No. 8/39

%""t tn"+5VDCsupp|y&GroundfromDig i ta iLabTra iner tothemodulepoints i ,e+5V&

GND.

Z. Set the Digiial Lab Trainer in TTL mode

3. connect the logic inputs from the main module to the module points A & B & c verify the truth table

of ODD ParitY Generator OutPut'

4 .App|y ineSameprocedureforEvenPar i tyGenerator&Ver i fy i t 'sTruthTable.

Page No. 9/ 39

INSTRUETION MANUAL

FOR

EX-OR Gate APP|ications

oBJEGTIVE:TostudyEXoRgateApp| icat ionasbinarywordComparator .

Module Description : Module Provided with below mentioned lC's with Logic Diagram printed


Quad 2-lnPut EX-OR Gate

Hex Inverter

Dual4-lnput NAND Gate

- 74LS86

- 74LS 04

- 74LS20

Module Desiqn

1. Connect the +5V DC supply & Ground from Digital Lab Trainer to the module

GND.

2. Setthe Digital Lab Trainer in TTL mode.

3. Connect the logic inputs from the Digital Lab Trainer to the module pointsA, B,

Also connect output logic to one of the terminal of I bit LED Display'

points i,e + 5V &

C , D , E , F , G & H .

l A c E G lFirstword

| ' lur-.oilo 'l

When First Word = Second Word the comparator output is Low i,e LED glow's Green & when First

word not equal Second Word the comprater O/P is High i.e. LED glow's RED .

PageNo.10/39

I

2

INSTRUCTION MANUALFCR

Demorgan's Theorenr

OBJECTIVE : To prove Demorgan's Theorem

Modrr le Descript ion : Module Provided with below mentioned

on the front panel & connections brought out at 2mm sockets"

lC's with Logic Diagram Printed

Tripple 3-lnPut AND Gate

Quad, 3lnPut NOR Gate

Hex inverter

- 741511

-74L527

- 74LS04

Module Design

Logic Gircuit for Demorgan's Theorem - 1

A.B.C = A+B+G

LT

$ a n

f , eZ C TI

OUTPUT

A+E+e

TzOUTPUT

. J

PageNo. 1 ' l i 39

ABC A+B+C

1

I

1

1

I

1

1

0

1

\

1

1

1

1

1

0

0

0

0

0

0

0

0'l

0 0 ' 1 1 1

0 1 1 ' l o

1 0 1 0 1

1 1 1 0 0

0 0 0 1 1

0 1 0 1 0

1 0 0 0 1

1 1 0 0 0

0

0

0

0

1

1

1

1

Truth Table:

Logic Circuit

A.B'C

' g )FfL4

for Demorgan's Theorem - 2

= A+B+C

ABc

TrOUTPUT

A-E.E

TZOUTPUT

A.B+-G -n.-e3 '

1 1

O 0

O 0

O 0

O 0

O 0

o 00 0

A+B+C

0

1

1,l

1

1

1

1

,

0

1

0

I

0

1

0

B

1

1

0

0

1

1

0

0

0

0

0

0

1

1

1

1

A B C A

0 0 1

0 1 1

1 0 1

1 1 1

0 0 0

0 1 0

1 0 0

1 1 0

Page No. 121 39

-J

PROCEDURE:

1. Connect tne

GND.

+5V DC supply & Ground from Digital Lab Trainer to the module points i'e + 5V &

Setthe Digital Lab Trainer in TTL mode'

Make the circuit for Demorgan's Theorem 1 and connect the logic inputs atA5, 85 & c5 and their

compl imentstoA6'86&C6'Respect ive ly f romsBi tDataSwi tchesofDig i ta |LabTra iner .The

output logic is observed on LED Display section of Digital Lab Trainer'

Verify the Truth Table for Demorgan's Theorem 1

Now make the connections according to circuit for Demorgan Theorem 2 and connect the logic

inputs at 46, 86 &. C6. Also their compliments to A5, 85 & C5. The output logic is observed on

LED Display section of Digital Lab Trainer.

Verify theTruth Table for Demorgan's Theorem 2'

Page No. 1 3/ 39

INSTRUCTICN MANi.' 'ALFOR

Code Conversion (Binary to Gray & Gray to Binary)

oBJECTIVE : To study Binary to Gray Code conversion & Gray to Binary code conversion'

M o d u r e D e s c r i p t i o n : M o d u r e p r o v i d e d w i t h b e r o w m e n t i o n e d r c ' s w i t h L o g i c D i a g r a m p r i n t e d


tC74862 inPut EX-OR Gate 2 Nos.

m"Module Diagram: p,ffiot (oDE convERslgn tBtltf,RY Tg cR6Y s cRflY To BlltgRY) NAFS

DE- 06ISO 9001:2000cdlfad cdFny

{MSB) (MsB)

G 3 -

{MSBI

GRAY TO BINARY

8 0 1

_ lBINARY TO GRAY

Truth Table:

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0 0

0 , 0

0 1

0 1

1 1

1 1

1 0

1 0

i o1 0

1 1

1 1

0 1

0 1

0 0

0 0

0

0

0

0

0

0

0

0

1

1

1

1,l

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1,l

0

0

0

0,l

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

1

0

1

0

1

0

1

0

1

BINARY TO GREY CODE CONVERSION Page No. 14139

Connect the +5V

GND.

Set the Digital Lab Trainer in TTL mode

BCD to GraY Gode :

? Connect the logic inputs from the Logic outputs of Digital Lab Trainer to the module points A' B' C

& D. Also connect output logics Qo, Q", Q" & Qo to the terminals of B bit LED Display section of

Digital Lab Trainer.

Verify the Truth Table.

Gray to BGD Code :

3. Connect the logic inputs from the Logic outputs of Digital Lab Trainer to the module points G0, G1,

G2 & G3. Atso connect output logics 80, 81,B;2& 83 to the terminals of B bit LED Display section

of DigitalLabTrainer.

4. VerifY the Truth Table.

D C s u p p l y & G r o u n d f r o m D i g i t a | L a b T r a i n e r t o t h e m o d u | e p o i n t s i ' e + 5 V &

G3 G2 G1 GO B1 BO83 82

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

' 0

0

0

0

1

1

1

1

0

0

0

0

1AI

1

1

0 '

0

1

1

0

0

1

1

0

0

1

1

0'

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

1

1

1

1

0

0

1

1

0

0

0

0

1

1

0

1,l

0

1

0

0

1

1

0

0

1

0

1

1

0

0 . 0

0 0

0 0

0 0

0 1

0 1

0 1

0 1

1 1

1 1

1 1

1 1

1 0

t 0

1 0

1 0

GREY TO BINARY CODE CONVERSION

J

Page No. 1 5/ 39

INSTRUCTION MANUALF O R

Code Gonversion (Binary to Excess-3 Codes)

OBJECTIVE : To study Binary to Excess -3 Code Conversion'

Module Description : Module Provided with below mentioned lC's with Logic Diagram printed

on the front panel & connections brought out at 2mm sockets.

1 .

2.

3.

GomPonents

lr}74322 inPut OR Gate.

lC 7408 2 inPutAND Gate

tC7404 NotGate

Module Diagram:

Truth Table:

Quantity

I

1

1

Page No. 1 6/ 39

coDE cotwERsloll{ BCDTO EXCESS-3 (ODES I

EO'l

0

1

0

1

0

I

0

1

0 r

1

0

1

H}

0

0

0

0

0

1

1

I

1

1

1

I

1

E2

0- 1

,l

1

1 1

0 0

0 0

0 1

0 1

. 1 0

1 0

1 ' , 1

1 1

E1

I

0

0

1

EKI

0

0

0

0

0

0

0

0

1

1

1

1

1

82

0

0

0

0

1

1' 1

1

0

0

0

0

1

B1

0

0

1

1

0

0

1

1

0

0

1

1

0

BO

0,l

0

1

0

1

0

1

0

1

0

1

0

PROCEDURE:.r connect ihe +5V DC supply & Ground from Digital Lab Trainer to the rnodule points i'e + 5V &

GND.

Setthe Digital Lab Trainer in TTL mode'

connect the logic inputs from the Logic outputs of Digital Lab Trainer to the module points B0' 81 '

82 & 83. Also connect output logics E0, E|, E2& E3 t'o the terminals of B bit LED Display section

of Digital LabTrainer'

Verifythe Truth Table'

PageNo.17139

INSTRUCTiON MANUALFOR

Bi narY Adder/ Su btractor

oBJEGT|VE:TostudyBinaryAdder/Subtractorusing|C7483.

Module Description : Module Provided with Logic Diagram printed on the front panel& connections

of lnputs & Outputs brought out at 2mm sockets'

THEORY:

For 4 bit numbersAddition or Subtraction, Parallel binary adder & subtractors are used here' For

adding Two 4 bit numbers we need 4 full adder connected in parallel. The two numbers being added are43,

M, A1, A0 & 83, FJ2,F,1, BO & the sum is s4, s3, s2, sl, s0. where s4 indicates overflow carry if the

sum exceeds from bits'

For subtracting teo 4 bit numbers, we need four Full subtractors. we can directly subtract 4 bit

numbers i.e. We can subtract 4 bit numbers i.e. We can subtract 83 82 81 B0 from A3' A2' A1' A0'

Module Diagram:

E>htY

[D

BfnsRY ADogR I SOBTRd(TOB

"*lSt

Sz

St

S!

,,

. 'S"'3

ere* k

.3,30{r k

.3ee* k(tsB) =

OUTPU'INDICATOR

. J

Page No. 1 8/ 39

Logic Gircuit for 4 Bit Adder : OUTPUT INDICATOR

LoGIG'0 '

Logic Circuit for 4 Bit Subtractor :

FIRST I'YORD INPUT SECOND YIIORD INPUT

PROCEDURE:

1. Connect the +5V DC supply & Ground from Digital Lab Trainer to the module points i,e + 5v &

GND.

2. Setthe Digital Lab Trainer in TTL mode'

3. Connect the circuit as show in Logic Circuit 4 BitAdciition i.e. connect 4 Logic outputs from Digital

Logic Trainer to the inputs of lC 7483, First Word lnput'

Connectother4Logic inputstotheBinputs(SecondWord)of lC7483'

Connect the Logic'0' to CARRY (CrN) input through patchcoard'

Apply Binery i/p's at First & second word & observe the corresponding Addition output at output

indicators.Page No. '19/ 39

4.

5.

o .

lc 7483 13

8 1 0 ' { 6 4 7 ' ' 1

A3 lA2 lA{ Bz ler lBo

FIRST WORD INPUT SECOND WORD INPUT

OUTPUT INDICATOR

{ 5 2 6 9

lG 7483 13

8 1 0 1 6

For ExamPle:-

Add

0 1 0

A 3 p a A 1

1

BO1 & 1 0

AO 83 82

5

11

1

B1

i i )

I

1

1

11

I

0

1

I

0

0

1

I

1

1

0

0

1

1

1

For 4 Bit Subtractor: ,

Note: Alwaysapplyhighernumberinputat"A', inputascompareto"B'input' l fword"B"ismoreposit ive

as compared to word 'A" in that case this circuit will show wrong answers'

7. connect the circuit according to Lcgic circuit For 4-Bit subtractor- Coonect 4 logic inputs to the

"A" inputs of lC 7483.

connect other4 logic inputs to the "B" word of lc 7483 as shown in Figure'

Apply Logic'1' to carry (ClN) i.e' +5 VDC through patchcoard'

This subtractorcircuitcan show maximum 15 numbers cutput i.e, 1111 if subtraction remains in

plu.s position i.e..inputsAwillremains positive as compared to B inputs' ignore cont' indicator'

For ExamPle:-

Subtractor

A 3 p a A 1

1 1 1

1

0

1

0

1

0

1

0

1

0

0

1

Page No. 20/ 39

1 815

8.

9.

10 .

AO

I

BO

0

83 82 81

0 0 q

ip15

0

0

0

0

0

I

4

1 5


Encoder/ Decoder (8 to 3 Line Encoder & 3 to 8 Line Decoder)

OBJECTIVE : To study Encoder / Decoder (8 to 3 Line Encoder, 3 to 8 Line Decocier)



Component

1. lC 741532 2 input OR Gate

2. lC 741511 3 inputAND Gate

3. lC 74LS04 Hex Inverter

Logic Diagram:

Quantity

3

1

o1

v

{)3

04

D€

m

EilCODER/DECODER{8 TO 3 UttE E|(ODER"3 TO E UNE DECODER I

8 TO 3 LINE ENCODER

DO

D1

m

D3

tr

D5

D6

D7ITruth Table for 8 to 3 Line {Encoder) :

Page No. 21l39

BO

rAND

t-l l-F

ANOGATE

t-ANOGATE

B1

AND -

GATE

AND

+rL_+r ANO

F AND

E ANDGATE

3 TO 8 LINE DECODER

Y ZD 5 D 6 D 7 X

0 0 0 , 00 0 0 0

0 0 0 0

0 0 0 0

0 0 0 1

1 0 0 1

0 1 0 1

0 0 1 1

Dt

0

0

0

0

1

0

D2

0

0

1

0

0

0

0

0

D3

0

0

0

1

0

0

DO D1

1 0

0 1

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 1

1 0

1 1

0 0

0 1

1 0

1 1

0 0

0 0

Truth Table for 3 to I Line (Decoder) :

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

NOTE : Four Input OR Gate is designed using three 2 input OR Gates.

1, Connect the +5V DC supply & Grounci from Digital Lab Trainer to the module points i,e + 5r,/ &GND.

2. Setthe Digital Lab Trainer in TTL mode.

8 to 3 Encoder :

Connect the logic inputs from the Logic outputs of Digital Lab Trainer to the rnodule points D0, D1 ,D2,'D3, D4, D5, DO & D7. Also.Connect output logics X, Y & Z io the terminalsof 8 bit LED Displaysection of Digital Lab Trainer.Verify the Truth Table for g to 3 Encoder.

to 8 Decoder:

connect the iogic inputs from the Logic outputs of Digital Lab Trainerto the module points 80, B1& 82' Also connect output logics D0, D1, D2, D3, D4, D5, D6 & D7 to the terminals of g bit LEDDisplay section of Digital Lab Trainer.Verify the Truth Table 3 to g Decoder.

BZ Bl B0 Do D1 D2 D3 D'l Ds D6 D7

___-J

Page No. 22l 39


Multiplexer/ Demultiplexer (4:1 Line Multiplexer & 1:4 Line Demultiplexer)

OB;ECTIVE : To study Multiplexer / Demultiplexer (4 -1 Line Mux, 14 Line Demux.)



1 .

2.

ComPonent

lC 7415153 (4:1 Line Multiplexer)

tC 741S155 (1:4 Line Demult iplexer)

QuantityIt

1

Multiplexer

.l: . ,, Multiplexer means many into one i.e multiplexer is a logic circuitwhich has many inputs butsingle

output. A muitiplexer accepts several data inputs but allow only ane of them at a time to get through to the

output.

l-ogic Gircuit for 4:1 Multiplexer : Ao

Bo

Co

DO

INPUT OUTPUTSr. No STROBESELECTINPUT

1

2

3

4

GO

0

0

0

0

S1

0

0

1

1

s00

1

0

1

YO

AO

BO

c0DO

To perform 4 to 1 line multiplexer experiment, We have used lC 741sg.lt has 4 Line inputs (A0; 80,D0) & only one output YO G0 is the Strobe input (Active low) Sl, & S0 are select lines. these tines

one out of from inputs at output for e.g. if we will apply 00 at 51 & S0 first input 41 will be selected

6 I C

7u 4

4 . 1 t

f,

s 3't4 2

. __J

Page No. 23l 39

Demult iPlexer

The demultiplexer perform the reverse operation of multiplexer. lt accepts a single input & distributers

it over several outPuts'

Logic Gircui t for 1:4 Demult iplexer :

DATAINPUT

STROBE

OUTPUTDICATORS

SELECT STiNPUT

So

Truth Table For 'l:4 Demultiplexer :

INPUT OUTPUTSr. No STROBE SELECT INPUT

1

2

3

4

Ga

0

0

u

0

s10

0

1,,

SO

0

1

0

1

Y

YO

Y1

Y2

Y3

Connect the +5V DC supply & Ground from Digital Lab Trainer to the module points i,e. + 5V &GND.

Setthe Digital Lab Trainer in TTL mode.

to 1 Line Multiplexer :Connect the logic inputs from the Logic outputs of Digital Lab Trainer to the Input points of Multiplexercircuit using lc 74LS 1 53 & output at terminal of 8 bit LED Dispray section of Digital Lab rrainer.Verify the Truth Table for 4 to 1 Multiplexer.

to 4 Line Demult iplexer :Apply logic '1' (+sv DC) at input terminal of Demultiptexer & connect output terminals y0, y1, y2& Y3 to B bit LED Display section of Digital l_ab Trainei.Verify the Truth Table for 1 to 4 Demultiplexer.

: Here you realise from Truth Table that the output is Logic Low at the selected channel & the othershow Logic High this is due to the fact that the output treminal acts as inverter of input data.

1 6 I1 - ,' I C

I2 6

41

3 _ 5)f,

- . --- ] ' - - ] , . . . ' -F

Page No. 24l 39


Fl ip Flops (RS, D, JK, T Fl ip Flops)

OBJECTIVE : To study Flip - Flops {R-S, D, J-K & T Type Flip Flops)

Module Descript ion : Module Provided with below mentioned lG's with Logic Diagram printed


1. lC 741576 (Dual JK FliP FloP)

,2. lC 741500 (Quad 2 Input NAND Gate)

3. lC 741510 (Dual3 Input NAND Gate)

'4'. lc74LS74 (DualD Flip Flop)

:Module Design

Page N0.25l39

JK FLIP FLOP

L

H

L

H

H

H

H

H

L

t-

H

H

H

H

H I L

L I H

H I H

o , l qH l r -

L I H

tobe used

L

H

L

H

H

H

L

H

H

L

H

a,

J K F l i n F

INPUT OUTPUT

PRESET CLEAR CLOCK J K a o

L

H

L

H

H

H

H

H

L

L

H

H

H

H

X

X

X

-rL_J1_

_rL

JL

X

X

X

L

H

L

H

X

X

X

L

L

H

H

qH

L

TO

L

H

H

qL

I HI

GGLE

PROGEDURE:

1. Connect the +5V DC supply & Ground from Digital Lab Trainer to the module points i,e. + 5V &

GND.

2. setthe Digital LabTrainer in TTL mode.

R-S Fl ip Flop:

Connect the R, S, PR., CLR terminals to the Logic outputs of Digital Lab Trainer and Clock terminal

to Pulser Switch (Active High) of Digital Logic Trainer.

Connect O & O terminals to the output indicators (B Bit LED Display Section of Digital Logic

Trainer).

Verify the Truth Table for RS Flip Ftops.

F l ip F lop:

Connect the J, K, PR & CLR terminals to the Logic outputs of Digital Lab Trainer and Clockterminal to Pulser Switch (Active High) of Digital Logic Trainer.Connect O & a terminals to the output indicators (8 Bit LED Display Section of Digital LogicTrainer).

Verify the Truth Table for JK Flip Flops.

Type Ftip Ftop :Connect the D, PR & CLR terminals to the Logic outputs of Digital Lab Trainer and Clock terminalto Pulser Switch (Active High) of Digital LogicTrainer.Connect O & E- terminals to the output indicators (B Bit LED Display Section of Digitat LogicTrainer).

Verify the Truth Table for D Flip Flops.

T F l ip F lop

INPUT OUTPUT

T o E-1 Toggle

Page No. 26/ 39

"T'Type FtiP FloP :

12. Now make connection for toggle Ftip Flop by appty Pulse at Clock terminaland logic High input at

PR & CLR terminals'

13. ConnecJ o & o terminals to the output indicators (B Bit LED Display Section of Digital Logic

Trainer)'

14. Verifl the Truth Table fcrT Flip Flops'

NOTE: Logic'f is internally given to the JK terminals'

,9.iii=,i.i1i":

Page No. 27l39

, , - - - J


4-Bit Shift Register (serial in Parallel Out)

oBJECTIVE : To study 4-Bit shi f t Register (ser ial in Paral lelout using lc 74LS95)

fi *oou," Description : Module Provided with Logic Diagram printed on the front panel & connections

brought out at 2mm sockets'

Module Design

Oa

t c o. 7€5

c

B

(MSB)

,,3m

3m la{LsB)

A SHIFT register is basicaliy a storage medium where one or more binary words may be stored.

a counter, it is also made up of binary storage elements, usually flip-flops. These elements are

in such a way that the bit stored there can be moved or shifted from one element to another

element. All of the storage registers are activated simultaneously by a single input'CLOCK'or

IFT' pulse. When a shift puise is applied, the data stored in the shift register is moved one position

to left or to right as desired.

Page No. 28/ 39

i

I

SHIFT RESISTORS

OUTPUT INDIGATORS

SERIEL INPUT

9 Q A Q s Q c e o14

a" rc 7495LOGIC INPUTS 7

I A B c D

Log ic C i r cu i t :

PROCEDURE:

1' Connect the +5y DC suppiy & Ground from Digital Lab Trainer to the module points i,e. + 5V &GND.

2.

J .

4.

5.

6 .

7 .

8.

9.

Set the Digital Lab Trainer in TTL mode.Connect the circuit as shown in Logic Circuit using patchcords.connect clock input to pulser switch (Active HIGH) of Digital Logic Trainer.Connect the terminals D, MODE & Serial lnput to Logic outputs from Digital Lab Trainer, put Serialinput at Logic '1..

Put the mode control switch to logic'0' to enable the lC perform Right Shift operation. put D inputto Ground (Logic'0').

Put serial Input to logic high (+5V DC). Apply 4 clock pulses from pulser switch one bv one andrecord the final output levels i,e. eA eB eC eD = 11j1.Set serial input to ground. Apply 4 clock pulses one by one and note down the direction in whichthe DATAshift (Output Data shift in Right Direction).Put mode control switch to Logic'1'to enable the lC perform Left Shift operation. Also put the Dinput to Logic '1'. Apply 4 clock pulses one by one and record the final output leveli ,e . QAQB QC QD = 1111

Set D input to Logic'0'i,e. GND. Apply 4 clock pulses one by one ote down the direction in whichthe DATAshift (Output Data shift in Left Direction).

10.

Page No. 29l 39

INSTRUCTION li ' iANUALFOR

4-Bit Synchronous Binary Counter (UP Counter)

OBJECTIVE : To study 4-BitSynchronous Binary Counter (UP Counter) using lG 74LS163.

Module Descripticn : Module Provided with Logic Diagram printed on the front panel & connections

brought out at 2mm sockets.

4 BtT SYNCHROTTOUS Bttt6RY COUNTER

Module Design

lC 74LS163 is an Synchronous 4-Bit Binary UP Counter. In this lC their are two separate enable

inputs, ENT & ENP. Setting either of these inputs to Logic '0'stops counting asynchronously. Ripple cany

(RC)output is nonnally at Logic'0'and goes to togic'1'whenever

the counter reaches its highest count. ENT to Logic'0' also

inhibits RC changing from Logic'0'to Logic'1'. By changing

Logic inputs at PA PB PC PD we can also decide the highest

output count.

PROGEDURE:

1 .

2.

3.

4.

5.

o,

7 .

Connect the +5V DC supply & Ground from Digital

Lab Trainer to the module points i,e. + 5V & GND.

Setthe Digital Lab Trainer in TTL mode.

Apply Logic '1 ' ( *5V DC)to ENT ENP & CLR.

Now Starts applying clock pulses through pulser switch

(Active High) of Digital Lab Trainer.

We observe that the Logic Indicators starts glowing in

, the following pattern as shown in Table.

Verify the Truth table.

Connect ABCD terminal to the logic Output terminals

of Digital Logic Trainer.

r l. l

(0P cooltTER)

CK

ENI

ENP

CR

L

OD

Oc

QB

?41 63

G

QD oc QB OA

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0,l

0

1

0

1

0

J

Page No. 30/ 39

I T.ISTRUCTI O N IV1ANUALFOR

4-Bit Binary Rippte Counter (Up/ DOWN Counter)

OBJECTIVE : To study 4-Bit Binary Ripple counter (Up/ DowN counter) using lc 74LS193.

Module Description : Module Provided with Logic Diagram printed on the front panel & connectionsbrought out at 2mm sockets.

Module Design

lc 74LS193 is a synchronous 4-Bit uP/ DowN Binary counter. In this lc, for up counting theclock is applied at count UP terminaland count DowN is connected to Logic,1,. For DowN countingclock is applied at counfDowN terminarwith count-Up connected to Logic,1,.

PROCEDURE:

1' connect the +5y DC supply & Ground from Digital Lab rrainer to the module points i,e. + 5y gGND.

2. Setthe Digitat Lab Trainer in TTL mode.FOR UP-COUNTER:

3. Connect Count-Up terminalto active High pulser terminal Logic ,1, (+SV DC) to Count_DOWNterminal and apply clock pulseslhrough pulser switch.

4' The output indicators grow in the increasing pattern from ,0000, to ,1111 ,.FOR DOWN4OUNTER:

5' Connect count-DowN terminal to Active High pulser terminal Logic ,1, to cK-Up terminal andapply Clock pulses through pulser switch.

6. The output indicators grow in the decreasing pattern from,1111,to ,0000,.

CLOCKINPU'

CLEAR

(,

PUSIJ TO

4 BrT BrItf,Ry RrppLE cguNrER (qp Dowlr cooHTERl

Oo

UP

DN

QB

CR

7413 O^

(MsB)

eree le

.qe+ ^!a{LsB}

P a g e N o . 3 t l 3 9


BCD to 7-Segement Decoder

OBJECTIVE : To study Conversion of BCD Word to 7-Segement Display (Decimal) using lG 74L547.


Module Design- t

BCD TO 7 SEGI,IETIT DECODER

7 SEGMENTDISPLAY

A digital oitpr.v tn"t .it"ritt "i

t a=o a*me ; *rron"u, used to disptay decimat numericalsin digitalsystem. For using the display device the data has to be converted from same binarv code to thecode required for the display.

Truth Tabte :

I

ilD c B A OUTPUT

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

I

Page No 32l39

PROCEDURE:

1' connect the +5y DC supply & Ground from Digi tai Lab rrainer to the module pornts r ,e + 5v &^ r r nL)I\ LJ.

2. Set the Digi tal Lab Trainer in TTL mooe.3' connectA B c D input terminals to Logic outputs from B-Bit data switches of Digi tal Lab rrainer.4 Now verify the truth table for BCD to Z_Segement Decoder

Page No 33/39


Digital to Analog Converter (R-2R Network)

oBJEcrlvE : To study Digitat to Analog converter using R-2R Ladder Network.


Module Design

Formula to R-2R Ladder NetworkVor, = -(RJ 3R) . (V RI Z4l [gb. + 4br+ 26r+ l bol

Where b3, b2, b1, b0 are logic's at terminals D, C, B, A respectivety.

NOTE : We have adjusted the term -(R/ 3R) . (VJ Zol= 0.5V DG. So that the modute work with 0.5VDC as a steps size.

f,

+t2v Dc

-1?\t Oc

R=1 K2R-2K,3R=3K

Page No. 34/ 39

INPUT

MSB LSB

OUTPUT

VOLTAGE

(in DC Votts)A B c D0

0

0

0

0

0

0

0

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

I'l

1

I

0

0

1

1,l

0

0

1

1

0

0

1

1

Il 0, 1

0

I

. 0

-0.00

-0.50

-1.00

-1.50

-2.00

-2.50

-3.00

€.50

4.00-4.50

-5.00

-5.50

.6.00

€.50

-7.00

-7.50

PROGEDURE:

1' connect the +12y & -12v Dc & GND terminals from Digital Labrrainer to the module points i,e.+12V & _12V DC & cND.

2. Setthe Digital Lab Trainer in TTL mode.3' ConnectA B c D terminal to the Logic output terminals of Digital Logic Trainer. ..4' connect a digital Multimeter in 20 VDC range across theAnatog Voltage output terminals X & y5. Nowverify the,truth table.

Page No. 35/39 a

tp

1 4VGG I

1 3 1 2 l l l o 9

' t 2 3 4 5 6

Pin Description of lC 7400

HEX INVERTERPin Description of lC 7408

2.INPUT OR GATE

l a t S n

Ycc

2 - . 3 . 1 ! - . 5 6 - 7

Pin Deseriptlon of !C 74A2

f 2 l L 5 6 7

Pin Description oT lC Z +tl3-INPUT AND GATE

Pin Description

P a g e N o . 3 6 / 3 9

' 2 3 4 5 6 7

Pin Description of iC Z42O

0ulpl1sl - 9 e b c d .

r 5 t l 1 3 r z f l t o . !

6 7D'. Alnputr

i ? 3 4 5 6 7

Pin Description of lC T4B2

Vcc CLR 2Q 2CK 2pR 2e1 4 1 3 1 2 1 1 1 0 9

1 2 3 4 5 6 7I C L R 1 Q 1 C K 1 P R 1 Q 1 0 G N D

Pin Description of lG 7474

^, '; i i ', i i iPin Description rf lC Z4g3

2QI

1 28 C

' tngulr

1 K 1 Q1 6 1 s

2Q 2Q 2J'11 10 g

8r Sr Cor Cit q t { r t l n

E o A o $n t r g I

I

{II

1 2 3 4 5 6 7 81CI( IPR1CLR 1J VCC 2CK zPR2CLRPin Description of lC T4i6

'

tT B/hm nsl


1Q GND 2K1 4 1 3 1 2

PageNo.37 l39

OutFrtr

O( Cl(lq^ O3 Oq Oo Rs ls(Lordt

l 4 R t z . t r E I e

r l ( , 5 s 1


SE^LECI - Ddr Inputs - 6utPu1?G @^ *r zcz zct zco 2vt5 t|n t3 t2 l l to s

r 2 3 a 5 5 7 e

tn,6 tc3 rcz tct tco tv4r,self;n

-.!1L1 tnput: -Putput -


__Otd1l1rtr_ EtLDLR C O r O . O c q t L d

E l 5 t a B n n | 0 t

1 2 t 1 5 6 7* r - A B C O t l o d .ln t-----J Cont.

Itputt

Pin Description of iC 7495

C2 GZ A -OulPuts

Oata Slrobr SEtEf 2tB 2Y2 2Yl ?Y0

1 5 1 1 1 3 1 2 1 1 t 0 9

1 2 3 4 5 5 7 8Detr Strobc SELECI lY3 lYz lYt tYO

Cl Gt A _ Outputs _


triprrlr on$ulr -Ine|rtr -P^ Cr 80ncr Crfrt tqd t bf5 t4 tt 'fz ll t0 I

2 t a s 6 ? {O6 q Ceud Cosot Oc Oo,

Ooqn UpOulgutr -I||)uitt- Outputr


t ? 3 ( 5 6 7 r 0lher CX PA PE pc po Eneblcrr'{, ---&h l|Pstl- P _.

Pin Description of lC 74163 .

Irb

lnpul

5 6

Page No. 38/ 39

FU J Jo Jr L f

B z+

Ffr

O F( r ==- +

(lzFT , Ful 3> o .z zzoz


Ffo.2

(,zFE||t

oo

I

JJ:)z

Fl,rloLlro

7 6

tc 7412 3

Page No. 39/ 39

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LOGIC SYSTEM AND DESIGN - Yolamnitians.yolasite.com/resources/LSD Lab Manual Scan.pdf · LOGIC SYSTEM AND DESIGN LAB MANUAL (scan) Computer ... Binary Adder/ Subtractor ... Flip Flops