1
Implementation circuit using AND - OR gates Implementation
circuit using NAND gates only Implementation circuit using NOR
gates only Full Adder circuit (XOR AND OR) Parity generator &
Parity Checker (XOR) 4-Bit Adder Subtracter ( IC : 83 XOR )
Implementation function using Decoder ( IC : 155 expansion )
Implementation function using MUX ( IC : 151 ) Design circuit using
Flip Flop 4 Bit Counter with Parallel load 4 Bit Shift Register
Random Generator Mod n counter Frequency Divider magnitude
comparator 10 16 20 23 26 27 29 33 38 42 43 44 45 48
2
: 7002 8002 1 Section . : Digital Design .
. .
.
: Breadboard Open Book .
* . 3
- : 1's Complement 0 1 1 0 . : 1's Complement : 2)1001010011 ( 2
)0110101100 ( .
- : 2's Complement 2's Complement : 1 - 1's Complement 1's
Complement 1 . : 2's Complement 2)0000001111( : 1's Complement
2)1111110000( 0 1 1 0 1 : 1's Complement1111110000 +1 0000001000 1
1+1=2 2 (10)2 = (2)10 Binary system 0 1 .
2's Complement 2)0000001111( 2 )0000001000( 2 - 1's Complement :
1 0 1 1 0 . : 2's Complement 2)0000001111( 2)0000001000( .
4
The
rules of Boolean Algebra
0 1 0 1 0 0 1 1
are: AND Operations ()= = = = 0 0 0 1
1 True 1 AND
X X X X
0 1 x x'
= = = =
0 x x 0
0 1 0 1 + + + + 0 0 1 1
OR Operations (+)= = = = 0 1 1 1
1 True 1 OR
x x x x
+ + + +
0 1 x x'
= = = =
x 1 x 1
0' = 1 1' = 0
NOT Operations (')
Associative Law(xy)z = x(yz) = xyz (x+y)+z = x+(y+z) = x+y+z
NOT 0 0 1 1 = x
( x' )'
Distributive Lawx(y+z) = (xy) + (xz) x+(yz) = (x+y) (x+z)
Commutative Lawxy = yx x+y = y+x
Precedencexy = xy xy+z = (xy) + z x+yz = x + (yz)
DeMorgan's Theorem(xy)' = x' + y' (x+y)' = x' y' (NAND)
(NOR)
: x + 0 =x x + x' = 1 x+x=x ( x' )' = x x+1=1 x+y=y+x x +( y +z)
=( x+y ) z x ( y + z ) = x . ( y + z ) = xy + xz ( x + y )' = x' .
y' x + xy = x : + . 1 0 1 0 x . 1 =x x . x' = 0 x.x=x ( x' )' = x
x.0=0 x.y=y.x x . ( y . z ) = xyz x + ( y . z ) = x + yz = ( x + y
) .( x + z ) ( x . y )' = x' + y' x.x+y =x( x+y ) =x
5
: DeMorgan's Theorem (xy)' = x' + y' : (OR) + ( AND)
. ( . ) variables complement (x+y)' = x' y'
:
(AND)
.
( OR) + ( + ) variables complement F= ( x'yz' + x'y'z )' :
.
( OR) + ( + ) complement 1 - F= ( x'yz' )'.( x'y'z )' ( AND)
( AND)
. variable complement 2 - F= ( x + y' + z ) . ( x + y + z' ) (
OR) +
x x.1
x + xy = x + xy = x - 1 : + xy = = = x x x -2 -3 -4
x . (1+y) x . 1
:
ANDing & ORing Venn diagram
x+y
x.y6
Name
Graphic symbol
Algebraic function
Truth Tablex 0 0 1 1 x 0 0 1 1 x 0 1 y 0 1 0 1 y 0 1 0 1 F 1 0 F
0 0 0 1 F 0 1 1 1
AND
F = xy
OR
F=x+y
Inverter
F = x'
Buffer
F=x
x 0 1 x 0 0 1 1 x 0 0 1 1 x 0 0 1 1 x 0 0 1 1 y 0 1 0 1 y 0 1 0
1 y 0 1 0 1 y 0 1 0 1
F 0 1 F 1 1 1 0 F 1 0 0 0 F 0 1 1 0 F 1 0 0 1 7
NAND
F = ( xy )'
NOR
F = ( x + y )'
Exclusive-OR ( XOR )Exclusive-NOR or equivalence
F = xy' + x'y = x+y F = xy + x'y' = ( x + y )'
Logic function :
Logic expression
-
) product of sum
( - ) sum of product ( - : 1 - Boolean Algebra 5 . 2 - : K - Map
Variables .
Logic gates 7 x y x 'y 'xy 'xy
Logic diagram
-
Variables Normal form ' x . y AND gate x inputs y inverter
input AND Complement form y' X AND inverter :
Complement form Logic diagram inverter IC .: ( F = x'y'+x'yz'+yz
:) Simplify : Variable : Boolean Algebra ORing Variable 1 :
diagram: 1 AND gate & 1 OR gate F = x'y'+x'yz'+yz
]=x'y'+y[x'z'+z ])'= x'y'+y[(x'+z)(z+z 1 . )= x'y'+y[(x'+z
=x'y'+yx'+yz =x'[y'+y]+yz 1 ['=x =x'+yz ]+yz ] F = x'y'+x'yz'+yz
=x'[y'+yz']+yz =x'[(y'+y)(y'+z')]+yz ['=x 1 .(y'+z')]+yz : diagram:
3 AND gates & 1 OR gates
=x'(y'+z')+yz =x'y'+x'z'+yz
8
. Logic diagram
: : F = x'y'+x'yz'+yz
: ( Boolean Algebra ) K-map : F=x'+yz Normal form : sum of
product product of sum F ( ) OR ] ( ) AND [ 1 AND gate 1 OR gate
& yz ' x & yz 1 inverter gate : x 'x F y yz z
F=x'y'+x'z'+yz Normal form F ( )OR ( )AND : 3 inverter gates
& 1 OR gate & 3 AND gates :
x
'x
'x'y
y
'y 'z
'x'z yz
F
z
? Implement function F using AND OR gates and test its Truth
table 2- Truth table . : 1- . 3 - Logic diagram gates. . 4 - DC LED
ICs 5 - . Truth table
9
: ? Implement function F = x'y'+x'yz'+yz , using AND OR gates
and test its Truth table : 1 - . F=x'+yz 2 - Truth table : F : 1='
)x( (0=)yz = (1=0+1 =)F=x'+yz F : 0=' )x( (1=)yz = (1=1+0 =)F=x'+yz
yz F x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 yz 0 0 0
1 0 0 0 1 F=x'+yz 1 1 1 1 0 0 0 1
3 - Logic diagram ( Complement form : ) inverter
'x y z1 2
1 3 2
23
3
F
80
yz4 - : ICs & LED & DC
Logic diagram gate IC output input pin IC 23 OR IC 1 Pin ' x 2
Pin 3 Pin AND IC 80 .
: AND & OR Pin Assignments
2-input AND
2-input OR : Vcc 5 Volts . Ground : GND .01
IC 23 80 4 gates Breadboard 5 AND gates . IC
Negative Positive
LED : : LED output . gate output1 output 0 . LED Pin output OR
IC Pin 3 LED GND . LED Positive Negative
IC 5 Volts DC supply LED Ground DC supply LED LED LED . 5 - :
Truth table variables ICs 1 0 . x 1 Node ) 5 Volts DC(Vcc Z 0 NODE
. Ground 1: 0=: x=y=z 1 Pin OR IC ' x 1 ( ) Vcc 2 Pin OR IC 3 Pin
AND IC 1 Pin AND IC y 0 ( )Ground 2 Pin AND IC z 0 ( )Ground 3 Pin
OR IC LED F 0= ( x=y=z LED 1=. ) F 2: 1=: x=1,y=0,z 1 Pin OR IC ' x
0 ( )Ground 2 Pin OR IC 3 Pin AND IC 1Pin AND IC y 0 ( )Ground 2
Pin AND IC z 1 ( )Vcc 3 Pin OR IC LED F 1= ( x=1,y=0,z LED 0=. ) F
.
Breadboard 1 2 : ( 25 )
11
Minterms & Maxterms Variables Y 0 0 1 1 0 0 1 1 Minterms
Term Designation 'x'y'z 0m x'y'z 1m 'x'yz 2m x'yz 3m 'xy'z 4m xy'z
5m 'xyz 6m xyz 7m Maxterms Term Designation x+y+z 0M 'x+y+z 1M
x+y'+z 2M 'x+y'+z 3M x'+y+z 4M 'x'+y+z 5M x'+y'+z 6M 'x'+y'+z
7M
X 0 0 0 0 1 1 1 1
Z 0 1 0 1 0 1 0 1
Truth table . Minterms & Maxterms Minterms 0 1=') x'y'z 1 (
0= x=y=z 0 m . sum of product Maxterms 1 0 ( 1= x=y=z 7 m 0=' )
x'+y'+z . product of sum function Minterms Maxterms : * : Minterms
Minterms 1 : 1 = 6 m1 & m3 & m : sum of product ('F(xyz)=
(m1 , m3 , m6) = )x'y'z + x'yz + xyz * : Maxterms Maxterms 0 : =1 6
m1 & m3 & m : product of sum )'F(xyz)= (M0 . M2 . M4 . M5 .
M7 ) = )x+y+z((x+y'+z)( x'+y+z)( x'+y+z')( x'+y'+z
-
-
-
K-map Variable
Two-Variable mapx 0 0 1 1 y 0 1 0 1 Minterms 'x'y x'y 'xy xy 0m
1m 2m 3m x y 0 x 1 0 0
y 1
'x'y 'x'y
'x'y2
1 3
'x'y
map 22 power . Variables : OR function :( F = x + y ) K-map: : 1
- Truth Table F 1 3 m1 & m2 & m Minterms F 1 . K-map 21
1s 4 2 1 ( 2 ) 1 1 F : 1s x ' x y ' y . F x ( y 3 ) m xy : F ' x
' ( y 0 )m x'y' : F x y x + y : F x y F = x + y 2 - map . map x 1 x
map y 1 y . 1s . F = x + y y x 0 0 1 1 y 0 1 0 1 F=x+y 0 1 1 1 x y
0 x 1 0 0 1
12
1 3
1
1
Three-Variable mapy x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0
1 0 1 0 1 Minterms 'x'y'z x'y'z 'x'yz x'yz 'xy'z xy'z 'xyz xyz 0m
1m 2m 3m 4m 5m 6m 7m x yz 0 x 1 00 'x'y'z 'xy'z 0 4 10 x'y'z xy'z 1
5 11 x'yz xyz 3 7 01 'x'yz 'xyz 2 6
z
map 32 power . Variables : )7,6,4,3( = )F(x,y,z : Minterms F1 .
1 Minterms map 1s 8 4 2 1 map Z' X Z yF = xz' = yz y
0 4
1 5
1 1z
3 7
2 6
x
1
1
31
Four-Variable mapw 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x 0 0 0 0 1 1
1 1 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1
0 1 0 1 0 1 0 1 0 1 Minterms w'x'y'z' w'x'y'z w'x'yz' w'x'yz
w'xy'z' w'xy'z w'xyz' w'xyz wx'y'z' wx'y'z wx'yz' wx'yz wxy'z'
wxy'z wxyz' wxyz m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14
m15 yz wx 00 01 1 w'x'y'z 5 w'xy'z 13 wxy'z 9 wx'y'z z 11 3 w'x'yz
7 w'xyz 15 wxyz y 10 2 w'x'yz' 6 w'xyz' 14 wxyz' x
0 00 w'x'y'z ' 4 01 w'xy'z' 11 12 wxy'z'
w
8 10 wx'y'z'
11 10 wx'yz wx'yz'
1 1w
. Variables power 42 map y Simplify F( w,x,y,z ) =
(0,1,2,4,5,6,8,9,12,13,14) : 1 1 61 8 4 2 Minterms : : map 0 1 3 2
F =y' + w'z' + xz' 1 1 4 12 8
-
1 1 1
5 13 9
7 15 11
1 1
6 x 14 10 Simplify F( w,x,y,z ) = (0,2,3,5,7,8,9,10,11,13,15) :2
F = xz + x'z' + yz + wz : -
1 1
z y 0 4 12 w 8 1 5 13 9 3 7 15 11
1
1 1 1 1
1
2 6 x 14 10 14
1 1 1
1
1
z
Five-Variable map'A BC 00 10 11 B 01 8 9 E 11 01 DE 00 0 4 21 10
1 5 31 11 3 7 51 A D 01 2 6 C 41 B 01 42 52 E 72 62 11 82 92 13 03
BC 00 10 DE 00 61 02 10 71 12 11 91 32 D 01 81 22 C
map 52 power . Variables 52 & 92 & 9 & 31 1 . BD'E
map ). F (A,B,C,D,E
1s . ) F( w,x,y,z K-map
( 01 ) 1: ( F = x'y'+x'yz'+yz :) Simplify : Truth table 01
)7,3,2,1,0( = )F(xyz map F = x' + yz y 01 .
1x
0 4
1
1 5
1 1z
3 7
1
2 6
51
2: Simplify F(A,B,C,D) = BD + BCD' + AB'C'D', and implement it
with two-level NAND gate circuit :1- K-map map BD B D . C 0 4 21 A
8 1 5 31 9 3 7 51 11 2 6 B 41 01
1 1
1 1
1 1
1
D 1s 'F = BD + BC + AB'C'D 2- Logic diagram ( Complement form :
) inverterB D BD
BCC A 'B 'C 'D
F
'AB'C'D
two-level NAND gate circuit : AND NAND complement NAND OR gatex
y z
+ 'x' + y 'z
x y z
')( xyz
') x' + y' + z' = ( xyz
: DeMorgan : 61
:B D1 2
00
3
4
1
C A 'B 'C 'D
5
00
6
2 31
01
21
F
1 2 4 5
02
6
: 2-input NAND & 3-input NAND & 4-input NAND Pin
Assignments
)00( 2-input NAND
)01( 3-input NAND
)02( 4-input NAND
Minterms 1 map : )51,31,8,7,5( = ) F (A,B,C,D 0 m 0= F 8 m 1=. F
LED output ) 0 0 0 0 ( 0 m LED. ) 0 0 0 1 ( 8 m LED.
Breadboard : ( 35 )71
: Product of sum : Simplify F (A,B,C,D) = ( 0,1,2,5,8,9,10 ) in
sum of Product & Product of sum : map 1s F sum of Product
Minterms 1s F 1 F 0 ] [complement of F 0 map ' F sum of Product ' F
( F' )' DeMorgan's Theorem F . Product of sum C C
1
0 4 21
1 1
1 5 31
3 7 51 11
1
2 6 41 B A
0
1 5 31 9 D
0 0 0 0
3 7 51 11
2 6 41 01 B
1 0 0
4 21 8
0 0
A
0
1
8
1
9 D
01 1
F : sum of Product F = B'C' + B'D' + A'C'D
'F'= AB + CD + BD
( (0s
F (F')' : Product of sum ') 'F = (AB + CD + BD )= (A' + B')(C' +
D')(B' + D : ) 01,9,8,5,2,1,0 ( = )F (A,B,C,D )
51,41,31,21,11,7,6,4,3 (F (A,B,C,D) = F = B'C' + B'D' + A'C'D )F=
(A' + B')(C' + D')(B' + D
Product of sum . NOR gates
81
:Dont care : ) 5,2,0 ( = )Simplify F (A,B,C,D) = ( 1,3,7,11,15 )
& d (A,B,C,D ) 5,2,0 ( = ) d (A,B,C,D Dont care Dont care .
Dont care sum of Product & Product of sum map x . 1s & 0s C
C -
x
0 4 21
1 x
1 5 31 9 D
1 1 1 1
3 7 51 11
x
2 6 41 01 B
x 0 0A
0 4 21 8
1 5 31 9 D
3 7 51 11
x 0 0 0
2 6 41 01 B
x 0 0
A 8
0
F : sum of Product F = CD + A'D
'F'= AC' + D
( (0s
F (F')' : Product of sum ')'F = (AC' + D )= D (A' + C
Dont care .
91
Implement F (A,B,C,D) = (0,1,2,9,11)
&
d(A,B,C,D) = (8,10,14,15) using 2-input NOR gates . :
: Product of sum NOR gates : C 0 1 5 13 9 DA C' D' B'
0 0 x
3 7 15 11
2 6 14 10 B
F'= B + A'CD
(0s ( (F')' : Product of sum F
0 0A
4 12 8
0 0
0 x x
F = (B + A'CD)' = B' (A + C' + D')
x
Logic diagram (A + C' + D')F
:-2 input NOR gates NOR complement NOR OR AND gate x y
x' y'
x y
( x + y)'
X' y'
=
( x + y)'
: DeMorgan : :
A C' D' B'
F
A C' D' B'
F
20
gates : complement :
x
x'
A 'C 'D
F'B B
B
A 'C 'D B
F
2-input NOR gates 3-input NOR gates gates : 3-input NOR gates '
] ' [ A + C' + D ' ]' [ ( A + C' ) + D ( A + C' )' . D :A 'C D
B
F
NORA 'C D B
AND :
NOR
F
NOR :
A 'C
FD B
12
2 IC 5 NOR ( IC NOR gate D ' D ) :
A 'C 'D B
2 3
20
1
5 6
4
20
9 8
20
01
11 21
31
20
F
: 2-input NOR Pin Assignments
A,B,C,D LED . output
ANDNANDx y ')(xy F y F = xy 'x F 'y x y x
OR'x 'y F = (x'y')' = x + y F x
NOT
F 'F = (xx)' = x
x
NOR
')(x+y
y
F
x 'F = (x + x)' = x
F
F = ( x' + y' ) = xy
F=x+y
Breadboard : ( 45 )
22
x 0 0 1 1
y 0 1 0 1
2-binary input & 2-binary output Half Adder . x & y (
augend ( ) addend( -2 : binary input . S & C ) carry ( ) sum (
-2 : binary output C S . S is the least significant bit CS 0 0 :
Truth table x =y = 1 C =1 0 1 : S & C map 0 1 1 0 y y 0 0
-
0x
12
1 3
0x
02
1 3
1
0
0C= xy
1
S = x'y + xy' =x + y
: Logic diagram x y
S C
x 0 0 0 0 1 1 1 1
y 0 0 1 1 0 0 1 1
z 0 1 0 1 0 1 0 1 0 4 1
3-binary input & 2-binary output Full Adder . x & y
& z -3 binary input . S & C ) carry ( ) sum ( -2 : binary
output . S is the least significant bit CS C S : Truth table x =y =
z = 1 S = C =1 0 0 : S & C map 0 1 0 1 S = x'y'z + x'yz' +
xy'z' + xyz = x + y + z 1 0 0 1 C = xy + xz + yz = xy + x'yz + xy'z
1 0 = xy + z (x'y + xy') = xy + z (x + y) 1 0 1 1 y y 1 0 1 5 0 1 3
1 7 0 6 x 4 1 5 2 0 1 1 1 3 7
-
2 6
0 x
1
z
z
23
: Logic diagramx y
S
Cz
Full Adder 2 Half Adder :x y
1S 1C
2S S 2C C map F = x + y + z y
z
0 x 1
0 4
1 0
1 0 5 1
3 1 7 0
2 6
z map Full Adder Carry . y 0 4 1 5 1 1 3 7 2 6
x
1
1
z
Truth table Full Adder 2 LED S C 1 = . x = y = z
42
: Full Adder
x y
1 2
3
86
4 6 5
86
S
1 2
4
08
3 5
08
6
1 2
32
3
C
z: 2-input OR & 2-input AND & 2-input XOR Pin
Assignments
) 55 ( : Breadboard
25
0
1Sender
1Receiver Parity Bit
0x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1
1P 0 1 1 0 1 0 0 1
1
0
1
1
P
x y z
Bits Bits.- Parity .) even or odd ( P
P
1 : ) 3-bit even parity generator ( x , y , z :
P 0 1 x,y,z P 1 1 x,y,z - map P P = x + y + z
Logic diagram LED output P x , y , z x 0 0 0 0 0 0 0 0 1 1 1 1 1
1 1 1 y 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 z 0 0 1 1 0 0 1 1 0 0 1 1 0
0 1 1 P 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C 0 1 1 0 1 0 0 1 1 0 0 1 0
1 1 0 2: ) 4-bit even parity checker ( x , y , z ,p : C 1 1 P &
x&y&z . C 0 1 P & x&y&z . map C C = x + y + z +
p Logic diagram LED output C x , y , z , p -
x y C z p
.
62
. 4-bits Full Adder . 1 A = A4 A3 A2 A 1 B = B4 B 3 B 2 B 0 C .
1 C4 S4 S 3 S 2 S outputs . Second Full Addes 1 C Delay 2 C 1 B2
& A 2 & C 1 C 1 ( B 1 & A ) . 4- Bit Parallel Binary
Adder :
-
4 B4 A 4C
3 B3 A
2 B2 A
1 B1 A 0C
4S1101 1011 2-complement
3C3 S1101 +1101 01110
2C2 S
1C1 S :
4-bit . 4-bit 2-complement
:
2- 1 = 0C
: : 1- B 'B
4B 4A 4C
3B 3A
2B 2A
1B 1A 1 = 0C
4S
3C3 S
2C2 S
1C1 S
:
x x 0 X-OR = Buffer
x 1
: :X-OR
72
'X X-OR = converter
4 bit Parallel Binary Adder Subtracter : X-OR B412 13
B39
B24 5 1
B12
10
8611
86
86
86
A41
8
A33
6
A28
3
A110
16
4
7
11
C0 = M83 832
C414 15
836
83
13
9
S4
C3
S3
C2
S2
C1
S1
. M=1 M=0 M Mode C0 : 4 bit Parallel Binary Adder Subtracter
& 2-input XOR Pin Assignments
B4
S4
C4
C0 GND
B1
A1
S1
A4
S3
A3
B3
VCC
S2
B2
A2
Breadboard A= 1000 : 0011 B=
Add 0 1 0 1 1 Sub. 1 0 1 0 1
) 56 - 57 ( :
28
. inputs & outputs Decoder inputs n outputs 2 . Decoder ) (
2 * 4 Decoder :n
A & B 00 0 1 = 0D A B Minterms 0D3 D2 D1 D A & B 0 0
'A'B 0m 0 0 0 1 11 0 1 A'B 1m 0 0 1 0 3 1 = 3 D 1 0 'AB 2m 0 1 0 0
. 1 1 AB 3m 1 0 0 0 2 * 4 Decoder 0 = A = B inverter 1 = A = B AND
AND 1 ... outputs Decoder
: Decoder With Enable Enable Decoder 0 ( ) OFF Decoder 1 ( ) ON
Decoder . E 0= E outputs 0 1= E inputs .- E .
X Don't care A B 0 = E
92
Active low & Active high : Active high Minterm 1 Active 0 .
Inactive : Active low Minterm 0 Active 1 . Inactive E .
)OFF( Decoder 1= E ) ON( Decoder 0= E inverter E AND gates 0=E
1= E Decoder IC Active low .
: Decoder : ) 3 , 0 ( = )F (x , y : Decoder 0 m3 m 1=. F- Active
high Decoder : OR gate
x y
4*2 Decoder
0I 1I 2I 3I
F
E- Active low Decoder : NAND gate
x y
4*2 Decoder
0I 1I 2I 3I
NOT-OR
FAND-NOT
E
= NAND
x y
4*2 Decoder
0I 1I 2I 3I
F
E03
. Implement Full Adder using 3 * 8 Decoder if S ( x,y,z ) = (
1,2,4,7 ) & C ( x,y,z ) = ( 3,5,6,7 ) :1 2
:
x y z
3 13
Pin 1 & 15
IC = 155
I0 I1 I2 I3 I4 I5 I6 I7
9 10 11 12 7 6 5 4
4 5
20
6
S
Pin 1 & 15
E
Pin 2 & 14
9 10 12 13
20
8
C
: 3 * 8 Decoder & 4-input NAND Pin Assignments
VCC
x
E
z
I3
I2
I1
I0
155
3 * 8 Decoder
x
E
y
I7
I6
I5
I4
GND
4-input NAND ( 20 )
. 11 S & C LED xyz= 111
31
054 G = E 1 C=x, B=y, A=z OFF ON 0
Breadboard : ( 85 )
y z
Decoder : 1 - : Implementation 3 * 8 Decoder using two 2 * 4
Decoder
x
: 0= x=y=z 0 m 0 1 X Decoder Decoder 4 * 2 0= A y=z E 0 0D 0 1
Active low Decoder A E 1 1 0 D 3 * 8 Decoder 2 * 4 Decoder 2 - :
Implementation 4 * 16 Decoder using five 2 * 4 Decoder
y z y w x z y z y z
0I 1I 2I 3I 4I 5I 6I 7I 8I 9I 01I 11I 21I 31I 41I 51I3
most significant bit 4 * 2 Decoder bits Decoders wxyz - . Active
high
23
3 - : Implementation 4 * 16 Decoder using four 2 * 4 Decoder
'w 'x
y z
0I 1I 2I 3I 4I 5I 6I 7I 8I 9I 01I 11I 21I 31I 41I 51I3
'w x
y z
w 'x
y z
w x
y z
0I 1I 2I 3I
4 * 1 MUX
Output
1S
2S
output n 2n selectors . inputs input selectors . output inputs :
) . ( 4 * 1 MUX : 0 = 2 S1 = S 0 I output 1 = 3S1 = S 3 I output
.
-
: . Implement Function F( A,B,C,D ) = ( 0,3,5,6,8,9,14,15 )
using MUX : 8 * 1 MUX 3 bits selectors 8 = 32 = . inputs B , C , D
selectors . A most significant bit : ) selectors ( B , C , D ) .
control bit ( A Truth table . 4 Variables control bit ' A A I 8 0 I
7. I : ' A Truth table Minterms A 0 Minterm I 0= A 7m0, m5, m A 0 0
I 5 5 I 7 7I ' A Minterms A 1 . 1- 2- 3- 4-
33
Minterms 1= F : ) 51,41,9,8,6,5,3,0 ( = ) . F( A,B,C,D I : 7 I
51 A . I7 = A I . MUX : 0 = A = B = C =D selectors 0 = 2 S0 = S1 =
S 000 0 selectors 0 I = 1 1= output : 1 = A = 0 , B = C =D
selectors 1 = 2 S0 = S1 = S 1 1 1 7 selectors 7 I = A 0 0= output
.
5- 6- 7- 8-
0I'A A
1I 1 9I1=A
2I 2 010=2I
3I 3 11'I3= A
4I 4 210=4I
5I 5 31'I5= A
6I 6 411='I6=A + A
7I 7 51I7=A
0 81='I0=A + A
A 0 0 0 Minterms 0 = A 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Minterms 'w'x'y'z w'x'y'z 'w'x'yz w'x'yz 'w'xy'z w'xy'z 'w'xyz
w'xyz 'wx'y'z wx'y'z 'wx'yz wx'yz 'wxy'z wxy'z 'wxyz wxyz 0m 1m 2m
3m 4m 5m 6m 7m 8m 9m 01m 11m 21m 31m 41m 51m
Minterms 1 = A
1 A 0 'A 0 'A 1 A
0I 1I 2I 3I 4I 5I 6I 0 I7 S 2 S 1 S
Output
B
C
D
43
: 8 * 1 MUX Pin Assignments
VCC
I4
I5
I6
I7
S2 D
S1 C
S0 B
151 3 * 8 MUX
I3
I2
I1
I0
y
y'
E
GNDE = 0 ( ON ) E = 1 ( OFF )
4 3 2 1 15 14 13 12
I0 I1IC = 151 I2 I3 I4 I5 I6 I7
: Pin
5
y
9
10
11
B
C
D
) 59 ( : Breadboard
- Implement Function F( A,B,C,D ) = ( 0,3,5,6,8,9,14,15 ) using
MUX : . 1 * 4 MUX selectors : . control bits ( C , D ) selectors (
A , B ) 35
: selectors
-
0I'C'D C'D
1I 4 5 6 7'I1= C'D + CD =C+D
2I 8 9 01 11I2=C'D' + C'D '= C
3I 21 31 41 51I3= CD' + CD =C
C&D . T.T C .T.T D 1
0 1 2 3I0=C'D' + CD ') =( C + D
D .T.T C 1 C&D . T.T 1
'CD
CD
:
C D C D A 'C C
1*4 y MUX
B
I1 = C + D 0-1-1-0 X-OR function
63
Combinational Circuits . Sequential Circuits :Input Output next
state
Combinational Circuits
Input
Combinational Circuits
Output Memory
Feed back
Storing
: Sequential Circuits 1 - :Asynchronous Sequential Circuits
output Feed back input . 2 - : . Output Trigger : 1 - : Level Clock
signal generation output (+ve )level trigger )-ve level trigger (
+ve clock . 2 Sec output . 2 - : Edge Clock signal generation
output (+ve )edge trigger )-ve edge trigger ( output ) clock ( +ve
). clock ( -ve+ve level trigger
-ve level trigger
-ve edge trigger
+ve edge trigger
Flip Flop Function table
73
: Flip Flop clock Q' Q Bit Flip Flop . CK or CP or CLK . next
atate Q(t+1) Present state Q(t) -
1- R S Flip FlopR 0 0 0 0 1 1 1 1 S 0 0 1 1 0 0 1 1 Q (t) 0 1 0
1 0 1 0 1 0 1 1 1 0 0 ? ? Q(t+1)
Function table
R 0 0 1 1
S 0 1 0 1 Q (t) 1 0 ?
Q(t+1) No Change Set Reset Undefined
No Change No Change Set, If S = 1 Then output = 1 Set, If S = 1
Then output = 1 Reset, If R = 1 Then output = 0 Reset, If R = 1
Then output = 0 Undefined Undefined
2- D Flip Flop ( Data Flip Flop ) input = outputFunction table D
0 1 0 1 Q(t+1) Reset Set
3- J K Flip FlopFunction table J 0 0 1 1 K 0 1 0 1 Q (t) 0 1 Q'
(t) Q(t+1) No Change Reset , If K = 1 Set , If J = 1 Toggle =
inverter
4- T Flip Flop ( Toggle Flip Flop )Function table T 0 1 Q (t) Q'
(t) Q(t+1) No Change Toggle = inverter 38
: Flip Flop Clock sign
+ve level trigger
-ve level trigger
+ve edge trigger
-ve edge trigger
CLK
CLK
CLK
CLK
. Design 2 Bit up counter using JK Flip Flop : : counter A,B 2
Bit . 0 1 2 3 0 Up 2 bit : . A & B 2 Flip flop 2 bit 1 - :
Counter State Diagram 2 -
00 11 10: State Table 3 - Present state A 0 0 1 1 B 0 1 0 1 Next
state A 0 1 1 0 B 1 0 1 0 A Flip Flop JA 0 1 x x KA x x 0 1 B Flip
Flop JB 1 x 1 x KB x 1 x 1
01
AB A,B in Present state AB in Next state AB in Present state :
01 00 00 01 AB in Next state
) B in Present state) Q(t) )B in Next state) Q(t+1)
) A in Present state) Q(t) )A in Next state) Q(t+1)
39
Q (t) 0 0 1 1
Q (t+1) 0 1 0 1
J 0 1 x x
K x x 1 0
No Change or Reset Toggle or Set Toggle or Reset No Change or
Set . Q (t+1) Q (t)
0 Q (t+1) Reset No Change Q (t+1) = 0 Q (t) = 0 : J=0 , K=0 JK
Flip flop Function table K J . K=x 0 J K Reset J=0 , K=1 No Change
0 Q (t+1) Reset Toggle Q (t+1) = 0 Q (t) = 1 : J=1 , K=1 JK Flip
flop Function table K J . J=x 1 k j Reset J=0 , K=1 Toggle : Flip
flop State equations 4 - B JA = B 0 KA = B 0 B
0A
1 x
1 3
xA
x2
1 3
x
2
0
1
B JB = 1 0 JB = 1 0
B
1A
x2
1 3
xA
12
1 3
1
x
x
1
: Logic Diagram 5 - JA KA QA Q' A A'
CLK JB 1 KB Q' QB B B' 40
6 - : 67 IC Type 754 .
) Clear ( CLR ) Preset ( PR 1 J K Flip flop Pin Assignments
:
VCC CLR CLR
CK
KB
JB
PR
QB
211 J K Flip FlopCK KA JA QA Q'A Q'B GND
PR
CLK Function Generator Pin 31 & 1 IC frequency . negative (
) Ground
positive ( ) Life
Breadboard: ( 06 )
14
. 15 4 61 0 Bit Binary Counter . 9 4 61 0 Bit B.C.D. Counter : 4
Bit Binary Counter A & B & C & D : Inputs - 1 QA QB QC
QD . QA & QB & QC & QD : Outputs - 2 .: 1 61 Cout - 3
cout clear : 0 Count - 4 4 Bit Binary load . inputs Counter CLK
count . outputs : Clear - 5 : Load - 6 A B C D . 0 next state CLK
clear . Asynchronous control 161 IC Function Table . CLK Clear 0 1
1 1 Clock x Load x 0 1 1 Count x x 1 0 Function Clear outputs to 0
Load inputs data Count to next binary value No change in output
-
-
. inputs : 4 Bit Binary Counter Pin Assignments CLR . clear 0 IC
inputs 6 pin 3 most significant bit Least significant bit outputs
pin most significant bit 11 Least significant bit 14
VCC Cout
QA QB161
QC QD
Load
4 Bit Binary Counter
Count
CLR
CK
A
B
C
D
GND
: Function Table 4 Bit Binary/B.C.D. Counter Pin Assignments
VCC
A
CLR
B0 C 0
Load
C
D
Clear 1 0 0
Load 1 0 1
Function Clear Load Count
193 ( Binary Counter ) 192 ( B.C.D. Counter )
B
Q B QA
Down
CK
Up
QC QD
GND
42
291 Pin Assignments 391 IC . B.C.D. Counter Binary Counter most
significant bit 9 Pin 161 IC 1 B0 4 Pin CLK Down counter IC C0 5
Pin CLK Up counter 61 . 1 61
-
) 61 ( : Breadboard
Serial Output ( SO )
1Serial Input ( SI ) A CLK
0
1
0
B
C
D
1
0
1
Shift register right 4 bit Shift register right with parallel
load Serial Output ( SO ) QA QB QC QD Serial Input ( SI )
A CLK
B
C
D
4 bit Shift register left with parallel load VCC
QA
QB
QC QD Q'D
CK sh/load: 4 bit Shift register Pin Assignments
:
1954 bit Shift register
. CLR = 0 SI : Shift left 15 SO 7 . 0 9
CLR
J SI K'
A
B
C
D
GND
43
IC : 1 - Pin 9 ( ) Shift / load control 1 Shift right 0 Shift
left Shift left . 2 - ': J & K input = output . D flip flop D J
K
1 3
: . Design Random generator 0 1 0 1 = A B C D
68QA
2
QB QCB C
QDD
Serial Input ) ( SI
A
Shift register right XOR . . 0 = A = B = C = D XOR 0 . 51 0000 1
cycle 51 Maximum cycle : :
1-
2- 3- 4- 5-
1 0 0 0 1 0 1
0 1 0 0 0 1 0
1 0 1 0 0 0 1
0 1 1 0 1 0 0 0 XOR gate Pin Assignments IC 591 :Random
generator 0 0 0 1 0 1 0
Register Function table
Breadboard: ( 26 )
44
. 4 bit counter : 3 7 3 3 . 5 n 0011 . Design mod n counter
stated with 3 & n = 5 using 4 bit counter :1 : . ABCD = 0011 1
- 1 Q 2 - . 0111 7 NAND gate Input QA QB QC QD 3 3 - 3 7 load cout
3 load=0 & clear=1 4 Bit Binary clear count function Function
table Counter CLK count clear = count = load =1 load function 7
Function table A B C D . load = 0 ABCD 3 Clear = 1 , count = 1 :
Function table 4 - : NAND 5 - count load 1 NAND 3 1100 Load (3)
count load 1 NAND 4 0010 6 count load 1 NAND 5 1010 7 1110 count
load 1 NAND 0110 . ABCD 3 load 0 NAND
Clear 0 1 1 1
Clock x
Load x 0 1 1
Count x x 1 0
Function Clear outputs to 0 Load inputs data Count to next
binary value No change in output
. Design mod n counter stated with 11 & n = 5 using 4 bit
counter :2
NAND . 1111 1 51 outputQA QB QC QD
cout CLK 4 Bit Binary CounterA B C D
load clear count
45
: 0 1 0 1
cout CLK 4 Bit Binary CounterA B C D
load clear count
NAND output 1 inverter output 0 NAND
QA QB QC QD
cout CLK
load clear count
: 15 5 1 cout . 15
4 Bit Binary CounterA B C D
0 0 0 . . . 0 0 . . . . 0 0
0 0 0 . . . 0 0 . . . . 0 0
0 0 0 . . . 0 0 . . . . 0 1
0 0 0 . . . 0 1 . . . . 1 0
0 0 0 . . . 1 0 . . . . 1 0
0 0 0 . . . 1 0 . . . . 1 0
0 0 1 . . . 1 0 . . . . 1 0
0 1 0 . . . 1 0 . . . . 1 0
1 2 3
. Design mod n counter from 5 to 24 using 4 bit counter : 3 : .
two ( 4bit counter ) 0 23 . 51 load = clear = count 1 . load =
clear = 1
15 16cout QA QB QC QD load 2 A B C D clear count cout QA QB QC
QD load clear 1 count A B C D
31 32CLK
46
Design mod n counter from 0 to 4 using 4 bit counter clear NAND
. 4 CLK clear 4 4 5 0 : load
QA QB QC QD
cout CLK
Load clear count
4 Bit Binary CounterA B C D
1 2
00
3
QA QB QC QD
QA QB QC QD
cout CLK
load clear count
cout 161 CLKA B C D
loadClear=1 Count=1
4 Bit Binary CounterA B C D
. : Pin Assignments NAND gate & 4 bit binary counter
CLR . clear 0 IC inputs 6 pin 3 most significant bit Least
significant bit outputs pin most significant bit 11 Least
significant bit 14
VCC Cout
QA QB
QC QD
Load
161 4 Bit Binary Counter
Count
CLR
CK
A
B
C
D
GND
) 63 ( : Breadboard
47
f/16 f/8 f/4 f/2QD QC QB QAcout Load=1
CLK ( +ve edge )
4 Bit Binary CounterA B C D
Clear=1 Count=1
0
1
2
3
4
5
6
7
CLK ( +ve edge ) T ( CLK )
QAT ( QA)
QBT ( QB)
T ( QA) = 2 T ( CLK ) , If Frequency F = 1 / T , Then : F( QA )
= [ F (CLK ) /2 ] T ( QB) = 4 T ( CLK ) , If Frequency F = 1 / T ,
Then : F(QB) = [ F (CLK ) /4 ] T ( QC) = 8 T ( CLK ) , If Frequency
F = 1 / T , Then : F(QC) = [ F (CLK ) /8 ] T ( QD) = 16 T ( CLK ) ,
If Frequency F = 1 / T , Then : F(QD) = [ F (CLK ) /16 ] . counter
F by 128 QD QC QB QA co ut CL K
load Clear=1 Count=1
A B C D
: Design Frequency divider by 5 : 1 : . 4 0 n = 5 mod n counter
1 - . CLK signal 5 load signal 2 - . CLK signal 5 Qc signal 3 - 2 3
4 0 1 2
0
1
CLK ( +ve edge ) T ( CLK )
loadT ( load)
QCT ( QC) 48
T ( load) = 5 T ( CLK ) , If Frequency F = 1 / T , Then :
F(load) = [ F (CLK ) /5 ] T ( QC) = 5 T ( CLK ) , If Frequency F =
1 / T , Then : F( QC ) = [ F (CLK ) /5 ] : Design Frequency divider
by 5 ( from 3 to 7 ) : 2 . NAND : 3 7 1110 F by 5 QD QC QB QA co ut
CL K load Clear=1 A B C D
most significant bit load : NAND input
Count=1
: signals 3 4 5 6 7 3 4 5
CLK ( +ve edge ) T ( CLK )
loadT ( load)
QCT ( QC)
: Design Frequency divider by 123 : 3 : . ) counters 321 . ( n
counter 1 - . 27 2 - 321 ( 2 ) 821 . NAND input most significant
bit load signal 3 -
. F by 5 load 1
. 00 161 IC
49
00
QD QC QB QA
cout CLKA B C D
load1=Clear 1=Count
CLR 0 clear . inputs IC pin 6 most significant bit 3 Least
significant bit outputs pin 11 most significant bit 41 Least
significant bit
VCC Cout
Q A QB
QC Q D
Load
Count
CLR
CK
A
B
C
D
GND
signal Oscilloscope: 1 - load NAND output 1 Channel . 2 - CLK
Function generator . 10 KHz 3 - Oscilloscope 1 CH signal signal
Square wave x-axis Time / Div position
cycle T : * 2.0 ( =1 )* * Time/Div Time/Div . : 21 5.0 : 100.0 *
5.0 * 2.0 * 21 = T 4 - T F . F = 1 / T 1 84 F load 5/1 F CLK F 5/1
F Function generator CLK 0002 .
Breadboard: ( 46 )
05
Breadboard - : Breadboard . Node Vcc 5 Volts x 1 Node
Node
Node
Node
Node
Node Ground 5 Volts x 0 Node
input inputs .
15
) 10 11 ( : Implementation function F = x'y'+x'yz'+yz , using
AND OR gates
1 variable : Vcc
: y y Truth table
: z Truth table z
variable : Ground 0
: x' Truth table x'
x=1,y=0,z=1 ) )m5 2 : 1 variable : Vcc
x=y=z= 0 ) )m0 1 : 1 variable : Vcc
variable : Ground 0
variable : Ground 0
52
Simplification F(A,B,C,D) = BD + BCD' + AB'C'D', and
implementation it with two-level NAND gate ) 16 17 ( : circuit1
variable : Vcc
LED
: B B Truth table
: Ground variable 0
D
C
A
B'
C'
D'
) 17 ( : A=1, B=C=D=0 m8 LED
1 variable : Vcc
2 nodes
: Ground variable 0
53
Implementation F (A,B,C,D) = (0,1,2,9,11) & d(A,B,C,D) =
(8,10,14,15) using 2-input NOR gates ) 20 21 - 22 ( : variable :
Vcc 1
: B B Truth table
: D' D' Truth table
LED
: A A Truth table
: C' C' Truth table
: Ground variable 0
54
) 23 24 - 25 ( : Full Adder
1 variable : Vcc
LED S=1
z
LED C=1
x
y
: Ground variable 0
) 23 24 - 25 ( :
x = y = z = 1 Full Adder
1 variable : Vcc
: Ground variable 0
55
4 bit Parallel Binary Adder - subtracter: ( 82)
1 : A 1 A A 0C 4A 4C 3A
: Vcc variable 1
2A
NODE 04 C X-OR
4B 4S 3B
1S
3S
2S
, A B 82 0 M 1 LED LED
2 nodes
1B 2B : Ground variable 0
65
)28 ( : 4 bit Parallel Binary Adder - subtracter
variable : Vcc 1
variable : Vcc 1
variable : Vcc 1
: Ground variable 0
)28 ( : 4 bit Parallel Binary Adder - subtracter
variable : Vcc 1
: Ground variable 0
57
Implementation Full Adder using 3 * 8 Decoder if S ( x,y,z ) = (
1,2,4,7 ) & C ( x,y,z ) = ( 3,5,6,7 ) ) 31 ( : E = 0 or 1
variable : Vcc 1
x
z
C
S
y
: Ground variable 0
E=0 ( ON ) 11 S & C LED xyz= 111 variable : Vcc 1
: Ground variable 0
58
) 33-34-35 ( Implementation Function F( A,B,C,D ) = (
0,3,5,6,8,9,14,15 ) using 8 * 1 MUX variable : Vcc 1
A'
A
D C
B
Output
A' : Ground variable 0
E = 0 ( ON ) A : A Truth table A=B=C=D=0 LED 1 I0 MUX T.T.
59
) 39-40-41 ( Design 2 Bit up counter using JK Flip Flop
variable : Vcc 1
B or QB 00 11 least significant bit
A or QA 00 11 most significant bit CLK Function Generator
: Ground variable 0
60
) 42 ( 4 Bit Binary Counter
QD QC cout QA QB load count
variable : Vcc 1
clear D count load
C
B
A : Ground variable 0
CLK Function Generator 61
Random generator ( 44 )
: Vcc variable 1
CLK Function Generator
0 = Control = control 1 Function table 44 XOR ' J & K SI
ABCD 0101 44 . 26 : Ground variable 0
Design mod n counter from 0 to 4 using 4 bit counter ( 74 )
( QC ) ( ) : Vcc variable 1
QD ( QB )
: Ground variable 0 0=A=B=C=D
CLK Function Generator
0 4 0 .
36
) 47 ( Design Frequency divider by 5
QA variable : Vcc 1
QC QB
Oscilloscope ( CH1 )
: Ground variable 0 A=B=C=D=0
CLK Function Generator
64
