Manage scaling challenges for silicon success

Executive summarySemiconductor companies are faced with significant challenges related to technology scaling, design scaling, and system scaling. These challenges have a broad impact on design development, manufacturing, and functional operation, which all impact the bottom line.

This paper discusses the challenges and the specific impact of a Silicon Lifecycle Solutions approach that includes DFT, operations, and Embedded Analytics in enabling companies to deal with the complexity associated with these challenges in a simplified and well-organized, reliable, and predictable manner.

Ron Press, Siemens Digital Industries Software

Siemens Digital Industries Software

siemens.com/eda

Manage scaling challenges for silicon successWhy new tools for test and monitoring are vital in today’s changing semiconductor landscape

White paper | Manage scaling challenges for silicon success

2Siemens Digital Industries Software

Introduction

Semiconductor companies must move faster than ever, constantly work to lower the cost of development and production, respond to changing customer demands, create new business models and out-innovate the competition.

In this challenging business environment, complexity is a key challenge. Within semiconductor design, complexity is a result of scaling of technology, designs, and systems. The leading semiconductor companies continually refine and optimize all aspects of chip design and fabrication to manage the challenges of scaling. Figure 1 illustrates the three scaling challenges.

In recent years, Siemens has transformed itself into a company that is oriented around digital transformation. Siemens Digital Industries Software now spans product lifecycle management to software, electronics, manufacturing, operations, and the internet of things analytics. The expanded scope is reflected in the Xcelerator portfolio, combining all the elements necessary to design the smart products of the future—creating a digital twin that connects the digital thread from design to manufacturing to in-life.

The Xcelerator portfolio includes the Tessent Silicon Lifecycle Solutions (SLS), which includes the entire line of software, intellectual property (IP), and services for test, operations/yield analysis, and in-life monitoring.

The core concept behind SLS is to create an infrastructure that makes designs more testable, achieves high-quality test, identifies defects and hidden yield limiters, and moves beyond test into in-life monitoring.

Technology scalingNew nodes

Design scalingTake advantage of integration

System scalingValidation and the digital twin

Figure 1. Three scaling challenges that affect semiconductor makers.

Tessent addresses the three industry scaling challenges with best-in-class software and IP:

• Technology scaling — Physics-driven software technologies improve test and diagnosis quality and fidelity.

• Design scaling — Award-winning, patented software and IP that simplifies the complexity of huge designs with plug-and-play infrastructure and SoC-level DFT.

• System scaling — IP and software enables not just the regular testing of devices during their functional life, but also allows performance monitoring, security, over-the-air updates, and more resiliency.

Figure 2 illustrates the Tessent response to the three scaling challenges.



Technology scalingNew nodes

Design scalingTake advantage of integration

System scalingValidation and the digital twin

• Shift left DFT• True Hierarchical DFT• Streaming Scan Network• 3DIC DFT

• ATPG performance scaling• Chain resolution scaling• Statistical diagnosis (FEOL/BEOL)• Defect-oriented test

• Built-in self-test• In-system test• Embedded analytics• Lifecycle management

Figure 2. Tessent responses to the three scaling challenges that affect semiconductor makers.

The increasingly important role of IC test and monitoring—which includes design-for-test (DFT), operations, and Embedded Analytics—is indisputable. Older approaches to IC test, yield enhancement, and in-life monitoring simply can’t keep up. Adopting innovative solutions for IC test and monitoring throughout the lifecycle of the device helps your tame and leverage complexity as a competitive advantage.

Each of the Tessent solutions offers massive scaling and cost efficiencies, saving not just time and cost, but boosting market success as companies harness the complexity of today’s changing semiconductor landscape.

This paper explores the high costs of outdated DFT, operations, and monitoring solutions, and presents the new approaches that can directly impact the viability of a business, including:

• Achieve very high test quality, including for safety-critical devices

• More efficient DFT that integrates into common design flows and system requirements

• Plug-and-play DFT that enables hierarchical methodologies, reducing the costs of DFT implementation

• Faster yield ramp for new product introduction, new manufacturing processes, and yield improvement for mature processes. AI-driven methods to analyze production test fails and point out hidden yield limiters to speed up yield ramp

• In-field, real-time test, functional monitoring, analysis, and updates for the lifecycle of the device



The high costs of outdated DFT

Legacy DFT methodologies result in missed time-to-market, higher than expected test costs, lower than expected chip quality, slower yield ramp, and no ability to maintain the device in-life. There are many reasons for this, all of which have to do with the three scaling challenges: technology scaling, design scaling, and system scaling. There is such a fast migration to smarter DFT practices that companies not employing them will be at a competitive disadvantage.

Technology scaling affects defect detection and yieldThe core function of DFT is to catch defects in manufactured silicon and ensure that a part will operate as designed once it’s placed in-system. If you ship too many bad parts, then your entire business can suffer. Part of the problem in achieving the target test quality in advanced manufacturing processes is that most of the defects now occur within the standard cells, not just in the interconnect. The traditional fault models simply cannot reliably detect defects inside of cells, and in fact, many companies have stopped using stuck-at or transition patterns at all. Without an upgrade to the DFT tools and methodologies, SoCs designed at advanced nodes can’t achieve the high-quality required for many markets today.

Yield improvement relies on high defect detection. Reducing the number of failing die and improving the reliability of the manufacturing process has a direct impact on business. Structural test patterns are used to detect failing die before they are shipped to customers, and the data from the failing tests provide valuable information about the mechanism(s) causing the die to fail that can be leveraged to improve yield faster, which has a significant effect on the bottom line.

A thorough analysis of failing scan test data—called scan diagnosis—is regularly used by companies that own their own fabrication facilities, pure-play foundries, and fabless semiconductor companies. Companies designing at advanced nodes need to quickly determine yield limiters, especially if they are related to a specific cell layout or geometry.

Design scaling affects DFT implementationAs SoCs get larger and more complex, incumbent tool solutions for IC test begin to break down. Chip makers who continue with full, flat test or partitioned-based approaches with manual steps suffer severe time-to-market delays. Particularly for manycore designs with lots of integrated cores, a flat DFT flow is infeasible. In addition to the design size and number of cores, today’s designs present too many dependencies between DFT setup for various technologies, like BIST, scan test, and other test instruments. The dependencies can make the DFT implementation flow a bottleneck in the design schedule. Finally, the increasing amount of 2.5D and 3D integration requires next-level DFT technologies. The costs are seen in lost market windows because of the long implementation time, higher test costs, and lower test quality.

System scaling affects product performance and in-life managementTime to market and the performance of a product once in the field are both affected by the increased complexity of today’s SoCs. How do chip makers optimize the design for the target market more quickly, given that the chip will be embedded in increasingly complex electronics systems and networks? Winning in the market means getting the chip right the first time, and providing the tools to keep that chip working at its best throughout the product lifecycle.

Validation engineers need visibility into the hardware and software operation and their system-level interactions in simulation, emulation, prototyping, and first silicon, all the way through packaging and system installation. This reaches to in-field analysis, monitoring, and updating that affects performance, reliability, functional safety, and cybersecurity.

Driven by unstoppable technological and market forces outlined above, system scaling is a challenge that is already threatening to overcome legacy approaches to managing the complexity and risk that comes with it.



Siemens Tessent test, operations, and Embedded Analytics have been developed over years of research and development by a world-class team of engineers. Strong partnerships throughout the semiconductor ecosystem ensure that the Tessent solutions are both well targeted to solve key challenges, and high-quality. Semiconductor companies today need to employ next-level DFT capabilities to remain competitive, including:

• Using physics instead of dice or logic design to detect manufacturing defects.

• Performing true SOC-level DFT with packetized test, which enables the optimization of core level DFT and pattern generation independent of how blocks are embedded.

• Improving yield through machine-learning powered diagnosis-driven yield analysis (DDYA)

• Monitoring, analyzing, and optimizing in-life

Detecting all the defectsThe most fundamental function of DFT is to catch manufacturing defects in manufactured silicon and ensure that a part will operate as designed once it’s placed in-system. Defect coverage refers to the entire universe of potential defect types. This includes known fault models such as stuck-at, transition delay, path delay, IDDQ, bridging, cell-aware, and more. The cell-aware fault model was developed over 15 years to detect potential defects within technology cells.

More recently, Tessent developed defect-oriented test that provides new types of bridge, opens, cell-aware/timing-aware, and cell-neighborhood tests. These newer pattern types are not just for special cases or automotive-level DPPM requirements. With unique silicon detection results in the 1000+ DPPM ranges, a number of companies have standardized on cell-aware tests and no longer apply stuck or transition patterns.

An additional advancement to defect-oriented test is the ability to apply critical-area calculations from the physical design to choose and sort test patterns based on where defects are most likely to occur. This improves defect detection and DFT efficiency.

Next-level DFT technologies

The latest addition to the Tessent TestKompress software is ATPG Boost, which enhances IC test coverage and throughput in hierarchical DFT approaches like packetized test and also for flat designs.

Boost DFT efficiencyWith the growth in design sizes, design flows have become more hierarchical, creating design cores that are functionally complete all the way through physical design. The finished blocks are then instantiated into the top level of a chip or to chiplets then to chip top. Companies that tried to continue with full, flat ATPG or partitioned-based approaches with manual steps suffered severe time-to-market delays.

Tessent offers many features to improve DFT efficiency. These include full hierarchical DFT—a full plug-and-play methodology that has proven to dramatically improve all aspects of DFT. Hierarchical DFT removes DFT from the design’s critical path to tapeout, reduces ATPG run time, pattern count, and usage of compute resources. For large SoC designs, hierarchical DFT has become the standard practice.

Taking plug-and-play to the next level is Tessent Streaming Scan Network (SSN), a packetized scan delivery system that enables simultaneous testing of any number of cores, helping shorten test time by enabling high-speed data distribution. The SSN architecture is shown in figure 3.

Figure 3. Tessent Streaming Scan Network is a transformative technology for packetized test delivery used by most major semiconductor companies.



SSN efficiently handles imbalances between cores and supports testing of any number of identical cores at a constant cost. It also provides a plug-and-play interface in each core that simplifies scan timing closure and is well-suited for abutted tiles. Tessent SSN test is already being used by the majority of the leading semiconductor companies.

All the Tessent technologies are built on a unified DFT environment, called Tessent Connect, illustrated in figure 4. Tessent Connect operates as an “intent-driven” environment, reducing many steps and accelerating time-to-market. Users can work at a higher level of abstraction. The challenge of inserting DFT, creating patterns, and integrating the DFT functions at the top level are all managed in a plug-and-play environment. Without such an integrated platform, companies struggle to manage DFT functions such as BIST during ATPG and would have many steps to integrate core-level DFT and patterns at the top level.

Ramp yield fasterMeeting market demands for chip capacity has become a daunting challenge as the number of foundry options shrinks and the number of applications grows for fabless companies. Subtle interactions between process (foundry) and designs (fabless) create previously unresolvable defect mechanisms. Concurrently, failure analysis costs rise along with time to root cause. Leveraging DFT and production test results to improve yield is a requirement to achieve time-to- volume and profitability. Tessent Diagnosis delivers the highest resolution location and defect signatures from manufacturing test data. When Tessent Diagnosis and Tessent YieldInsight are combined, they form a matched pair where unique machine-learning algorithms find hidden systematic yield limiters. Figure 5 shows the Tessent SiliconInsight software in action.

The new reversible scan chain diagnosis technology in Tessent Diagnosis, used for node qualification and early technology ramp, delivers 4x speed-up in failure analysis time. Cell-aware diagnosis locates faults within standard cells.

The Tessent SiliconInsight software targets new product qualification, reducing characterization iterations during first silicon bring-up of new products. It can be used in the desktop lab configuration or connect directly to the ATE using ATE-Connect accelerating bring up of ATPG, MBIST, LBIST, and IJTAG.

Figure 5. Machine-learning powered Tessent SiliconInsight finds hidden yield limiters.

Figure 4. Tessent Connect is advanced end-to-end DFT automation that creates more reliable, predictable, and sustainable hierarchical DFT flows.



In-life test, monitoring, and optimizationFor some end products, the need to test, monitor, optimize, and update the silicon continues during its functional life in the world. Testing is accomplished by on-chip test structures like BIST, and for automotive chips, is controlled by the Tessent Safety Island and the Tessent MissionMode controller.

For monitoring and optimization, on-chip functional analytics provides system-level visibility of the functional behavior of a chip. Tessent Embedded Analytics (EA) ensures that your chip does what it was designed to do, safely and securely. It is a powerful platform combining software and on-chip hardware that helps semiconductor companies solve complex design problems and improve the reliability and performance of their products by leveraging data throughout the product lifecycle. A high-level illustration of the EA is illustrated in figure 6.

Tessent EA enables real-time monitoring and analysis of the functional behavior of complex ICs at any level of detail – from the complete SoC to individual instructions and bus transactions, and with a unified view of hardware and software operation.

Figure 6. The Tessent Embedded Analytics platform (green) comprises silicon IP and a software interface, together with libraries, APIs, an SDK and database functionality. The platform enables analytics applications (red) to

As part of the Siemens Xcelerator portfolio, the right SoC and embedded system data can add enormous value to a digital twin strategy.

Potential application spaces include advanced predictive yield of embedded systems, through to digital representations of infrastructure and whole systems of systems such as manufacturing facilities, data centers, and IoT fleets.

Embedded Analytics also brings a new set of functionality to simulation, emulation, and prototyping phases, enhancing Siemens EDA products such as the Questa Advanced Simulator and Veloce™ Strato™ Emulation Platform as well as the Veloce Prototyping System. This approach enables a unified view of the SoC across the whole development cycle, allowing teams to correlate results from phase to phase and set up efficient feedback loops for optimizing the product, both for this product generation and for the generations that will follow.



To stay competitive in the semiconductor industry, companies need to partner with a DFT solution provider that is low risk, trustworthy, and has a proven track record of co-developing scalable technologies with their partners that work in a variety of design flows. Focusing on these types of challenges with our partners has made Tessent the clear market leader and a safe choice DFT solution provider. Our strong partnerships across the semiconductor ecosystem also make Siemens well positioned to continue advancing DFT technology for future needs.

Related resourcesThe following resources describe next-level Tessent technologies in more depth.

Tessent Silicon Lifecycle Solutions

Streaming Scan Network: An efficient packetized data network for testing of complex SoCs

Optimal End-to-End DFT Automation with Tessent Connect

Overcoming Systematic Yield Limiters with Diagnosis-Driven Yield Analysis

Embedded Analytics: A platform approach

Intel dramatically improves test quality with Tessent Cell-Aware test

Conclusion

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09/21 BM

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Manage scaling challenges for silicon success