March 6, INST02, Novosibirsk1 Electronics for the e experiment at PSI Short introduction Trigger electronics DAQ electronics Slow Control For the

March 6, INST02, Novosibirsk 1

Electronics for the e experimentat PSI

• Short introduction• Trigger electronics• DAQ electronics• Slow Control

For the MUEGAMMA collaborationStefan Ritt

(Paul Scherrer Institute, Switzerland)


Search for e down to 10-14

1m

e+

Liq. Xe ScintillationDetector

Drift Chamber

Liq. Xe ScintillationDetector

e+

Timing Counter

Stopping TargetThin Superconducting Coil

Muon Beam

Drift Chamber

MEG Detector

• LFV Process forbidden by SM

• oscillations expected to enhance LFV rate

• Present limit: 1.2 • 10-11 (MEGA)

• SUSY Theories: ~ 10-12

• LFV Process forbidden by SM

• oscillations expected to enhance LFV rate

• Present limit: 1.2 • 10-11 (MEGA)

• SUSY Theories: ~ 10-12

Required:

• stopping rate: 108/s

Resolutions (all FWHM):

• Ee: 0.7%

• E: 1.4% @ 52.8 MeV

• e: 12 mrad

• te: 150ps

Required:

• stopping rate: 108/s

Resolutions (all FWHM):

• Ee: 0.7%

• E: 1.4% @ 52.8 MeV

• e: 12 mrad

• te: 150ps

Ee = 52.8 MeV

Kinematics e= 180°

E = 52.8 MeV

e


Detector Design

2002

2003

2004

2005

2006

2007

Tests & Design

Assembly

Engineering Run

Data taking

.

.

.1m


Status Large Prototype• Currently largest

LXe detector in (224 PMTs, 150l),

• Contains all critical parts of final detector

• Currently tested with 40 MeV ’s in Tsukuba, Japan

• First results in energy and position resolution expected next weeks


Trigger ElectronicsTrigger Electronics


Trigger Requirements

Beam rate 108 s-1

Fast LXe energy sum > 45MeV 2103 s-1

interaction point e+ hit point in timing counter time correlation – e+ 200 s-1

angular corrlation – e+ 20 s-1

Beam rate 108 s-1

Fast LXe energy sum > 45MeV 2103 s-1

interaction point e+ hit point in timing counter time correlation – e+ 200 s-1

angular corrlation – e+ 20 s-1

Ee = 52.8 MeV

Kinematics e= 180°

E = 52.8 MeV

e

M.C.

• Total ~800 PMTs

• Common noise contributes significantly to analog sum

• AC coupling Baseline drift

• How to evaluate of shower center?

• Total ~800 PMTs

• Common noise contributes significantly to analog sum

• AC coupling Baseline drift

• How to evaluate of shower center?


Digital Trigger

VMEInterface(Cypress)

3.3V 2.5V

LVDS

FPGA

SRAM

LVDS

LVDS

LVDS

FPGA

FPGA

FPGA

SRAM

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

Type2

LVDS

LVDS

Type1

8 channels8 channels

clck, clear


3.3V 2.5VFADC

LVDS

FPGA

SRAM

FADC

FADC

FADC

FADC

FADC

FADC

FADC

LVDS

FPGA

FPGA

FPGA

SRAM

LVDS

48 bits output

100MHz 10bit


3.3V 2.5VFADC

LVDS

FPGA

SRAM

FADC

FADC

FADC

FADC

FADC

FADC

FADC

LVDS

FPGA

FPGA

FPGA

SRAM

LVDS

48 bits output

100MHz 10bit


3.3V 2.5VFADC

LVDS

FPGA

SRAM

FADC

FADC

FADC

FADC

FADC

FADC

FADC

LVDS

FPGA

FPGA

FPGA

SRAM

LVDS

48 bits output

100MHz 10bit


3.3V 2.5VFADC

LVDS

FPGA

SRAM

FADC

FADC

FADC

FADC

FADC

FADC

FADC

LVDS

FPGA

FPGA

FPGA

SRAM

LVDS

48 bits output

100MHz 10bit

• All PMTs in trigger• Board hierarchy with LVDS interconnect• Use FPGA with double capacity

• All PMTs in trigger• Board hierarchy with LVDS interconnect• Use FPGA with double capacity


Lat

ch

Lat

ch

Lat

ch

Lat

ch

Lat

ch

Baseline SubtractionBaselineSubtractionL

atch

10 bit

100 MHz Clock

-+

<thr

+

-

BaselineRegister

Uses ~120 out of 5000 logic cells

8 channels/FPGA use 20% of chip

Uses ~120 out of 5000 logic cells

8 channels/FPGA use 20% of chip

Baselinesubtracted

signal LUT10x10

Calibrated and

linearized signal


QT Algorithmoriginal

waveform

smoothed anddifferentiated (Difference Of

Samples)Threshold in DOS

Region for pedestal

evaluation

integration area

t

• Inspired by H1 Fast Track Trigger (A. Schöning)

• Hit region defined when Difference of Samples is above threshold

• Integration of original signal in hit region

• Pedestal evaluated in region before hit

• Time interpolated using maximum value and two neighbor values in LUT 1ns resolution for 10ns sampling time

• Inspired by H1 Fast Track Trigger (A. Schöning)

• Hit region defined when Difference of Samples is above threshold

• Integration of original signal in hit region

• Pedestal evaluated in region before hit

• Time interpolated using maximum value and two neighbor values in LUT 1ns resolution for 10ns sampling time

10ns


Trigger latency

BS

BS

BS

BS

Max

Max

Max

.

.

.

T[ns] 0 50 100 110 120..200 220 230

>45MeV

e+

AND

10 stages = 1024 chn

. . .

ADC

ADC

ADC

ADC

.

.

.

Inter-board communication: 120nsTotal: 350ns (simulated)

~600 chn. / 10 bitAt 100 MHz

75 GB/sprocessing powerIn 2 VME crates


Prototype board

ADCSignal-

Generator DACFPGA

• Trigger built by INFN, Pisa• Fully simulated

• Trigger built by INFN, Pisa• Fully simulated


DAQ ElectronicsDAQ Electronics


DAQ Hardware Requirementsn

E[MeV]50 51 52

e

t

PMTsum

e

e

e

51.5 MeV

0.511 MeV

• ’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm)

• Timely separated ’s need waveform digitizing > 300 MHz

• If waveform digitizing gives timing <100ps, no TDCs are needed

• ’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm)

• Timely separated ’s need waveform digitizing > 300 MHz

• If waveform digitizing gives timing <100ps, no TDCs are needed

~100ns

e


Domino Sampling ChipExisting:

• 0.5 – 1.2 GHz sampling speed

• 128 sampling cells• Readout at 5 MHz, 12 bit• ~ 60 $/channel

Needed:• 2.5 GHz sampling speed• Circular domino wave• 1024 sampling cells• 40 MHz readout• < 100ps accuracy

Existing:• 0.5 – 1.2 GHz sampling

speed• 128 sampling cells• Readout at 5 MHz, 12 bit• ~ 60 $/channel

Needed:• 2.5 GHz sampling speed• Circular domino wave• 1024 sampling cells• 40 MHz readout• < 100ps accuracy

C. Brönnimann et al., NIM A420 (1999) 264


New Domino Ring Sampler (DRS)

• Free running domino wave, stopped with trigger

• Sampling speed 2 GHz (500ps/bin), trigger gate sampling gives 50ps timing resolution

• 1024 bins 150ns waveform + 350ns delay

• Free running domino wave, stopped with trigger

• Sampling speed 2 GHz (500ps/bin), trigger gate sampling gives 50ps timing resolution

• 1024 bins 150ns waveform + 350ns delay

input


DAQ Board8

inpu

ts

triggergate

FADC

3 state switches

FPGA

SRAMshift register

• 9 channels 1024 bins / 40 MHz = 230 s acceptable dead time

• Zero suppression in FPGA• QT Algorithm in FPGA (store waveform if multi-hit)• Read out through VME or LVDS

• 9 channels 1024 bins / 40 MHz = 230 s acceptable dead time

• Zero suppression in FPGA• QT Algorithm in FPGA (store waveform if multi-hit)• Read out through VME or LVDS

40 MHz 12 bit


3.3V 2.5V8 channel

DRS

TriggerInput

Board inter-connect

FPGA

FPGA

SRAM

SRAM

SRAM

SRAM

FADC

8 channelDRS

8 channelDRS

FADC

8 channelDRS

Trigger BUS(2nd level tr.)

domino wave


Status DRS

• Simulation finished in AMS 0.35 process

• Layout started• Switch to 0.25 process• First version summer ’02• Readout with trigger

prototype board• Costs per channel:

~25$ (board) + 6$ (chip)


“Redefinition” of DAQ

Conventional New

AC coupling Baseline subtraction

Const. Fract. Discriminator

DOS – Zero crossing

ADC Numerical Integration

TDCBin interpolation (LUT)

Waveform Fitting

Scaler (250 MHz) Scaler (50 MHz)

Oscilloscope Waveform sampling

400 US$ / channel 50 US$ / channel

TDCDisc.

ADC

Scaler

Scope

FADC

FPGA

SRAM

DSC ~GHz

100 MHz


Slow Control ElectronicsSlow Control Electronics


Slow ControlHV

PC

RS

232

12345

Temperature, pressure, …

GP

IB

Valves

??? 15° C

heater

PLC

12:30 12.3

12:45 17.2

13:20 15.2

14:10 17.3

15:20 16.2

18:30 21.3

19:20 18.2

19:45 19.2

MIDASDAQ

Eth

ern

et

Terminal Server


Slow Control BusHV

Temperature, pressure, … Valves

heater

MIDASDAQ


Field Bus Solutions

• CAN, Profibus, LON available

• Node with ADC >100$• Interoperatibility not

guaranteed• Protocol overhead• Local CPU? User

programmable?• How to integrate in HV?

(CAEN use CAENET)

• CAN, Profibus, LON available

• Node with ADC >100$• Interoperatibility not

guaranteed• Protocol overhead• Local CPU? User

programmable?• How to integrate in HV?

(CAEN use CAENET)


Generic Node

• ADuC812 / C8051F000 Micro controllers

• RS485 over flat ribbon• Flat ribbon connector• Power through bus• Costs ~30$• Piggy back board

• ADuC812 / C8051F000 Micro controllers

• RS485 over flat ribbon• Flat ribbon connector• Power through bus• Costs ~30$• Piggy back board

B

RxD

9

INT

A

7

54

21

9

1

8

1 5

TC

KT

DI

TM

ST

DO

2

+3

V

4

A5 A4

1 1

P0.

2

TxD

1

P0.

4

B

+ 3V

-12V

+ 3V

6

0

3

2 2

1 6 2

1

+3

V

DG

ND

+1

2V

8

P 0

11.0

59 M

Hz

AG

ND

+3V

I/O _2

1 0

I/O _1

D E

A

RES

5V

in in

g nd g nd

/RS TP3 .4

+5VD G N D

J1

7

4

1

J1

+ 3V

J3

LED

+ 5V

0 6

+3

V

+3

V

2 2

SCS 200

A7 A6

J2

9

A2 A1

2J4

P0.

3

D I

R OR E

g nd

V c c

MAX1483

RE

SE

T

+ 5V

C 4 2 ,2uF

n c

in in

g nd

g ndn c

1 o ut

n c

8in

g nd

78L03

+ 12V

C 7 2 ,2uF

P 1

+5V

D G N D

56

23

0

P 2

4K

7R

2

1

AG

ND

-12

V

AV

+ AG

ND

1 2 .10 .2001

S C S 200

R .S CH M ID T

A0

1 o ut 8n c

C 6 2 ,2uF

RE

SE

T

C1

22

,2u

F

C9

27p

F

C 10 2 ,2uF

79L12V R 3

78L12

V R 1

J2

A3

C 3 2 ,2uF

V R 2C 2 2 ,2uF

C 1 2 ,2uF

+ 15V

-15v

4K 7R 1

Pau l-Scherrer-InstitutCH-5432 Villigen / PSI

C 112 ,2uF

C8

27p

F

C 5 2 ,2uF

17

AV

+

20

/RS

T6

2V

DD

23

P3

.35

9P

1.7

26

P3

.05

6P

0.7

29

TD

O5

3P

2.3

32

P1

.55

0P

0.5

1 6AV +

1 3A IN 6

1 0A IN 3

7A IN 0

4C P 0 +

1C P 1 -

3 3 P 2 .0

3 6 P 1 .2

3 9 P 0 .0

4 2 P 0 .1

4 5 P 3 .7

4 8 P 0 .3

19

XTA

L2

18

XTA

L1

1 5A G N D

1 2A IN 5

9A IN 2

6V R E F R

5A G N D

8A IN 1

11A IN 4

1 4A IN 7

63

DA

C1

64

DA

C0

3C P 0 -

2C P 1 +

22

TC

K

25

P3

.1

28

TD

I

31

VD

D

24

P3

.2

27

P2

.1

30

DG

ND

60

P1

.6

57

P3

.5

54

P2

.2

51

P2

.5

55

P0

.6

58

P3

.4

52

P2

.4

3 4 P 1 .4

3 7 P 1 .1

4 0 V D D

4 3 P 2 .7

3 5 P 1 .3

3 8 P 1 .0

4 1 D G N D

4 6 P 3 .6

4 7 P 0 .2

4 4 P 2 .6

21

TM

S6

1D

GN

D

49

P0

.4

6051F000

U 1


2 versions

• Generic node with signal conditioning• Sub-master with power supply and PC

connection (Parallel Port, USB planned)• Integration on sensors, in crates• RS232 node planned

BUS OrientedBUS Oriented

Crate OrientedCrate Oriented

• 19” crate with custom backplane• Generic node as piggy-back• Cards for analog IO / digital IO / °C / 220V• crate connects to parallel port (USB)


Midas Slow Control Bus

• 256 nodes, 65536 nodes with one level of repeaters• Bus length ~500m opto-isolated• Boards for voltage, current, thermo couples, TTL IO, 220V

output• Readout speed: 0.3s for 1000 channels• C library, command-line utility, Midas driver, LabView driver• Nodes are “self-documenting”• Configuration parameters in EEPROM on node• Node CPU can operate autonomously for interlock and

regulation (PID) tasks (C programmable)• Nodes can be reprogrammed over network

http://midas.psi.ch/mscb

• 256 nodes, 65536 nodes with one level of repeaters• Bus length ~500m opto-isolated• Boards for voltage, current, thermo couples, TTL IO, 220V

output• Readout speed: 0.3s for 1000 channels• C library, command-line utility, Midas driver, LabView driver• Nodes are “self-documenting”• Configuration parameters in EEPROM on node• Node CPU can operate autonomously for interlock and

regulation (PID) tasks (C programmable)• Nodes can be reprogrammed over network

http://midas.psi.ch/mscb


High Voltage System

C node

Op

to-c

ou

ple

rs

External HV


HV performance

• Regulates common HV source• 0-2400V, ~1mA• DAC 16bit, ADC 14bit• Current trip ~10s • Self-calibration with two high

accuracy reference voltages• Accuracy <0.3V absolute• Boards with 12 channels,

crates with 192 channels• 30$/channel (+ext. HV)

• Regulates common HV source• 0-2400V, ~1mA• DAC 16bit, ADC 14bit• Current trip ~10s • Self-calibration with two high

accuracy reference voltages• Accuracy <0.3V absolute• Boards with 12 channels,

crates with 192 channels• 30$/channel (+ext. HV)

Prototype


Conclusions• FPGA-based trigger with 100MHz FADC designed• 2 GHz waveform sampling on all channels planned• HV system with 0.3V accuracy designed• New slow control system (30$/node, 300s readout)• Transition prototype series• Physics runs in 2005• Can be useful for other experiments• In case of interest: [email protected]

• FPGA-based trigger with 100MHz FADC designed• 2 GHz waveform sampling on all channels planned• HV system with 0.3V accuracy designed• New slow control system (30$/node, 300s readout)• Transition prototype series• Physics runs in 2005• Can be useful for other experiments• In case of interest: [email protected]

http://meg.psi.chhttp://meg.psi.ch

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Documents

March 6, INST02, Novosibirsk1 Electronics for the e experiment at PSI Short introduction Trigger electronics DAQ electronics Slow Control For the