Methodology of Modeling of the Internal Activity of a FPGA

Methodology of Modeling of the Internal Activity of a FPGA for Conducted Emission Prediction Purpose.Methodology to model the internal activity of a FPGA for conducted emission prediction purpose
C. Ghfiri –A. Boyer – A.Durier – S. Bendhia (1) IRT Saint Exupery, Toulouse, France
(2) INSA / LAAS CNRS, Toulouse, France
121,2 2
© IRT AESE “Saint Exupéry” - All rights reserved Confidential and proprietary document
CONTENTS
• PRESENTATION • IA CORE BLOCK CONSTRUCTION METHODS
3. METHODOLOGY PROPOSAL FOR COMPLEX IC IA CORE BLOCK CONSTRUCTION • IA CORE BLOCK CONSTRUCTION METHODOLOGY • DETERMINISTIC APPROACH • STOCHASTIC APPROACH
4. ICEM GENERATOR TOOL • WORKFLOW AND CASE STUDY • IA CORE BLOCK GENERATION • GLOBAL WORFLOW FOR CE CALCULATION • POWER INTEGRITY AND CE CALCULATION EXAMPLE
5. CONCLUSION AND PERSPECTIVES
INTRODUCTION CONTEXT AND ISSUES
• Electronic suppliers for aeronautics, space and automotive industries are facing to a strong economic competition.
• They are forced to use more and more COTS (Commercial off the shelf) components to reduce costs.
• Pros : COTS components own a high level of technological innovation

The use of EM numeric simulation tools allows to predict the conducted emissions at equipment level using harness, PCB and
IEC 62433-2 ICEM-CE models.
ICEM-CE MODEL PRESENTATION
path
Models the IC internal switching noise by equivalent current or voltage sources
This paper deals with the construction of a FPGA core Internal Activity block
The IEC 62433-2 Integrated Circuit Emission Model- Conducted Emission is a standard to model the conducted emission produced by an IC
Constructed from IBIS model or S-parameter measurements performed between the different pins of the IC.
The IA is extracted from normative IEC 61967-4 Conducted emissions 1 / 150 method.
Passive Distribution Network Internal Activity

ICEM-CE MODEL IA CORE CONSTRUCTION METHODS
New methods and tools to build the IA core block of complex IC ICEM-CE model are needed
• Among methods allowing the extraction of the IA core block, some are accessible for end user without specific IC knowledge The Inverse method based on the measurement of the external
current flowing in the ground or power supply pins (IEC 61967-4 Conducted emissions 1 / 150 method. Cons : The dependence to the PDN and the board model From basic technological
information about the technology and IC electrical characteristics as proposed by IC-EMC tools. Cons : The lack of available data From instantaneous dynamic power
consumption from a vector-based simulation Cons : The simulation time

• The proposed methodology is based on components manufacturer design tools which allow a vectorless average dynamic power estimation and static timing analysis from post-placement and route data.
• The proposed methodology is also based on the assumption that, if the transferred charge is respected, an acceptable estimation of the conducted emission can be obtained whatever the waveform of the instantaneous current consumption
METHODOLOGY PROPOSAL FOR COMPLEX IC IA CORE BLOCK CONSTRUCTION

Average dynamic power consumption estimation using XPA (Xilinx Power Analyzer) tool
IA BLOCK CONSTRUCTION METHODOLOGY DETERMINISTIC APPROACH
DDL
N
i
=1 α
Static timing analysis : data path delays for the extreme conditions of the Process / Voltage / Temperature corners
2 minmax τττ
avg TII .2max ⋅=

© IRT AESE “Saint Exupéry” - All rights reserved Confidential and proprietary document 8
• A first case study is a delay lines structure. Each delay line is composed of 100 inverters and several delay lines are cascaded to maximize the dynamic power consumption.
IA BLOCK CONSTRUCTION METHODOLOGY CASE STUDIES

• The second case study is based on 7-bit counters. 800 7-bit counters have been cascaded in parallel to maximize the dynamic power consumption
• The clock frequency is 16 MHz and there is no IO activity • The internal activity of the clock tree is separated from the internal activity
of the signals and the logic blocks.
Configuration Dynamic
(ns) Average toggle rate (%)
Logic Clock Logic Clock
VCC
VSS
I = − Delay = /2 = τ/ = τ/ T =
I = Delay = 0 = τ/ = τ/ T =
I = Delay = τ = τ/ = τ/ T =
IA clock IA logic
IA clock
IA logic
• The simulated peak-to-peak amplitude is misestimated because we supposed that the instantaneous transferred charge at each clock cycle is constant and equal to the average transferred charge per clock cycle
• Despite this supposition, the simulated spectral envelop shows a good tendency except in 80-300 MHz band ( error > 12dB)
IA BLOCK CONSTRUCTION METHODOLOGY DETERMINISTIC APPROACH : 7-BIT COUNTER

mean RMS error of 5,19 dB
Xilinx Power Estimator
α(i) : Toggle rate of logic block i (i) : Dynamic power of logic block i
Pdyn
)(iq
QL
( )∑ =
IA BLOCK CONSTRUCTION METHODOLOGY STOCHASTIC APPROACH
• The XPE tool estimates the dynamic power consumption of each active logic block
• For each logic block, the transferred charge is a random variable taking the value q with a probability α = toggle rate and the value 0 with a probability 1-α

• A variable IA was generated with the stochastic approach • In the time domain, the simulated peak-to-peak amplitude shows a good
correlation with the measurement. • The FFT of the simulated signal shows a good tendency except in 100-200
MHz band ( error > 10dB)
10 100 1000

Mean RMS error of 4,86 dB
ICEM MODEL GENERATOR WORKFLOW AND CASE STUDY
• A dedicated tool called ICEM Generator for IA construction has been developed. This tool integrates the algorithms of IA construction presented in this paper
• The tool needs only the generated power and timing reports from Xilinx software to extract automatically the IA core
Synthesize Post P&R
PCB, harness models, …
• The case study is a real time FFT function including filtering
• Used internal resources : 1792 CLB, 4 RAM Blocks, 1 DCM, 30 DSP blocks
• Power consomption : 49 mW

ICEM MODEL GENERATOR IA CORE BLOCK GENERATION

Generated IA
ICEM-CE PDN
PCB Model

A global working flow integrating ICEM-CE PDN RLC equivalent model, PCB model
calculated from imported route files and IA equivalent model generated by ICEM tool
allows to calculate the conducted emission of an equipment
• In the time domain, the simulated peak-to-peak voltage (14,6 mV) is very close to the measured p2p voltage (16 mV)
• In the frequency domain, the spectral trends is well estimated. The RMS error between the simulation and the measurement is 4,8 dB
Power integrity
Conducted Emission

• A new methodology of IA Core block construction has been proposed. This methodology is based on : Dynamic power analysis Static timing analysis
• Deterministic and statistical approaches have been proposed to determine the current sources : compared to the vector-based approach, these solutions provide a good estimation of the IA block in a very short time, without additional steps in the FPGA design flow and from a reduced set of data.
• An automatic tool for IA block extraction has been developed PERSPECTIVES • Some improvements are identified (PDN extraction and CE measurement
accuracy, CE set up modeling accuracy, Monte Carlo analysis,..) • Application of the methodology on other ICs families as µC or DSP • Integration of the I/O PDN and IA IOs into the ICEM Generator
CONCLUSION AND PERSPECTIVES

MANY THANKS FOR YOUR ATTENTION
This work is sponsored by
…. and the French National Agency for Research
[email protected]
Methodology to model the internal activity of a FPGA for conducted emission prediction purpose
CONTENTS
METHODOLOGY PROPOSAL FOR COMPLEX ICIA CORE BLOCK CONSTRUCTION
IA BLOCK CONSTRUCTION METHODOLOGYDETERMINISTIC APPROACH
IA BLOCK CONSTRUCTION METHODOLOGYCASE STUDIES
IA BLOCK CONSTRUCTION METHODOLOGYDETERMINISTIC APPROACH : 7-BIT COUNTER
IA BLOCK CONSTRUCTION METHODOLOGYSTOCHASTIC APPROACH
IA BLOCK CONSTRUCTION METHODOLOGYSTOCHASTIC APPROACH : 7-BIT COUNTER
ICEM MODEL GENERATORWORKFLOW AND CASE STUDY
ICEM MODEL GENERATORIA CORE BLOCK GENERATION
ICEM MODEL GENERATORGLOBAL WORKFLOW FOR CE CALCULATION
ICEM MODEL GENERATORPOWER INTEGRY AND CE CALCULATION EXAMPLE
CONCLUSION AND PERSPECTIVES
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Methodology of Modeling of the Internal Activity of a FPGA