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MicrocontroladoresMestrado em Eng. Física Tecnológica
Analog to Digital Conversion
Analog to Digital Conversion
FUNDAMENTALS OF SAMPLED DATA SYSTEMS
2.1 CODING AND QUANTIZING
2.5
Figure 2.4: Transfer Function for Ideal Unipolar 3-bit DAC
Figure 2.5: Transfer Function for Ideal Unipolar 3-bit ADC
DIGITAL INPUT (STRAIGHT BINARY)
ANALOG
OUTPUT
000 001 010 011 100 101 110 111
1/8
1/4
3/8
1/2
5/8
3/4
7/8
FS
0
ANALOG INPUT
DIGITAL
OUTPUT
(STRAIGHT
BINARY)
000
001
010
011
100
101
110
111
1/8 1/4 3/8 1/2 5/8 3/4 7/8 FS0
1 LSB
1/2 LSB
Transfer Function
Amplitude Quantization and Time Discretization
Digi
tal O
utpu
t
• Sucessive Aproximations method (SAR)• Iterative method. Digital guesses:
• First guess is DN-1 bit at 1, others at zero. N=8 Example: 0xb10000000 = 128.
• If VIN >= VDAC, then DN-1 bit is set.• If VIN < VDAC, then DN-1 bit is cleared.
• Second guess: DN-2 bit:• Ex. 0xb11000000 = 192
• … and the other bits until D0
• Result is read by CPU• For a N-bit ADC it needs N guesses, or N clock
cycles. • E.g N=10,
• During this interval, the voltage at the “inverting input” of the comparator must be fixed.
• A “Sample and & Hold” Circuit is necessary (why?)
• Importance of a VREF stable
Analog to Digital Converter
VDAC
VDAC = VREF * Digital Code /(2N – 1)
Sample and Hold Circuit• SAR ADC has two phases:
• “Aquisition, during “SAMPLE”: • “Conversion”, during “HOLD”
AVR 10 Bit ADC
• Up to 15 KSPS (ksamples per second)
• 6 analog single-ended channels multiplexed, in Arduino. (only one channel can be aquired at a time)
• Resolution 8 or 10 bit • Best resolution at AVCC=5V, ~ 5 mV
• AVCC- analog power or internal 1.1 V reference
• AREF is the reference voltage. (Range)
ATmega328P [DATASHEET]7810D–AVR–01/15
206
Figure 23-1. Analog to Digital Converter Block Schematic Operation
The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC data registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is blocked.
Prescaler
-
+
15 0
ADC MultiplexerSelect (ADMUX)
MUX Decoder
AVCC
8-Bit Data Bus
AREF
GND
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
10-Bit DAC
InputMUX
Sample and HoldComparator
Internal 1.1VReference
Conversion Logic
ADC ConversionComplete IRQ
ADC CTRL and StatusRegister (ADCSRA)
ADC Data Register(ADCH/ADCL)
ADIF
ADEN
REF
S1
REF
S0
ADLA
R
MU
X3
MU
X2
MU
X1
MU
X0
Cha
nnel
Sel
ectio
n
ADSC
ADIF
ADFR
ADPS
2
ADPS
1
ADPS
0
ADIE
BandgapReference
TemperatureSensor
ADC
[9:0
]
ADCMultiplexerOutput
ADC and S&H Block
MUX Block
Analog Range
ADC Start Conversion
AVR ADC clock
• The ADC requires a dedicated clock for timing and conversion (SAR Guess Logic)
• It is NOT the sampling frequency!
• For the ATMega it should be between 50kHz and 200kHz • It is generated from the CPU frequency and a prescaler
(2, 4, 8, 16, 32, 64, 128)• Eg. 16Mhz/128 = 125 kHz,
ADC Timer clock
ADC Acquisition Timing
• Acquisition is triggered by software (set ADSC flag)• Or other hardware sources:
• Timer0/1 Overflow/compare match (constant sample rate)• Timer1 Input Capture Event• External pin INT0• Free running - the end of one conversion triggers another-.
(Fastest sample rate).• When a conversion ends an ADC Event
interrupt is fired, if enabled. CPU then reads convered value (8 or 10 bit)
ATmega328P [DATASHEET]7810D–AVR–01/15
210
Figure 23-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 23-7. ADC Timing Diagram, Free Running Conversion
Table 23-1. ADC Conversion Time
ConditionSample and Hold
(Cycles from Start of Conversion) Conversion Time (Cycles)First conversion 13.5 25
Normal conversions, single ended 1.5 13
Auto triggered conversions 2 13.5
1 2 3 4 5 6 7 8 9 10 11 12 13 1 2Cycle Number
One Conversion
Sign and MSB of Result
LSB of Result
Next Conversion
MUX and REFSUpdate
PrescalerReset
PrescalerReset
ConversionComplete
ADC Clock
TriggerSource
ADIF
ADATE
ADCH
ADCL
Sample and Hold
11 12 13 1 2 3 4Cycle Number
One Conversion
Sign and MSB of Result
LSB of Result
Next Conversion
MUX and REFSUpdate
ConversionComplete
ADC Clock
ADSC
ADIF
ADCH
ADCL
Sample and Hold
ADC Timing
• Minimum 13.5 ADC clock cycles per sample.
• 125 kHz ADC clk MAX ~ 10 kSPS
Start Acquisition/
Sampling
Start Converstion/
Hold
END Conversion
AVR ADC Example CodestartTimer0(){
// Set the Timer 0 Mode 2 CTCTCCR0A |= (1 << WGM01);// Set the value that you want to count toOCR0A = 0xF9; // set prescaler to 1024 and start the timer TCCR0B |= (1 << CS02) | (1 << CS00);
}
ISR(ADC_vect){//Read 10-bit values
ADCval = ADCL;ADCval = (ADCH << 8) + ADCval;//clear timer compare match flagTIFR0=(1<<OCF0A);
}
volatile int ADCvalue =0;
int main() {// config ADCADMUX = 1;// use #1 ADC channel// use AVcc as the referenceADMUX |= (1 << REFS0);// clear bit for 10 bit resolution ADMUX &= ~(1 << ADLAR);// 128 prescale for 16Mhz ADCSRA |=(1 << ADPS2) | (1 << ADPS1) | (1 <<ADPS0); // Enable Unit, auto-trigger, and ISR ADCADCSRA |= (1 << ADEN)|(1<<ADATE) |(1<<ADIE) ; //set ADC trigger source - Timer0 compare match AADCSRB |= (1<<ADTS1)|(1<<ADTS0);
sei(); // enable global InterruptsstartTimer0();for(;;){ // Endless Loop
run_your_function(ADCvalue);}
}}
ADC Precision
• Resolution of 10 bit = 5V/(2^N-1) ~ 5mV
• Reference Voltage should be as stable as possible
• Precision is usually lower• “Noise Reduction Mode”,
• the CPU is put on sleep mode to avoid interference.
• Clock should also be stable
ADC Precision and Clock Jitter
• For constant sample rate best is to trigger ADC with a Timer
• Precision depends on• Clock speed• Clock Stability (jitter)
180 3 Sampling
Fig. 3.12 The ideal sampling moments (dashed) shift in an arbitrary fashion in time if the sampleclock is disturbed by jitter
See Sect. 2.7.16 for some theoretical background and the relation to phase noise.Figure 3.12 shows the effect of shifting sample moments. If a sinusoidal signal
with a radial frequency ω is sampled by a sample pulse with jitter, the amplitudeerror is estimated as:
A(nTs +∆T (t)) = Asin(ω × (nTs+∆T (t)) (3.23)
∆A(nTs) =dAsin(ωt)
dt×∆T (nTs) = ωAcos(ωnTs)∆T (nTs). (3.24)
The amplitude error is proportional to the slope of the signal and the magnitude ofthe time error. If the time error is replaced by the standard deviation σjit describingthe timing jitter, the standard deviation of the amplitude σA is estimated as:
σA =
√1T
∫ T
t=0(ωAcos(ωt)σjit)2dt =
ωAσjit√2
. (3.25)
Comparing this result to the root-mean-square value of the sine wave A/√
2 overthe time period T results in the signal to noise ratio:
SNR =
(1
ωσjit
)2
=
(1
2π f σjit
)2
(3.26)
or in decibel (dB):
SNR = 20 10log(
1ωσjit
)= 20 10log
(1
2π f σjit
). (3.27)
For sampled signals the above relations hold for the ratio between the signal powerand the noise in half of the sampling band. This simple relation estimates the effectof jitter, assuming no signal dependencies. Nevertheless it is a useful formula tomake a first-order estimate.
Aliasing Problem
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Image Aliasing
Frequency Aliasing<latexit sha1_base64="yBgaix1dGDqzAkMdYr1NMfAMZtI=">AAACbHicbZHZSgMxFIYz4163ulwoIhwsigiWpNYFRKgK4qWCVaFTSiZNbWhmIckItfbKN/TOR/DGZzCdVqnLgcDPf77DSf74sRTaYPzmuCOjY+MTk1OZ6ZnZufnswuKtjhLFeJlFMlL3PtVcipCXjTCS38eK08CX/M5vnff6d49caRGFN6Yd82pAH0LREIwaa9WyL6dSUA3eMVzUCgAn8AxkBwjGsAuH+Nkaexgun8DzMkPkXp8sfJHkIEWLKWpZGIaLKbz/xe4Ty1qHfMO1bA7ncVrwV5CByKFBXdWyr149YknAQ8Mk1bpCcGyqHaqMYJJ3M16ieUxZiz7wipUhDbiudtKwurBpnTo0ImVPaCB1hyc6NNC6HfiWDKhp6t+9nvlfr5KYxlG1I8I4MTxk/UWNRIKJoJc81IXizMi2FZQpYe8KrEkVZcb+T8aGQH4/+a+4LeTJQb5wXcyVzgZxTKI1tIG2EUGHqIQu0RUqI4benXlnxVl1Ptxld81d76OuM5hZQj/K3foEoMWpJg==</latexit>
Alias F2 = |1 ⇤ 100� 70| = 30Hz
Alias F3 = |2 ⇤ 100� 160| = 40Hz
Alias F4 = |5 ⇤ 100� 510| = 10Hz
• But 10, 30 and 40 Hz are not present in the signal
Nyquist Criterium
• Nyquist criterion requires that the sampling frequency be at least twice the highest frequency contained in the signal.
<latexit sha1_base64="zJ5Kv6/mbLAAw7EWt4cUXLxkPms=">AAAB/nicbVC7SgNBFL3rMyY+VsXKZjAKVmE3hVpJiI1lBPOAJCyzk9lkyOzsMjMbCEvAX7GxUMRO7P0DOz9EayePQhMPXDiccy/33uPHnCntOJ/W0vLK6tp6ZiOb29za3rF392oqSiShVRLxSDZ8rChnglY105w2Yklx6HNa9/tXY78+oFKxSNzqYUzbIe4KFjCCtZE8+yDwUoVDs0p0RwhdoiIqe3XPzjsFZwK0SNwZyZeOv17fB7nvimd/tDoRSUIqNOFYqabrxLqdYqkZ4XSUbSWKxpj0cZc2DRU4pKqdTs4foROjdFAQSVNCo4n6eyLFoVLD0DedIdY9Ne+Nxf+8ZqKDi3bKRJxoKsh0UZBwpCM0zgJ1mKRE86EhmEhmbkWkhyUm2iSWNSG48y8vklqx4J4VijcmjTJMkYFDOIJTcOEcSnANFagCgRTu4RGerDvrwXq2XqatS9ZsZh/+wHr7ATxtmMk=</latexit>
fsampling > 2BW
How to Avoid Aliasing • Solutions:• Increase Fs
• Remove F2, F3, and F4, before sampling
• Anti-aliasing electronic Filter
Low Pass Filters
First Order<latexit sha1_base64="+TvE+YNfICrmaZADcveOsIN/Yng=">AAACAXicbVDLSsNAFJ34rPUVdaHiZrAIrkrShXYjFLtxWcU+oAlhMp20QyeTMDMRSogbf8WNC0Xc+hPiTjdu/Qynj4W2HrhwOOde7r3HjxmVyrI+jLn5hcWl5dxKfnVtfWPT3NpuyCgRmNRxxCLR8pEkjHJSV1Qx0ooFQaHPSNPvV4d+84YISSN+rQYxcUPU5TSgGCkteeZe4OEz6AQC4dTO0hJ0YgqvYDXzzIJVtEaAs8SekEKl/PW2+/m9X/PMd6cT4SQkXGGGpGzbVqzcFAlFMSNZ3kkkiRHuoy5pa8pRSKSbjj7I4JFWOjCIhC6u4Ej9PZGiUMpB6OvOEKmenPaG4n9eO1FB2U0pjxNFOB4vChIGVQSHccAOFQQrNtAEYUH1rRD3kE5D6dDyOgR7+uVZ0igV7ZNi6VKncQ7GyIEDcAiOgQ1OQQVcgBqoAwxuwT14BE/GnfFgPBsv49Y5YzKzA/7AeP0B9lOZsQ==</latexit>
fc =1
2⇡RC
Second Order Sallen key
