Midterm presentationMidterm presentationWinter 2010Winter 2010

Performed by:Performed by:Tomer Michaeli 052792769Tomer Michaeli 052792769Liav Cohen 301242509Liav Cohen 301242509

Supervisor: Shlomo Beer GingoldSupervisor: Shlomo Beer GingoldIn collaboration with:In collaboration with:

characterization of synchronizerscharacterization of synchronizers and metastabilityand metastability

Our project subject

Direct measurements of synchronization Circuits and comparison to measurement results by a built-in self on chip characterization unit.

Project goals

Learning the direct measurement method.

Building and improving the measurement system for synchronization to characterize performance of synchronizers.

Project environment

Test Chip 65nm

FPGA board

Signal generator

DLP socket (PC)

The test environment is composed by the FPGA board that generates control and data signals for the 65nm Synchronizer test chip.

Achievements

Learning the measurement system. Learning the chip characteristics and

the measurement system GUI Initial results

Top level design

f1=6.245 MHz

f2=6.25MHz (FPGA clock)

FF

DSO80204BScope

Input

TRIGGERDATA

Searching for metastability

f1=6.245 MHz)data( 160.13 ns

f1=6.25 MHz)clock(

160 ns

FF out

The difference between the two clocks is 130 ps. The frequency of the FF output is 5 Khz (frequencies difference of

inputs) . The FF setup time is usually 50 ps so a metastability can occur at a 5

Khz rate. If we determine the difference to be lower than 130 ps we get less

chances for metastability. On the other hand, the probability to metastability will grow.

200 μs

The GUI

Test chip- top level design

(DATA)

Test chip- Digital logic block

The oscilloscope

The output of the flip-flop (FF) is connected through the PLD to the trigger input of the oscilloscope

The FPGA clock signal is connected through the PLD to the data channel of the scope

The digital sampling scope is capable of continuous data accumulation and the results are available for statistical analysis.

The oscilloscope

Each data point accumulated by the scope represents one sampled rising transition of the clock signal.

Its horizontal displacement indicates the delay from the clock input to the data output of the FF.

Initial results

figure [1]

figure [2]

Previously known results [1]

Initial results

In figure [2] we see the distribution of the samples propagation delay (how much longer it takes the output to be update relative to normal propagation delay).

White color indicates the largest number of cases with normal propagation delay.

Previously known results [2]

Project Schedule

Task Duration

-Learning the subject and building the measurement system

- Learning the chip characteristics and its GUI.

6 weeks

Initial results2 weeks

Resultscomparison to the results from the

chip

4 weeks

Results’ Analyzing 3 weeks

References

[1] Yaron Semiat and Ran Ginosar, ‘Timing Measurements of Synchronization Circuits’ , Technion, Haifa.

[2] Shlomo Beer Gingold, ‘Test Chip (Sinc_test_chip)’, Technion, Haifa.