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Mixed-Signal Test Bus IEEE1149.4
1
IEEE 1149.4 Mixed-Signal Test Bus
An overview of this new testability bus standard,
along with a discussion of the architecture and
how to use it.
Mixed-Signal Test Bus IEEE1149.4
2
IEEE 1149.4: Mixed-signal Test Bus Standard
Development history
Basic guidelines
Test bus requirements
Standard architecture
Measurement example
Mixed-Signal Test Bus IEEE1149.4
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Development History
September 1991Informal meeting of 15 companies in San Jose, CADraft of mission statement, objectives, request to IEEE
October 1991ITC meeting attracted 30 companiesWorking Group authorized by Test Bus Steering
Committee
Working Group meetingsSince October 1991Regular meetings: 3 times per year at major test events
Mixed-Signal Test Bus IEEE1149.4
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Mission Statement
To define, document, and promote the use of a
standard mixed-signal test bus that can be used
at the device, sub-assembly, and system levels
to improve the controllability and observability of
mixed-signal designs and to support mixed-signal
built-in test structures in order to reduce
test development time and costs,
and improve test quality.
Mixed-Signal Test Bus IEEE1149.4
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Basic Guidelines
Providing test bus facilities to meet the mission objectives
Oriented toward industry: design, test, and manufacturing
Maintaining compatibility with 1149.1 test bus features
Coordinating with IEEE 1149.1 and mainly the IEEE 1149.1B-1994International industry and academic experts
Mixed-Signal Test Bus IEEE1149.4
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Basic Guidelines
IEEE1149.4 does NOT seek toSolve all mixed-signal test problemsDictate mixed-signal test strategies
IEEE1149.4 DOES intend toREDUCE the difficulty in mixed-signal testingFACILITATE design-for-testPROMOTE concurrent design & test approaches
Mixed-Signal Test Bus IEEE1149.4
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Mixed-Signal Printed Circuit Assembly
Mixed-Signal Test Bus IEEE1149.4
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Common Defects on a mixed-signal PCA
Shorts D-D A-A D-A
Opens Z Direct Connections
Missing Component Wrong Component
D D
D
D
D
D
A
A
D
D
D
A
A
A
D
D
D
A
A
A
D
D
D
A
D D
D
D
D
D
A
A
D
D
D
A
Mixed-Signal Test Bus IEEE1149.4
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CORE CORE
TDITMSTCKTDO
VirtualTest
Probe
CONNECTOR PRINTED CIRCUIT ASSEMBLY
IEEE 1149.1 Boundary-Scan Architecture
Mixed-Signal Test Bus IEEE1149.4
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Simple, Extended and Differential Interconnects
Mixed-Signal Test Bus IEEE1149.4
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Handling Analog Pins: Pre-1149.4
Digitalsection
1149.1 Test Access Port
Analoginputs
Digitalinputs
TDI
TMS
TCK
Analogoutputs
Digitaloutputs
TDO
Analogsection
DBM DBM
DBMDBM
DBMDBM
DAC ADC TDI: Test Data In (1149.1)
TMS: Test Mode Select (1149.1)
TCK: Test ClocK (1149.1)
TDO: Test Data Out (1149.1)
DBM: Digital Boundary Module
(Boundary-Scan Cell)
Mixed-Signal Test Bus IEEE1149.4
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Handling Analog Pins: with 1149.4
TDI: Test Data In (1149.1)
TMS: Test Mode Select (1149.1)
TCK: Test ClocK (1149.1)
TDO: Test Data Out (1149.1)
DBM: Digital Boundary Module
(Boundary-Scan Cell)
ABM: Analog Boundary Module
Analogsection
Digitalsection
1149.1 Test Access Port
Analoginputs
Digitalinputs
TDI
TMS
TCK
Analogoutputs
Digitaloutputs
TDO
DBM
DBM
ABM
ABM
DBM
DBM
ABM
ABM
Mixed-Signal Test Bus IEEE1149.4
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Structure of a basic 1149.4 chip (minimal config)
TMS
TDI TDO
TCK
AT2
AT1
DIGITALI/O PINS
ANALOG
I/O PINS
TBIC (Test Bus
Interface Circuit)
Analog TestAccess PortATAP
VH
VL
VG
VH
VL
VG
Internal Test Bus (AB1, AB2 )
Core
Circuit
Analog BoundaryModule(ABM)
Digital BoundaryModule(DBM)
Test Control Circuitry
TAP ControllerInstruction register and
decoder
Digital Test
Access Port
(TAP ) as in
IEEE1149.1
Digital Test
Access Port
(TAP) as in
IEEE1149.1
Boundary
Scan Path
Mixed-Signal Test Bus IEEE1149.4
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Analog Boundary Module: Input Pin
Core
TBIC
VTH VH VL VG
-+
SB2SB1
AB1
AB2
Analogfunction pin
AT1
AT2
SD
Coredisconnect
Internal analogtest bus
ABM Switch ControlFrom TDI To TDO
SH SL SG
Input value can be sensed, digitised (against VTH), and
captured in the register
Current path into the core via AT1, AB1 and SB1
Ability to disconnect the receiving core from the pin using SD and drive either a 1 or a 0 (SH or SL)
ABMs can be implemented with actual switches or can be integral in the analog circuit.
Mixed-Signal Test Bus IEEE1149.4
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Analog Boundary Module: Output Pin
Dot 1 mode Logic 1/0 to output via SH/SL Digital signal input capture via
comparison with VTH
Compatible with 1149.1 Extest, Preload/Sample
Analog mode: each pin can source an analog current via
AB1/SB1, or capture an analog voltage via
SB2/AB2 form a current return to VG
(usually ground) via SG be disconnected from the core
via SD
Core
TBIC
VTH VH VL VG
-+
SB2SB1
AB1
AB2
Analogfunction pin
AT1
AT2
SD
Coredisconnect
Internal analogtest bus
ABM Switch ControlFrom TDI To TDO
SH SL SG
Mixed-Signal Test Bus IEEE1149.4
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Analog Output Cell
- +-+
S9 S10
S5 S8 S7 S6
Vclamp
AB1 AB2
VH
VL
VTH
S1
S4S3
S2
AT1
AT2
Provision forinterconnect test
Bus connectionand calibration
VH and VL allow fixed
“1” and “0” values (for EXTEST) using S1, S2, S3, S4
ATn disconnected from ABn via S5, S8
Noise suppression via S9, S10, Vclamp when
ABn not in use
Mixed-Signal Test Bus IEEE1149.4
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Analog Boundary-Scan
AT1AT2
Z4
RZ1
Z3Z2
DR
+
DR
+
DR
+
DR
+
CORE
TAP
DR
+
DR
+
DR
+
DR
+
CORE
TAP
DR
+
DR
+
DR
+
DR
+
CORE
TAPTDI
TMSTCK
TDO
Mixed-Signal Test Bus IEEE1149.4
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AT1AT2
Z4
RZ1
Z3Z2
DR
+
DR
+
DR
+
DR
+
CORE
TAP
DR
+
DR
+
DR
+
DR
+
CORE
TAP
DR
+
DR
+
DR
+
DR
+
CORE
TAPTDI
TMSTCK
TDO
Constant Current
Test of R, Measurement V1
Mixed-Signal Test Bus IEEE1149.4
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Test of R, Measurement V2
AT1
AT2
Z4
RZ1
Z3Z2
DR
+
DR
+
DR
+
DR
+
CORE
TAP
DR
+
DR
+
DR
+
DR
+
CORE
TAP
DR
+
DR
+
DR
+
DR
+
CORE
TAPTDI
TMSTCK
TDO
Constant Current
Mixed-Signal Test Bus IEEE1149.4
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Test of R, Result
R = (V2 - V1) / I
Results for three impedances (Z1, Z2, Z3) can be calculated and checked against correct values!
This metrology was proven and presented at the 1993 ITC by Ken Parker in a paper entitled: “Structure and Metrology for an Analog Testability Bus” by Ken Parker, John McDermid, and Stig Oresjo of HP.
Mixed-Signal Test Bus IEEE1149.4
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IEEE 1149.4 Types of Testing
Interconnect : Short, Open
Parametric Testing : Passive Element measurement
Internal Testing : DfT (Design for Test) , BIST (Built-In Self-Test)
Mixed-Signal Test Bus IEEE1149.4
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For Further Information
Officers:
Adam Osseiran, IEEE 1149.4 Working Group Chair
Fluence Technology (Europe) [email protected] Stephen Sunter, Vice Chair
LogicVision, CANADA [email protected] Adam Cron, Editor (previous Chair)
Synopsys, USA [email protected] Elbert Nhan, Secretary
Johns Hopkins University, USA
The IEEE 1149.4 Web page: http://grouper.ieee.org/groups/1149/4/
Mixed-Signal Test Bus IEEE1149.4
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To Learn more ....
The IEEE Standard Document 0-7381-1755-2 SH94761-NCD; 59$
ITC97, P8.2; IEEE D&TC, Fall 96, pp. 98-101 (Cron, Viewlogic)
ITC93, P15.2 (Parker et al, HP); ITC96, P15.1 (Whetsel, TI); ITC96, P4.2
(Lofstrom, KLIC)
K. Parker, “Boundary-Scan Handbook: Analog & Digital”, Kluwer, 1998
(2nd Edition). Chap. 7
Perry, “Fundamentals of Mixed-Signal Test”, 1999, <www.soft-test.com>
A. Osseiran, “Analog & Mixed-Signal Boundary Scan: a Guide to the
1149.4 Test Standard”, Kluwer, 1999, <www.wkap.nl>
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