Modeling and Control of Three-Phase PWM Converters...Dushan Boroyevich: Modeling and Control of Three-Phase PWM Converters Tutorial at PECon 2008, Johor Bahru, Malaysia, 30 November

1

Center for Power Electronics SystemsA National Science Foundation Engineering Research Center

Virginia Tech, University of Wisconsin - Madison, Rensselaer Polytechnic InstituteNorth Carolina A&T State University, University of Puerto Rico - Mayaguez

Modeling and Control ofThree-Phase PWM Converters

Dushan BoroyevichVirginia Tech, Blacksburg, Virginia, USA

presented at:

The 2nd IEEE International Power & Energy ConferenceJohor Bahru, MALAYSIA

30 November 2008

PECon 2008

DB-2

Outline

1. Introduction2. Switching Modeling and PWM3. Average Modeling4. Small-Signal Modeling5. Closed-Loop Control Design

6. More Complex Converters

PECon2008

Dushan Boroyevich: Modeling and Control of Three-Phase PWM ConvertersTutorial at PECon 2008, Johor Bahru, Malaysia, 30 November 2008

2

DB-3

Diode Rectifier SCR Rectifier

First Three-Phase Converters

DB-4

Three-Phase Diode Rectifierwith Current Load

)cos( tVv ama ω=

)3

2cos( πω −= tVv amb

)3

2cos( πω += tVv amc0

300

600

0 60 120 180 240 300 360

Rectified Voltage

|vab| |vbc| |vca|

-600

-300

0

300

600

0 60 120 180 240 300 360

va vb vc

iaamV

amV⋅3

amV⋅5.1

Phase Voltage & Current


3

DB-5

Three-Phase Diode Rectifierwith Capacitive Load

Per phase load current

DB-6

Boost Rectifier Buck Inverter Voltage Source Inverter (VSI)

Buck Rectifier Boost InverterCurrent Source Inverter (CSI)

Three-Phase Pulse Width Modulated (PWM) Converters


4

DB-7

Three-Phase Applications

Power Factor Correction

Adjustable input displacement factorRegulated dc bus voltage

Three-phase PWM

Rectifier

InputFilter

DC Loadsor other

ConvertersFilter DC

Bus

AC Motor Drives

VSI with uncontrolled rectifier or CSI with SCR rectifierFirst and still the most common applicationRegulated output ac voltage or current (amplitude and frequency)

Rectifier FilterInputFilter

ACMotor

Three-phase PWM

Inverter

Usually only unidirectional power flow

DB-8


Uninterruptible Power Supply (UPS) – Parallel

Energy Storage (Battery)

Three-phase AC Load

Three-phase PWM

Inverter

Three-phase AC Load

Three-phase PWM

Converter

Three-phase PWM

Rectifier

Energy Storage (Battery)

Uninterruptible Power Supply – Series

• High efficiency• Power interruption• No power quality

improvement to source or grid

• Lower efficiency• No power interruption• Improvement source power quality• Input power quality improvement


5

DB-9


AC-AC Power Conversion

Cascade connection of Boost rectifier and VSI or Buck rectifier and CSIAdjustable displacement factor at input and outputBidirectional power flowUtility applications (e.g. UPFC)

Three-phase PWM

Rectifier

InputFilter

Three-phase AC Load

Three-phase PWM

Inverter

OutputFilter

Active Filters

Three-phase PWM

Converter

Three-phase Nonlinear

or Reactive Load

• Power factor control• Reduced current distortion• Improved damping• Utility applications

(e.g. STATCOM)

DB-10

source Input Filter

Controller

Switchingnetwork

Output Filter Load

Feedforward Feedback

• Switching network is discontinuous and nonlinear

?

Generalized Structure of A Power Converter


6

DB-11

Three-phase PWM converters below 100 kW operate with relatively high switching frequency (20 kHz - 100 kHz)

Elimination of audible noiseReduction of the size of reactive componentsSignificant improvement in waveform quality and closed-loop perfomance

Motivation

Only systems with switching frequency much higher than the line frequency will be studied!

1. MODELING

2. CONTROL DESIGN

DB-12

Modulator

CurrentControl

OutputControl

Three-phasePWM

Converter

CurrentFeedback

OutputFeedback

Small-signal modeling ofThree-phase PWM convertersThree-phase modulatorCurrent controllers

Modeling


7

DB-13

Control design ofCurrent controlOuter control loops

Modulator

CurrentControl

OutputControl

Three-phasePWM

Converter

CurrentFeedback

OutputFeedback

Control Design

DB-14

Steps in Modeling of Three-PhasePWM Converters

1. Switching model– Time-discontinuous– Time-varying– Non-linear

2. Average model in stationary coordinates– Time-continuous– Time-varying– Non-linear

3. Average model in rotating (synchronous) coordinates– Time-continuous– Time-invariant– Non-linear

4. Small-signal model– Time-continuous– Time-invariant– Linear


8

DB-15

Focus

• Power converter modeling for control design!• Only converters utilizing high-frequency synthesis:

• Minor emphasis on modulation• Only classical, small-signal control approach• No power stage design and optimization• No power device discussion• No topology evaluation, only control implications• No application considerations

mm ωω <<

DB-16

Outline

1. Introduction• Vector representation of three-phase variables

2. Switching Modeling and PWM3. Average Modeling4. Small-Signal Modeling5. Closed-Loop Control Design


PECon2008


9

DB-17

Y-connection Δ-connection

3-phase 4-wire

Three-Phase Circuits - Source

DB-18


3-phase 4-wire

Three-Phase Circuits - Load


10

DB-19


Three-Phase Variables

0≡++ cba iii

0≡++ cabcab vvv

0≠++ cnbnan vvv

0≡++ cba iii

0≡++ cabcab vvv

n

anv

bnvcnv

ai

bi

ci

a

b

c

abv

bcv

cavcai

bciabi

ai

bi

ci

a

b

c

0≠++ cabcab iii

baab vvv −=

cbbc vvv −=

acca vvv −=

abcaa iii −=

bcabb iii −=

cabcc iii −=

DB-20

-100

0

100

0 180 360 540 720

vb vc

cba vvv ++

va

Sinusoidal, Balanced, Symmetrical


11

DB-21

-100

0

100

0 180 360 540 720

vb vc

cba vvv ++

va

Non-sinusoidal, Balanced, Symmetrical

DB-22

-100

0

100

0 180 360 540 720

vb vc

cba vvv ++

va

Non-sinusoidal, Unbalanced, Symmetrical


12

DB-23

-100

0

100

0 180 360 540 720

vbvc

cba vvv ++

va

Non-sinusoidal, Balanced, Asymmetrical

DB-24

-100

0

100

0 180 360 540 720

vb

vc

cba vvv ++

va

Non-sinusoidal, Unbalanced, Asymmetrical


13

DB-25

Euclid vector representations

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

)()()(

)(tvtvtv

tv

c

b

ar

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

)()()(

)(tititi

ti

c

b

ar

Euclidean Space:

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

001

aur

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

010

bur

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

100

cur

a

b

cvr

av

bv

cv

Vector Representations of Three-Phase Variables

DB-26

θ

vr

wr

222221

211

,|||| n

n

ii vvvvvvv +++==>=< ∑

=

Krrr

∑=

==>=<n

iii

TT wvvwwvwv1

, rrrrrr

||||||||max||||

0 xx

xr

r

rAA

≠∀=

Vector Multiplication andNorms in Euclidean Spaces

• Inner product:

• Vector norm (length):

θcos, ⋅⋅>=< wvwv rrrr• “Dot” product:

θsin|||| ⋅⋅=× wvwv rrrr• “Cross” product:

• Norm of a matrix:


14

DB-27

• Multiplication of a vector with any nonsingular matrix, T, of the same order:

abcxyz vv rr⋅= T

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡⋅= −

001

1 in Tabcxur

ab

c

x

z

y

Change of Coordinates

is equivalent to the representation of the same vector in a different coordinate system (xyz), whose unit vectors have the following coordinates in the original coordinate system (abc):

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡⋅= −

010

1 in Tabcyur

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡⋅= −

100

1 in Tabczur

• If , new coordinates are also orthogonal.0,,, === xzzyyx uuuuuu rrrrrr

DB-28

tva cos=

)3

2cos( π−= tvb

)3

2cos( π+= tvc

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

c

b

a

ph

vvv

vr

ab

c

phvr

llv −r

Example: Balanced Three-Phase Voltages in abc Space


15

DB-29

0≡++ cba iii 0≡++ cabcab vvv

This defines a 2-dimensional subspace χ , perpendicular to the vectorin abc-space.

αβγ -space is traditionally defined by:• α -axis is chosen as

projection of the a-axis onto χ ,

• γ -axis is co-linear with vector

• β - axis is defined by right-hand rule.

[ ]T111

[ ]T111

a

b

c

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

111

χ

Change of Coordinates ( abc to αβγ )

DB-30

The transformation matrix

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

−

−−

=

21

21

21

23

230

21

211

32

/ abcTαβγ

abcabc vTv rr⋅= /αβγαβγ

abcabc iirr

⋅= /Tαβγαβγ

1|||| / =abcTαβγ ab

c

χ α

γ

β

Transformation Matrix . abcT /αβγ

⇒⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

111

abcxr

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

300

αβγxr

Example:


16

DB-31

⎥⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢⎢

⎣

⎡

−−

−=== −

21

23

21

21

23

21

2101

321

/Tαβγ/abcαβγ/abcabc TTT αβγ

αβγαβγ vTv abcabcrr

⋅= /

αβγαβγ iTi abcabcrr

⋅= /

Transformation Matrix .αβγ/abcT

DB-32

tva cos= )3

2cos( π−= tvb )

32cos( π

+= tvc

abcabc vTv rr⋅= /αβγαβγ

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

c

b

a

abc

vvv

vr

Example: Balanced Three-Phase Voltages in αβγ Space

phvrllv −

r


17

DB-33

RL

av

bvcvR R

L L

ai

bi

ci

vidtid

dtidiv rr

rrrr 11 −− +=⇔+= LRLLR

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

c

b

a

vvv

vr

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

c

b

a

iii

ir

vTv xxrr

⋅= iTi xx

rr⋅= such that xvr xi

rand are constant

xT is differentiable and invertible.

Example: State-Space Equations

are sinusoidal in steady-state! Find a coordinate transformation:vr ir

and

, ,

in steady state, and

DB-34

RL

av

bvcvR R

L L

ai

bi

ci

dtid

ivr

rr LR +=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

c

b

a

iii

ir

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

+

−=⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

)3

2cos(

)3

2cos(

)cos(

πω

πω

ω

tV

tV

tV

vvv

v

m

m

m

c

b

ar

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

RR

R

000000

R

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

LL

L

000000

Lvidtid rrr

⋅+⋅−= −− 11 LRL

Example: State-Space Equations


18

DB-35

Natural Response

τττ dveietit

tt ⋅⋅⋅+⋅= −−⋅−⋅− ∫−−

)()0()( 1

0

)(11 rrrLRLRL

Forced Response

⎥⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢⎢

⎣

⎡

⋅⋅−

+−+

⋅⋅+

+−−

⋅−−

⋅+⋅⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

⋅−

⋅−

⋅−

⋅−

tLR

tLR

tLR

mtLR

c

b

a

eZ

LRt

eZ

LRt

eZRt

ZVe

iii

ti

23)

32cos(

23)

32cos(

)cos(

)0()0()0(

)(

ωφπω

ωφπω

φω

r

RLω

φ arctan=222 LRZ ω+=φω jj eZLR ⋅=+=Z

where per-phase impedance, Z , at the source frequency, ω , is defined as:

Example: State-Space Equations – Solution

DB-36

vTv xxrr

⋅=

iTi xx

rr⋅=

where: xvr xir

and are constant in steady state

:xT differentiable and invertible

Want to find change of variables:

[ ]

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

−+

−−

−

⋅=∞→

)3

2cos(

)3

2cos(

)cos(

)(lim

φπω

φπω

φω

t

t

t

Iti mt

r

RLω

φ arctan=

222 LR

VI mm

ω+=

0lim ≠⎥⎦

⎤⎢⎣

⎡∞→ dt

idt

r

Example: State-Space Equations –Steady State Solution


19

DB-37

A rotating vector in αβγ space can be a constant vector in a rotating space

α

β

d

q

θ

vr

dv

αvqv

βv ⎥⎦

⎤⎢⎣

⎡⎥⎦

⎤⎢⎣

⎡−

=⎥⎦

⎤⎢⎣

⎡

β

α

θθθθ

vv

vv

q

d

cossinsincos

)0()(0

θττωθ += ∫ dt

Where ω is the rotating speed

Transformation Matrix . αβ/dqT

DB-38

Transformation Matrix .αβγ/0dqT

Preserve the same third axis, that is 0-axis is the same as γ-axis

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡−=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

γ

β

α

θθθθ

vvv

vvv

0

q

d

1000cossin0sincos

Therefore

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡−=

1000cossin0sincos

T / θθθθ

αβγdq0T

dq0dq0dq0αβγ TTT αβγαβγ /1

// == −

1|||| / =αβγdq0T


20

DB-39

Transformation Matrix .abcdqT /0

abcabcdq0dq0 vTv rr⋅= /

abcabcαβγdq0αβγαβγdq0dq0 vTTvTv rrr⋅⋅=⋅= /// αβγ

Therefore

where

abcdq0abcdq0 TTT /// αβγαβγ ⋅=

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

+−−−−

+−

=

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

−

−−

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡−=

21

21

21

)3

2sin()3

2sin(sin

)3

2cos()3

2cos(cos

32

21

21

21

23

230

21

211

1000cossin0sincos

32 πθπθθ

πθπθθ

θθθθ

Park’s Transformation

1|||| / =abcdq0T Tabcdq0abcdq0dq0abc TTT /

1// == −

DB-40

tva cos= )3

2cos( π−= tvb )

32cos( π

+= tvc

abcabcdq0dq0 vTv rr⋅= /

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

c

b

a

abc

vvv

vrphvr

llv −

r

Example: Balanced Three-Phase Voltages in dq0 Space


21

DB-41

[ ] ccbbaa

c

b

a

cba iviviviii

vvvivivp ++=⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡⋅==⋅=

rrrrr T

00qqddccbbaa iviviviviviviviviv ++=++=++ γγββαα

It can be easily proved that:

where v & i are corresponding voltages and currents in a three-phase circuit.

Power Definition in Three-Phase Circuits

DB-42

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

+

−=⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

)3

2cos(

)3

2cos(

)cos(

πω

πω

ω

tV

tV

tV

vvv

v

am

am

am

c

b

ar

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

−+

−−

−

=⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

)3

2cos(

)3

2cos(

)cos(

φπω

φπω

φω

tI

tI

tI

iii

i

am

am

am

c

b

ar

RL

av

bvcvR R

L L

ai

bi

ci

RLω

φ arctan=where:

Example:Power in Sinusoidal Steady State


22

DB-43

Example:Power in Sinusoidal Steady State

φφ cos23cos|||||||||||| amam IVivivP =⋅=⋅=

rrrr

φφ sin23sin|||||||||||| amam IVivivQ =⋅=×=

rrrr

RL

av

bvcvR R

L L

ai

bi

ci

DB-44

)cos( φω += tVv amaφφ j

amama eVV ⋅=∠=V

ref

amV

φ

Phasors are defined ONLY for sinusoidal steady state!

aV

Phasor Representation

• Vector representation is NOT phasor representation!


23

DB-45

[ ] [ ])sin(j)cos(ReRe)cos( φωφωφω φ +++=⋅=+= tVtVeVtVv mmj

mma

φφ jrms

ma eVV

⋅=∠=2

V

Phasors are defined ONLY for sinusoidal steady state!

ref

rmsV

φ

aV

Phasors are very useful for the analysis of linear systems without transients, which are excited by constant single frequency (ω ) sinusoidal generators.

( )tjama etVv ωφω ⋅⋅=+= VRe2)cos(

Phasor Representation

DB-46

Outline

1. Introduction2. Switching Modeling and PWM

• Switching model of VSI & boost rectifier• Space vector modulation for VSI & boost rectifier• Other modulations for VSI & boost rectifier• Switching model and modulation for CSI & buck rectifier

3. Average Modeling4. Small-Signal Modeling5. Closed-Loop Control Design


PECon2008


24

DB-47

• Boost Rectifierwhere Vm is the peakvalue of the line-to-lineinput voltage

mdc VV >

dcv

CAv ABvBCv

Laps bps cps

ans bns cns

C R

p

n

avbv

cv

• Voltage Source Inverter(VSI)

mdc VV > Load

aps bps cps

ans bns cns

L

C

p

n

dcvCAvBCv

ABvav

bvcv

Boost Rectifier / Voltage Source Inverter

vdc

Vm

VSI / BOOST RECTIFIERDC VOLTAGE RANGE

t|vab| |vbc| |vca|

DB-48

Switching function:

s =1, v = 0, if switch s is closed

0, i = 0, if switch s is open

• Voltage source or capacitor cannot be shorted• Current source or inductor cannot be open

Switching constraints:

s

iv

v

iv

i

Current bi-directional two-quadrant switch

Method of Modeling Switching Network


25

DB-49

• Three-Switch (Single-Pole-Double-Throw)

Boost RectifierVoltage Source Inverter

Allowed switching combinations:

;1=+ inip ss },,{ cbai ∈

p

n

aps bps cps

ans bns cns

avbv

cv

• Define Voltage-Unidirectional Single-Pole-Double-Throw Switch and switching function

;1 inipi sss −== },,{ cbai ∈

p

n

av

bv

cv

as

bs

cs

00

0

11

1

ai

bi

ci

dci

dcv

DC-Voltage-UnidirectionalThree-Phase Switching Network

DB-50

Find the relationships:

av

bv

av

bv

av

bv

av

bv

0=aps 0=bps 0=aps 1=bps

1=aps 0=bps 1=aps 1=bps

),( dcababab vsfv = ),( dcbcbcbc vsfv = ),( dccacaca vsfv =

),,,( cbaijidc iiisfi =

dcv dcv

dcv dcv

0=abv dcab vv −=

dcab vv = 0=abv

dcab

dcbpap

baab

vs

vssvvv

=

−=−=

)(

bbpaapdc isisi +=

dci dci

dci dci

ai

bi

ai

bi

ai

bi

ai

bi

Development of Switching Model(Boost rectifier / Voltage source inverter)


26

DB-51

Define phase-leg switching function

aps bps cps

ans bns cns

avbv

cv

ai

bi

ci

dci

dcv

;1 inipi sss −== },,{ cbai ∈

sa sb sc sa-sb sb-sc sc-sa idc vab vbc vca0 0 0 0 0 0 0 0 0 00 0 1 0 -1 1 ic 0 -vdc vdc0 1 0 -1 1 0 ib -vdc vdc 00 1 1 -1 0 1 ib+ic -vdc 0 vdc1 0 0 1 0 -1 ia vdc 0 -vdc1 0 1 1 -1 0 ia+ic vdc -vdc 01 1 0 0 1 -1 ia+ib 0 vdc -vdc1 1 1 0 0 0 ia+ib+ic 0 0 0


DB-52


Instantaneous voltage equation Instantaneous current equation

dc

ca

bc

ab

dc

ac

cb

ba

ca

bc

abv

sss

vssssss

vvv

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

−−−

=⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡[ ]

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡⋅=

c

b

a

cbadciii

sssi

Note that: baab sss −= baab vvv −=

p

n

av

bv

cv

as

bs

cs

00

0

11

1

ai

bi

ci

dci

dcv

……


27

DB-53

Relationship Between Line-to-Line Current and Phase Current

caaba iii −=

abbcb iii −=

abbccaababbccaabba iiiiiiiiii 3)(2)( =+−=−−−=−

)(31

baab iii −= Similarly )(31

cbbc iii −= )(31

acca iii −=

Assume 0=++ cabcab iii

ai

bi

ci

abi

bcicai

[ ]⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡⋅=−+−+−=

−+−+−=++=

ca

bc

ab

cabcabaccacbbcbaab

bccacabbcbcaabaccbbaadc

iii

sssssississi

iisiisiisisisisi

)()()(

)()()(

bccac iii −=

DB-54

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

−−−

=⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=−

ac

cb

ba

ca

bc

ab

ll

vvvvvv

vvv

vr

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

−−−

=⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=−

ac

cb

ba

ca

bc

ab

ll

ssssss

sss

sr

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

−−−

=⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=−

ac

cb

ba

ca

bc

ab

ll

iiiiii

iii

i31r

p

n

av

bv

cv

as

bs

cs

00

0

11

1

ai

bi

ci

dci

dcvdcllll vsv ⋅= −−

rr

llT

lldc isi −− ⋅=rr

where:

Boost Rectifier / Voltage Source Inverter Switching Model


28

DB-55

Outline





PECon2008

DB-56

Switching States forBoost Rectifier / Voltage Source Inverter

idc vab

Vdc

sa scsb0

1

00

00

0 00

0 00

0

11

11 1

1

1

1

111

icib

ib+ic

0

iaia+icia+ib

ia+ib+ic

Switching state

pnn

ppn

npnnpp

nnp

pnp

ppp

nnnvcavbc

Vdc

Vdc

Vdc

Vdc

Vdc

-Vdc

-Vdc

-Vdc

-Vdc

-Vdc

-Vdc

00

000

0

0000

00

p

n

av

bv

cv

as

bs

cs

00

0

11

1

ai

bi

ci

dci

dcV


29

DB-57

Vector Space of Line-to-Line Variables

a

c

b

ab bc

ca

α

β

ab

bc

ca

[1 1 1]T

χχ

• Phase variables (a, b and c) produceline-to-line variables (ab, bc and ca) in plane-χ

• Line-to-line variables (ab, bc and ca) do not haveγ-component in αβγ-coordinate system

DB-58

Line-to-Line Voltage Space Vector

where⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡⋅=⎥

⎦

⎤⎢⎣

⎡

ca

bc

ab

abc

vvv

Tvv

/αββ

α

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

−

−−⋅=

23

230

21

211

32

/ abcTαβ

abα

βbc

ca

ρ

vα

vβ

θ

• Space vectorθ⋅ρ= jevr

22 vv βα +=ρ

⎟⎠

⎞⎜⎝

⎛=θ

α

β−

vv1tan

If Vm is the amplitude of balanced, symmetrical, three-phase line-to-line

voltages, then mV23

⋅=ρ

vr


30

DB-59

Switching State Vector [pnn]

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

⋅

⋅=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

−⋅

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

−

−−⋅=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡⋅=⎥

⎦

⎤⎢⎣

⎡=

dc

dc

dc

dc

pnnca

bc

ab

abcpnn

pnn

V

V

V

V

vvv

Tvv

V

2123

0

23

230

21

211

32

/αββ

αr

θ⋅ρ== j1pnn eVVrr

dcV2 ⋅=ρ

°=⎟⎟⎠

⎞⎜⎜⎝

⎛=θ

α

β− 30vv1tan

ab, α

βbc

ca

ρ

vα

vβ

θ

1Vr

DB-60

Switching State Vector [ppn]

⎥⎦

⎤⎢⎣

⎡⋅

=⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

−⋅

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

−

−−⋅=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡⋅=⎥

⎦

⎤⎢⎣

⎡=

dcdc

dc

ppnca

bc

ab

abcppn

ppn VV

Vvvv

Tvv

V2

00

23

230

21

211

32

/αββ

αr

θ⋅ρ== j2ppn eVVrr

dcV2 ⋅=ρ

°=⎟⎠

⎞⎜⎝

⎛=θ

α

β− 90vv1tan ab, α

βbc

ca

ρ

vβ

θ

2Vr


31

DB-61

Switching State Vector [ppp]

⎥⎦

⎤⎢⎣

⎡=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡⋅

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

−

−−⋅=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡⋅=⎥

⎦

⎤⎢⎣

⎡=

00

000

23

230

21

211

32

/

pppca

bc

ab

abcppp

ppp

vvv

Tvv

V αββ

αr

0VV 0ppp ==rr

ab, α

βbc

ca

0Vr

DB-62

Switching State Vectors

dcV2 ⋅

Sector I

IV

III

II

V

VI

at center point

30

150

90

-90

-150

0

-30

00

ρ θ (°)

ab, α

bc

ca

β

][ pnnV1

r

][ ppnV2

r

][npnV3

r

][nppV4

r

][nnpV5

r

][ pnpV6

r

][ pppV0

r

][nnnV0

r

][ pnnV1

r

][ ppnV2

r

][npnV3

r

][nppV4

r

][nnpV5

r

][ pnpV6

r

][][ nnnpppV0 ==r


32

DB-63

Reference Voltage Vector, Vref

ab, α

bc

ca

β

θvα

vβθ

β

α ⋅ρ=⎥⎦

⎤⎢⎣

⎡= j

refref e

vv

Vr

m22 V

23vv ⋅=+=ρ βα

tvv1 ω=⎟

⎠

⎞⎜⎝

⎛=θ

α

β−tan

where

In general,

( )( )( )⎥

⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

°+ω⋅°−ω⋅

ω⋅=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

120tV120tVtV

vvv

m

m

m

refca

bc

ab

coscos

cos

Assume

)()()( tjmref etV

23tV θ⋅⋅=

r

ρ ][ pnnV1

r

][ pnpV6

r

][ ppnV2

r

][npnV3

r

][nppV4

r

][nnpV5

r

at center point][][ nnnpppV0 ==r

refVr

DB-64

Si

ii

T

0i

T

0ref TTdtVdtV

iS

=⎟⎟⎠

⎞⎜⎜⎝

⎛= ∑∑ ∫∫ ,

rr

Vref (α)

V1(α) V2(α)

T1 T2 T0TS

t

Total area of = Area of

∫ ∫∫∫+

+

++=21

1

S

21

1S TT

T

T

TT02

T

01

T

0ref dtVdtVdtVdtV

rrrrFor example

vα

Definition of High Frequency Synthesis


33

DB-65

Step 1 : Choose desired switching state vectors to synthesize

Step 2 : Calculate the duty ratios of chosen switching state vectors

Step 3 : Make the sequence of chosen switching state vectors

refVr

Space Vector Modulation

DB-66


ab, α

bc

ca

β

θ

vα

vβ ρ ][ pnnV1

r

][ pnpV6

r

][ ppnV2

r

][npnV3

r

][nppV4

r

][nnpV5

r

][][ nnnpppV0 ==r

refVr

ia

ib

ic

va

vc

vb

sa

sb

sc

p

n

Vdc

idc

a

bc

1

0 1

0 1

0

I

IV

III

II

V

VI

φ

ρ

2Vr

0Vr

1Vr

11 Vdr

⋅

22 Vdr

⋅ refVr


34

DB-67

ab, α

bc

ca

β

Sector I

location Chosen vectors

Sector II

Sector VI

Sector III

Sector IV

Sector VV

VI

I

III

II

IV

• Minimize the number of switching

• Minimize the harmonic distortion

Choose minimum numberof switching state vectors

adjacent to .refVr

65 VandVrr

21 VandVrr

16 VandVrr

32 VandVrr

43 VandVrr

54 VandVrr

0Vandr

refVr

][ pnnV1

r

][ pnpV6

r

][npnV3

r

][nppV4

r

][ ppnV2

r

][nnpV5

r


refVr

Step 1 : Choice of Switching State Vectors

DB-68

∫ ∫∫∫+

+

++=21

1

S

21

1S TT

T

T

TT02

T

01

T

0ref dtVdtVdtVdtV

rrrr

2211Sref TVTVTV ⋅+⋅=⋅rrr

2211S T6060

VT01

VT ⋅⎥⎦

⎤⎢⎣

⎡°°

⋅+⋅⎥⎦

⎤⎢⎣

⎡⋅=⋅⎥

⎦

⎤⎢⎣

⎡φφ

⋅ρsincos

sincos

)sin( φ−°⋅ρ

⋅== 60V3

2dTT

11

S

1

φ⋅ρ

⋅== sin2

2S

2

V32d

TT

210 dd1d −−=φ

From HF synthesis definition,

Assume is constant in TS ,

where °−θ=φ 30

ρ

refVr

2Vr

0Vr

1Vr

11 Vdr

⋅

22 Vdr

⋅ refVr

Step 2 : Duty Ratio of Switching State Vectors at Sector I


35

DB-69

)sin( φ−°⋅ρ

⋅== 60V3

2dTT

NN

S

N

φ⋅ρ

⋅==+

++ sin

1N1N

S

1N

V32d

TT

1NN0 dd1d +−−=

Other sectors have the same results of duty ratio.

where ( ) °−°⋅−−θ=φ 30601NN : sector number ( 1 ~ 6 )

ρ

φ

1NV +

r

1N1N Vd ++ ⋅r

0Vr

NVr

NN Vdr

⋅

refVr

Duty Ratio of Switching State Vectors

DB-70

)sin( φ−°⋅= 60VVd

dc

mN

φ⋅=+ sindc

m1N V

Vd

1NN0 dd1d +−−=

Define the modulation index

For all the switching state vectors, dcN V2V ⋅=

dc

m

VVM =

)sin( φ−°⋅= 60MdN

φ⋅=+ sinMd 1N

1NN0 dd1d +−−=

and mV23

⋅=ρ

Modulation Index


36

DB-71

ab, α

bc

ca

βAssume d0 = 0, then dN + dN+1 = 1

The trajectory of makesa hexagon.

( )( )

( )

1

30VV

30M60Mdd

dc

m

1NN

=

φ−°⋅=

φ−°⋅=φ+φ−°⋅=+ +

cos

cossin)sin(

( )φ−°=∴

30VV dc

m cos

refVr

][ pnnV1

r

][ pnpV6

r

][ ppnV2

r

][npnV3

r

][nppV4

r

][nnpV5

r


refVr

Maximum Amplitude of Vref

DB-72

Maximum Amplitude of Vref

ab, α

bc

ca

βAssume M = 1, then

The trajectory of makes

a circle whose radius is

1VV

dc

m =

dcm VV =∴

dcV⋅23

This trajectory of representsthe largest 3-phase sinusoidalvoltage that can be synthesized.

θ⋅⋅= jdcref eV

23V

r ][ pnnV1

r

][ pnpV6

r

][ ppnV2

r

][npnV3

r

][nppV4

r

][nnpV5

r


refVr

refVr

refVr


37

DB-73

Step 3 : Sequence of Switching State Vectors

TS

Sa

Sc

Sb

V1 V2 V0

T2T1 T0

Sa

Sc

Sb

V1 V2

T0

V2

T12

T22

T12

T22

V1V0

TS

Asymmetricalsequence

Symmetricalsequence

3-phasecommutation

2-phasecommutation

Feedback

Feed forward

=⎟⎟⎠

⎞⎜⎜⎝

⎛== ∑ ∫∫

=1i

T

0i

T

0ref

iS

dtVdtVrr

DB-74

TS

T2T1

Sa

Sc

Sb

T0 /2 T0 /2

TS

T2T1T0 /2 T0 /2

V0 V0V1 V2 V0 V1 V2 V0

• Use both zero switching state vectors

• Asymmetrical sequence

• Six commutations per switching cycle

< Example in sector I >

• 3Φ-LA has same characteristics

Sequence of SSVs – SVM 1(Three-Phase – Right Aligned: 3Φ-RA)


38

DB-75

TS

Sa

Sc

Sb

TS

V0 V1 V2 V0

• Use both zero switching state vectors

• Symmetrical sequence

• Six commutations per switching cycle

Low THD

V1V2


T04

T12

T22

T02

T22

T12

T04

T04

T12

T22

T02

T22

T12

T04

V0 V0V1 V2 V0 V1V2

Sequence of SSVs – SVM 2(Three-Phase – Centered: 3Φ-C)

DB-76

TS

T2T1

Sa

Sc

Sb

T0

V1 V2 V0 [ppp]

• Use zero vectors alternatively in adjacent switching cycle

• Asymmetrical sequence in TS , but symmetrical in 2·TS

• Three commutations


50 % switching loss reduction

V1V2 V0 [nnn]

TS

T1T2 T0

• Introduction of harmonics around ST2

1⋅

Sequence of SSVs – SVM 3(Three-Phase – Double-Period: 3Φ-2T)


39

DB-77

• Use a zero vector in one switching cycle

• Asymmetrical sequence


Reduced switching losses

TS

Sa

Sc

Sb

V1 V2 V0[ppp]

TS

• Four commutations

Sector I, III, V : [ppp]Sector II, IV, VI : [nnn]

T2T1 T0 T2T1 T0

V1 V2 V0[ppp]

• 2Φ-LA has same characteristics

Sequence of SSVs – SVM 4(Two-Phase – Right Aligned: 2Φ-RA)

DB-78

• Use a zero vector in one switching cycle

• Symmetrical sequence


Reduced switching losses

TS

Sa

Sc

Sb

V1 V2 [ppp]

• Four commutations

Sector I, III, V : [ppp]Sector II, IV, VI : [nnn]

T0

V1

Low THD

V2

T12

T22

T12

T22

TS

T0T12

T22

T12

T22

V2 [ppp]V1 V2

Sequence of SSVs – SVM 5(Two-Phase – Centered: 2Φ-C)


40

DB-79

• Possible sequences: 2Φ-RA-mL, 2Φ-LA-mL, or 2Φ-C-mL

• Reduce the switching losses up to 50% compared to 3Φ modulations, assuming that switching losses are proportional to the current

• Choose a zero switching state vector to avoid switching the phase with the highest instantaneous current

|ia| > |ic| ?No

YesV0 = [ppp]

V0 = [nnn]

Choice of zero vector in sector I (pnn, ppn, and ppp or nnn)

Sequence of SSVs – SVM 6 (Minimum-Loss SVM)

(Two-Phase – Right Aligned – minimum Loss: 2Φ-RA-mL)

DB-80

Sector Ivab

vbc

vca

va

vc

vbia

ic

ib

nnnppp nnn

δ

vab

vbc

vca

va

vc

vb

ia

ic

ib

δ

ppp

• Switching loss reduction = 50%°≤ 30δ °> 30δ

• Switching loss reduction < 50%• •

(pnn, ppn)

Sector I

(pnn, ppn)

LineVoltages

PhaseVoltages

PhaseCurrents

Example of 2Φ- x -mL SVM in Sector Ifor balanced, symmetrical, sinusoidal, steady-state case


41

DB-81

THD of line-to-line voltage THD of phase currentwith L + VABC load/source

With the Fourier series ,1

2n

2n

V

VTHD

∑∞

==∑∞

=

ω⋅=1n

tjnn eVV

Modulation index, M Modulation index, M0 1 0 1

3Φ

3Φ-C

2Φ

3Φ or 2Φ3Φ-2T

3Φ-C

RA or LA 3Φ-2T

RA or LA

Calculated and switching-model simulation results for .lineS ff ⋅>100

Comparison:Total Harmonic Distortion (THD)

DB-82

For RA or LA modulations:

Relative peak-to-peak current ripple

where TP = TS , exceptTP = 2TS , for 3Φ-2T.

( ) Sdc

pp TMML

VI ⋅⋅−⋅⋅

⋅= 1

32

Modulation index, M0 1

For centered modulations:

( ) Pdc

pp TMML

VI ⋅⋅−⋅⋅

= 13

2Φ or 3Φ-C

2Φ or 3ΦRA or LA

or3Φ-2T

M : modulation indexL : load inductance

Comparison:Peak-to-Peak Current Ripple


42

DB-83

• Number of commutationsper switching cycle:

3Φ-x : 6

2Φ- x -mL avoids switching the phase with highest current between -30° and 30°.

3Φ-2T : 32Φ-x : 4

SVM2

SVM1,3,53Φ-x

3Φ-2T

min Loss

2Φ-xMax Loss

Comparison: Switching Losses

DB-84

Outline





PECon2008


43

DB-85

Pulse WidthModulation

Feedforwardscheme

Feedbackscheme

Sinusoidal PWM

Third-harmonic injection PWM

Space vector modulations(SVM1, 2, 3, 4 and 5)

Hysteresis current control

Space vector modulations(SVM 6)

Pulse AmplitudeModulation

Modulation Methods

DB-86

Sinusoidal Pulse Width Modulation(SPWM)

vavref

vcar

sap

san

2Vdc

2Vdc

• Determine the switching state by magnitude of vref and vcar

If |vref| > |vcar|, then sap on,If |vref| < |vcar|, then san on

• Switching frequency is the same as carrier wave frequency, fc

fsin

fc


44

DB-87

va

2Vdc

Va(1)

-Va(1) 2Vdc

va(1) : Fundamental of v a

refav

refaV

vcar

Vcar

Vcar

t

t

refaV−

dc

1a

dc

1a

car

refa

VV2

2V

VVV )()( ⋅

=⎟⎠⎞

⎜⎝⎛

=car

refadc

1a VV

2VV ⋅=)(

Waveforms of Single-Phase SPWM

DB-88

refbvref

av refcv

ia

ib

ic

sa

sb

sc

p

n

2Vdc

2Vdc

vcvbva

vcar

refV

refV−

Vcar

Vcar

t

Three-Phase SPWM


45

DB-89

refbv

refav

refcv

V1 V1V2 V2V0V0 V0

pnn

ppn

ppp

nnn

pnn

ppn

t

vcar

TS

t

t

t

sa

sb

sc

nnn

T0N T0P T0N

Assume and areconstant in a switching cycle.

refc

refb

refa vvv ,

Symmetrical (Center-based)Three-phase commutation

SVM 2

)( carrefa

car

SN0 Vv

V4TT −⋅⋅

−=

)(

)(

carrefc

car

S

carrefc

car

SSP0

VvV4T

VvV4T

2T

2T

+⋅⋅

=

−⋅⋅

+=

Modulation Example of SPWM in Sector I

DB-90

V1 V1V2 V2V0V0 V0

pnn

ppn

ppp

nnn

pnn

ppn

TS

t

t

t

sa

sb

sc

nnn

T0N T0P T0N

V1

V2

d1·V1

d2·V2

φV0

ρ

)sin( φ−°⋅⋅== 60VV2d

TT

1

m1

S

1

φ⋅⋅== sin2

m2

S

2

VV2d

TT

210 dd1d −−=)cos( φ−°⋅⋅−=

==

304

TVV

4T

4TT

2T

S

dc

mS

0N0

P0

refvr

Modulation Example of SVM2 in Sector I


46

DB-91

10 20 30 40 500

0.05

0.1

0.15

60

T0NT0P2

T0N+ T0P2

0.05

0.1

0.15

φ in sector I ( o )

TTS

T0N

T0N+ T0P2

TTS

10 20 30 40 500 60

φ in sector I ( o )

• In SPWM, assume Vref = Vcar

• In SVM2, assume Vm = Vdc

)cos( φ−°⋅−=

==

304

T4

T4TT

2T

SS

0N0

P0

0.125

0.067

0.067

)( refrefaref

SN0 Vv

V4TT −⋅⋅

−=

)( refrefcref

SP0 VvV4T

2T

+⋅⋅

=

φ⋅= cosrefrefa Vv

( )°+φ⋅= 120Vv refrefc cos

where

Zero Vector Timings in Sector I

DB-92

Maximum AC Voltage of SPWM

dcm V23V ⋅=

By definition: θ⋅⋅= jm

ref eV23vr

The maximum AC voltage:

The trajectory in SPWM:refvr θ⋅⋅= jdc

ref eV22

3vr

1551

2V3

VVV

dc

dc

SPWMm

SVMm .=⎟⎠

⎞⎜⎝

⎛ ⋅=

The maximum AC voltage of SVM: dcm VV =

SVM produces 15.5% highermaximum output than SPWM !

abα

bc

ca

β

][ pnnV1

r

][ pnpV6

r

][ ppnV2

r

][npnV3

r

][nppV4

r

][nnpV5

r

refvr

at center][][0

nnnpppV

==

r


47

DB-93

78504

2V42

V

V

V

dc

dc

Square1

SPWM1 .max)(

max)(

=π=⎟⎠⎞

⎜⎝⎛ ⋅

π

⎟⎠⎞

⎜⎝⎛

=

2Vdc

Over modulation region isnon linear with more harmonics

2V4 dc⋅

π

)(1VVcar

t

1 3.24 car

ref

VV

Overmodulation

Squarewave

switching

• Vref ≤ Vcar : Linear modulation• Vref > Vcar : Over modulation

Vref

Over Modulation of SPWM

DB-94

ref1v )(

t

ref3

ref1

ref VVV )()( +=

t3VtVv ref3

ref1

ref ω⋅+ω⋅= sinsin )()(

ref3v )(

refv

ref3V )(

refV

0

ref1V )(

ref1V )(−

Third-Harmonic Injection PWM


48

DB-95

The maximum AC voltageis 15.5 % more than SPWM

1V ref =

⎟⎠⎞⎜

⎝⎛ θ⋅+θ⋅= 3

61Vv ref

1ref sinsin)(In general,

1551

23

1V ref1 .)( =

⎟⎠⎞

⎜⎝⎛

=

1

ref1v )(

t

refv

1551V ref1 .)( =

0

Assume ,

then

Maximum AC Voltage of Third-Harmonic Injection PWM

DB-96

( ))60sin(

sin60sin22

021

0

φφφ

+°=+−°=

+++−=dddd

Vv

dc

a

1

-1

1

-1

1

-1

4T0

2T0

av

TS

bv

cv( )

)30sin(3

sin60sin22

021

0

°−⋅=

+−°−=

++−−=

φ

φφ

ddddVv

dc

b

4T0

2T1

2T1

2T2

2T2

a

dc

c

v

ddddVv

−=+°−=

+−−−=

)60sin(22

021

0

φ

Average Values of Phase-to Neutral Voltage for SVM 2 (3Φ-C) in Sector I


49

DB-97

( )

)90sin(3

)30sin(3

sin60sin22

021

0

θ

φ

φφ

−°⋅=

−°⋅=

−−°=

+−+−=dddd

Vv

dc

a

( )

)60sin()60sin(

sin60sin22

021

0

°−−=+°−=

−−°−=

+−−−=

φφ

φφ

ddddVv

dc

a

• In sector II, • In sector III,

0 120 180 240 300 36060

0

-1

1

θ ( o )

va

Sector I Sector IVSector II Sector III Sector V Sector VI

23

Average Values of Phase-to Neutral Voltage for SVM 2 (3Φ-C)

DB-98

1va =1

-1

1

-1

1

-1

av

TS

bv

cv)sin( φ−°⋅−=

⋅−=++−=

6021d21

dddv

1

021b

2T1

2T1

2T2

2T2

)sin()(

φ+°⋅−=+⋅−=+−−=

6021dd21dddv

21

021c

T0

• If ia is the largest current,

• If ic is the largest current,

( )( ) 1602

1602dddv 210a

−θ+°⋅=−φ+°⋅=

++−=

sinsin

Average Values of Phase-to Neutral Voltage for SVM 6 (2Φ-C-mL) in Sector I


50

DB-99

0 120 180 240 300 36060

0

-1

1

θ ( o )

va

Sector I Sector IVSector II Sector III Sector V Sector VI

0

-1

1

va

0 120 180 240 300 36060θ ( o )

0.60.2-0.2-0.6

• M = 1

• M = 0.8

Average Values of Phase-to Neutral Voltage for SVM 6 (2Φ-C-mL)

DB-100

iref

sap

san

2Vdc

2Vdc

Load

i

β

• Switching frequency is varyingin one switching cycle.

If , then sap on,

If , then san on

iiref >β

−2

iiref <β

+2β

iref

it

Hysteresis Current Control


51

DB-101

Pros and Cons of Hysteresis Current Control

• Simple to implement• Excellent dynamic performance

• Strong harmonics lower than the switchingfrequency (Subharmonics)

• No intercommunication betweenthe individual hysteresis controllers

Increase the switching frequencyat lower modulation index

• A tendency at lower speed to lock intolimit cycle of high-frequency switching

• Not strictly limit the current error

Pros:

Cons:

in time domain

in frequency domain

DB-102

Outline





PECon2008


52

DB-103

Buck Rectifier / Current Source Inverter– similar approach but different results –

• CSI

• Buck Rectifier

Av

Bv

Cv

aps bps cps

ans bns cns

RC

L

dcv

p

n

av

bv

cv

aps bps cps

ans bns cns

L

C

p

n

dcv

Av Bv Cvav

bvcv

R

{ }|})(||,)(||,)(max{|min tvtvtvV cabcabtx∀

=

⎟⎟⎠

⎞⎜⎜⎝

⎛=< mxdc VVV

23

•

• Unidirectional DC current

• Bi-directional DC voltage

Vx

vdc

t|vab| |vbc| |vca|

CSI / BUCK RECTIFIERDC VOLTAGE RANGE

DB-104

• Two single-pole-triple-throw (SPTT) current-unidirectional switches

• Allowed switching combinations:

aps bps cps

ans bns cns

p

n

avbv

cv

;1=++ ckbkak sss },{ npk ∈

• Topology: • Three-phase terminals are

voltage controlled• DC port is current controlled• Six current-unidirectional,

voltage-bi-directional, switches

Av

Bv

Cv

p

n

avbv

cv

Av

Bv

Cv

dci

dci

DC-Current-UnidirectionalThree-Phase Switching Network


53

DB-105

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

c

b

a

abc

vvv

vr

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

−−−

=⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

cncp

bnbp

anap

c

b

a

abc

ssssss

sss

sr

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

c

b

a

abc

iii

ir

dcabcabc isi ⋅=rr

abcTabcpn vsv rr

⋅=

where:

p

n

avbv

cv

Av

Bv

Cv

dciai

bi

ci

as bs cs

pnv

Buck Rectifier / Current Source Inverter Switching Model

DB-106


dcI2 ⋅

30

150

90

-90

-150

-30

0

ρ θ (°)

0

][abI1

r

][acI2

r

][bcI3

r

][baI4

r

][caI5

r

][cbI6

r

][aaI0

r

][bbI0

r

][ccI0

r at center point][][][ ccbbaaI0 ===r

θ

iα

iβρ

a, α

b

c

β

refIr

][abI1

r

][acI2

r][baI4

r

][caI5

r

][bcI3

r

][cbI6

r


54

DB-107

Outline

1. Introduction2. Switching Modeling and PWM3. Average Modeling

• Average model of boost rectifier• Average model of VSI• Average models in rotating coordinates

4. Small-Signal Modeling5. Closed-Loop Control Design


PECon2008

DB-108

Boost Rectifier Switching ModelState-Space Equations

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡+

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

−−−

+⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

−−−

=⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

ca

bc

ab

ca

bc

ab

ac

cb

ba

ac

cb

ba

CA

BC

AB

vvv

iii

dtdL

vvvvvv

iiiiii

dtdL

vvv

3

Rv

dtdvCi dcdc

dc +=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡−

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

ca

bc

ab

CA

BC

AB

ca

bc

ab

vvv

Lvvv

Liii

dtd

31

31

RCvi

Cdtdv dc

dcdc −=

1

dtdiLv

dtdiLv b

aba

AB −+=p

n

C R

L dcv

dci

ai

bi

ciCAv ABv

BCv

0

1av

bv

as

csbs0

10

1

cv


55

DB-109

Boost Rectifier Switching ModelState-Space Equations

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=−

CA

BC

AB

LL

vvv

vr

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=−

ca

bc

ab

ll

vvv

vr

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=−

ca

bc

ab

ll

iii

ir

llLLll v

Lv

Ldtid

−−− −=

rrr

31

31

RCvi

Cdtdv dc

dcdc −=

1

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=−

ca

bc

ab

ll

sss

sr

dcllll vsv ⋅= −−rr

llT


dcllLLll vs

Lv

Ldtid

⋅−= −−− rrr

31

31

RCv

isCdt

dv dcll

Tll

dc −⋅= −−

rr1

DB-110

Applying an average operator to switching model ττ= ∫−

dxT

txt

Tt

)(1)(

• Switch duty cycle

• Phase-leg duty cycle

• Line-to-line duty cycle

dττsT

tsdt

Ttapapap ∫

−

== )(1)(

anapa ddd −== 1

ba

t

Ttababab dddττs

Ttsd −=== ∫

−

)(1)(

• KVL and KCL

• Linear components

0=Σi0=Σv

RR iRv =dtidLv L

L =dtvdCi C

C =

Average Circuit Modeling


56

DB-111

dcabab vsv ⋅=

dcabdcab

t

Ttdcabab vdvsτdτvτs

Tv ⋅=⋅≈⋅= ∫

−

)()(1

Averaging of Quadratic Terms

if maximum-frequency components of are .)(tvdc T21<<

dclldclldcll vdvsvs ⋅=⋅≈⋅ −−−rrr

llT

llllT

llllT

ll idisis −−−−−− ⋅=⋅≈⋅rrrrrr

DB-112

ττττττ dvsL

vLT

ddt

idT

t

Ttdcllll

t

Tt

ll ∫∫−

−−−

− ⋅−= ))()(31)(

31(1)(1 rr

r

ττττττ dRC

visCT

ddt

dvT

t

Tt

dcll

Tll

t

Tt

dc ∫∫−

−−−

−⋅= ))()()(1(1)(1 rr

Applying average operatordcllLL

ll vsL

vLdt

id⋅−= −−

− rrr

31

31

RCvis

Cdtdv dc

llT

lldc −⋅= −−

rr1

dcllLLll vd

Lv

Ldtid

⋅−= −−−

rrr

31

31

RCvid

Cdtvd dc

llT

lldc −⋅= −−

rr1⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=−

ca

bc

ab

ll

ddd

dr

Development of Boost Rectifier Average Model


57

DB-113

dci

dcab vd ⋅

abi

bci

cai

Averaging

Lai

bi

ciABv

BCv C

Rdcv

Switching Model

Average Model

dcllLLll vs

Lv

Ldtid

⋅−= −−− rrr

31

31

RCvis

Cdtdv dc

llT

lldc −⋅= −−

rr1

dcllLLll vd

Lv

Ldtid

⋅−= −−−

rrr

31

31

RCvid

Cdtvd dc

llT

lldc −⋅= −−

rr1dcbc vd ⋅

dcca vd ⋅

CAv

p

n

C

RL dcv

dci

ai

bi

ciCAv ABv

BCv

0

1av

bv

as

csbs0

10

1

cv

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

−−−

=−

ac

cb

ba

ll

ssssss

sr

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

−−−

=−

ac

cb

ba

ll

iiiiii

i31r

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=−

CA

BC

AB

LL

vvv

vr

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=−

ca

bc

ab

ll

ddd

dr

Average Model of Three-Phase Boost Rectifier

DB-114

dcv

dcab vd ⋅

dcbc vd ⋅

dcca vd ⋅

ABv

BCv

CAv

abi

bci

caiabab id ⋅ bcbc id ⋅ caca id ⋅

L3

L3

L3

C R

• Third order system due to degeneration

Another Equivalent Circuit forBoost Rectifier Average Model


58

DB-115

dcab vd ⋅

dcbc vd ⋅

ABv

BCv

abi

bci

L3

L3

dcVabab id ⋅

bcbc id ⋅

caca id ⋅

C

R

Steady-State Operation under Balanced Sinusoidal Excitation

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

π+π−=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

)3/2cos()3/2cos(

)cos(

ωtVωtV

ωtV

vvv

m

m

m

CA

BC

AB

Given:

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

π+π−=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

)3/2cos()3/2cos(

)cos(

ωtIωtI

ωtI

iii

m

m

m

ca

bc

ab

Goal:

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

−π+−π−

−=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

)3/2cos()3/2cos(

)cos(

θωtDθωtD

θωtD

ddd

m

m

m

ca

bc

ab

Assume:

⎥⎦⎤

⎢⎣⎡ −

π+

π++−

π−

π−+−= )

32cos()

32cos()

32cos()

32cos()cos(cos θωtωtθωtωtθωtωtIDi mmdc

dci

⎥⎦⎤

⎢⎣⎡ −

π+++−

π−++−+= )

342cos(cos)

342cos(cos)2cos(cos

2θωtθθωtθθωtθIDi mm

dc

const.cos23const.cos

23

==⇒== θIRDVθIDi mmdcmmdc

DB-116

Steady-State Operation under Balanced Sinusoidal Excitation

Can use positive sequence phasors for steady state:

dcabABAB VωL ⋅+⋅= DIV 3j

11]1,0[,, ≤≤−⇒∈−≡−= abbpapbpapbaab dddddddd

)cos(,const. θωtVDvdVv dcmdcabdcdc −⋅=⋅⇒==

2m

ABV

=V2m

ABI

=I

θVDθVDV dcmdcmdcab sin

2jcos

2⋅

⋅−⋅

=⋅D

θRDVI

θDVV

RDωLθ

m

mm

m

mdc

m222

1

cos32,

cos,4sin

21

⋅==⎟⎟⎠

⎞⎜⎜⎝

⎛= −

mdcm VVD ≥⇒≤ 1


59

DB-117

Outline





PECon2008

DB-118

aps bps cps

ans bns cns

L

C

p

n

dcvCAvBCv

ABvav

bvcv

R

LLdcllll v

Lvs

Ldtid

−−− −⋅=

rrr

31

31

llT


LLllLL v

RCi

Cdtvd

−−− −=

rrr11

Averaging

LLdcllll v

Lvd

Ldtid

−−− −⋅=

rrr

31

31

llT

lldc idi −− ⋅=rr

LLllLL v

RCi

Cdtvd

−−− −=

rrr11

Development of VSI Average Model


60

DB-119

L3

L3

L3

RC

• Fourth order system due to degeneration

RC

RC

dcab vd ⋅

dcbc vd ⋅

dcca vd ⋅

abab id ⋅ bcbc id ⋅ caca id ⋅

dcv

ABv

BCv

CAv

abi

bci

cai

dci

Equivalent Circuit forVSI Average Model

DB-120

L3

L3

L3

RC

• Steady-state ac voltages and currents are sinusoidal if• Difficult to define small-signal model. Operating point ?

RC

RC

dcab vd ⋅

dcbc vd ⋅

dcca vd ⋅

abab id ⋅ bcbc id ⋅ caca id ⋅

dcv ABv

BCv

CAv

abi

bci

cai

dci

For:

⇒⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

π+π−=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

)3/2cos()3/2cos(

)cos(

ωtDωtD

ωtD

ddd

m

m

m

ca

bc

ab

const.=dcV

Steady-State Operation under DC Input and Balanced Sinusoidal Duty-Cycles

dcABdcabAB VV

ωCRRωL

ωCRR

≤⇒⋅⋅

++

+= VDV

j13j

j1

and


61

DB-121

Outline





PECon2008

DB-122

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

+−−−−

+−

=

21

21

21

)3

2sin()3

2sin(sin

)3

2cos()3

2cos(cos

32

/πωπωω

πωπωω

ttt

ttt

T abcdq0

Choose

where: ω=2πf, f is ac line frequency(source frequency for boost rectifier;desired output frequency for VSI)

abcdq0 XTX ⋅= dq0abc XTX ⋅= −1

)( / abcdq0TT =

Coordinate Transformation


62

DB-123

dcllLLll vd

Lv

Ldtid

⋅−= −−−

rrr

31

31

RCvid

Cdtvd dc

llT

lldc −⋅= −−

rr1

dcdq0dq0dq0 vdT

LvT

LdtiTd

⋅⋅−⋅=⋅ −−

− rrr

111

31

31)(

RCviTTd

Cdtvd dc

llT

lldc −⋅⋅= −

−−

rr11

dq0abc XTX ⋅= −1

dcdq0dq0dq0

dq0 vdL

TvL

Tdtid

Tidt

dT⋅⋅−⋅=⋅+⋅ −−−

− rrr

r

31

31 111

1

RCviTdT

Cdtvd dc

llT

lldc −⋅⋅⋅⋅= −−

rr)(1

×T

Coordinate Transformation– Boost Rectifier –

DB-124


dcdq0dq0dq0

dq0 vdL

vLdt

idi

dtdTT ⋅−=+⋅

− rrr

r

31

311

RCvid

Cdtvd dc

dq0Tdq0

dc −⋅=rr1

RCviTdT

Cdtvd dc

llT

lldc −⋅⋅⋅⋅= −−

rr)(1

dcdq0dq0dq0

dq0 vdL

vLdt

idi

dtdTT ⋅−=+⋅

− rrr

r

31

311

dq0ll ddTrr

=⋅ − dq0ll iiTrr

=⋅ −


63

DB-125

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

+−+−

−−−−

−−

⋅

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

+−−−−

+−

=

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

+−+−

−−−−

−−

⋅=

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

+−+

−−−

−

⋅=⋅=⋅−

0)3

2cos()3

2sin(

0)3

2cos()3

2sin(0cossin

32

21

21

21

)3

2sin()3

2sin(sin

)3

2cos()3

2cos(cos

32

0)3

2cos()3

2sin(

0)3

2cos()3

2sin(0cossin

32

)

21)

32sin()

32cos(

21)

32sin()

32cos(

21sincos

32(

T1

πωωπωω

πωωπωωωωωω

πωπωω

πωπωω

πωωπωω

πωωπωωωωωω

πωπω

πωπω

ωω

tt

tttt

ttt

ttt

tt

tttt

T

tt

tt

tt

dtdT

dtdTT

dtdTT


DB-126

23)

32(cos)

32(coscos 222 =++−+

ππ xxx

Using the following trigonometric relationships

23)

32(sin)

32(sinsin 222 =++−+

ππ xxx

0)3

2cos()3

2sin()3

2cos()3

2sin(cossin =+⋅++−⋅−+⋅ππππ xxxxxx

0)3

2cos()3

2cos(cos =++−+ππ xxx

0)3

2sin()3

2sin(sin =++−+ππ xxx



64

DB-127

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡ −=⋅

−

0000000

1

ωω

dtdTT

dcdq0dq0dq0dq0 vd

Liv

Ldtid

⋅−⋅⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡ −−=

rrrr

31

0000000

31 ω

ω

Therefore:dcdq0dq0

dq0dq0 vd

Lv

Ldtid

idt

dTT ⋅−=+⋅− rr

rr

31

311

RCvid

Cdtvd dc

dq0Tdq0

dc −⋅=rr1

RCvid

Cdtvd dc

dq0Tdq0

dc −⋅=rr1


DB-128

dc

ca

bc

ab

CA

BC

AB

ca

bc

ab

vddd

Lvvv

Liii

dtd

⋅⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡−

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

31

31

[ ]RCv

iii

dddCdt

vd dc

ca

bc

ab

cabcabdc −

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡⋅=

1

(abc coordinates)

dc

0

q

d

0

q

d

0

q

d

0

q

d

vddd

Liii

vvv

Liii

dtd

⋅⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡−

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡⋅

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡ −−

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

31

0000000

31 ω

ω

[ ]RCv

iii

dddCdt

vd dc

0

q

d

0qddc −

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡⋅=

1 (dq0 coordinates)

State-Space Equations– Boost Rectifier –


65

DB-129

Equivalent Circuit in dq0 Coordinates– Boost Rectifier –

di L3

dvqiLω3

dcd vd ⋅

qi L3

qvdiLω3

dcq vd ⋅

0i L3

0vdc0 vd ⋅

dcv

dd id ⋅ qq id ⋅ 00 id ⋅

C R

.3j,3j,3j cabcab iωLiωLiωL ⋅⋅⋅

The cross-coupling terms,

and ,

in dc coordinates (dq0),

account for the voltage drops

across inductances at line

frequency in ac coordinates,

qiωL3 diωL3

DB-130

0≡++ CABCAB vvv

0≡++ cabcab iii

0≡++ cabcab ddd

Since

0i L3

0vdc0 vd ⋅

0≡0v

0≡0i

0≡0d

0-channel can be omitted

0-Channel


66

DB-131

dcv

dd id ⋅ qq id ⋅

C R

di L3

dvqiLω3

dcd vd ⋅

qi L3

qvdiLω3

dcq vd ⋅

dcq

d

q

d

q

d

q

d vdd

Lii

vv

Lii

dtd

⋅⎥⎦

⎤⎢⎣

⎡−⎥

⎦

⎤⎢⎣

⎡⋅⎥

⎦

⎤⎢⎣

⎡ −−⎥

⎦

⎤⎢⎣

⎡=⎥

⎦

⎤⎢⎣

⎡

31

00

31

ωω

[ ]RCv

ii

ddCdt

vd dc

q

dqd

dc −⎥⎦

⎤⎢⎣

⎡⋅=

1

Equivalent Circuit in dq0 Coordinates– Boost Rectifier –

DB-132

LLdcllll v

Lvd

Ldtid

−−− −⋅=

rrr

31

31

llT

lldc idi −− ⋅=rr

LLllLL v

RCi

Cdtvd

−−− −=

rrr11

Transformation

(abc coordinates)

dq0dq0dcdq0dq0 v

Livd

Ldtid rrrr

31

0000000

31

−⋅⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡ −−⋅= ω

ω

dq0Tdq0dc idi

rr⋅=

dq0dq0dq0dq0 v

RCvi

Cdtvd rrrr

1

0000000

1−⋅

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡ −−= ω

ω

(dq0 coordinates)

State-Space Equations– Voltage Source Inverter –


67

DB-133

dqdqdcdqdq v

Livd

Ldtid rrrr

31

00

31

−⋅⎥⎦

⎤⎢⎣

⎡ −−⋅=

ωω

dqTdqdc idi

rr⋅=

dqdqdqdq v

RCvi

Cdtvd rrrr

10

01−⋅⎥

⎦

⎤⎢⎣

⎡ −−=

ωω

dcv

dd id ⋅ qq id ⋅C

R

di L3dv

qiLω3

dcd vd ⋅

L3qvdiLω3

dcq vd ⋅ R

C

qi

dci

dvCω

qvCω

Equivalent Circuit in dq0 Coordinates– Voltage Source Inverter –

DB-134

Buck Rectifier / CSI dq0 Model– similar approach but different results –

R

R

Cdcd id ⋅ dvdi

dcq id ⋅ qvqi

C

qvCω

dvCω

dcd id ⋅dvdi

dcq id ⋅qvqi

RC

dd vd ⋅

qq vd ⋅

L

dcvpnv

dci

dd vd ⋅

qq vd ⋅

L

dcv pnv

dciCurrent Source Inverter (CSI)

Buck Rectifier


68

DB-135

Outline

1. Introduction2. Switching Modeling and PWM3. Average Modeling4. Small-Signal Modeling

• Small-signal model of boost rectifier• Small-signal model of VSI• Three-phase modulator modeling

5. Closed-Loop Control Design


PECon2008

DB-136

Linearization

Autonomous dynamic system:

If is analytic it can be expressed as Taylor series:fr

Retaining the first 3 terms results in linear approximation of :fr

But the dynamic system is NOT linear because:

A Bx&r = xr ur+ 0≠gr+

K

rrr

rrrrrrr

rr

rrrrr

r

rrr

rrr

rrrrr

r

rrrrrrrrr

+

⎥⎦

⎤⎢⎣

⎡−

∂∂

+−−∂∂

∂+−

∂∂

+

+−⋅∂

∂+−⋅

∂∂

+=

202

002

0000

22

0200

2

000

000

00

)(),())((),()(),(!2

1

)(),()(),(),(),(

uuu

uxfuuxxux

uxfxxx

uxf

uuu

uxfxxx

uxfuxfuxf

)(),()(),(),(),( 000

000

00 uuu

uxfxxx

uxfuxfuxf rrr

rrrrr

r

rrrrrrrrr

−⋅∂

∂+−⋅

∂∂

+≅

000

000

000000 ),(),(),(),(),( u

uuxfx

xuxfuxfu

uuxfx

xuxf

dtxd r

r

rrrr

r

rrrrrrr

r

rrrr

r

rrrr

⋅∂

∂−⋅

∂∂

−+⋅∂

∂+⋅

∂∂

≅

),( uxfdtxd rrrr

=


69

DB-137

Linearization

)(),()(),(),(),( 000

000

00 uuu

uxfxxx

uxfuxfuxfdtxd rr

r

rrrrr

r

rrrrrrrrrr

−⋅∂

∂+−⋅

∂∂

+≅=

dtxd

dtxd

dtXd

dtxd ~~ rrrr

=+=

uUu ~rrr+=

uu

uxfxx

uxfdtxd

UXUX

~),(~),(~

),(),(

rr

rrrr

r

rrrr

rrrr⋅

∂∂

+⋅∂

∂≅

If is an equilibrium point , and is perturbation around it:),( UXrr

)~

,~

( ux rr),( 00 ux rr

0),( ≡UXfrrr

xXx ~rrr+=

0=dtXdr

),(

),(

UXu

uxfrr

r

rrr

∂∂

=B

uxx ~~~ rr&r ⋅+⋅= BA

),(

),(

UXx

uxfrr

r

rrr

∂∂

=A

DB-138

Average Large-Signal ModelBoost Rectifier

dcv

dd id ⋅ qq id ⋅

C R

di L3

dvqiLω3

dcd vd ⋅

qi L3

qvdiLω3

dcq vd ⋅

A steady-state operating point:

md VV ⋅=23

(Vm: Max line-to-line voltage)

0=qV

dc

dd V

VD =

dc

dq V

LID ω3−=

d

dcd DR

VI⋅

=

0=qI


70

DB-139

Linearization – Boost Rectifier

dcq

d

q

d

q

d

q

d vdd

Lii

vv

Lii

dtd

⋅⎥⎦

⎤⎢⎣

⎡−⎥

⎦

⎤⎢⎣

⎡⋅⎥

⎦

⎤⎢⎣

⎡ −−⎥

⎦

⎤⎢⎣

⎡=⎥

⎦

⎤⎢⎣

⎡

31

00

31

ωω

[ ]RCv

ii

ddCdt

vd dc

q

dqd

dc −⎥⎦

⎤⎢⎣

⎡⋅=

1

Linearization

dcq

ddc

q

d

q

d

q

d

q

d vDD

LV

dd

Lii

vv

Lii

dtd ~

31

~~

31

~~

00

~~

31

~~

⋅⎥⎦

⎤⎢⎣

⎡−⋅

⎥⎥⎦

⎤

⎢⎢⎣

⎡−

⎥⎥⎦

⎤

⎢⎢⎣

⎡⋅⎥

⎦

⎤⎢⎣

⎡ −−⎥

⎦

⎤⎢⎣

⎡=

⎥⎥⎦

⎤

⎢⎢⎣

⎡

ωω

[ ] [ ]RCv

ii

DDCI

Idd

Cdtvd dc

q

dqd

q

dqd

dc~

~~

1~~1~−

⎥⎥⎦

⎤

⎢⎢⎣

⎡⋅+⎥

⎦

⎤⎢⎣

⎡⋅=

DB-140

Small-Signal Model – Boost Rectifier

⎥⎦

⎤⎢⎣

⎡⋅

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

+⎥⎥⎦

⎤

⎢⎢⎣

⎡⋅

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

−

−

+⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

⋅

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

−

−−

−

=⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

q

d

q

d

qd

dc

dc

dc

q

d

qd

q

d

dc

q

d

vv

L

L

dd

CI

CI

LV

LV

vii

RCCD

CD

LD

LD

vii

dtd

~~

00310

031

~~

30

03

~

~~

13

0

30

~

~~

ω

ω

A Bx&r = xr ur+ D vr+

IntrinsicSystem Dynamics

ControlInput

DisturbanceInput


71

DB-141

Small-Signal Model – Boost Rectifier

dcv~

dd Id ⋅~

C R

di~ L3

dv~

qiL~3ω

dcd vD ~⋅

qi~ L3

qv~

diL~3ω

dcq vD ~⋅

dcd Vd ⋅~

dcq Vd ⋅~

dd iD ~⋅ qq Id ⋅~

qq iD ~⋅

DB-142

Open-Loop Transfer Functions

)()()()()(

~~

*221

21

pspspszszsK

di idddidddiddd

d

d

+⋅+⋅+

+⋅+⋅=

)()()(

)(~~

*221 pspsps

zsK

di iddqiddq

q

d

+⋅+⋅+

+⋅=

0

20

40

60

80

-300

-250

-200

-150

-100

1 10 100 1000 10000 100000

-40

-20

0

20

40

60

0

50

100

150

200

1 10 100 1000 10000 100000Frequency [rad/sec] Frequency [rad/sec]

Mag

nitu

de [d

B]

Pha

se [°

]


72

DB-143


)()()(

)()(~~

*221

21

pspsps

zszsK

d

i iqddiqddiqdd

d

q

+⋅+⋅+

+⋅+⋅=

)()()(

)()(~~

*221

*

pspsps

zszsK

d

i iqdqiqdqiqdq

q

q

+⋅+⋅+

+⋅+⋅=

-40

-20

0

20

40

60

-200

-150

-100

-50

0

50

1 10 100 1000 10000 100000

0

20

40

60

80

80

100

120

140

160

180

1 10 100 1000 10000 100000Frequency [rad/sec] Frequency [rad/sec]

Mag

nitu

de [d

B]

Pha

se [°

]

DB-144


)()()(

)()(~~

*221

1

pspsps

zszsK

dv RHPvdcdqvdcdq

q

dc

+⋅+⋅+

−⋅+⋅=

)()()()()()(

~~

*221

21

pspspszszszsK

dv RHPvdcddvdcddvdcdd

d

dc

+⋅+⋅+

−⋅+⋅+⋅=

Frequency [rad/sec] Frequency [rad/sec]

Mag

nitu

de [d

B]

Pha

se [°

]

0

20

40

60

80

-50

0

50

100

150

200

1 10 100 1000 10000 100000

-40

-20

0

20

40

60

-200

-100

0

100

200

1 10 100 1000 10000 100000


73

DB-145

Outline





PECon2008

DB-146

Average Large-Signal Model – VSI

A steady-state operating point:

qd

d CVR

VI ω−=

dq

q CVR

VI ω+=

dc

qdd V

LIVD

ω3−=

dc

dqq V

LIVD

ω3+=

dcv

dd id ⋅ qq id ⋅C

R

di L3dv

qiLω3

dcd vd ⋅

L3qvdiLω3

dcq vd ⋅ R

C

qi

dci

dvCω

qvCω


74

DB-147

Linearization – VSI

Linearization

⎥⎦

⎤⎢⎣

⎡−⎥

⎦

⎤⎢⎣

⎡⋅⎥

⎦

⎤⎢⎣

⎡ω

ω−−⋅⎥

⎦

⎤⎢⎣

⎡=⎥

⎦

⎤⎢⎣

⎡

q

d

q

ddc

q

d

q

dvv

Lii

vdd

Lii

dtd

31

00

31

[ ] ⎥⎦

⎤⎢⎣

⎡⋅=

q

dqddc i

iddi

⎥⎦

⎤⎢⎣

⎡−⎥

⎦

⎤⎢⎣

⎡⋅⎥

⎦

⎤⎢⎣

⎡ −−

⎥⎥⎦

⎤

⎢⎢⎣

⎡=⎥

⎦

⎤⎢⎣

⎡

q

d

q

d

q

d

q

d

vv

RCvv

ii

Cvv

dtd 1

001ω

ω

⎥⎦

⎤⎢⎣

⎡−

⎥⎥⎦

⎤

⎢⎢⎣

⎡⋅⎥

⎦

⎤⎢⎣

⎡ω

ω−−⋅⎥

⎦

⎤⎢⎣

⎡+⋅

⎥⎥⎦

⎤

⎢⎢⎣

⎡=

⎥⎥⎦

⎤

⎢⎢⎣

⎡

q

d

q

ddc

q

ddc

q

d

q

dvv

Lii

vDD

LV

dd

Lii

dtd

~~

31

~~

00~

31

~~

31

~~

[ ] [ ] ⎥⎦

⎤⎢⎣

⎡⋅+

⎥⎥⎦

⎤

⎢⎢⎣

⎡⋅=

q

dqd

q

dqddc I

Idd

ii

DDi ~~~~

~

⎥⎦

⎤⎢⎣

⎡−⎥

⎦

⎤⎢⎣

⎡⋅⎥

⎦

⎤⎢⎣

⎡ −−

⎥⎥⎦

⎤

⎢⎢⎣

⎡=⎥

⎦

⎤⎢⎣

⎡

q

d

q

d

q

d

q

d

vv

RCvv

ii

Cvv

dtd

~~1

~~

00

~~

1~~

ωω

DB-148

Small-Signal Circuit Model – VSI

dcv~

dd Id ⋅~

C R

di~

L3

dv~qiL~3ω

qi~

L3

qv~diL~3ω

dcd Vd ⋅~

dd iD ~⋅ qq Id ⋅~

qq iD ~⋅

RC

dci~ qvC~ω

dvC~ω

dcd vD ~⋅

dcq Vd ⋅~

dcq vD ~⋅


75

DB-149

Small-Signal State-Space Model – VSI

dcq

d

q

ddc

dc

q

d

q

d

q

d

q

d

vL

DL

D

dd

LV

LV

vvii

RCC

RCC

L

L

vvii

dtd ~

00

3

3

~~

0000

30

03

~~

~~

110

1013100

0310

~~

~~

⋅

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

+⎥⎥⎦

⎤

⎢⎢⎣

⎡⋅

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

+

⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢

⎣

⎡

⋅

⎥⎥⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢⎢⎢

⎣

⎡

−ω−

ω−

−ω−

−ω

=

⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢

⎣

⎡

A Dx&r = xr ur+ B + vr

DB-150

Outline





PECon2008


76

DB-151

Natural and Uniform Sampling

+_

Modulatingsignal

Natural Sampling Uniform Sampling

TS

Ton

TS

Ton

Carrier

+_

0

1

0

1

DB-152

Trailing- and Leading-Edge Modulation

+_

Trailing-Edge Modulation Leading-Edge Modulation

+_

TS

Ton

TS

Ton

Both are the natural sampling

0

1

0

1


77

DB-153

Review of Modulator Modeling for DC-DC Converters

Natural sampling

• Unity gain• No delay

Uniform sampling

1. Trailing-edge modulation• Unity gain• Phase delay at a modulation frequency

2. Leading-edge modulation• Unity gain• Phase delay at a modulation frequency

ms ωTD ⋅⋅

( ) ms ωTD ⋅⋅−1

DB-154

Three-Phase Modulator Modeling

All naturally sampled modulators can be modeled by the constantgain term

• Modulators associated with analog controllers

Small-signal models have to be derived for uniformly sampledthree-phase modulators

• Modulators associated with digital controllers

carm V

F 1=

refav vcar

Vcar

Vcar

t


78

DB-155

Example – for Boost Rectifier and VSI

Trailing-edge modulation (2Φ-RA)

Two out of three switching functions always have pulsessynchronized to the beginning of the switching period

TS

Sa

Sc

Sb

pnn ppn ppp

Sab

Sca

Sbc

msab ωTD ⋅⋅

( ) msca ωTD ⋅⋅−1

Phase delays:

DB-156

Approximate Average Model of Digital Modulator

refdd dd

refqd qd

dsTe−

qsTe−

DigitalModulator

refdd~

dd

refqd~

qd

refdd

refqd

dd~

qd~

refd

d

dd

~~

refd

q

d

d~

~

refq

q

d

d~

~

refq

d

dd

~~ +

+

+

+

≈

sqd TTT ≈≈

desired model ofactual

actual

CoordinateTransform.

InverseCoordinateTransform.


79

DB-157

Outline


• Control approach• Current-loop design• Voltage-loop design• Limiting


PECon2008

DB-158

Classical Linear Control Design Approach

Power stageControl1

Control2

Output1

Output2

Compensator

Power stageControl1

Control2

Output1

Output2

Compensator2

Compensator1

Multi-Input-Multi-Output

Single-Input-Single-Output


80

DB-159

Closed-Loop Control Design

• Based on small-signal models

Advantage• Classical control design methods can be used

(Bode plots, root loci, etc.)

Disadvantages• Design is valid only at a certain operating point• The approach does not guarantee large-signal stability

DB-160

Control Structure: Cascade Control

1. Inner current controla. Bang-bang current control (and

PWM) in stationary coordinatesb. Current control in stationary

coordinates with two independent or three dependent current controllers (P, PI, or resonant regulators)

c. Current control in rotating coordinates with two independent current controllers (P or PI regulators)

2. Outer output voltage or torque / flux / speed / position control (PI regulators)

Modulator

CurrentControl

OutputControl

Three-phasePWM

Converter

CurrentFeedback

OutputFeedback


81

DB-161

Control Realization

1. Completely analog controlComplete analog control is rarely used because ofhardware complexity

2. Combination of analog and digital controlAnalog current control in stationary and digital outputvoltage or speed and flux control

3. Completely digital controlUsed in most new designs

DB-162

3 - PhaseSwitching Network

Phase-to-linecurrenttransf.

Coordinatetransf.

Inversecoordinate

transf.

SVM

6

Phase-locked

loop (PLL)

vA

vB

vCia ib

cos θ

sin θ

iab ibc

id iq dd dq

dα dβcos θ

sin θ

Open-loop Boost Rectifier Control


82

DB-163

COORDINATETRANSFORM.

INVERSE COORD.TRANSFORM.

SVM

A/D A/D

A/D

A/D

A/D

A/D

D/A

D/A

6

DSP

GENERATIONPLL & sin θ, cos θ

Open-loop Boost Rectifier ControlDigital Signal Processor (DSP) Implementation

refdd ′ref

qd ′

ABv

BCv

abi bci

di′

qi′

di

qi

αd βdrefdd

refqd

DB-164

refdd ′ ref

qd ′refdD ref

qDref

dd~′ refqd~′

3 - PhaseSwitching Network

A/D

6

DSPA/D D/A(ZOH)

ImpedanceAnalyzer

Test signalOutput signal

di′ qi′

di

qirefdd ref

qd

Transfer Function Measurement Set-up


83

DB-165

di~′

qi~′

di~

qi~

refdd~

refqd~

BOOSTRECTIFIERSMALL-SIG.

MODEL

s s (k+2) TsComputational

delay PWM delay

Sampling instant

k T (k+1) T

Modified small-signal model

dd~

qd~

dcv~

dsTe−

qsTe−

dcv ′~

“Digital Control Interface”

cT

csTe−

csTe−

qd TT ,

csTe−

Digital Delay

DB-166

Simplified approximations in continuous time domain:

di~′

qi~′

di~

qi~

refdd~

refqd~

BOOSTRECTIFIERSMALL-SIG.

MODEL

dd~

qd~

dcv~

dsTe−

qsTe−

dcv ′~

“Digital Control Interface”

( )

( )122

1

1221

2

2

deldel

deldelsT

sTsT

sTsT

e del

++

+−≈−

Often choose: switchingsamplingqdcdel TTTTTT =≈≈≈≈

csTe−

csTe−

csTe−

Digital Delay


84

DB-167

Outline




PECon2008

DB-168

Current Loop Design

dcvdd id ⋅ qq id ⋅

C R

di L3dv

qiLω3dcd vd ⋅

qi L3qv

diLω3dcq vd ⋅

Hv Hid

Hiq

vref

v’dc

idref

iqref

di′

qi′

refqd

dd qd

refdd

di qiDigital Control Interface


85

DB-169

Control-to-Current Transfer Function

)()()()()(

~~

*221

21

pspspszszsK

di idddidddiddd

d

d

+⋅+⋅+

+⋅+⋅=

sK

KH ipid +=

Mag

nitu

de [d

B]

Pha

se [°

]

10

20

30

40

50

60

70

-300

-250

-200

-150

-100

0.1 1 10 100 1000 10000 100000Frequency [Hz]

DB-170

Control-to-Current Transfer Function

)()()(

)()(~~

*221

*

pspsps

zszsK

d

i iqdqiqdqiqdq

q

q

+⋅+⋅+

+⋅+⋅=

sK

KH ipiq +=

Mag

nitu

de [d

B]

Pha

se [°

]

10

20

30

40

50

60

70

80

100

120

140

160

180

0.1 1 10 100 1000 10000 100000Frequency [Hz]


86

DB-171

Current Loop-Gain

• D channel loop-gain Td• Bandwidth is limited by delay (fsw=20kHz)

Mag

nitu

de [d

B]

Pha

se [°

]

-20

0

20

40

60

80

-350

-300

-250

-200

-150

-100

-50

0

0.1 1 10 100 1000 10000 100000Frequency [Hz]

DB-172

Current Loop-Gain

• Q channel loop-gain Tq• Bandwidth is limited by delay (fsw=20kHz)

Mag

nitu

de [d

B]

Pha

se [°

]

-20

0

20

40

60

80

100

-350

-300

-250

-200

-150

-100

-50

0.1 1 10 100 1000 10000 100000Frequency [Hz]


87

DB-173

Current Regulation

• Peak is more pronounced when gain increases

-20

-15

-10

-5

0

5

-350

-300

-250

-200

-150

-100

-50

0

0.1 1 10 100 1000 10000 100000

-20

-15

-10

-5

0

5

0.1 1 10 100 1000 10000 100000

-400

-300

-200

-100

0

0.1 1 10 100 1000 10000 100000Frequency [Hz] Frequency [Hz]

Mag

nitu

de [d

B]

Pha

se [°

]

dref

di

i~

~′

qref

q

ii

~~′

DB-174

Current Loop with D and Q Decoupling

Hv Hid

Hiq

vref

v’dc

idref

i’d

iqref

i’q

3ωL/v’dc

3ωL/v’dc

qsT

dcq

sTdcq

refd

sTrefd ie

vωLdeviωLdedd ddd

d′⋅⋅

′+=⋅′′+=⋅= −−− 13)/3(

))

refqd

refdd

dsT

dcq

sTdcd

refq

sTrefq ie

vωLdeviωLdedd qqq

q′⋅⋅

′−=⋅′′−=⋅= −−− 13)/3(

))

refqd)

refdd)


88

DB-175

Decoupled D and Q Channels

di L3

dvdcd vd ⋅

)

qi L3

qvdcq vd ⋅

)

dcv

dd id ⋅ qq id ⋅

C R

• Similar to two parallel dc-dc boost converters after d and q decoupled

qqsT

dc

dcdcd

qdcd

iωLievvLωvd

iωLvd

d 33

3

−′′

+=

=−

−)))

ddsT

dc

dcdcq

ddcq

iωLievvLωvd

iωLvd

q 33

3

+′′

−=

=+

−)))

0≈

0≈

DB-176

Cross-Coupling Effect After Decoupling

qref

di

i~

~′

dref

q

ii

~~′


89

DB-177

Outline




PECon2008

DB-178

Output Voltage Loop Design

)()()(

~~

HL

RHP

dref

dcc psps

zsKiv

G+⋅+

−⋅==

-200

-150

-100

-50

0

0.1 1 10 100 1000 10000 100000Frequency [Hz]

Pha

se [°

]M

agni

tude

[dB

]

-20

-15

-10

-5

0

5

10


90

DB-179

COMPENSATOR DESIGN

Voltage compensator

Place z as high as possible for required phase margin.Place p for loop-gain

attenuation.Attainable voltage-loop bandwidth:

ωc

Outer loop-gain

Gc

Hv

zv pv v

v

ω < 1/4 zc RHP

K (1 + s / z )vvH =v s (1 + s / p )v

DB-180

Attainable Voltage Loop Bandwidthwith Delay

-10

0

10

20

30

10100

1,00010,000

-350-300-250-200-150-100

-50

K

Frequency [kHz]

Gai

n [d

B]Ph

ase

[deg

]

Voltage compensator

Zero is placed close to the crossover to improve the phase margin

K (1 + s / z )vvH =v s (1 + s / p )v

Kv


91

DB-181

Time Domain Simulation Results

Phase voltages and currents (PFC operation)

Output voltage

DB-182

Outline




PECon2008


92

DB-183

LIMITING IN THREE-PHASE CONVERTERS

Modulator

CurrentControl

OutputControl

Three-phasePWM

Converter

CurrentFeedback

OutputFeedback

Limiter

Limiter

DB-184

Boost Rectifier/VSI Switching State Hexagon

ab

bc

ca

v ref

Maximal attainable voltage vector lies on the hexagonFor sinusoidal average output voltages the voltage vector must be inside the inscribed circle

dcrefref Vdv ⋅⋅=

23rr

1123 22 ≤+⇒≤⇒⋅≤ qd

refdc

ref dddVvrr

Duty Cycle Limiting


93

DB-185

d lim q lim

Vector angle is kept constant( d ) and ( d ) should be fed back to the anti-windup current controllersIf output of each current controller is limited separatelyit can result in unattainable voltage vector

dd

dq

limd q

limd d

dlimref

d ref

1If 22 >+ qd dd

22limqd

dd dd

dd+

=

22limqd

qq dd

dd

+=

Duty Cycle Limiting

DB-186

idref

id

iqref

iq

3ωL/vdc

3ωL/vdc

refqd

refdd

Ki /s

Kp

μ

Ki /s

Kp

μ

ddlim

ddlim

dqlim

dqlim

Variable Limit PI (“Smart Anti-windup”) Current Controllers

μ → ∞


94

DB-187

Maximal current magnitude is limited

(i ) + ( i )ref ≤ Imaxd2 ref

q2√

Limiting of each reference current component is determined by the control algorithm

EXAMPLEBoost rectifier control

Output voltage

regulator

Imaxidref ( i )d

reflim

( i )qref

limiqref

(I ) - ( i )max2 ref

d2√ lim

CurrentControl dq

dd

Input displacement

factor controller

ref

ref

Current Limiting

DB-188

Outline


6. More Complex Converters• Three-phase four-wire (four-phase) converter• Multilevel converters• Parallel converters

PECon2008


95

DB-189

Limitations of Three-Leg Converters

2RR

R

Output Voltages

-2.4

-1.8

-1.2

-0.6

0

0.6

1.2

1.8

2.4

0 30 60 90 120 150 180

• There is no path for the neutral current.• Output voltages are unbalanced.

Conventional inverter is not good for highly unbalanced load.

AvBvCv

aibici

AvCvBv

Nv

dcv

DB-190

• Provide three-phase four-wire• Deal with unbalanced and nonlinear load

R

R 2R

dcv

av bvcv

xvAv Bv Cv

Nv

aibici

ni nL

L

C

Load

Applications

Advantages• The fourth leg provides a neutral current path• Compared to generating vn with capacitive divider:

• Much smaller dc-link capacitance is needed • Full utilization of dc-link voltage (15% higher) with SVM


96

DB-191

Three-Dimensional Space Vector forFour-Leg Converter

• Vγ is the zero-sequence component• Vγ is related to the neutral current

α

−β

γ

V→

Vα

Vβ

Vγ

0=++= cnbnan VVVVγ

a-b-c coordinates α−β−γ coordinates

dcv

av bvcv

xvAv Bv Cv

Nv

aibici

ni nL

L

C RA

RB RC

DB-192

A Nonlinear Load

Vector Trajectory

in α-β-γCoordinates

Trajectory Projection on

α-β Plane

Trajectory Projection on

γ -Axis

Desired voltage

for sinusoidal

Load current

[ ]TCBA iii

-600-400

-2000

200400

600

-600-400

-2000

200400

600

-500

0

500

AlfaBeta

Gam

ma

0.3 0.302 0.304 0.306 0.308 0.31 0.312 0.314 0.316-500

-400

-300

-200

-100

0

100

200

300

400

500

Vga

mm

a

time0.2950.295 0.3 0.305 0.31 0.315 0.32

-150

-100

-50

0

50

100

150

Il gam

ma

time

-300-200

-1000

100200

300

-300-200

-1000

100200

300-300

-200

-100

0

100

200

300

AlfaBeta

Gam

ma

-500 0 500-600

-400

-200

0

200

400

600

Alfa

Bet

a

-300 -200 -100 0 100 200 300-300

-200

-100

0

100

200

300

Alfa

Bet

a

[ ]Tcxbxax vvv[ ]TCNBNAN vvv

Ai

Bi

Ci

Ni

C

N

B

A

Three Single-Phase Diode Bridge Rectifiers with C Filter


97

DB-193

Switching Model

dcv

avbv

cvxv

AvBv

Cv

Nv

aibici

Ni

L

C

LAi LBi LCi

dci

nL

[ ]⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡⋅=

c

b

a

cbadc

iii

sssi dc

c

b

a

cx

bx

ax

vsss

vvv

⋅⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

xps aps bps cps

ans bns cnsxns

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

−−−

=⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

xpcp

xpbp

xpap

c

b

a

ssssss

sss

cbaN iiii −−−=

DB-194

Average Model in Stationary Coordinates

• Controlled voltage sources are balanced for balanced load• Controlled voltage sources are unbalanced for unbalanced load• Difficult to describe the circuit operation in abc coordinates

dcvdci

axvbxvcxv

xv

L

C

aibici

NinL

LAi LBi LCi

AvBv

Cv

Nv

dc

c

b

a

cx

bx

ax

vddd

vvv

⋅⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡[ ]

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡⋅=

c

b

a

cbadc

iii

dddi⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

π+ωπ−ω

ω=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

)3/2cos()3/2cos(

)cos(

tVtV

tV

vvv

m

m

m

refCN

BN

AN


98

DB-195

Average Model in Rotating Coordinates

+

+

+

+

++

++

d

q

0

dv

qv

ov

dωCv

qωCv

qωLi

dωLi

di

qi

oi

Ldi

Lqi

Loi

C

L

nLL 3+

dcd vd ⋅

dcq vd ⋅

dco vd ⋅

• 2 decoupled subsystems with reduced system orders• Transfer functions can be derived based on the dc operating point

dcv dci

ooqqdddc idididi ⋅+⋅+⋅=

L

C

C

DB-196

Transfer Functions

102 103

40

60

Gai

n (d

B)

102 103-180-90

090

180

Phas

e (d

egre

e)

Frequency (Hz)

+

+

+

+

102 103

1020304050

Gai

n (d

B)

102 103-180-90

090

180

Phas

e (d

egre

e)

Frequency (Hz)

• Sampling delay and PWM delay are incorporated in the model• The derived model agrees with the measurement very well

dd

qd

od

d

d

dv

q

d

dv

d

q

dv

q

q

dv

o

o

dv

dv

qv

ov

d

d

dv

q

d

dv


99

DB-197

Impact of Load Power Factor on Control-to-Output Voltage TFs

Resistive, capacitive (PF=-0.8), and inductive (PF=0.8) are all at 150 kW

Graph4

25.0

30.0

35.0

40.0

45.0

50.0

55.0

60.0

65.0

70.0

f(Hz)5.0 10.0 20.0 50.0 100.0 0.2k 0.5k 1.0k 2.0k 5.0k

(dB) : f(Hz)

db((vd/dd))

db((vd/dd))

db((vd/dd))

Resistive LoadPF = 1

Capacitive LoadPF = -0.8

Inductive LoadPF = 0.8

• Capacitive load shift the resonant frequency to lower frequency• Inductive load leads to a higher system order and higher resonant peaking• Both capacitive and inductive loads are worse loads than resistive load

d

ddv

DB-198

Control Block Diagram

VA

VB

VC

VN

4-leg Inverter Unbalanced and Nonlinear LoadFilter

Modulator Rotating Transformation

abc/dqo

VAN,BN,CNIABC

VdqoIdqo

Vdqo_ref-

+Current

CompensatorVoltage

Compensator

ddqo

Rotating Transformation

dqo/abc

dan dbn dcn

Vdc

+-


100

DB-199

Double-Loop Design

CONVERTERCONVERTER

+

+

+

+

–

–

–

drefv

qrefv

orefv

dv

ov

dd

qd

od

vdH

vqH

voH

d

d

di

q

d

di

d

q

di

q

q

di

o

o

di

–

–

–

idH

iqH

di

qi

oiioH

• Decoupling is not included

drefi

qrefi

orefi

d

d

iv

q

q

iv

o

oiv

+

+

q

d

iv

d

q

iv L

O

A

Dqv

DB-200

Switching State Vectorsin Three-Dimensional Space

a b

βα

γ

c

axvbxv

cxvdcv

xa

bc

n

p

dcv

n pnn

dcv

n npnn nnpn ppnn pppn abc

• 8 Switching State Vectors with non-negative γ-component

p abc

• 8 Switching State Vectors with non-positive γ-component

• 2×6 vectors with non-zero α & β• 2 “zero vectors” with non-zero γ• 2 zero vectors

β

γ

α

γ

a b

c

axvbxv

cxvdcv

xa

bc

n

p

• 16 Switching State Vectors

pnnn

pnnp

abcx


101

DB-201

Three-Dimensional Switching Vectors

pnnn

ppnn

npnn

nppn

nnpn

pnpn

pppn

pnnp

nnpp

npnp pnpp

ppnp

nppp

nnnp

ppppnnnn

α

−β

γ

pnnx

ppnxnpnx

nppx

nnpx pnpx

pppx

nnnx

V23 g

β

α

where x={p,n}

Projection on α−β plane

α

γ

dcvv3

1=γ

dcvv3

2=γ

dcvv3

3=γ

0=γv

dcvv3

1−=γ

dcvv3

2−=γ

dcvv3

3−=γ

dcv32

DB-202

Three-Dimensional SVM Step 1: Prism Identification

Prism II Prism III

Prism IV Prism V Prism VI

Prism I

pnnn

pnnp

ppnn

pppn

nnnp

nnnnpppp

Vref ppnp

ppnn

ppnp

npnn

pppn

nnnp

nnnnpppp

Vref

npnp

npnn

npnp

nppn

pppn

nnnp

nnnnpppp

Vrefnppp

nppn

nppp

nnpn

pppn

nnnp

nnnnpppp

Vref

nnpp

nnpn

nnpp

pnpn

pppn

nnnp

nnnnpppp

Vref pnpp

pnpn

pnpp

pnnn

pppn

nnnp

nnnnpppp

Vref

pnnp


102

DB-203

Three-Dimensional SVM Step 2: Tetrahedron Identification

pnnn

pnnpppnp

ppnn

pppn

nnnp

nnnnpppp

Vref

Tetrahedron 1

[+ 0 0]

[0 - -][0 0 -]

pnnn

pnnpppnp

ppnn

pppn

nnnp

nnnnpppp

Vref

Tetrahedron 2

[+ 0 0]

[+ + 0]

[0 0 -]

pnnn

pnnp

ppnp

ppnn

nnnp

nnnnpppp

Vref

pppn

Tetrahedron 4

[0 0 -]

[0 - -] [- - -]

pnnn

pnnpppnp

ppnn

pppn

nnnp

Vref

nnnnpppp

Tetrahedron 3

[+ 0 0]

[+ + 0]

[+ + +]

DB-204

Three-Dimensional SVM:Step 3: Duty-Cycle Calculation

332211 VdVdVdVref

rrrr++=

3210 1 dddd −−−=

1Vr

2Vr

0Vr

3Vr

refVr


103

DB-205

Sa

Sb

Sc

Sf

V1V2VZ1 V3

Ts(k) Ts(k+1)

1d2d

(a) Rising-Edge Aligned

3d

Sa

Sb

Sc

Sf

(b) Falling-Edge AlignedTs(k) Ts(k+1)

V3V2 VZ1V1

1d 2d 3d

Sa

Sb

Sc

Sf

(c) Symmetric AlignedTs(k) Ts(k+1)

V3V2 VZ1V1 V1V3 V2

2d1

2d2

2d2

2d1

2d3

2d3

Sa

Sb

Sc

Sf

V2V1 VZ1 V2 V1

zd1d 2d zd1d2d

(d) Alternative SequenceTs(k) Ts(k+1)

V3 V3

3d 3d

zd

zd

zd

VZ1

Three-Dimensional SVM: Step 4: Switching Sequencing (Minimum Loss)

DB-206

Experimental Results with Only Voltage Loops Closed

ILA

ILB

ILC

In

VAG

VBG

VCG

In

Output voltage and neutral currentLoad current and neutral current

Unbalanced Load


104

DB-207

A Four-Leg Inverter with Common-Mode Filter Function

• Common-Mode Noise

• A 4-Leg Inverter for Common-Mode NoiseElimination

• A New Modulation and Control Scheme for InverterPower Supplies with Unbalanced/Nonlinear Load

DB-208

A Four-Leg Inverter with Common-Mode Filter Function

4-leg inverter for unbalanced / nonlinear load

In order to have both functions, we need

A new switching modulation strategy

A new control design because of the series capacitor in neutral leg

4-leg inverter for common-mode reduction

If , there is NO common-mode noise!

0≡+++ xcba vvvv


105

DB-209

Use Only Switching Vectors with2 p’s and 2 n’s

6 available switching vectors out of 24 vectors

α

β

γ

pnnn

ppnn

npnn

nppn

nnpn

pnpn

pppn

pnnp

nnpp

npnppnpp

ppnp

nppp

nnnp

ppppnnnn

γ =1

γ =2/3

γ =1/3

γ =0

γ =-1/3

γ =-2/3

γ =-1

ref

α

β

pnnp

ppnnnpnp

nppn

nnpp pnpn

ref

npnp4ppnn3pnnp2pnpn1ref VVVVV ⋅+⋅+⋅+⋅= dddd

14321 =+++ dddd

DB-210

Common-Mode Noise Reductionand Trade-Offs

250V/div 25V/div

Conventional 4-leg inverter 4-leg inverter with CM reduction

Common-mode voltage Common-mode voltage

Three-phase inductor current Three-phase inductor current

100A/div 100A/div

• DM ripple is increased because of reduced vector choice• 15% smaller maximum modulation index


106

DB-211

Outline



PECon2008

DB-212

Major Multilevel Three-Phase Topologies

C1

0

VdSc1

Sc2

Sc3

vb vc

va

Sc’1

Sc’2

Sc’3

Sb1

Sb2

Sb3

Sb’1

Sb’2

Sb’3

Sa1

Sa2

Sa3

Sa’1

Sa’2

Sa’3

C2

C3

C1

0

VdSc1

Sc2

Sc3

vb vc

Cf Cf

va

Cf Cf

Cf

Cf

Cf

Cf

CfSc’1

Sc’2

Sc’3

Sb1

Sb2

Sb3

Sb’1

Sb’2

Sb’3

Sa1

Sa2

Sa3

Sa’1

Sa’2

Sa’3

C2

C3

C2a

vaC1a

C3a

C2b

C1b

C3b

C2c

C1c

C3c

va1

va2

va3

vbvb1

vb2

vb3

vn

vcvc1

vc2

vc3

Nabae, 1980; Choe, 1991; Carpita, 1991Diode clamped Flying capacitor

Meynard, 1992

Cascaded H-bridge


107

DB-213

Merits of Multilevel Converter Technologies

Advantages• Easy voltage sharing among devices• Improved spectral performance of output waveforms

• Reduced dv / dt resulting in reduced reflections and damage to insulation• Reduced switching and conduction losses

Disadvantages• Increased number of devices• Increased control complexity• Depending on topology:

– Issues with capacitors balancing – Issues with bi-directional power flow

Vab/Vdc

3-levlel 4-levlel 5-levlel

DB-214

Multilevel Converter Control

Comp. Comp. dqabc SVM Power Stage

& Load

Standard ac current and voltagecontrol in dq0 coordinates

• Average and small-signal models are the same as for two-level VSIor boost rectifier, except for multiple dc voltages

• Closed-loop control of ac quantities in rotating dq coordinates is the same as for two-level VSI or boost rectifier

• Additional controller for voltage balancing on dc-link capacitors• Modulator is significantly more complex

refdqvr refdqir

dqabc

dqabc

abcir

abcvr

DC CapacitorBalancing

dcvr


108

DB-215

-2-1

01

2

-2-1

01

2

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

020

vab/Vdcvbc/Vdc

v ca/V

dc

vab

vca

vbc

200 220

022002

202

210

120

021

012

102

201

121010

101212

122011

112001

211100

221110

REFV→

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

−−−

⋅=ikkjji

Vv dcijkr

..

..

...

0

1

n-2

n-1

a

b

c

a

b

c

1...0

n-1n-2..

1...0

n-1n-2..

1...0

n-1n-2..+

+

+

+Vdc

Vdc

Vdc

Vdc

• Voltage space-vectors can be represented in a three dimensional line-to-line coordinate system

Space-Vector Representation of Three-Level Converters

• Switching model of n-level converter:Three single-pole n-throw switches

DB-216

Voltage Space-Vectors of Three-Level Converters

200022

120

102

210

012

002 202

220020

021 221110

211100

101212

112001

122011

121010

201

REFM→

0 1 2

1

2

α

β

0=++ cabcab vvv:KVL

REFV→

• All the voltage space-vectors of a three-phase converter are located on a plane

va

vc

vbsa

sb

scvdc

vdcva

vc

vbsa

sb

scvdc

vdc

va

vc

vbsa

sb

scvdc

vdcva

vc

vbsa

sb

scvdc

vdc

• Every small vector has two corresponding switching states—redundancy.

Large Vector LV→

Medium Vector MV→

Small Vector SV→

Small Vector SV→

• Voltage space-vectors have different length: small, medium and large.

1

2

0

1

2

0

1

2

0

1

2

0


109

DB-217

SVM for Multilevel Three-Phase Converters?

• Switching states: n3 =125

• Switching vectors: 3n(n-1)+1 = 61

• Triangular areas: 6(n-1)2 = 96

Five-level converter

Complexity?Speed?

How to do SVM? 0 0 1

0 0 2

0 0 3

0 0 4

0 1 0

0 1 1

0 1 2

0 1 3

0 1 4

0 2 0

0 2 1

0 2 2

0 2 3

0 2 4

0 3 0

0 3 1

0 3 2

0 3 3

0 3 4

0 4 0

0 4 1

0 4 2

0 4 3

0 4 4 1 0 0

1 0 1

1 0 2

1 0 3

1 0 4

1 1 0

1 1 2

1 1 3

1 1 4

1 2 0

1 2 1

1 2 2

1 2 3

1 2 4

1 3 0

1 3 1

1 3 2

1 3 3

1 3 4

1 4 0

1 4 1

1 4 2

1 4 3

1 4 42 0 0

2 0 1

2 0 2

2 0 3

2 0 4

2 1 0

2 1 1

2 1 2

2 1 3

2 1 4

2 2 0

2 2 1

2 2 3

2 2 4

2 3 0

2 3 1

2 3 2

2 3 3

2 3 4

2 4 0

2 4 1

2 4 2

2 4 3

2 4 4

3 0 0

3 0 1

3 0 2

3 0 3

3 0 4

3 1 0

3 1 1

3 1 2

3 1 3

3 1 4

3 2 0

3 2 1

3 2 2

3 2 3

3 2 4

3 3 0

3 3 1

3 3 2

3 3 4

3 4 0

3 4 1

3 4 2

3 4 3

3 4 4

4 0 0

4 0 1

4 0 2

4 0 3

4 0 4

4 1 0

4 1 1

4 1 2

4 1 3

4 1 4

4 2 0

4 2 1

4 2 2

4 2 3

4 2 4

4 3 0

4 3 1

4 3 2

4 3 3

4 3 4

4 4 0

4 4 1

4 4 2

4 4 3

0 0 1

0 0 2

0 0 3

0 0 4

0 1 0

0 1 1

0 1 2

0 1 3

0 1 4

0 2 0

0 2 1

0 2 2

0 2 3

0 2 4

0 3 0

0 3 1

0 3 2

0 3 3

0 3 4

0 4 0

0 4 1

0 4 2

0 4 3

0 4 4 1 0 0

1 0 1

1 0 2

1 0 3

1 0 4

1 1 0

1 1 2

1 1 3

1 1 4

1 2 0

1 2 1

1 2 2

1 2 3

1 2 4

1 3 0

1 3 1

1 3 2

1 3 3

1 3 4

1 4 0

1 4 1

1 4 2

1 4 3

1 4 42 0 0

2 0 1

2 0 2

2 0 3

2 0 4

2 1 0

2 1 1

2 1 2

2 1 3

2 1 4

2 2 0

2 2 1

2 2 3

2 2 4

2 3 0

2 3 1

2 3 2

2 3 3

2 3 4

2 4 0

2 4 1

2 4 2

2 4 3

2 4 4

3 0 0

3 0 1

3 0 2

3 0 3

3 0 4

3 1 0

3 1 1

3 1 2

3 1 3

3 1 4

3 2 0

3 2 1

3 2 2

3 2 3

3 2 4

3 3 0

3 3 1

3 3 2

3 3 4

3 4 0

3 4 1

3 4 2

3 4 3

3 4 4

4 0 0

4 0 1

4 0 2

4 0 3

4 0 4

4 1 0

4 1 1

4 1 2

4 1 3

4 1 4

4 2 0

4 2 1

4 2 2

4 2 3

4 2 4

4 3 0

4 3 1

4 3 2

4 3 3

4 3 4

4 4 0

4 4 1

4 4 2

4 4 3

DB-218

Coordinates and Transformation

⎥⎦

⎤⎢⎣

⎡

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

+−

−−

+

−

−

=⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡=

refq

refd

dcca

bc

ab

ref vv

Vddd

d

)3

2sin(

)3

2sin(

)3

2cos(

)3

2cos(sincos

321

πθ

πθ

πθ

πθθθ

r

0,-1,1

0,-2,2

-1,0,1

-1,-1,2

-2,2,0

-2,1,1

-2,0,2

1,-1,0

1,-2,1

0,1,-1

-1,2,-1

-1,1,0

2, 0,-2

2,-1,-1

2,-2,0

1,1,-2

1,0,-1

0,2,-2

ab

bc

ca

0 0 1

0 0 2

0 1 0

0 1 1

0 1 2

0 2 0

0 2 1

0 2 2 1 0 0

1 0 1

1 0 2

1 1 0

1 1 2

1 2 0

1 2 1

1 2 2

2 0 0

2 0 1

2 0 2

2 1 0

2 1 1

2 1 2

2 2 0

2 2 1

• Transform

from dq to abc:dcref VV

r

• Choose line-to-line coordinates: ab, bc and caq

d

refVr

dref→


110

DB-219

falls in a triangle as follows:

Identify the Vectors and Calculate their Duty Cycles

0,-1,1

0,-2,2

-1,0,1

-1,-1,2

-2,2,0

-2,1,1

-2,0,2

1,-1,0

1,-2,1

0,1,-1

-1,2,-1

-1,1,0

2, 0,-2

2,-1,-1

2,-2,0

1,1,-2

1,0,-1

0,2,-2

ab

bc

ca

dref→

• Calculate the floor and ceiling of the projections: cacaca

bcbcbc

ababab

cdfcdfcdf

≤≤≤≤≤≤

, ,

refcabcab dfffr

then2 If −=++

dref→

cabcab fcf , ,)( bcbc fd −

cabcab cff , ,)( caca fd −

cabcab ffc , ,)( abab fd −

dref→

cabcab ccf , ,)( abab dc −

cabcab fcc , ,)( caca dc −

cabcab cfc , ,)( bcbc dc −

falls in a triangle as follows:refcabcab dfffr

then1 If −=++•

•

DB-220

1. The projections are

2. The floors and ceilings are

An Example

202.1=abd 440.0=bcd 642.1−=cad

1=abf2=abc

0=bcf1=bcc

2−=caf1−=cac

358.01,0,1440.02,1,1202.02,0,2

1,0,1

2,1,1

2,0,2

=−=−

=−=−

=−=−

−

−

−

caca

bcbc

abab

fddfddfdd

3. Since , the nearest three vectors and their duty cycles are:

1−=++ cabcab fff

0,-1,1

0,-2,2

-1,0,1

-1,-1,2

-2,2,0

-2,1,1

-2,0,2

1,-1,0

1,-2,1

0,1,-1

-1,2,-1

-1,1,0

2, 0,-2

2,-1,-1

2,-2,0

1,1,-2

1,0,-1

0,2,-2

ab

bc

ca

dref→

→dref with a length of 1.7 and an angle of 45º from ab axis


111

DB-221

p n n

NPINP

CDCSa

Sc

Sb

CDC

iaib

ic

Large vectors do not affect NP balance

Vab= VdcVbc= 0Vca= -Vdc

Ampitude=

Phase =

dcV32

⋅

o0

VabVca

Vbc

p n nn p p

p p nn p n

n n p p n p

Vca= Vdc

Vab= Vdc

Vbc= 0

Capacitor Balancing Problem in Three-LevelNeutral-Point (NP) Clamped Converter

INP = 0

DB-222

Full load current is connected to NPfor the duration of the medium vectorduty cycle

Vab= VdcVbc= - Vdc/2Vca= -Vdc/2

Ampitude = Vdc

Phase = o30-

VabVca

Vbc

o n p

p o n

o p n

n p o

n o p p n o

Vca= Vdc/2

Vab= VdcVbc= Vdc/2

p n o

NPINP

CDCSa

Sc

Sb

CDC

iaibic

Medium vectors affect the charge balance in the neutral point causing the low frequency ripple

INP = ic


112

DB-223

p o o

NPINP

CDCSa

Sc

Sb

CDC

iaib

ic

Small vectors come in pairs

Freedom to select either vector in a pair helps balance NP

Vab= Vdc/2Vbc= 0Vca= -Vdc/2

Ampitude =

Phase =

dcV31

⋅

o0

NPINP

CDCSa

Sc

Sb

CDC

iaib

ic

o n n

VabVca

Vbc

p o oo n n

o p on o n

o p pn o o

o o pn n o

p o po n o

p p oo o n

Vca= Vdc

Vab= Vdc

Vbc= 0

Small vectors also affect the capacitor charge balance and their effect can be controlled

INP = ia

INP = ib + ic = – ia

DB-224

Modified SVM algorithm can effectively compensatethe voltage ripple in the neutral point

• Based on the commanded balancing effort, virtual small vector• can be computed (need to use both vectors every cycle)

)evev(v32V j2

caj

bcabγγ +⋅+=

32πγ =

• Compute the location of voltage space vectors in every switching cycle

• Determine the sector location of the current VREF

• Compute the duty cycles

0VSV→

LV→

MV→

→'0SV0SV

→

S0'

S0VS0 Vc)(1VcV→→→

⋅−+⋅= [ ]0,1c ∈


113

DB-225

Ripple free area

power factor angle (deg)

mod

ulat

ion

inde

x m

VabVca

Vbc

Va

Vb

Vc

ILOAD

VREFφ

φ

Neutral point can be balanced in every switching cycle only in the part of the operating region

DB-226

Ripple free areadt

I(t)iQ

T

0 a

NP∫=

0

1

2

Vpos

Vneg

0

Vdc

Cdc

Cdc

+

+

iNPNP

Finding the normalized charge ripple for all operating conditions helps design dc-link capacitors


114

DB-227

0

2000

4000

6000

8000

10000

12000

14000

1 0.8 0

μFSystem Parameters• 1800 V DC bus• 1% NP ripple• 200 A Peak current

max_DC

maxDC U

IKC2Δ

⋅=⋅ K - normalized amplitude of

NP charge

m=0.9

cos(φ)

With NP controlWithout NP control

As expected, the effect of NP charge control diminishes for the decreasing power factor angle

DB-228

Balancing of clamping capacitor for flying capacitorconverter is load-independent

ica1= ia ica1= - ia

• The inner capacitor handles only switching frequency ripple current• There is no clamping diode reverse recovery problem• The modulation and higher level control remains the same

• Flying capacitor converters with any number of levels can be balanced.• Diode-clamped converters with number of levels above three CANNOT!

Van= Vpn/2

CdcVpn a

Sa1

Sa2

Sa3

Sa4

Cdcia

ica1

n 0

p 2

+ CdcVpn a

Sa1

Sa2

Sa3

Sa4

Cdcia

ica1

n 0

p 2

+


115

DB-229

Outline



PECon2008

DB-230

Motivation

Gen

DC Distribution Bus

Filter Motor

DC/AC

AC/DC

Filter

DC/DC

AC/DC

Filter

DC/ACFilter

R

A Distributed Power System • Modular design• N+1 redundancy (reliability)• No limit for current level• Maintainability• Availability• Reduced cost, size and weight• Improved performance

Parallelability


116

DB-231

Possible Solutions

• Separate power supplies• Transformer isolation• Inter-phase reactors• Six-leg converter

A Six-Leg Converter

PowerSupply

#2

PowerSupply

#1

Controller

Transformer

Inter-PhaseReactors

DB-232

Issues – ModelingChallenges

• High-order system• Coupling

Converter #1

C2

Converter #2

dV

qV

1dI

2dI

2qI

1qI

13L

23L

13L

23L

113 qILω

113 dILω

223 qILω

223 dILω

11 dd Id 11 qq Id

22 dd Id 22 qq Id

1dcI

2dcI

dcV

1C

dcd Vd 1

dcq Vd 1

dcd Vd 2

dcq Vd 2

RExisting results

• High-order multi-input-multi-output modeling1

• Reduced order modeling2

2Mao, 1994

1Matakas, 1993


117

DB-233

Issues – Load Sharing

Challenge

• Load sharing• Voltage regulation• Modular design

Existing results

• Master/Slave1

• Droop2

Converter #1

Converter #2

Control #2

Control #1 Load-sharingcontrol

Input Output

Converter #1

Converter #2

Control #2

Control #1

Input Output

Master/Slave

DroopPoor Voltage Regulation

P

V

GoodLoad

Sharing

PoorLoad

Sharing

Good Voltage Regulation

1Siri, 19922Jamerson, 1994

DB-234

Issues – Zero-Sequence Current

source/load

load/sourceI0

a b

ab

source/load

load/sourceI0

a b c

a b c

source/load

load/sourceI0

a b c n

a b c n


118

DB-235

Phase-Leg Averaging

dcVdcIaI

aa Id ⋅dca Vd ⋅0

aVai

aps

ans

av

dcidcv

0

aps

ans

Tad

avdcV

dci

aI

T

t

t

ab

c

DB-236

An Averaged Three-Phase Converter Model

phase-leg model

converter model

cI

dcc Vd ⋅

cV

dcVdcI

0

bI

dcb Vd ⋅

bV

dca Vd ⋅

aVaI

aa Id ⋅ bb Id ⋅ cc Id ⋅

dcVdcIaI

aa Id ⋅dca Vd ⋅0

aV


119

DB-237

Extraction of Zero-Sequence Components

Define:

Where:

cbaz dddd ++=

0333 =−+−+− )d(d)d(d)d(d zc

zb

za

0''' =++ cba ddd

3' z

aaddd −=

3' zaa

ddd +=

A zero-sequence component ≡ the sum of all phases components

cba IIII ++=0 e.g.

3' z

bbddd −= 3

' zcc

ddd −=

3' zbb

ddd += 3' zcc

ddd +=

DB-238

The Model with Zero-Sequence Components

• For a single converter, there is a zero-sequence voltagebut no zero-sequence current because

cIcV

dcVdcI

0

bI bVaVaI

3dcz Vd ⋅

dca Vd ⋅'dcb Vd ⋅'

dcc Vd ⋅'

aa Id ⋅'bb Id ⋅'

cc Id ⋅'

3)/II(Id cbaz ++⋅

0≡++ cba III


120

DB-239

Zero-Sequence Current in Parallel Converters

2cI2cV

2dcI

2bI 2bV2aV2aI

32 dcz Vd ⋅ 32222 )/II(Id cbaz ++⋅

1aI1aV

dcV

1dcI01bI 1bV

1cV1cI

31 dcz Vd ⋅

dcc Vd ⋅'1dcb Vd ⋅'

1dca Vd ⋅'1

31111 )/II(Id cbaz ++⋅

I0

01I

02I

dcc Vd ⋅'2dcb Vd ⋅'

2dca Vd ⋅'2

1'1 cc Id ⋅1

'1 bb Id ⋅1

'1 aa Id ⋅

2'2 cc Id ⋅2

'2 bb Id ⋅2

'2 aa Id ⋅

DB-240

An Averaged Model of Zero-Sequence Dynamic

222

2'

22

111

1'1

133 a

adca

dcza

adca

dcz IRdt

dILVdVdIRdt

dILVdVd ⋅−−⋅+⋅=⋅−−⋅+⋅

0210

2121 I)R(Rdt

dI)L(L)d(dV zzdc ⋅+++=−⋅

21 LL + 21 RR +

)d(dV zzdc 21 −⋅

In AC side, there are three-loops forming three equations:

Equivalent circuitI0

222

2'2

211

11

'1

133 b

bdcb

dczb

bdcb

dcz IRdt

dILVdVdIRdt

dILVdVd ⋅−−⋅+⋅=⋅−−⋅+⋅

222

2'2

211

11

'1

133 c

cdcc

dczc

cdcc

dcz IRdt

dILVdVdIRdt

dILVdVd ⋅−−⋅+⋅=⋅−−⋅+⋅


121

DB-241

Zero-Sequence Duty Cycle

For example:

1d

2dpnn

npn

nnp

ppn

npp

pnp

as

bs

csppp ppn pnn nnnnnn pnn ppn

21d

40d

22d

22d

21d

021

002021

5.125.0)5.0()5.0(

ddddddddddddd cbaz

++=+++++=++=

40d

20d

DB-242

A New Zero-Sequence Control Variable k

pppdk ≡ i.e. the duration of zero-vector ppp

021

002021

32)()(

kdddkdkddkddddddd cbaz

++=+++++=++=

Therefore:

as

bs

csppp ppn pnn nnnnnn pnn ppn

0kd21d

2)1( 0dk−

2)1( 0dk−

22d

22d

21d

• k is not definable in minimum lossSVM schemes


122

DB-243

• I0 can be controlled by controlling k1 dynamically

• High control bandwidth can be achieved becauseit is a first-order system

0I21 LL + 21 RR +

)d(dV zzdc 21 −⋅

0I21 LL + 21 RR +

01 503 )d.(kVdc −⋅

01

0221012121

5033232

)d.-(k)dkd(ddkdddd zz

=++−++=−

where k2 is set to 0.5

A New Zero-Sequence Modelwith the New Control Variable k

DB-244

Implementation

• This part is added ontoa regular controller for asingle converter.

LoadSource

va2 vb2vc2

va1vb1

vc1

ia2ib2ic2

ic1ib1ia1

vdc

0

idc2

idc1i0

0

PI k

aps

dd qd

0kdaps

i0

bpscps

ans bps bns cps cns


123

DB-245

Simulation Results

Without Zero-sequence control With Zero-sequence control(Two converters with different switching frequencies operate independently)

ia1

ia2

5A/div

i01

i02

5A/div

i01 i02

5A/div

ia1 ia2

5A/div

DB-246

Clock Phase ShiftingCommon-Mode Voltage Reduction

0

2/dcv+2/dcv−

2/dcv+2/dcv−

6/dcv−

1as

1bs

1cs

2as

2bs

2cs

Common-mode voltage


124

DB-247

ia1 ia2

ia

20A/div

Clock Phase ShiftingDifferential-Mode Ripple Reduction

DB-248

Thank You

The work and contributions are by many CPES faculty, students, and staff.

Many global industrial and US government sponsors of CPES researchare gratefully acknowledged.

This work was supported in part by

ERC Program of the US National Science Foundation under Award Number ECC-9731677

This trip was partially sponsored by

Joint PELS / IAS / IES Chapter ofIEEE Malaysia Section

IEEE Power Electronics Society(PELS)

PECon2008


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Documents

Modeling and Control of Three-Phase PWM Converters...Dushan Boroyevich: Modeling and Control of Three-Phase PWM Converters Tutorial at PECon 2008, Johor Bahru, Malaysia, 30 November