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Agile, eXtensible, fast I/O Module for the cyber-physical era De-CPS 2016: Workshop on Challenges and New Approaches for Dependable and Cyber-Physical System Engineering Pisa, Italy, 17 June 2016 Modeling Multi-Board Communication in the AXIOM Cyber-Physical System Roberto Giorgi, Somnath Mazumdar, Stefano Viola, Paolo Gai, Stefano Garzarella, Bruno Morelli, Dionisios Pnevmatikatos, Dimitris Theodoropoulos, Javier Bueno, Antonio Filgueras, Daniel Jimenez-Gonzalez, Carlos Alvarez, Xavier Martorell, Eduard Ayguade University of Siena (Coordinator Partner)

Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

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Page 1: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

Agile, eXtensible, fast I/O Module for the cyber-physical eraDe-CPS 2016: Workshop on Challenges and New Approaches

for Dependable and Cyber-Physical System Engineering

Pisa, Italy, 17 June 2016

Modeling Multi-Board Communicationin the AXIOM Cyber-Physical System

Roberto Giorgi, Somnath Mazumdar, Stefano Viola, Paolo Gai, Stefano Garzarella, Bruno Morelli, Dionisios Pnevmatikatos, Dimitris Theodoropoulos, Javier Bueno, Antonio Filgueras, Daniel

Jimenez-Gonzalez, Carlos Alvarez, Xavier Martorell, Eduard Ayguade

University of Siena

(Coordinator Partner)

Page 2: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

2AXIOM id. 645496

http://www.axiom-project.eu

Page 3: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

Agenda

1) Introduction on the AXIOM IoT stack

2) Importance of the high-speed interconnect

3) Details about the interfaces

4) Initial results

3AXIOM id. 645496

http://www.axiom-project.eu

Page 4: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

AXIOM OBJECTIVES• OBJ1) Realizing a small board that is flexible, energy efficient and modularly scalable

– Flexibility: FPGA provides acceleration, custom interconnects, ability to distribute threads across boards

– Energy efficiency: low-power ARM, FPGA

– Modularly scalable: fast+inexpensive interconnects based on SATA/USB-C, distributed shared memory across boards

• OBJ2) Easy programmability of multi-core, multi-board, FPGA– Programming model: Improved OmpSs

– Runtime & OS: improved thread management

• OBJ3) Leveraging Open-Source software to manage the board– Compiler: BSC Mercurium

– OS: Linux

– Drivers: provided as open-source by partners

• OBJ4) Easy Interfacing with the Cyber-Physical World– Cyber-Physical World: integrating Arduino support for a plenty of pluggable board (so-called “shields”)

– Platform: building on the UDOO experience from SECO

• OBJ5) Enabling real time movement of threads– Runtime: will leverage the EVIDENCE’s SCHED_DEADLINE scheduler (i.e. EDF) included Linux 3.14,

UNISI’s low-level dataflow-based thread management techniques

• OBJ6) Contribution to Standards– Hardware: SECO is founding member of the Standardization Group for Embedded Systems (SGET)

– Software: BSC is member of the OpenMP consortium

4AXIOM id. 645496

http://www.axiom-project.eu

Page 5: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

EASY PROGRAMMABILITY

VIA OPENMP-SS (OMPSS)

`

Only 3 lines of code to

- accelerate code on FPGAs

- distributed code across

several AXIOM boards

5AXIOM id. 645496

http://www.axiom-project.eu

Page 6: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

AXIOM – THE MODULE

• KEY ELEMENTS

– K1: ZYNQ FPGA (INCLUDES 6 ARM CORES)

– K2: ARM GP CORE(S)

– K3: HIGH-SPEED & INEXPENSIVE INTERCONNECTS

– K4: SW STACK – OMPSS+LINUX BASED

– K5: OTHER I/F (ARDUINO, USB, ETH, WIFI, …)

6AXIOM id. 645496

http://www.axiom-project.eu

Page 7: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

CAN WE DO THAT ?• SECO/UNISI achievements:

– 2014: UDOO-ARM (99 $ PC+Arduino) � 600k$ on Kickstarter

– 13th April 2016: UDOO-x86 (PC+Arduino, 10x faster than

Raspberry-3) � 100k$ in 7 hours (!) on Kickstarter

7AXIOM id. 645496

http://www.axiom-project.eu

Page 8: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

Core1

CoreN

(GPU)

I/O

hub

PL

HIGH SPEED

TRANCEIVERSMC

XSM

MEM…

…

SoC1

Core1

CoreN

(GPU)

I/O

hub

PL

HIGH SPEED

TRANCEIVERSMC

XSM

MEM…

…

SoC2

Core1

CoreN

(GPU)

I/O

hub

PL

HIGH SPEED

TRANCEIVERSMC

XSM

MEM…

…

SoC3

Core1

CoreN

(GPU)

I/O

hub

PL

HIGH SPEED

TRANCEIVERSMC

XSM

MEM…

…

SoC4

AXIOM Cluster Architecture

AXIOM id. 645496

http://www.axiom-project.eu

Page 9: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

First AXIOM Board – under review

AXIOM id. 645496

http://www.axiom-project.eu9

Page 10: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

Axiom NIC: type of messages

• Multiple type of messages

– Small messages (payload embedded in the descriptor)

• RAW

– Very short message (up to 128 bytes)

• RAW NEIGHBOUR

– RAW message to neighbour node

– Big messages (payload as a pointer in the descriptor)

• RDMA read/writes

– Remote DMA transfer between two nodes

• LONG

– Based on RDMA, but without specify a destination address

– Pool of buffers provided by the receiver node

AXIOM id. 645496

http://www.axiom-project.eu10

Page 11: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

Axiom NIC: queues

• Multiple queue available

– TX/RX small messages

• RAW and RAW NEIGHBOUR

– TX/RX big messages

• LONG and RDMA

• Port in each descriptor

– To address process in the node

– Process can bind one or more ports

AXIOM id. 645496

http://www.axiom-project.eu11

Page 12: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

1 byte

src field

dst field

payload byte0 of word 0

payload byte1 of word 0

payload byte2 of word 0

payload byte3 of word 0

msg id

TYPEvc

payload size

payload byte0 of word 1

payload byte1 of word 1

payload byte2 of word 1

payload byte3 of word 1

…

PORT

send raw data

src field

dst field

msg id

TYPEvc

payload size

dstAddr0

dstAddr3

dstAddr2

dstAddr1

payload byte0 of word 0

payload byte1 of word 0

payload byte2 of word 0

payload byte3 of word 0

…

PORT

1 byte

send data from local memory to

remote address

src field

dst field

msg id

TYPEvc

payload size

srcAddr0

srcAddr3

srcAddr2

srcAddr1

PORT

payload size

dstAddr0

dstAddr3

dstAddr2

dstAddr1

1 byte

read data from remote node

AXIOM Interconnect packets

Page 13: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

Initial network configuration

• Hypothesis– Makers will likely connect nodes in a random way

– They will expect to connect to a single node to run an application on the cluster

• Prerequisite– One node used as an interface to the cluster:

• Usually called master node

• E.g.: connected with ethernet or Wi-Fi

• Initialization– The master node starts a discovery algorithm

• Node_id assigned on each node

– Then the routing table is computed and distribited

– After that, the network is fully working

AXIOM id. 645496

http://www.axiom-project.eu13

Page 14: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

AXIOM Recursive Discovery Algorithm

int ax_discovery(node, next_id) {

node.my_id = next_id++;

for <each neighbour> {

if <neighbour node already have an ID> {

<skip it>

} else {

next_id = ax_discovery(neighbour, next_id);

}

}

return next_id;

}

/* start the discovery algorithm on the master node */

next_id = 0;

ax_discovery(master, next_id);

AXIOM id. 645496

http://www.axiom-project.eu

Page 15: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

Initial results

Page 16: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

Programming Model Level

Msg. size (bytes) Avg. messages/s

Matmul 536 - 22000 - 32500 68 - 74

N-body 3072 - 5400 - 8192 62 - 107

App / cores per

node

1 2 3 4

Matmul (1 node) 0.28 0.57 0.84 1.11

Matmul (2 nodes) 0.52 1.01 1.52 1.54

N-body (1 node) 0.15 0.30 0.46 0.58

N-body (2 nodes) 0.17 0.35 0.61 0.72

• Message Statistics

• Application Performance (Gflops)

AXIOM id. 645496

http://www.axiom-project.eu

Page 17: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

PS7

DDR

AXI lite interconnect

AXI meminterconnect

ACP

GP0

AXIDMA

Tx+ -

MGTclk+ -

Rx

Aurora64b/66b

+

-

Block Diagram of Two ZC706 FPGA Boards

Connected With SMA Cables

AXIOM id. 645496

http://www.axiom-project.eu

LUTs LUTs (%) FFs FFs (%) BRAMs BRAMs (%)

10583 4.8% 12452 2.8% 5 0.9%

Resource Utilization

Page 18: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

0

100

200

300

400

500

1 4 32 256 4096 32768 65536

av

era

ge

th

rou

gh

pu

t (M

B/s

ec)

data size in words

single-trip round-trip

Achieved Throughput

Network throughput when using the Aurora IP to exchange data

between two ZC706 FPGA boards with a single MGT transceiver.

AXIOM id. 645496

http://www.axiom-project.eu

Page 19: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

AXIOM NIC registers

• Have been emulated using QEMU on ARM64bit

– Communication between virtual machine emulated

using sockets on teh QEMU backend

• An initial implementation of the network in user

space has been done

– Discovery algorithm

– Routing Algorithm

– The nodes are able to deliver small messages using

user space programs

AXIOM id. 645496

http://www.axiom-project.eu19

Page 20: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

1

2

4

8

16

32

64

128

256

512

Matrix Size 128 Matrix Size 256 Matrix Size 512

READ BYTES

WRITTEN BYTES

DF-Threads Initial Results

AXIOM id. 645496

http://www.axiom-project.eu

N. Data set size

(normalized)

Page 21: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

Conclusions

• AXIOM is going to develop an innovative board

communication infrastructure that will power

next generation IoT boards

• The key message is:

– Cluster of small boards

– With uniform programming language based on

OpenMP

– Optimized thanks to FPGA and custom network

with RDMA

AXIOM id. 645496

http://www.axiom-project.eu21

Page 22: Modeling Multi-Board Communication in the AXIOM Cyber ... · AXI lite interconnect AXI mem interconnect ACP GP0 AXI DMA Tx +-MGT + - clk Rx Aurora 64b/66b +-Block Diagram of Two ZC706

Agile, eXtensible, fast I/O Module for the cyber-physical era

PROJECT ID: 645496

University of Siena

(Coordinator Partner)

AXIOM project --- http://www.axiom-project.eu


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