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Modeling of Distributed Gate Resistance of SiC PowerMOSFETs
Semester Thesis (FS 2021)
Fig. 1: SiC MOSFET: half of active cell - 2D TCAD structure (left); top view of the chip (right).
Introduction
Since their appearance on the market in 2010, Silicon Carbide (SiC) power MOSFETs have been gaining alot of popularity replacing silicon devices in high-end power applications.The aim of this semester thesis is investigation of a particular important problem: influence of SiC MOSFET’sgate fingers layout on its fast switching performance. Fast switching results in a large value of the gatecurrent, which comprises of displacement currents of the MOSFET’s gate-source and gate-drain internalcapacitances. Large gate current leads to a change of the gate-source voltage along the gate fingers andthereby to modification of switching curves in comparison to the standard MOSFET model, in which thedistributed internal gate resistance is simulated by a single lumped resistor.
Scope of the Thesis
The main tasks in this thesis can be divided as following:
• Literature survey on the simulation of the power MOSFET’s distributed gate resistance .
• Development of a physical model and correspondent mixed-mode TCAD simulation setup based on theexisting APS’s 2D SiC power MOSFET model. Perform switching simulations in TCAD. Compare themwith analogous compact model simulation. Analyze the results.
• Report and documentation.
Contact For more details please contact:
Supervisors: Dr. Alexander Tsibizov [email protected] ETL F24.1
Professor: Prof. Dr. U. Grossner [email protected] ETL F 28
